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CAD for VLSI Design - II

Lecture 5 V. Kamakoti and Shankar Balachandran

Overview of this Lecture


CMOS Transistor Theory
Delay Issues

MOSFET Voltages for CMOS Inverter


Cutoff
VGSn < VTn

Linear
VGSn VTn Vin VTn VDSn < VGSn VTn Vout < Vin VTn

Saturation
VGSn VTn Vin VTn VDSn VGSn VTn Vout Vin VTn VGSp VTp Vin VTp + VDD VDSp VGSp VTp Vout Vin VTp

NMO S

Vin < VTn

VGSp > VTp

PMO S

Vin > VTp+ VDD

VGSp VTp Vin VTp + VDD VDSp > VGSp VTp Vout > Vin VTp

Example: PMOS-NMOS Size Ratio


For a 0.25m CMOS process with VDD=2.5V and desired VM of 1.25V: VDSATn = 0.63V, VDSATp = -1V, kn = 115x10-6 A/V2, kp = 30x10-6 A/V2, VTn = 0.43V and VTp = -0.4V

(W (W

L )p L )n

115 10 6 0.63 ( 1.25 0.43 0.63 2 ) = 6 30 10 1.0 ( 2.5 1.25 0.4 1.0 2 )

= 3.5

VM versus Wp /Wn
1.8 1.7 1.6 1.5 1.4

1.3 1.2 1.1 1 0.9 0.8


0 1

10

Wp/Wn

10

VM versus Wp/Wn for 0.25um, 2.5V

VM is relatively insensitive to Wp/Wn around the center point. Small variations of the ratio do not change the VTC too much. For Wp=2Wn, VM1.2V Wp can be made only 2Wn instead of 3.5x or 3x saving some valuable area. Shifting of VTC by changing the Wn/Wp ratio results in a characteristics with asymmetric noise margins.

V (V)

Effect of Ratio r on Noise Margin

VM

VM

Delays in a Circuit

Sheet Resistance for a 0.25m Process


Material Metal1 (Al) Metal5 (Al) Polysilicon n+ diffusion p+ diffusion Silicided diffusion p or n-well Rs ( / ) 0.07 0.04 20 69 165 9 1500

Req depends strongly on the region of operation. For simple performance estimates use approximations: Using channel resistance in the linear region

MOSFET Channel Resistance Req


L Req = k W 1 C ox (VGS VT )

where, k =

Req as the average of the two end points of the transition during switching. For an NMOSFET switching on in an inverter,
Req = V DD 1 = + = ( ) R V V R V on out DD on out 2 2

1 V DS = 2 I DS

+
Vout =V DD

V DS I DS

Vout =

V DD

Req versus VDD


7 x 10
5

(Ohm) R

eq

0 0 .5

1 .5

2 .5

DD

(V)

Req of a min. size NMOSFET in 0.25m (VGS=VDD, VDS=VDDVDD/2)

Source and Drain Resistance

Effects of Resistance
Resistance affects performance RC delay Current supplied through resistive wire IR drop which degrades signal levels, especially important in the power distribution network reduces noise margin and changes logic levels as a function of the distance from the main supply terminals
Logic Logic Reduce distance between supply terminal & logic

Questions and Answers

Thank You

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