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AUTOMOTIVE MOSFET IRF1405 Typical Applications ● Electric Power Steering (EPS) ● Anti-lock Braking System (ABS)

AUTOMOTIVE MOSFET

IRF1405

Typical Applications

Electric Power Steering (EPS)

Anti-lock Braking System (ABS)

Wiper Control

Climate Control

Power Door

Benefits

Advanced Process Technology

Ultra Low On-Resistance

Dynamic dv/dt Rating

175°C Operating Temperature

Fast Switching

HEXFET ® Power MOSFET

D G S
D
G
S

V DSS = 55V

R DS(on) = 5.3m

I D = 169A

Repetitive Avalanche Allowed up to Tjmax

   

Description

 
TO-220AB

TO-220AB

 

Specifically designed for Automotive applications, this Stripe Planar design of HEXFET ® Power MOSFETs utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this HEXFET power MOSFET are a 175°C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These benefits combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications.

Absolute Maximum Ratings

 
 
 

Parameter

 

Max.

Units

I D @ T C = 25°C

Continuous Drain Current, V GS @ 10V

 

169

 

I D @ T C = 100°C

Continuous Drain Current, V GS @ 10V

 

118

A

I DM

Pulsed Drain Current

 

680

P D @T C = 25°C

Power Dissipation

 

330

W

 

Linear Derating Factor

 

2.2

W/°C

V GS

Gate-to-Source Voltage

 

± 20

V

E AS

Single Pulse Avalanche Energy

 

560

mJ

 

I AR

Avalanche Current

See Fig.12a, 12b, 15, 16

A

E AR

Repetitive Avalanche Energy

mJ

dv/dt

Peak Diode Recovery dv/dt

 

5.0

V/ns

T

J

Operating Junction and Storage Temperature Range

 

-55

to + 175

 

T

STG

 

°C

 

Soldering Temperature, for 10 seconds

300 (1.6mm from case )

 

Mounting Torque, 6-32 or M3 screw

 

10 lbf•in (1.1N•m)

 

Thermal Resistance

Parameter

Typ.

Max.

Units

R

θJC

Junction-to-Case Case-to-Sink, Flat, Greased Surface Junction-to-Ambient

–––

0.45 °C/W

R

θCS

0.50 –––

R

θJA

–––

62

www.irf.com

1

Electrical Characteristics @ T J = 25°C (unless otherwise specified)

@ T J = 25°C (unless otherwise specified)   Parameter Min. Typ. Max. Units  
 

Parameter

Min.

Typ.

Max.

Units

 

Conditions

V

(BR)DSS

Drain-to-Source Breakdown Voltage

55

–––

–––

V

V

GS = 0V, I D = 250µA

V (BR)DSS /T J

Breakdown Voltage Temp. Coefficient

–––

0.057

–––

V/°C

Reference to 25°C, I D = 1mA

R

DS(on)

Static Drain-to-Source On-Resistance

–––

4.6

5.3

m

V

GS = 10V, I D = 101A

V

GS(th)

Gate Threshold Voltage

2.0

–––

4.0

V

V

DS = 10V, I D = 250µA

g

fs

Forward Transconductance

69

–––

–––

S

V

DS = 25V, I D = 110A

I

Drain-to-Source Leakage Current

–––

–––

20

µA

V

DS = 55V, V GS = 0V

 

DSS

–––

–––

250

V

DS = 44V, V GS = 0V, T J = 150°C

I

Gate-to-Source Forward Leakage

–––

–––

200

nA

V

GS = 20V

 

GSS

Gate-to-Source Reverse Leakage

–––

–––

-200

V

GS = -20V

Q

g

Total Gate Charge

–––

170

260

 

I D = 101A

 

Q

gs

Gate-to-Source Charge

–––

44

66

nC

V

DS = 44V

Q

gd

Gate-to-Drain ("Miller") Charge

–––

62

93

V

GS = 10V

t

d(on)

Turn-On Delay Time

–––

13

–––

 

V

DD = 38V

t

r

 

Rise Time

–––

190

–––

ns

I D = 110A

 

t

d(off)

Turn-Off Delay Time

–––

130

–––

R

G = 1.1

t

f

 

Fall Time

–––

110

–––

V

GS = 10V

 

L

D

Internal Drain Inductance

–––

4.5

–––

 

Between lead, 6mm (0.25in.)

D G
D
G
 

L

S

Internal Source Inductance

–––

7.5

–––

nH

from package and center of die contact

S

 

C

iss

Input Capacitance

–––

5480

–––

 

V

GS = 0V

C

oss

Output Capacitance

–––

1210

–––

pF

V

DS = 25V

C

rss

Reverse Transfer Capacitance

–––

280

–––

ƒ

= 1.0MHz, See Fig. 5

C

oss

Output Capacitance

–––

5210

–––

V

GS = 0V, V DS = 1.0V,

ƒ = 1.0MHz

C

oss

Output Capacitance

–––

900

–––

V

GS = 0V, V DS = 44V,

ƒ = 1.0MHz

C

oss eff.

Effective Output Capacitance

–––

1500

–––

V

GS = 0V, V DS = 0V to 44V

Source-Drain Ratings and Characteristics

 
 

Parameter

Min.

Typ.

Max.

Units

 

Conditions

I

S

Continuous Source Current (Body Diode)

–––

–––

169

MOSFET symbol showing the integral reverse p-n junction diode.

D G S
D
G
S

I

SM

Pulsed Source Current (Body Diode)

–––

–––

680

V

SD

Diode Forward Voltage

–––

–––

1.3

V

T

J = 25°C, I S = 101A, V GS = 0V

t

rr

Reverse Recovery Time

–––

88

130

ns

T

J = 25°C, I F = 101A

 

Q

rr

Reverse RecoveryCharge

–––

250

380

nC

di/dt = 100A/µs

t

on

Forward Turn-On Time

Intrinsic turn-on time is negligible (turn-on is dominated by L S +L D )

Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11). Starting T J = 25°C, L = 0.11mH R G = 25, I AS = 101A. (See Figure 12). I SD 101A, di/dt 210A/µs, V DD V (BR)DSS , T J 175°C Pulse width 400µs; duty cycle 2%.

C oss eff. is a fixed capacitance that gives the same charging time as C oss while V DS is rising from 0 to 80% V DSS . Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. Limited by T Jmax , see Fig.12a, 12b, 15, 16 for typical repetitive avalanche performance.

1000 VGS TOP 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 100 10 4.5V
1000 VGS TOP 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 100 10 4.5V
1000
VGS
TOP
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM
4.5V
100
10
4.5V
20µs PULSE WIDTH
T
J
=
25
°
C
1
0.1
1
10
100
I
, Drain-to-Source Current (A)
D

V DS

, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

1000 T = 25 ° C J T = 175 ° C J 100 10
1000
T
= 25
°
C
J
T
= 175
°
C
J
100
10
V
DS
= 25V
20µs PULSE WIDTH
1
4
6
8
10
12
I
, Drain-to-Source Current (A)
D

V GS

, Gate-to-Source Voltage (V)

Fig 3. Typical Transfer Characteristics

1000 VGS TOP 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 100 4.5V 20µs
1000
VGS
TOP
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM
4.5V
100
4.5V
20µs PULSE WIDTH
T
J
=
175
°
C
10
0.1
1
10
100
I
, Drain-to-Source Current (A)
D

V DS

, Drain-to-Source Voltage (V)

Fig 2. Typical Output Characteristics

3.0 I = 169A D 2.5 2.0 1.5 1.0 0.5 V = 10V GS 0.0
3.0
I
= 169A
D
2.5
2.0
1.5
1.0
0.5
V
= 10V
GS
0.0
-60 -40 -20
0
20
40
60
80 100 120 140 160 180
T
, Junction Temperature(
° C)
J
R
DS(on)
, Drain-to-Source On Resistance
(Normalized)

Fig 4. Normalized On-Resistance Vs. Temperature

)AnruC

t (r

er

ecu--

oSi

tor

D a n,

I D

100000 = 0V, f = 1 MHZ V GS = C SHORTED C iss gs
100000
= 0V,
f = 1 MHZ
V GS
=
C
SHORTED
C iss
gs + C gd ,
C ds
=
C
C rss
gd
C oss = C ds + C gd
10000
Ciss
Coss
1000
Crss
100
1
10
100
atcapaC,C
)pecni
F(

V DS , Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage

1000 T = 175 ° C J 100 T = 25 ° C J 10
1000
T
=
175
°
C
J
100
T
=
25
°
C
J
10
V
= 0 V
GS
1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
I
, Reverse Drain Current (A)
SD

V SD

,Source-to-Drain Voltage (V)

Fig 7. Typical Source-Drain Diode Forward Voltage

(V) Fig 7. Typical Source-Drain Diode Forward Voltage 20 I D = 101A V = 44V
20 I D = 101A V = 44V DS V = 27V DS 16 12
20
I
D
=
101A
V
= 44V
DS
V
= 27V
DS
16
12
8
4
FOR TEST CIRCUIT
SEE FIGURE
13
0
0
60
120
180
240
300
Q
, Total Gate Charge (nC)
G
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
10000
V
, Gate-to-Source Voltage (V)
GS

1000

100

10

1

OPERATION IN THIS AREA LIMITED BY R DS (on) 100µsec 1msec Tc = 25°C 10msec
OPERATION IN THIS AREA
LIMITED
BY R DS (on)
100µsec
1msec
Tc
=
25°C
10msec
Tj = 175°C
Single
Pulse
0
1
10
100
1000

V DS , Drain-toSource Voltage (V)

Fig 8. Maximum Safe Operating Area

200 LIMITED BY PACKAGE 160 + - 120 ≤ 1 ≤ 0.1 % 80 Fig

200 LIMITED BY PACKAGE 160 + - 120 ≤ 1 ≤ 0.1 % 80 Fig
200
LIMITED BY PACKAGE
160
+
-
120
≤ 1
≤ 0.1 %
80
Fig 10a. Switching Time Test Circuit
40
V
DS
90%
0
25
50
75
100
125
150
175
T
, Case Temperature (
°
C)
C
10%
V
GS
Fig 9. Maximum Drain Current Vs.
Case Temperature
t d(on)
t r
t d(off)
t f
Fig 10b. Switching Time Waveforms
1
D = 0.50
0.20
0.1
0.10
0.05
0.02
SINGLE PULSE
0.01
(THERMAL RESPONSE)
P
DM
0.01
t
1
t
2
Notes:
1. Duty factor
D = t
/ t
1
2
2. Peak T
=
P
x
Z
+ T
J
DM
thJC
C
0.001
0.00001
0.0001
0.001
0.01
0.1
t 1 , Rectangular Pulse Duration (sec)
Thermal Response (Z
)
I
, Drain Current (A)
thJC
D

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

15V L DRIVER V DS D.U.T R G + - V DD I AS 20V
15V
L
DRIVER
V DS
D.U.T
R G
+
-
V DD
I AS
20V
0.01Ω
t p

A

Fig 12a. Unclamped Inductive Test Circuit

I AS

V (BR)DSS t p
V (BR)DSS
t
p
Fig 12b. Unclamped Inductive Waveforms Q G Q GS Q GD V G Charge Fig
Fig 12b.
Unclamped Inductive Waveforms
Q G
Q GS
Q GD
V G
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator Same Type as D.U.T. 50KΩ .2µF 12V .3µF + V DS D.U.T. -
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
.3µF
+
V DS
D.U.T.
-
V
GS
3mA
I G
I D

Current Sampling Resistors

Fig 13b. Gate Charge Test Circuit

Sampling Resistors Fig 13b. Gate Charge Test Circuit 1200 I D TOP 41A 71A 1000 BOTTOM
1200 I D TOP 41A 71A 1000 BOTTOM 101A 800 600 400 200 0 25
1200
I
D
TOP
41A
71A
1000
BOTTOM
101A
800
600
400
200
0
25
50
75
100
125
150
175
Starting T , Junction Temperature(
° C)
J
E
, Single Pulse Avalanche Energy (mJ)
AS

Fig 12c. Maximum Avalanche Energy Vs. Drain Current

4.0 3.5 3.0 I D = 250µA 2.5 2.0 1.5 -75 -50 -25 0 25
4.0
3.5
3.0
I
D = 250µA
2.5
2.0
1.5
-75
-50
-25
0
25
50
75
100
125
150
175
V
aV,
cia
)Ver
(
thG )(S

T J , Temperature ( °C )

Fig 14. Threshold Voltage Vs. Temperature

mrgenEehcnlaavA )J(y

,RA

E

1000 Duty Cycle = Single Pulse Allowed avalanche Current vs 0.01 avalanche pulsewidth, tav 100
1000
Duty
Cycle
= Single Pulse
Allowed avalanche
Current vs
0.01
avalanche
pulsewidth,
tav
100
assuming
∆ Tj
=
25°C due to
avalanche losses
0.05
0.10
10
1
1.0E-08
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
)euehcnlA
aav
t (n ArrC

tav (sec)

Fig 15. Typical Avalanche Current Vs.Pulsewidth

600

500

400

300

200

100

0

TOP Single Pulse BOTTOM 10% Duty Cycle I D = 101A 25 50 75 100
TOP
Single Pulse
BOTTOM
10% Duty Cycle
I D = 101A
25
50
75
100
125
150
175

Starting T J , Junction Temperature (°C)

Fig 16. Maximum Avalanche Energy Vs. Temperature

Notes on Repetitive Avalanche Curves , Figures 15, 16:

(For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption:

Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax . This is validated for every part type.

2. Safe operation in Avalanche is allowed as long asT jmax is not exceeded.

3. Equation below based on circuit and waveforms shown in Figures 12a, 12b.

4. P D (ave) = Average power dissipation per single avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche).

6. I av = Allowable avalanche current.

7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25°C in Figure 15, 16). t av = Average time in avalanche. D = Duty cycle in avalanche = t av ·f Z thJC (D, t av ) = Transient thermal resistance, see figure 11)

P D (ave) = 1/2 ( 1.3·BV·I av ) = T/ Z thJC I av = 2 T/ [1.3·BV·Z th ]

E AS (AR) = P D (ave) ·t av

+ • • • - + - + - • • •
+
-
+
-
+
-

+

-

• • • - + - + - • • • + - Driver Gate Drive
Driver Gate Drive P.W. Period D = P.W. Period V =10V GS D.U.T. I SD
Driver Gate Drive
P.W.
Period
D =
P.W.
Period
V
=10V
GS
D.U.T. I SD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V DS Waveform
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
Ripple ≤ 5%
SD

For N-channel HEXFET ® power MOSFETs

Dimensions are shown in millimeters (inches) 10.54 (.415) - B - 3.78 (.149) 10.29 (.405)

Dimensions are shown in millimeters (inches)

10.54 (.415) - B - 3.78 (.149) 10.29 (.405) 2.87 (.113) 3.54 (.139) 4.69 (.185)
10.54
(.415)
- B -
3.78
(.149)
10.29
(.405)
2.87
(.113)
3.54
(.139)
4.69
(.185)
2.62
(.103)
4.20
(.165)
- A -
1.32
(.052)
1.22
(.048)
6.47
(.255)
6.10
(.240)
4
15.24
(.600)
14.84
(.584)
1.15 (.045)
LEAD ASSIGNMENTS
MIN
1 - GATE
1
2
3
2 - DRAIN
3 - SOURCE
4 - DRAIN
14.09
(.555)
4.06
(.160)
13.47
(.530)
3.55
(.140)
3X 0.93 (.037)
0.69
(.027)
3X 0.55 (.022)
0.46 (.018)
3X 1.40 (.055)
1.15 (.045)
0.36 (.014)
M
B
A
M
2.92
(.115)
2.64
(.104)
2.54 (.100)
2X

NOTES:

1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.

2 CONTROLLING DIMENSION : INCH

3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.

4

HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.

EXAMPLE: THIS IS AN IRF1010 PART NUMBER 1789 INTERNATIONAL LOT CODE 1997 RECTIFIER ASSEMBLED ON
EXAMPLE:
THIS IS AN IRF1010
PART NUMBER
1789 INTERNATIONAL
LOT CODE
1997 RECTIFIER
ASSEMBLED ON WW 19,
LOGO
IN THE ASSEMBLY LINE "C"
DATE CODE
YEAR 7 =
1997
ASSEMBLY
LOT CODE
WEEK 19
LINE C

TO-220AB packages are not recommended for Surface Mount Application.

Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q101] market. Qualification Standards can be found on IR’s Web site.

Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 8/03

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