World Applied Sciences Journal 4 (1): 142-149, 2008 ISSN 1818-4952 IDOSI Publications, 2008

A Six Transistors Full Adder

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K. Navi, 2 V. Foroutan, 1 B. Mazloomnejad, 2 Sh. Bahrololoumi, 1 O. Hashemipour and 2 M. Haghparast

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Faculty of Electrical and Computer Engineering, Shahid Beheshti University, Tehran, Iran Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran
Abstract: A new six transistors multiple-valued current mode one bit full adder is presented. Simulations results utilizing standard 0.18 m CMOS technology illustrate a significant improvement in terms of number of transistors, chip area and propagation delay. Key words: Full adder multiple-valued logic current mode CMOS VLSI design

INTRODUCTION Using Multiple Valued Logic (MVL) have potential advantages in chips performing extensive arithmetic operations due to the reduction in the number of MOS transistors and relaxed wiring requirements due to the smaller word size [1]. The MVL is a potential alternative to Binary logic [2-4]. Reducing the amount of interconnects and the number of active devices on a given chip [13]. By extending MVL off-chip, we can also reduce chip pinout. These reductions can improve performance in terms of speed, area and power dissipation. The MVL circuits are generally operated in two modes of voltage or current. Current Mode Logic (CML) has some advantages over voltage mode MVL. Implementing voltage-mode MVL requires partitioning the total voltage range, zero to supply voltage in to many discrete levels. Thus, the dynamic range and the noise margin are highly dependent on the supply voltage. In current-mode circuits, currents are usually defined to have logical levels that are integer multiple of a reference current unit. Current can be copied, scaled and algebraically sign-changed with a simple current mirror. The frequently used linear sum operation can be performed simply by wiring, resulting in a reduced number of active devices in the circuit [18]. Using current instead of voltage as the alternating parameter is possible. Of course the designing of c ircuits should be in another way [2-5, 25]. One of the most important arithmetic operations in computer arithmetic is addition. For implementing any other arithmetic operation such as subtraction, multiplication or even logarithmic function we need efficient adders [6]. In recent years several variations of

different logic styles have been proposed to implement 1-bit adder cells [7-10, 15]. 3-valued and 4-valued circuits have been defined for implementing 2-input and 3-input adders with Borrow/carry save redundant number representation, which is the number representation used in [14]. They are based on 3-valued to binary converter (3-BC) and 4valued to binary converter (4-BC) circuits. These circuits are fundamental ones. Moreover, as we will detail, the 4-BC cell is the current-mode binary full adder [5]. The paper begins with a discussion of fourvalued CML circuitry for one bit adder followed by a description of MVL current mode circuits. Then the implementation of current mode circuits and its related problems are discussed and finally the proposed six transistor adder based on MVL method is introduced. MATERIALS AND METHODS Four valued CML circuit for 1-bit adder: Currentmode multi-valued circuits have m different current levels, ranging from 0 to (m-1). One basic operation is the analog sum of currents, which is free to implement. The basic cell is called 4-BC (4 valued input current to binary outputs converter). It is used to implement the current mode one bit adder according to Fig. 1 [19]. Three binary current inputs are summed and the analog sum is decomposed according to 'sum' and 'carry' binary current outputs, as shown in Table 1.

Fig. 1: Current mode one bit adder

Corresponding Author: Majid Haghparast, Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran

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Table 1: Sum and carry binary current outputs i 0 1 2 3 icarry 0 0 1 1 isum 0 1 0 1

Table 2: Gj, L j, in, isum and icarry .functions i 0 1 2 3 G0 0 1 1 1 G1 0 0 1 1 G2 0 0 0 1 L0 1 0 0 0 L1 1 1 0 0 L2 1 1 1 0 icarry 0 0 1 1 isum 0 1 0 1

Adders can be implemented in many different ways. The simplest way for implementing an adder is by using and simplifying their truth table in standard ways. The classic and conventional way of implementation is digital implementation, but there exist other efficient ways [23]. By using threshold detectors we can present other ways for implementing adders [5, 21-22, 24]. To operate with m different current levels, (m-1) threshold detectors are needed and the tolerance constrains are more and more difficult to satisfy when the number of current levels increases. It is roughly know that 8 levels is an upper limit for many technologies [5]. The threshold detectors can be implemented by the binary functions L j (i) and Gj (i) as described below. Letter G and L are driven from the beginning of Greater and Less, respectively. If i>j Then Gj (i) =1 Else Gj (i) =0 If i>j Then Lj (i) =1 Else Lj (i) =0 So we can consider that Lj (i)= G i . The output can simply be implemented with Gj (i) and Lj (i) functions:
i carry = G1 ( in)

requires no extra elements. Another feature in current mode is that the direction of current can be used to show the sign and as a result the additional bit for representing the sign in numeric system, can be eliminated. The interesting feature in current mode circuits is that we can design various circuits using threshold detector and changing threshold value and sometimes by increasing or decreasing the number of inputs. The designing of threshold value is possible by changing only the threshold detector transistors dimensions. As can be observed, the uniform structure of current mode circuits, easily allows the designer to increase the number of inputs, while in the voltage mode, this is only possible with increasing the number of transistors. This is simply possible because the circuit input is an aluminum or poly-silicon system. Figure 2, shows the basic circuit for various current mode logic circuits such as: 2-input AND/OR, 3-input AND/OR, N -input AND/OR and other necessary logic circuits such as Majority function [20-21]. One can design the desired function by setting the threshold value. Iin , can be a factor of the unit current, which means it can represent the logic two, three, four, etc [5, 26, 27]. The implementation of majority function with given equation: I1 I2 +I1 I3 +I2 I3 , is shown in Fig. 3 [20,21]. If the sum of the inputs is greater than logic 1.5 (threshold value) then the output current will be equal to reference current else, there is no current at the output.

(1) (2) Fig. 2: Basic current mode circuit for different logical functions

i sum = G 0 ( in) L 1(in) +G 2( in)

Table 2 presents the truth table of G j, L j , in, i s um and icarry. In equation II, the terms [G 0 (i n ) * L 1 ( in)] and

[G 2 ( in) ] cannot be simultaneously equal to 1. (+) can

be implemented as a logical (Or) or as an analog sum. This results in a cell which has 13+2 transistors [5]. MVL current mode circuits: As mentioned before, the main advantage of current mode comparing to the voltage mode is that the summation in current mode 143

Fig. 3: Majority function

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Fig. 4: Symbolic diagram of current source

obtaining well copied currents, the high output resistance of current mirror is necessary and the conventional double cascade current mirror as shown in Fig. 6 is adopted generally [11]. However, this mirror is unsuitable for low-voltage circuits because it makes the minimum value of output voltage become about VT+2V , where V = Iin / K [11]. In order to overcome this disadvantage, a highswing MOS current mirror with minimum V out = 2V was proposed [17], but it needs a bias current which is respected by a maximum value of this input current. Another scheme of current source is shown in Fig. 7, [13]. A small signal analysis of the NMOS current mirror shown in Fig. 7 shows the inherent delay between current in and current out is proportional to the Cgs /g m. The transfer function of current-in, to currentout is:
Io (s) g m2 1 = Ii( s ) g m1 1 + s(C gs1 + C gs2 ) / g m1

From the single-pole transfer function, we see there is a time constant = (C gs1 + C gs2) / gm1 between input and output currents. We know a single-pole transfer function will have a step response that rises as: Fig. 5: Voltage switched current source (VSCS) Basic circuit elements: Each current mode chip consists of four basic blocks [1]. Current Comparators (CC), Current Mirror (CM), Current Source (CS) and Voltage Switched Current Sources (VSCS). These four building blocks implement four linear functions necessary to make large functional blocks. Input and output value in CMMVL have to be integer multiples of the unit step current. However, internal values of the signal levels inside functional blocks can take any value. Constant function: Figure 4 implements the constant function [1]: I=Iconst .,(Iconst .>=0). Logic levels represent constant in CMMVL. They can be generated by P-type or N-type transistors, depending on the current sourcing or sinking. Voltage Switched Current Source (VSCS): VSCS implements current source in which the output current is determined by a logic function implemented in the switching logic block Fig. 5 [1]. Current mirror: Current mirror circuits are widely used in MVL circuits. Beside their conventional job of copying a specified current they are needed to convert source to sink currents or sink to source currents. For 144
o (t)

g t / = m2 ii (1 e ) g m1

We can define a propagation delay for this circuit as the time it takes for the output to rise to half of its final value.
Cgs1 + C gs2 t p = 0.69 = 0.69 gm1

It appears that we can decrease propagation delay by increasing current levels (increases gm), but larger current levels require larger devices and more parasitic capacitance. It is shown below that we can reduce delay by increasing current levels. Analysis for PMOS current mirror is identical. CML circuits often have poor noise margins because of threshold variation and other effects. Since the current threshold variations in V t will significantly alter the currents. We also have geometry mismatch and current mismatch due to channel length modulation in current mirrors. These three different effects combined are expressed in the following equation:
i I W / L 2Vt = + + Vds I W/L V gs Vt

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Fig. 9: CMOS current source Fig. 6: Double cascade current mirror

Fig. 7: NMOS current source Fig. 10: Current source

Fig. 8: Current comparator with a)Current output b)Voltage output c)CC symbol Short channel devices further worsen mirror accuracy, since channel length modulation factor) is inversely proportional to L [13]. Current comparator: Current Comparator, implements the step function where the output value "y" can be either voltage or current signal and "1" represent preset unit value of the output (Fig. 8). It compares two current and generates a voltage output or a current output [1]. 145

Fig. 11: Simplified current source Current threshold detector is key component in CMMVL circuits [28]. The discrimination between different logic-level current is implemented on the threshold detector. The power dissipation of any MVCM logic circuits primarily depends on that of threshold detectors.

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Circuit Implementation Issue: Here, we will consider the actual implementation of current sources and threshold detectors. Current source: The basic operators are the current sources, which deliver a given level of current. In [12], depleted PMOS transistors are used to implement the current sources. With depleted MOS transistors, truth current sources, that only depends on the threshold
2 voltages can be obtained by Ip = 1 2 PC ox Wp L V tp ,
p

when connecting the transistor gate and source. But depleted PMOS transistors are not available with a standard CMOS technology [5]. A current source can be designed by an enhancement-mode NMOS (or PMOS) transistor with the reference voltage V m (or V rp). The typical current source has been shown in Fig. 9, [16]. The current source value is determined by the diode-connected T1 PMOS and NMOS transistors. T4 is connected by the input C. When it is on, 'I' is mirrored by T1 and T3. It is presented again in Fig. 10 with different transistor sizes. Another one can be defined as follows: It simply uses a PMOS transistor, assuming that it is working in saturated mode when a low level voltage input is applied on its gate (Fig. 9). Figure 11 illustrates a simplified current source [5]. Applying different W/L ratio we can simply generate different current levels. Threshold detector: We have first implemented the threshold detector according to the scheme presented in Fig. 12 [16]. It has 5 transistors. The threshold detector compares a copy of the input current Iin (through T1T2) with reference current that is obtained by using (T3-T4) current mirror. In this paper we present the threshold detector, which is shown in Fig. 13. The threshold function is simply implemented by CMOS inverter, which the NMOS transistor (mn11) forms a current mirror with the transistor that sinks the input current (mn1). The size of CMOS inverter strongly depends on threshold value and the voltage on n1. The output voltage of the "inverter" controls the PMOS transistor which acts as a current source which has the constant current equal to, two times the unit reference current. We consider two versions: The version 1 has 20A current level. The version 2 has 10A current level. Constant: Logic levels in CMMVL can be generated with current sources using either enhancement mode Ptype or N -type transistors, depending on the current sourcing or sinking. In ideal case, the saturation value 146

Fig. 12: Threshold detector circuit

Fig. 13: CMOS Threshold detector circuit of the drain current I d used as a constant current is written as:
Id = K(W/L)(VT )2

K, W, L and V T are the transcoductance parameter, the channel width, the channel length and the threshold voltage of the p-channel depletion-mode MOSFET, respectively. The unit current can be set at the specified value using dose control. This type of current source is quite insensitive to the fluctuation of the supply voltage VDD and requires no bias source or connection other than VDD [12]. Ne w six transistors current mode adder: In this section, the design of the new current mode adder and

World Appl. Sci. J., 4 (1): 142-149, 2008

its performance is described. The new full adder circuit consists of two sections. One is a new 4-BC cell and the other is a PMOS transistor like carry circuit. The new 4-BC cell is shown in Fig. 14. It has 5 current sources, a CMOS inverter as threshold detector (mn2, mp2), one current mirror (mn1, mn3) and 2 PMOS transistors (mp3, mpc). These current sources deliver the constant function. According to the truth table, the carry output must be 0 or 1, this means that the PMOS transistor (mpc) should have 0A or 20A; for this purpose we need a current source (Iconst2). We know that the current, which flows in transistor, strongly depends on the transistor sizing and the voltage on its gate. So, this current source is eliminated by setting the transistor sizing to deliver reference current, when its gate is low. First, the threshold value is determined. The 1.5 logic is selected for this purpose. For exa mple, if the current of logical 1 equals to 20A then logical 1.5 would be 30A. The input transistor, (mn1), takes the sum of input currents. The input transistor, (mn1), acts as a resistor, it takes input currents and add them. This current flows i n drain and passes through the resistor and as a result, generates an specific voltage, (Vn1), on its gate. Setting the dimensions of this transistor is very important. This voltage pulse, (Vn1), acts as an input voltage for CMOS inverter. We should set the transistor sizing that it can act as a threshold detector with 1.5 logic threshold value. Whenever the algebraic addition of inputs exceeds 1.5 logic it goes from high to low, which activates the PMOS transistors, (mpc, m p3) and as a result Iconst3 and Iconst2 flows in mp3 and mpc, respectively. At the same time mn3 delivers Iconst4 (it must be equal to Iconst1 ) and as a result, the algebraic sum of logic level is obtained from the discrimination between these currents. Iconst2 represents the logic level for carry function. Transistor mpc delivers one unit current reference. Its dimensions are equal to input transistor's dimensions. Iconst3 , delivers two unit current reference and Iconst4 delivers a current equal to input current. The discrimination between these logic-level current, represent the logic level current for SUM. Instead of using these current references, (Iconst3, Iconst4 ), we adjusted the PMOS(mp11) and NMOS (mn11) transistor sizing, to fix the current which delivered. Transistor mp11 has delivers 40A. The size of mn11 must be equal to mn1 transistor sizing, in order to deliver a copy of input current in the output. Therefore eliminating extra current sources and hence decrease the number of transistors. 147

Fig. 14: New 4-BC cell

Fig. 15: A 6 transistors full adder Proposed 4 -BC cell: In this section we introduce a unique design style for new 4 -BC cell. It is shown in Fig. 15. It uses only 6 transistors. This 4-BC cell consists of a single PMOS transistor as current source (mp3), a CMOS inverter as detector (mn2, mp2) and one current mirror (mn1, mn3). This cell has 1 mirror as the input stage to read the input current Iin (mn1) and generate one copy that goes into output current mirror (mn3). Four possible outputs can result from that action: a) If I<Ithreshold ; [(Iin = 0,20A)], the output voltage, Vout , will be high; mpc, mp3 will be off and resulting in the output signal, C=0.

While this time, the input current mirrored by mn3 and it will have one unit current and sum can be zero or 1 respectively for 0A or 20A current input.

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b) If I>Ithreshold ; [(Iin = 40A, 60A)], the output voltage, V out , will be low and PMOS transistors (mpc, mp11) will be on, it results mpc have one unit current (20A) and results C=1. Also the input current will be mirrored by (mn3) and will be subtracted by two unit reference current that is generated by mp3, two possible outcomes can result from that action: c) If AIin = 60A( 3Iref ) , then Sum=1.

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d) If Iin = 40 A( 2Iref ) , then Sum=0. CONCLUSION We have presented two versions of current mode 1-bit adder. Their related propagation delays are 70ps, 150ps respectively. These adders use only 6 transistors. The chip density advantage of the multi-valued approach is significant. We have performed simulations using HSPICE in a 0.18m technology at 27 centigrade; with 1.8 volt supply voltage. The simulation results demonstrate that we have achieved a significant improvement in terms of transis tor count, chip area and propagation delay. The minimum number of transistors reported in current mode was 11 and it is 10 in voltage mode. That is we have achieved 40% performance in terms of transistor count and the improvement in speed is about 2.5%. This design is roughly two times faster than the other current mode adders. In comparison to the conventional 28 transistor adder we have more than 4.5 times reduction in terms of transistor count and more than 20% improvement in speed. REFERENCES 1. Radanovic, B., Mark Syrzycki, 1996. "Current Mode COMS Adders Using Multiple-Valued Logic", IEEE, pp: 190-193. Temel, T., and A. Morgul, 2004. "Implementation of Multi-Valued Logic Gates Using Full Current Mode CMOS Circuits", Analog Integrated Circuits and Signal Processing , KAP., 39(2):191-204. Temel, T., 2002. "Current-mode CMOS Design of Multi-valued Logic Circuits", Ph.D. Thesis, Bogazici University, Dep. of Electrical and Electronics Engineering. Mourgl, A. and T. Turgay, 2004. "A New Level Restortion Circuit for Multi-valued Logic", Proc. of IEEE ISCAS'04, Vancover, CA, pp: 649-652 . 148

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