HIP4080A

Data Sheet July 2004 FN3658.7

80V/2.5A Peak, High Frequency Full Bridge FET Driver

The HIP4080A is a high frequency, medium voltage Full Bridge N-Channel FET driver IC, available in 20 lead plastic SOIC and DIP packages. The HIP4080A includes an input comparator, used to facilitate the hysteresis and PWM modes of operation. Its HEN (high enable) lead can force current to freewheel in the bottom two external power MOSFETs, maintaining the upper power MOSFETs off. Since it can switch at frequencies up to 1MHz, the HIP4080A is well suited for driving Voice Coil Motors, switching power amplifiers and power supplies. HIP4080A can also drive medium voltage brush motors, and two HIP4080As can be used to drive high performance stepper motors, since the short minimum on-time can provide fine micro-stepping capability. Short propagation delays of approximately 55ns maximize control loop crossover frequencies and dead-times which can be adjusted to near zero to minimize distortion, resulting in precise control of the driven load. The similar HIP4081A IC allows independent control of all 4 FETs in a Full Bridge configuration. The Application Note for the HIP4080A is AN9404.

Features
Drives N-Channel FET Full Bridge Including High Side Chop Capability Bootstrap Supply Max Voltage to 95VDC Drives 1000pF Load at 1MHz in Free Air at +50C with Rise and Fall Times of Typically 10ns User-Programmable Dead Time Charge-Pump and Bootstrap Maintain Upper Bias Supplies DIS (Disable) Pin Pulls Gates Low Input Logic Thresholds Compatible with 5V to 15V Logic Levels Very Low Power Consumption Undervoltage Protection Pb-Free Available as an Option

Applications
Medium/Large Voice Coil Motors Full Bridge Power Supplies Switching Power Amplifiers High Performance Motor Controls Noise Cancellation Systems

Ordering Information
PART NUMBER HIP4080AIPZ (Note 1) HIP4080AIP HIP4080AIB HIP4080AIBZ (Note 1) NOTES: 1. Intersil Pb-Free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-Free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. 2. Add T suffix for Tape and Reel packing option. HIP4080AIP not available in Tape and Reel. TEMPERATURE RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE 20 Ld PDIP (Pb-Free) 20 Ld PDIP 20 Ld SOIC 20 Ld SOIC (Pb-Free) PKG. DWG. # E20.3 E20.3 M20.3 M20.3

Battery Powered Vehicles Peripherals U.P.S.

Pinout
HIP4080A (PDIP, SOIC) TOP VIEW
BHB HEN DIS VSS OUT IN+ INHDEL LDEL 1 2 3 4 5 6 7 8 9 20 BHO 19 BHS 18 BLO 17 BLS 16 VDD 15 VCC 14 ALS 13 ALO 12 AHS 11 AHO

AHB 10

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Harris Corporation 1995, Copyright Intersil Americas Inc. 2003, 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

HIP4080A Application Block Diagram

80V

12V

BHO BHS HEN DIS HIP4080A IN+ INALO AHS AHO BLO LOAD

GND

GND

Functional Block Diagram

(1/2 HIP4080A)
AHB 10 HIGH VOLTAGE BUS 80VDC

UNDERVOLTAGE VDD 16 HEN 2

CHARGE PUMP

LEVEL SHIFT AND LATCH

DRIVER 11

AHO AHS

CBS

12 TURN-ON DELAY DBS TO VDD (PIN 16)

DIS

3 15

VCC

OUT IN+ IN_ HDEL LDEL

5 6 7 8 9 + TURN-ON DELAY

DRIVER 13

ALO CBF

+12VDC BIAS SUPPLY

ALS 14

VSS 4

HIP4080A Typical Application (Hysteresis Mode Switching)

80V

1 BHB 12V DIS 2 HEN HIP4080A/HIP4080 3 DIS 4 VSS 5 OUT 6V IN 6 IN+ 7 IN8 HDEL 9 LDEL 10 AHB

BHO 20 BHS 19 BLO 18 BLS 17 VDD 16 VCC 15 ALS 14 ALO 13 AHS 12 AHO 11 12V

LOAD

GND

+ 6V

GND

HIP4080A
Absolute Maximum Ratings
Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . . . -0.3V to 16V Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on AHS, BHS . . . -6.0V (Transient) to 80V (25C to 125C) Voltage on AHS, BHS . . . -6.0V (Transient) to 70V (-55C to 125C) Voltage on ALS, BLS . . . . . . . -2.0V (Transient) to +2.0V (Transient) Voltage on AHB, BHB . . . . . . VAHS, BHS -0.3V to VAHS, BHS +VDD Voltage on ALO, BLO. . . . . . . . . . . . .VALS, BLS -0.3V to VCC +0.3V Voltage on AHO, BHO . . . . . . VAHS, BHS -0.3V to VAHB, BHB +0.3V Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . . . -5mA to 0mA Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns All Voltages relative to VSS, unless otherwise specified.

Thermal Information
Thermal Resistance (Typical, Note 3) JA (C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Maximum Power Dissipation at +85C SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .470mW PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .530mW Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Operating Max. Junction Temperature. . . . . . . . . . . . . . . . . . +125C Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300C (For SOIC - Lead Tips Only)

Operating Conditions
Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . +9.5V to +15V Voltage on ALS, BLS . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V Voltage on AHB, BHB . . . . . . . .VAHS, BHS +5V to VAHS, BHS +15V Input Current, HDEL and LDEL . . . . . . . . . . . . . . . .-500A to -50A Operating Ambient Temperature Range . . . . . . . . . .-40C to +85C
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE: 3. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

Electrical Specifications

VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K, and TA = +25C, Unless Otherwise Specified TJ = +25C TJ = - 40C TO +125C MIN MAX UNITS

PARAMETERS

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

SUPPLY CURRENTS AND CHARGE PUMPS VDD Quiescent Current VDD Operating Current VCC Quiescent Current VCC Operating Current AHB, BHB Quiescent Current Qpump Output Current AHB, BHB Operating Current AHS, BHS, AHB, BHB Leakage Current AHB-AHS, BHB-BHS Qpump Output Voltage IDD IDDO ICC ICCO IAHB, IBHB IN- = 2.5V, Other Inputs = 0V Outputs switching f = 500kHz, No Load IN- = 2.5V, Other Inputs = 0V, IALO = IBLO = 0 f = 500kHz, No Load IN- = 2.5V, Other Inputs = 0V, IAHO = IBHO = 0, VDD = VCC =VAHB = VBHB = 10V f = 500kHz, No Load VBHS = VAHS = 80V, VAHB = VBHB = 93V IAHB = IAHB = 0, No Load 8 9 1 -50 11 12 25 1.25 -25 14 15 80 2.0 -11 7 8 0.8 -60 14 15 100 3 -10 mA mA A mA A

IAHBO, IBHBO IHLK VAHB VAHS VBHB VBHS

0.62 11.5

1.2 0.02 12.6

1.5 1.0 14.0

0.5 10.5

1.9 10 14.5

mA A V

INPUT COMPARATOR PINS: IN+, IN-, OUT Offset Voltage Input Bias Current Input Offset Current Input Common Mode Voltage Range VOS IIB IOS CMVR Over Common Mode Voltage Range -10 0 -1 1 0 0.5 0 +10 2 +1 VDD -1.5 -15 0 -2 1 +15 4 +2 VDD -1.5 mV A A V

HIP4080A
Electrical Specifications
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K, and TA = +25C, Unless Otherwise Specified (Continued) TJ = +25C PARAMETERS Voltage Gain OUT High Level Output Voltage OUT Low Level Output Voltage Low Level Output Current High Level Output Current INPUT PINS: DIS Low Level Input Voltage High Level Input Voltage Input Voltage Hysteresis Low Level Input Current High Level Input Current INPUT PINS: HEN Low Level Input Voltage High Level Input Voltage Input Voltage Hysteresis Low Level Input Current High Level Input Current TURN-ON DELAY PINS: LDEL AND HDEL LDEL, HDEL Voltage VHDEL,V IHDEL = ILDEL = -100A 4.9 5.1 5.3 4.8 5.4 V IIL IIH VIN = 0V, Full Operating Conditions VIN = 5V, Full Operating Conditions VIL VIH Full Operating Conditions Full Operating Conditions 2.5 -260 -1 35 -200 1.0 -150 +1 2.7 -270 -10 0.8 -130 +10 V V mV A A IIL IIH VIN = 0V, Full Operating Conditions VIN = 5V, Full Operating Conditions VIL VIH Full Operating Conditions Full Operating Conditions 2.5 -130 -1 35 -100 1.0 -75 +1 2.7 -135 -10 0.8 -65 +10 V V mV A A SYMBOL AVOL VOH VOL IOL IOH IN+ > IN-, IOH = -250A IN+ < IN-, IOL = +250A VOUT = 6V VOUT = 6V TEST CONDITIONS MIN 10 VDD -0.4 6.5 -17 TYP 25 14 -10 MAX 0.4 19 -3 TJ = - 40C TO +125C MIN 10 VDD - 0.5 6 -20 MAX 0.5 20 -2.5 UNITS V/mV V V mA mA

GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO Low Level Output Voltage High Level Output Voltage Peak Pullup Current Peak Pulldown Current Under Voltage, Rising Threshold Under Voltage, Falling Threshold Under Voltage, Hysteresis VOL VCC - VOH IO+ IOUV+ UVHYS IOUT = 100mA IOUT = -100mA VOUT = 0V VOUT = 12V 0.7 0.8 1.7 1.7 8.1 7.6 0.25 0.85 0.95 2.6 2.4 8.8 8.3 0.4 1.0 1.1 3.8 3.3 9.4 8.9 0.65 0.5 0.5 1.4 1.3 8.0 7.5 0.2 1.1 1.2 4.1 3.6 9.5 9.0 0.7 V V A A V V V

HIP4080A
Switching Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K,
CL = 1000pF, and TA = +25C, Unless Otherwise Specified TJ = +25C PARAMETERS Lower Turn-off Propagation Delay (IN+/IN- to ALO/BLO) Upper Turn-off Propagation Delay (IN+/IN- to AHO/BHO) Lower Turn-on Propagation Delay (IN+/IN- to ALO/BLO) Upper Turn-on Propagation Delay (IN+/IN- to AHO/BHO) Rise Time Fall Time Turn-on Input Pulse Width Turn-off Input Pulse Width Disable Turn-off Propagation Delay (DIS - Lower Outputs) Disable Turn-off Propagation Delay (DIS - Upper Outputs) Disable to Lower Turn-on Propagation Delay (DIS - ALO and BLO) Refresh Pulse Width (ALO and BLO) Disable to Upper Enable (DIS - AHO and BHO) HEN-AHO, BHO Turn-off, Propagation Delay HEN-AHO, BHO Turn-on, Propagation Delay SYMBOL TLPHL THPHL TLPLH THPLH TR TF TPWIN-ON TPWIN-OFF TDISLOW TDISHIGH TDLPLH TREF-PW TUEN THEN-PHL THEN-PLH RHDEL = RLDEL = 10K RHDEL = RLDEL = 10K TEST CONDITIONS MIN 50 40 240 TYP 40 50 40 70 10 10 45 55 45 380 480 40 60 MAX 70 80 70 110 25 25 75 85 70 500 630 70 90 TJ = - 40C TO +125C MIN 50 40 200 MAX UNITS 90 110 90 140 35 35 95 105 90 600 750 90 110 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

TRUTH TABLE INPUT IN+ > INX 0 1 0 1 X HEN X 0 1 1 0 X U/V X 0 0 0 0 1 DIS 1 0 0 0 0 X ALO 0 1 0 1 0 0 AHO 0 0 1 0 0 0 OUTPUT BLO 0 0 1 0 1 0 BHO 0 0 0 1 0 0

HIP4080A Pin Descriptions

PIN NUMBER 1 SYMBOL BHB DESCRIPTION B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30A out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V. High-side Enable input. Logic level input that when low overrides IN+/IN- (Pins 6 and 7) to put AHO and BHO drivers (Pins 11 and 20) in low output state. When HEN is high AHO and BHO are controlled by IN+/IN- inputs. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs. When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). Chip negative supply, generally will be ground. OUTput of the input control comparator. This output can be used for feedback and hysteresis. Noninverting input of control comparator. If IN+ is greater than IN- (Pin 7) then ALO and BHO are low level outputs and BLO and AHO are high level outputs. If IN+ is less than IN- then ALO and BHO are high level outputs and BLO and AHO are low level outputs. DIS (Pin 3) high level will override IN+/IN- control for all outputs. HEN (Pin 2) low level will override IN+/IN- control of AHO and BHO. When switching in four quadrant mode, dead time in a half bridge leg is controlled by HDEL and LDEL (Pins 8 and 9). Inverting input of control comparator. See IN+ (Pin 6) description. High-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V. Low-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V. A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30A out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V. A High-side Output. Connect to gate of A High-side power MOSFET. A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. A Low-side Output. Connect to gate of A Low-side power MOSFET. A Low-side Source connection. Connect to source of A Low-side power MOSFET. Positive supply to gate drivers. Must be same potential as VDD (Pin 16). Connect to anodes of two bootstrap diodes. Positive supply to lower gate drivers. Must be same potential as VCC (Pin 15). De-couple this pin to VSS (Pin 4). B Low-side Source connection. Connect to source of B Low-side power MOSFET. B Low-side Output. Connect to gate of B Low-side power MOSFET. B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. B High-side Output. Connect to gate of B High-side power MOSFET.

HEN

DIS

4 5 6

VSS OUT IN+

7 8

INHDEL

LDEL

10

AHB

11 12 13 14 15 16 17 18 19 20

AHO AHS ALO ALS VCC VDD BLS BLO BHS BHO

HIP4080A Timing Diagrams

THPHL U/V = DIS 0 HEN 1 IN+ > INALO AHO BLO BHO TLPHL THPLH TDT TR TF (10% - 90%) (90% - 10%) TDT TLPLH

FIGURE 1. BISTATE MODE

THEN-PHL U/V = DIS 0 HEN IN+ > INALO AHO BLO BHO

THEN-PLH

FIGURE 2. HIGH SIDE CHOP MODE

TDLPLH TREF-PW U/V or DIS HEN IN+ > INALO AHO BLO BHO TUEN

TDIS

FIGURE 3. DISABLE FUNCTION

HIP4080A Typical Performance Curves

14.0 12.5 IDD SUPPLY CURRENT (mA) 12.0 10.0 8.0 6.0 4.0 2.0 8 10 12 14 VDD SUPPLY VOLTAGE (V) IDD SUPPLY CURRENT (mA)

VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K, and TA = +25C, Unless Otherwise Specified
13

12.0

11.5

11.0

10.5

10

200 400 600 800 SWITCHING FREQUENCY (kHz)

1000

FIGURE 4. QUIESCENT IDD SUPPLY CURRENT vs VDD SUPPLY VOLTAGE

FIGURE 5. IDDO NO-LOAD IDD SUPPLY CURRENT vs FREQUENCY (kHz)

5.0

FLOATING SUPPLY BIAS CURRENT (mA)

+125C 20.0 ICC SUPPLY CURRENT (mA) 4.0 +75C +25C 3.0 0C -40C 2.0

15.0

10.0

5.0

1.0

0.0 0 100 200 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz)

0.0 0 100 200 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz)

FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs FREQUENCY (LOAD = 1000pF)

2.5

FIGURE 7. ICCO, NO-LOAD ICC SUPPLY CURRENT vs FREQUENCY (kHz) TEMPERATURE

FLOATING SUPPLY BIAS CURRENT (mA)

COMPARATOR INPUT CURRENT (A)

1.0

1.5

0.5

0.5

200

400 600 800 SWITCHING FREQUENCY (kHz)

1000

-40

-20

20

40

60

80

100

120

JUNCTION TEMPERATURE (C)

FIGURE 8. IAHB, IBHB NO-LOAD FLOATING SUPPLY BIAS CURRENT vs FREQUENCY

FIGURE 9. COMPARATOR INPUT CURRENT IL vs TEMPERATURE AT VCM = 5V

HIP4080A Typical Performance Curves

-90 LOW LEVEL INPUT CURRENT (A) LOW LEVEL INPUT CURRENT (A) -25 0 25 50 75 100 125

VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K, and TA = +25C, Unless Otherwise Specified (Continued)
-180

-190

-100

-200

-210

-110

-220

-120 -50

-230 -40

-20

20

40

60

80

100

120

JUNCTION TEMPERATURE (C)

JUNCTION TEMPERATURE (C)

FIGURE 10. DIS LOW LEVEL INPUT CURRENT IIL vs TEMPERATURE

NO-LOAD FLOATING CHARGE PUMP VOLTAGE (V) 15.0

FIGURE 11. HEN LOW LEVEL INPUT CURRENT IIL vs TEMPERATURE

80

14.0

PROPAGATION DELAY (ns)

70

13.0

60

12.0

50

11.0

40

10.0 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (C)

30 -40 -20 0 20 40 60 80 100 120

JUNCTION TEMPERATURE (C)

FIGURE 12. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP VOLTAGE vs TEMPERATURE
525

FIGURE 13. UPPER DISABLE TURN-OFF PROPAGATION DELAY TDISHIGH vs TEMPERATURE

80

PROPAGATION DELAY (ns)

500

PROPAGATION DELAY (ns) -25 0 25 50 75 100 125 150

70

60

475

50

450

40

425 -50

30 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (C) JUNCTION TEMPERATURE (C)

FIGURE 14. DISABLE TO UPPER ENABLE TUEN PROPAGATION DELAY vs TEMPERATURE

FIGURE 15. LOWER DISABLE TURN-OFF PROPAGATION DELAY TDISLOW vs TEMPERATURE

10

HIP4080A Typical Performance Curves

450

VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K, and TA = +25C, Unless Otherwise Specified
80 70

REFRESH PULSE WIDTH (ns)

425

PROPAGATION DELAY (ns) -25 0 25 50 75 100 125 150

60 50 40 30

400

375

350 -50

20 -40

-20

20

40

60

80

100

120

JUNCTION TEMPERATURE (C)

JUNCTION TEMPERATURE (C)

FIGURE 16. TREF-PW REFRESH PULSE WIDTH vs TEMPERATURE

FIGURE 17. DISABLE TO LOWER ENABLE TDLPLH PROPAGATION DELAY vs TEMPERATURE

90.0 PROPAGATION DELAY (ns) PROPAGATION DELAY (ns)

90.0

80.0

80.0

70.0

70.0

60.0

60.0

50.0

50.0

40.0 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (C) 120

40.0 -40 -20 0 20 40 60 80 100 120

JUNCTION TEMPERATURE (C)

FIGURE 18. UPPER TURN-OFF PROPAGATION DELAY THPHL vs TEMPERATURE

FIGURE 19. UPPER TURN-ON PROPAGATION DELAY THPLH vs TEMPERATURE

90.0 PROPAGATION DELAY (ns) PROPAGATION DELAY (ns)

90.0

80.0

80.0

70.0

70.0

60.0

60.0

50.0

50.0

40.0 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (C) 120

40.0 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (C) 120

FIGURE 20. LOWER TURN-OFF PROPAGATION DELAY TLPHL vs TEMPERATURE

FIGURE 21. LOWER TURN-ON PROPAGATION DELAY TLPLH vs TEMPERATURE

11

HIP4080A Typical Performance Curves

13.5

VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K, and TA = +25C, Unless Otherwise Specified
13.5

GATE DRIVE FALL TIME (ns)

12.5 TURN-ON RISE TIME (ns) -20 0 20 40 60 80 100 120

12.5

11.5

11.5

10.5

10.5

9.5

9.5

8.5 -40 JUNCTION TEMPERATURE (C)

8.5 -40

-20

20

40

60

80

100

120

JUNCTION TEMPERATURE (C)

FIGURE 22. GATE DRIVE FALL TIME TF vs TEMPERATURE

6.0 HDEL, LDEL INPUT VOLTAGE (V)

FIGURE 23. GATE DRIVE RISE TIME TR vs TEMPERATURE

1500

1250 5.5 VCC - VOH (mV) 1000

5.0

750 -40C 500 0C +25C 250 +75C +125C 12 BIAS SUPPLY VOLTAGE (V) 14

4.5

4.0 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (C)

0 10

FIGURE 24. VLDEL, VHDEL VOLTAGE vs TEMPERATURE

FIGURE 25. HIGH LEVEL OUTPUT VOLTAGE, VCC - VOH vs BIAS SUPPLY AND TEMPERATURE AT 100A

1500 1250 GATE DRIVE SINK CURRENT (A)

3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 12 BIAS SUPPLY VOLTAGE (V) 14

1000 VOL (mV)

750 -40C 500 0C +25C +75C +125C 10

250

10

11

12

13

14

15

16

VCC, VDD, VAHG, VBHB (V)

FIGURE 26. LOW LEVEL OUTPUT VOLTAGE VOL vs BIAS SUPPLY AND TEMPERATURE AT 100A

FIGURE 27. PEAK PULLDOWN CURRENT IO- BIAS SUPPLY VOLTAGE

12

HIP4080A Typical Performance Curves

3.5 GATE DRIVE SINK CURRENT (A) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 LOW VOLTAGE BIAS CURRENT (mA)

VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K, and TA = +25C, Unless Otherwise Specified (Continued)
500 200 100 50 20 10 5 2 1 0.5 0.2 0.1 1 2 5 10 20 50 100 200 500 1000 10,000 3,000 1,000 100

10

11

12

13

14

15

16

VCC, VDD, VABH, VBHB (V)

SWITCHING FREQUENCY (kHz)

FIGURE 28. PEAK PULLUP CURRENT IO+ vs SUPPLY VOLTAGE

FIGURE 29. LOW VOLTAGE BIAS CURRENT IDD AND ICC (LESS QUIESCENT COMPONENT) vs FREQUENCY AND GATE LOAD CAPACITANCE

1000 500 LEVEL-SHIFT CURRENT (A) BIAS SUPPLY VOLTAGE, VDD (V)

9 UV+ 8.8

200 100 50

8.6

UV8.4

20 10 10 20 50 100 200 500 1000 SWITCHING FREQUENCY (kHz)

8.2 50 25 0 25 50 75 100 125 150 TEMPERATURE (C)

FIGURE 30. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs FREQUENCY AND BUS VOLTAGE
150

FIGURE 31. UNDERVOLTAGE LOCKOUT vs TEMPERATURE

120 DEAD-TIME (ns)

90

60

30

10

50

100 150 200 HDEL/LDEL RESISTANCE (k)

250

FIGURE 32. MINIMUM DEAD-TIME vs DEL RESISTANCE

13

IN2 IN1

+12V

POWER SECTION B+ 2 JMPR5

14
CONTROL LOGIC SECTION R29 + C6 DRIVER SECTION R21 CR2 R22 1 Q1 3 C4 1 Q3 2 C8 1 U2 CD4069UB 13 U2 CD4069UB 5 U2 CD4069UB 11 U2 CD4069UB 10 JMPR4 IN-/AHI 6 JMPR3 HEN/BHI R33 3 2 CW 1 2 CW 1 R34 3 12 JMPR2 IN+/ALI 2 JMPR1 OUT/BLI HIP4080A/81A U1 1 BHB BHO 20 2 HEN/BHI BHS 19 3 DIS BLO 18 4 V SS 5 OUT/BLI BLS 17 16 V
DD

3 L1 +12V 2 R23 1 Q2 3 2 R24 1 Q4 C1 L2 C2 AO BO

HIP4080A

9 LDEL 10 AHB

6 IN+/ALI V 15 CC 7 IN-/AHI ALS 14 8 HDEL ALO 13 AHS AHO CR1 C3 C5 ALS BLS 12 11

CX

CY

R30

R31 COM

NOTES: 1. DEVICE CD4069UB PIN 7 = COM. PIN 14 = +12V. 2. COMPONENTS L1, L2, C1, C2, CX, CY, R30, R31, ARE NOT SUPPLIED. REFER TO APPLICATION NOTE FOR HELP IN DETERMINING JMPR1 - JMPR4 JUMPER LOCATIONS.

FIGURE 33. HIP4080A EVALUATION PC BOARD SCHEMATIC

JMPR5

R29

R27

R28

R26

C7

C8 C6 + U1 HIP4080/81 CR2 Q1 C4 BHO BLO BLS Q2 1 R21 Q4 1 R22 R24 L1 1 Q3 1

C1

R32

IN1 I O IN2
JMPR1 JMPR2 JMPR3 JMPR4

L2

U2

DIS

C2

HDEL

CX

CR1 R33 R34

R30

CY

ALS

C5

BLS

FIGURE 33. HIP4080A EVALUATION BOARD SILKSCREEN

R31

15

GND

+12V

B+

COM

AO

BO

HIP4080A

ALS ALO AHO C3

R23

LDEL

HIP4080A Dual-In-Line Plastic Packages (PDIP)

N E1 INDEX AREA 1 2 3 N/2

E20.3 (JEDEC MS-001-AD ISSUE D)

20 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-

MILLIMETERS MIN 0.39 2.93 0.356 1.55 0.204 24.89 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 26.9 8.25 7.11 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93

MIN 0.015 0.115 0.014 0.045 0.008 0.980 0.005 0.300 0.240

MAX 0.210 0.195 0.022 0.070 0.014 1.060 0.325 0.280

-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E

A A1 A2 B B1 C D D1 E E1

-C-

eA eC
C

C A B S

eB

NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

e eA eB L N

0.100 BSC 0.300 BSC 0.115 20 0.430 0.150 -

2.54 BSC 7.62 BSC 10.92 3.81 20

2.93

16

HIP4080A Small Outline Plastic Packages (SOIC)

N INDEX AREA E -B1 2 3 H 0.25(0.010) M B M

M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A A1 B MIN 0.0926 0.0040 0.014 0.0091 0.4961 0.2914 MAX 0.1043 0.0118 0.019 0.0125 0.5118 0.2992 MILLIMETERS MIN 2.35 0.10 0.35 0.23 12.60 7.40 MAX 2.65 0.30 0.49 0.32 13.00 7.60 NOTES 9 3 4 5 6 7 8o Rev. 1 1/02

L SEATING PLANE

C D
h x 45o

-A-

D -C-

E e

0.050 BSC 0.394 0.010 0.016 20 0o 8o 0.419 0.029 0.050

1.27 BSC 10.00 0.25 0.40 20 0o 10.65 0.75 1.27

A1 0.10(0.004) C

H h L N

e
B 0.25(0.010) M C A M B S

NOTES: 1. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

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