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A 500 MHz GaAs Digital RF'Memory Modulator IC

Gary McMilliari, William Hallidy, Marty Hood, George Phan, Tan Chu, IGm Lau, Mike Lawrence, Bryan Thrailkill, Jimmy Phan, Andy Lee, Clark Musgrove, Mike Sanders, AI Morgan, Gary Schmidt, Gary Zreet
Systems & Processes Engineering Corporation (SPEC) 401 Camp Craft Road, Austin, TX 78746-6558 USA Phone 512-306-1 100, Fax 512-306-1 122, http://www.spec.com

Abstract - A single chip Digital Radio Frequency Memory (DRFM) Modulator provides time delay, Doppler shifting, ;and phaselamplitude modulation of RF signals. The digital IC lhas been implemented in Vitesse Semiconductor's H-GaAs III technology for operation up to 500 MHz, and was designed with COMPASS Design* Automation's CAE tools and SPEC'S standard cell libraries.

WIN

RF Frontend (Downconverter)

INTRODUCTION Digital RF Memories (DRFMs) are used to provide time delay of RF signals. DRFMs have been integrated into electronic countermeasures systems to spoof enemy radar systems, in radar simulators to synthesize a real-time targetclutter environment, and to simulate satellite or mobile communications networks.[ 1-31 A typical DRFM (see Fig. 1) consists of an RF frontend which downconverts an RF signal to a lower intermediate frequency (IF), an analog-to-digital converter (ADC) which samples the IF waveform, a memory to store the digitized waveform for a programmable time delay, modulators to apply i i Doppler shift and phase/amplitude scaling, a digital-toiinalog converter (DAC) to reconstruct the intermediate frequency waveform, and an RF backend to upconvert the IF i o the original RF carrier frequency. The RF frontend and backend is constructed of MMICs operating at microwave to millimeterwave frequencies. The IF is chosen to fit within the capabilities of available ADCs and IDACs used for sampling and reconstruction of the IF waveform. Narrowband DRFMs employ high resolution ADCs and DACs, while wideband DRFMs utilize high performance 6- to 8-bit ADCs operating in the GHz range. 'Wideband, high fidelity DRFMs operating with IFS in the 100 MHz to 500 MHz range with 12-bits of accuracy are desired for use in radar and communication system simulators and electronic countermeasure systerns, but are currently limited by the state-of-the-art in ADC technology. SPEC has developed a highly integrated DRFM chip which implements the two functions outlined in bold in IFig. 1, and operates up to 500 MHz at 12-bits of accuracy. 'The IC imparts a programmable tirne delay on the R F waveform using a large external memory and a small internal memory, and uses digital signal processing techniques to iipply a Doppler shift and phase and arnplitude modulation to {he RF waveform. The outputs from multiple DRFM IModulators can be digitally summed together to form a complete target/clutter signal environment.

IF
ADCs VQ Memory (Time Delay)

l+

Modulator (Doppler + Phase/Amplitude)

IF RF Backend (Upconverter)

I
Digital Clock

Local Oscillator
Fig. 1 . Digital RF Memory

This work was supported by the U S . Air Force Wright Laboratory under contract number F33615-93-C-1290 and the US. Army Missile Command under contract number DAAHOl-92-C-R 112.
I'

ARCHITECTURE A block diagram of the DRFM Modulator architecture is shown in Fig. 2. The IC captures in-phase and quadrature (VQ) components from the high speed ADCs., buffers the VQ data into a 192-bit word and writes the word into an external memory. The DRFM operates in a continuous acquisition (wrap around) mode. Data words are written and read on alternating cycles, and the address range separating the write and subsequent read determines the coarse time delay imparted on the sampled waveform. An internal memory is used in a similar fashion for fine time delay.

0-7803-3504-XI96 $5.00 0 1996 IEEE

GaAs IC Symposium 73

External SRAM (Coarse Delay)

Fine Delay

Direct Digital Synthesizer

Doppler Modulator

--b

Dual PhasdAmp Modulators

The DRFM Modulator IC datapaths and statemachines were designed to operate at a clock frequency of 500 MHz. After block place and route, static timing analysis indicates a critical path of 2.5 ns at 25 "C, or a 400 MHz clock

The 15 mm x 15 mm die contains 492,000 transistors. SPICE analysis predicts a power dissipation of 65 W at a 25 "C junction temperature. Additional component specifications are given in Table 2.

Fig. 2. DRFM Modulator Architecture

The time delayed VQ data is fed into a Doppler Modulator, which multiplies the VQ components by the sine and cosine outputs of a Direct Digital Synthesizer (DDS). The DDS generates signed 14-bit values on each clock cycle using an algorithmic approach developed at SPEC. A positive or negative Doppler frequency shift can be applied to the I and Q components by the DDS. The DDS frequency is set by an external controller through a 16-bit data port. The time delayed, Doppler shifted VQ components are then fed into two independent phase/amplitude modulators. Each modulator multiplies the VQ components by modulation coefficients, which are set by an external source through the data port. The outputs of the single-sideband modulators represent horizontal (H) and vertical (V) polarization signals, which in combination can be used to implement polarization modulation. Alternatively, the outputs can be combined to form I/Q inputs to an external analog vector modulator. Internal datapaths range from 12- to 16-bits. The DDS uses unsigned 16-bit compiled datapath elements to calculate signed 14-bit sinekosine components. The modulators operate on signed 12- and 14-bit data, and produce signed 14bit results. The VQ and H N data ports are ECL compatible, while the external SRAM data ports are 5V TTL compatible. High current open-drain drivers are used to drive the SRAM address bus, and require external pull-up resistors. The IC includes IEEE 1149.1 support, with boundary scan on all ECL and TTL UOs.

Transistors

492,000 600 96.6 pm

YO & Power Pads


Die Pad Pitch

Die Size Power Supply

15mmx15mm

Power Dissipation Package

5V (referenced to -2V) -2v 65 W @ 25 "C Junction Modified 557 pin PGA

DESIGN METHODOLOGY
SPEC'S IC development flow is shown in Fig. 3. COMPASS Design Automation's CAE tools and internally developed GaAs libraries are used to develop high performance GaAs ICs following the same design methodology used in submicron CMOS design. SPEC follows a top-down design methodology, starting with high level schematics entered in COMPASS' Logic Assistant tool. Typically, a designer draws a schematic containing all of the 1/0pads and a single logic block for the core logic. Inside the core logic block additional levels of schematic hierarchy are captured to specify the complete IC design. Many GaAs designs done at SPEC contain datapaths captured as graphical bit-slice specifications and control logic or decoders captured as VHDL specifications. The tools provide support for automatic generation of VHDL code from templates. In addition, the tools can create complete VHDL specifications for simulation from a combination of Logic Assistant schematics, datapath specifications, and embedded VHDL specifications. A VHDL Test Bench can be output to aid in test development. SPEC uses Model Technology's V-Systeflorkstation for VHDL simulation, which is compatible with VHDL produced by the COMPASS tools.

DESIGN SPECIFICATIONS The DRFM Modulator provides programmable time delay out to 128 ms in 2 ns increments, Doppler frequency shifting of +250 MHz in 0.1 Hz steps, and phase/amplitude modulation over a 14-bit dynamic range. Design specifications are listed in Table 1.
Table 1. DRFM MODULATOR DESIGN SPECIFICATIONS Sample Rate V Q Data Sample Size Maximum Time Delay
~~ ~~

5500MSPS
1 - 12 bits

0 - 128 ms

e Delay Resolution
Signal Latency

2ns
4 ns without modulation

Maximum Doppler Shift Doppler Resolution

k250 MHz (Nyquist limit)

0.1 Hz

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Enter Design using Logic Assistant

Generate Netlist using HDL Assistant

Generate he-Route SDF Timing Estimates

Generate Test Bench using; HDL Assistant

Model Technologys V-System/ Workstation

J
Logic Synthesis Datapath Compilation Placement &Routing Extraction

ASIC Synthesizer Datapath Compiler

Chipcompiler Interconnect Extractor

The DRFM Modulator required significant pipelining to achieve 500 MHz performance. Compiled datapaths, which implement a majority of the digital signal processing functions, were highly pipelined to meet the 2 ns cycle time goal. Data busses crossing the 15 mm square die were also pipelined to meet the 2 ns delay goal. Final chip assembly, including floorplanning and place and route, was done with COMPASSS Chipcompiler (see Fig. 4). Chipcompiler places and routes standard cell blocks then routes the standard cell and complied datapath blocks in channels between the blocks. SPEC is in the process of qualifying COMPASSS new nlevel metal place and route tool, PathFinder, for GaAs design. In the H-GaAs 111 technology, SPEC uses metal 1 and metal 2 for all signal routing, metal 3 for VDD (and some clock networks), and metal 4 for VSS. After place and route, the netlist is extracted with COMPASS Interconnect Extractor, which computes net resistance and capacitance from a physical model of the metal interconnects. These values are used to compute interconnect delays in the Delay Calculator. The timing delays computed by the Delay Calculator are used in QTV (COMPASS static timing analyzer) to analyze the critical paths throughout the chip and in QSIM for gate level simulation. The delays are back-annotated in the structural VHDL specification for simulation in the VHDL simulator. Finally, SPEC uses COMPASS Design Ride Checker and Netcompare tools to verify the design prior to final tapeout. A photo of the DRFM die is shown in Fig. 5.

VHDL Simulator QSIM Simulator QTV Static Timing Analyzer

GAASLIBRARIES SPEC has developed commercially available standard cell, U 0 and datapath compiler libraries for Vitesses H-GaAs E l process. The libraries have been characterized using Vitesses HSPICE model for the H-GaAs I11 process, and their performance has been proven in a number of GaAs ASICs. SPEC is currently developing standard cell libraries for Vitesses H-GaAs IV process and Motorolas CGaAsTM process.
ACKNOWLEDGMENT The authors wish to thank our contract monitors, Capt. Calvin Kasadate of the U.S. Air Force and Mr. John Cole of the US.Army, for their support.

Design Kule Checker (DRC) Screcncr & S P K CRC Tool

DRC,ERC,LVS

Tapeout

SrrCompare

Fig. 3. SPECs GaAs ASIC Design Flow The behaviorauRTL VHDL specifications in the design were synthesized with COMPASS Synthesizer, targeted to SPECs GaAs cell libraries. The ASIC Synthesizer has been modified to support GaAs Direct Current FET Logic (DCFL) static current requirements in addition to optimization for maximum dynamic performance. Datapath bit-slice specifications were compiled with COMPASS Datapath Compiler to optimized layout using SPECs datapath cell library. These highly optimized layout designs provide maximum density and highest performance for multi-bit datapaths. Regular datapath structures also significantly aid in reducing clock skew within the chip.

REFERENCES
[ 1J Digital RF Memories J. Electronic Defense, Jan. 1994 Supplement,
D. 19. [2] Proceedings Digital RF Memory Workshop 95 Atlanta, Georgia, Sept. 27-28, 1995. 131Marvin Potts Digital Single Sideband Modulator Baldwidth Study Wright Laboratory Tech Brief WL-TR-92-1032.

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Fig. 4. DRFM Modulator Place and Route Results in COMPASS Design Automations ChipCompileI

Fig. 5. DRFM Modulator Die Photo

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