2000 Fairchild Semiconductor lnternational

April 2000
Rev. A, April 2000
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QFET QFET QFET QFET
TM
FQB6N70 / FQI6N70
700V N-ChanneI MOSFET
GeneraI Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary,
planar stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the
avalanche and commutation mode. These devices are well
suited for high efficiency switch mode power supply.
Features
6.2A, 700V, R
DS(on)
= 1.5 @ V
GS
= 10 V
Low gate charge ( typical 30 nC)
Low Crss ( typical 15 pF)
Fast switching
100% avalanche tested
lmproved dv/dt capability
! "
!
!
!
"
"
"
! "
!
!
!
"
"
"
AbsoIute Maximum Ratings T
C
= 25C unless otherwise noted
ThermaI Characteristics
SymboI Parameter FQB6N70 / FQI6N70 Units
V
DSS
Drain-Source Voltage 700 V
l
D
Drain Current - Continuous (T
C
= 25C) 6.2 A
- Continuous (T
C
= 100C) 3.9 A
l
DM
Drain Current - Pulsed (Note 1) 24.8 A
V
GSS
Gate-Source Voltage 30 V
E
AS
Single Pulsed Avalanche Energy (Note 2) 600 mJ
l
AR
Avalanche Current (Note 1) 6.2 A
E
AR
Repetitive Avalanche Energy (Note 1) 14.2 mJ
dv/dt Peak Diode Recovery dv/dt (Note 3) 4.5 V/ns
P
D
Power Dissipation (T
A
= 25C) * 3.13 W
Power Dissipation (T
C
= 25C) 142 W
- Derate above 25C 1.14 W/C
T
J
, T
STG
Operating and Storage Temperature Range -55 to +150 C
T
L
Maximum lead temperature for soldering purposes,
1/8 from case for 5 seconds
300 C
SymboI Parameter Typ Max Units
R
JC
Thermal Resistance, Junction-to-Case -- 0.88 CW
R
JA
Thermal Resistance, Junction-to-Ambient * -- 40 CW
R
JA
Thermal Resistance, Junction-to-Ambient -- 62.5 CW
* When mounted on the minimum pad size recommended (PCB Mount)
S
D
G
D

-PAK
FQB Series
I

-PAK
FQI Series
G S
D
G
S D
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(Note 4)
(Note 4, 5)
(Note 4, 5)
(Note 4)
Rev. A, April 2000
EIectricaI CharacteristicsT
C
= 25C unless otherwise noted
Notes:
1. Repetitive Rating : Pulse width limited by maximum junction temperature
2. L = 29mH, l
AS
= 6.2A, V
DD
= 50V, R
G
= 25 , Starting T
J
= 25C
3. l
SD
6.2A, di/dt 200A/s, V
DD
BV
DSS,
Starting T
J
= 25C
4. Pulse Test : Pulse width 300s, Duty cycle 2%
5. Essentially independent of operating temperature
SymboI Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
DSS
Drain-Source Breakdown Voltage V
GS
= 0 V, l
D
= 250 A 700 -- -- V
BV
DSS
/ T
J
Breakdown Voltage Temperature
Coefficient
l
D
= 250 A, Referenced to 25C -- 0.78 -- V/C
l
DSS
Zero Gate Voltage Drain Current
V
DS
= 700 V, V
GS
= 0 V -- -- 10 A
V
DS
= 560 V, T
C
= 125C -- -- 100 A
l
GSSF
Gate-Body Leakage Current, Forward V
GS
= 30 V, V
DS
= 0 V -- -- 100 nA
l
GSSR
Gate-Body Leakage Current, Reverse V
GS
= -30 V, V
DS
= 0 V -- -- -100 nA
On Characteristics
V
GS(th)
Gate Threshold Voltage V
DS
= V
GS
, l
D
= 250 A 3.0 -- 5.0 V
R
DS(on)
Static Drain-Source
On-Resistance
V
GS
= 10 V, l
D
= 3.1 A -- 1.16 1.5
g
FS
Forward Transconductance V
DS
= 50 V, l
D
= 3.1 A -- 6.4 -- S
Dynamic Characteristics
C
iss
lnput Capacitance
V
DS
= 25 V, V
GS
= 0 V,
f = 1.0 MHz
-- 1100 1400 pF
C
oss
Output Capacitance -- 125 150 pF
C
rss
Reverse Transfer Capacitance -- 15 120 pF
Switching Characteristics
t
d(on)
Turn-On Delay Time
V
DD
= 350 V, l
D
= 6.2 A,
R
G
= 25
-- 25 60 ns
t
r
Turn-On Rise Time -- 70 150 ns
t
d(off)
Turn-Off Delay Time -- 55 120 ns
t
f
Turn-Off Fall Time -- 50 110 ns
Q
g
Total Gate Charge V
DS
= 560 V, l
D
= 6.2 A,
V
GS
= 10 V
-- 30 40 nC
Q
gs
Gate-Source Charge -- 6.5 -- nC
Q
gd
Gate-Drain Charge -- 13 -- nC
Drain-Source Diode Characteristics and Maximum Ratings
l
S
Maximum Continuous Drain-Source Diode Forward Current -- -- 6.2 A
l
SM
Maximum Pulsed Drain-Source Diode Forward Current -- -- 24.8 A
V
SD
Drain-Source Diode Forward Voltage V
GS
= 0 V, l
S
= 6.2 A -- -- 1.4 V
t
rr
Reverse Recovery Time V
GS
= 0 V, l
S
= 6.2 A,
dl
F
/ dt = 100 A/s
-- 340 -- ns
Q
rr
Reverse Recovery Charge -- 2.7 -- C
2000 Fairchild Semiconductor lnternational
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Rev. A, April 2000
0 5 10 15 20 25 30
0
2
4
6
8
10
12
V
DS
= 350V
V
DS
= 140V
V
DS
= 560V
Note : l
D
= 6.2 A

V
G
S
,

G
a
t
e
-
S
o
u
r
c
e

V
o
l
t
a
g
e

[
V
]
Q

, Total Gate Charge [nC]

10

10

10

0
400
800
1200
1600
2000
C
iss
=C
gs
+C
gd
(C
ds
=shorted)
C
oss
=C
ds
+C
gd
C
rss
=C
gd
Notes :
1. V
GS
=0V
2. f =1MHz C
rss
C
oss
C
iss

C
a
p
a
c
i
t
a
n
c
e

[
p
F
]
V
DS
, Drain-Source Voltage [V]
0.2 0.4 0.6 0.8 1.0 1.2 1.4
10
-1
10
0
10
1

25 150
Notes:
1. V
GS
=0V
2. 250sPulseTest
I
D
R

,

R
e
v
e
r
s
e

D
r
a
i
n

C
u
r
r
e
n
t


[
A
]
V
SD
, Source-Drain Voltage [V]
0 4 8 12 16 20
0
1
2
3
4
V
GS
= 20V
V
GS
= 10V
Note : T

= 25

R
D
S
(
O
N
)

[

]
,
D
r
a
i
n
-
S
o
u
r
c
e

O
n
-
R
e
s
i
s
t
a
n
c
e
I

, Drain Current [A]

2 4 6 8 10
10
-1
10
0
10
1

Notes:
1. V
DS
=50V
2. 250sPulseTest
-55
150
25
I
D

,

D
r
a
i
n

C
u
r
r
e
n
t


[
A
]
V
GS
, Gate-Source Voltage [V]
10

10

10

10

10

10

V
GS
Top: 15.0V
10.0V
8.0V
7.0V
6.5V
6.0V
Bottom: 5.5V
Notes :
1. 250s Pulse Test
2. T
C
=25

I
D
,

D
r
a
i
n

C
u
r
r
e
n
t

[
A
]
V
DS
, Drain-Source Voltage [V]
TypicaI Characteristics
Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics
Figure 3. On-Resistance Variation vs.
Drain Current and Gate VoItage
Figure 4. Body Diode Forward VoItage
Variation vs. Source Current and
Temperature
Figure 2. Transfer Characteristics Figure 1. On-Region Characteristics
2000 Fairchild Semiconductor lnternational
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Rev. A, April 2000
10

10

10

10

10

10

10

10

10

10 s

DC
10 ms
1 ms
100 s
Operation in This Area
is Limited by R

Notes :
1. T

= 25

C
2. T

= 150

C
3. Single Pulse

l
D
,

D
r
a
i
n

C
u
r
r
e
n
t

[
A
]
V

, Drain-Source Voltage [V]

1 0

1 0

1 0

1 0

1 0

1 0

1 0

1 0

1 0

1 0

N o t e s :
1 . Z
J C
( t ) = 0 . 8 8 /W M a x .
2 . D u t y Fa c t o r , D = t
1
/t
2
3 . T
J M
- T
C
= P
D M
* Z
J C
( t )
s i n g l e p u l s e
D = 0 . 5
0 . 0 2
0 . 2
0 . 0 5
0 . 1
0 . 0 1

J
C (
t
)
,

T
h
e
r
m
a
l

R
e
s
p
o
n
s
e
t

, S q u a r e W a v e P u l s e D u r a t i o n [ s e c ]
25 50 75 100 125 150
0
1
2
3
4
5
6
7

l
D
,

D
r
a
i
n

C
u
r
r
e
n
t

[
A
]
T

, Case Temperature []
-100 -50 0 50 100 150 200
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Notes:
1. V
GS
=10V
2. I
D
=3.1A

R
D
S
(
O
N
)
,

(
N
o
r
m
a
l
i
z
e
d
)
D
r
a
i
n
-
S
o
u
r
c
e

O
n
-
R
e
s
i
s
t
a
n
c
e
T
J
, Junction Temperature [
o
C]
-100 -50 0 50 100 150 200
0.8
0.9
1.0
1.1
1.2
Notes:
1. V

=0V
2. l

=250A


B
V
D
S
S
,

(
N
o
r
m
a
l
i
z
e
d
)
D
r
a
i
n
-
S
o
u
r
c
e

B
r
e
a
k
d
o
w
n

V
o
l
t
a
g
e
T
J
, Junction Temperature [
o
C]
TypicaI Characteristics (Continued)
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current
vs. Case Temperature
Figure 7. Breakdown VoItage Variation
vs. Temperature
Figure 8. On-Resistance Variation
vs. Temperature
Figure 11. Transient ThermaI Response Curve
t
1
P
DM
t
2
2000 Fairchild Semiconductor lnternational
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Rev. A, April 2000
Gate Charge Test Circuit & Waveform
Resistive Switching Test Circuit & Waveforms
UncIamped Inductive Switching Test Circuit & Waveforms
Charge
V
GS
10V
Q
g
Q
gs
Q
gd
3mA
V
GS
DUT
V
DS
300nF
50K
200nF 12V
Same Type
as DUT
Charge
V
GS
10V
Q
g
Q
gs
Q
gd
3mA
V
GS
DUT
V
DS
300nF
50K
200nF 12V
Same Type
as DUT
V
GS
V
DS
10%
90%
t
d(on)
t
r
t
on
t
off
t
d(off)
t
f
V
DD
10V
V
DS
R
L
DUT
R
G
V
GS
V
GS
V
DS
10%
90%
t
d(on)
t
r
t
on
t
off
t
d(off)
t
f
V
DD
10V
V
DS
R
L
DUT
R
G
V
GS
E
AS
= Ll
AS
2
----
2
1
--------------------
BV
DSS
- V
DD
BV
DSS
V
DD
V
DS
BV
DSS
t
p
V
DD
l
AS
V
DS
(t)
l
D
(t)
Time
10V DUT
R
G
L
l
D
t
p
E
AS
= Ll
AS
2
----
2
1
E
AS
= Ll
AS
2
----
2
1
----
2
1
--------------------
BV
DSS
- V
DD
BV
DSS
V
DD
V
DS
BV
DSS
t
p
V
DD
l
AS
V
DS
(t)
l
D
(t)
Time
10V DUT
R
G
LL
l
D
l
D
t
p
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Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
V
DS
+
_
Driver
R
G
Same Type
as DUT
V
GS
dv/dt controlled by R

controlled by pulse period

V
DD
L
l
SD
10V
V
GS
( Driver )
I
SD
( DUT )
V
DS
( DUT )
V
DD
Body Diode
Forward Voltage Drop
V
SD
I

, Body Diode Forward Current

Body Diode Reverse Current
l
RM
Body Diode Recovery dv/dt
di/dt
D =
Gate Pulse Width
Gate Pulse Period
--------------------------
DUT
V
DS
+
_
Driver
R
G
Same Type
as DUT
V
GS
dv/dt controlled by R

controlled by pulse period

V
DD
LL
l
SD
10V
V
GS
( Driver )
I
SD
( DUT )
V
DS
( DUT )
V
DD
Body Diode
Forward Voltage Drop
V
SD
I

, Body Diode Forward Current

Body Diode Reverse Current
l
RM
Body Diode Recovery dv/dt
di/dt
D =
Gate Pulse Width
Gate Pulse Period
-------------------------- D =
Gate Pulse Width
Gate Pulse Period
--------------------------
2000 Fairchild Semiconductor lnternational
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Package Dimensions
10.00 0.20
10.00 0.20
(8.00)
(4.40)
1.27 0.10 0.80 0.10
0.80 0.10
(2XR0.45)
9.90 0.20
4.50 0.20
0.10 0.15
2.40 0.20
2
.
5
4

0
.
3
0
1
5
.
3
0

0
.
3
0
9
.
2
0

0
.
2
0
4
.
9
0

0
.
2
0
1
.
4
0

0
.
2
0
2
.
0
0

0
.
1
0
(
0
.
7
5
)
(
1
.
7
5
)
(
7
.
2
0
)
0

~
3

1
.
2
0

0
.
2
0
9
.
2
0

0
.
2
0
1
5
.
3
0

0
.
3
0
4
.
9
0

0
.
2
0
(
0
.
4
0
)
2.54 TYP 2.54 TYP
1.30
+0.10
0.05
0.50
+0.10
0.05

2000 Fairchild Semiconductor lnternational

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Package Dimensions (Continued)
9.90 0.20
2.40 0.20
4.50 0.20
1.27 0.10 1.47 0.10
(
4
5

)
0.80 0.10
10.00 0.20
2.54 TYP 2.54 TYP
1
3
.
0
8

0
.
2
0
9
.
2
0

0
.
2
0
1
.
2
0

0
.
2
0
1
0
.
0
8

0
.
2
0
M
A
X
1
3
.
4
0
M
A
X

3
.
0
0
(
0
.
4
0
)
(
1
.
4
6
)
(
0
.
9
4
)
1.30
+0.10
0.05
0.50
+0.10
0.05

2000 Fairchild Semiconductor lnternational Rev. A, January 2000

TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx
Bottomless
CoolFET
CROSSVOLT
E
2
CMOS
FACT
FACT Quiet Series
FAST

FASTr
GTO
HiSeC
ISOPLANAR
MICROWIRE
POP
PowerTrench

QFET
QS
Quiet Series
SuperSOT-3
SuperSOT-6
SuperSOT-8
SyncFET
TinyLogic
UHC
VCX
DISCLAIMER
FAlRCHlLD SEMlCONDUCTOR RESERVES THE RlGHT TO MAKE CHANGES WlTHOUT FURTHER NOTlCE TO ANY
PRODUCTS HERElN TO lMPROVE RELlABlLlTY, FUNCTlON OR DESlGN. FAlRCHlLD DOES NOT ASSUME ANY
LlABlLlTY ARlSlNG OUT OF THE APPLlCATlON OR USE OF ANY PRODUCT OR ClRCUlT DESCRlBED HERElN;
NElTHER DOES lT CONVEY ANY LlCENSE UNDER lTS PATENT RlGHTS, NOR THE RlGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAlRCHlLD'S PRODUCTS ARE NOT AUTHORlZED FOR USE AS CRlTlCAL COMPONENTS lN LlFE SUPPORT
DEVlCES OR SYSTEMS WlTHOUT THE EXPRESS WRlTTEN APPROVAL OF FAlRCHlLD SEMlCONDUCTOR
lNTERNATlONAL.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance lnformation Formative or ln
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary First Production This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No ldentification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete Not ln Production This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.