EFSOT (Next Generation Environment-Friendly Soldering Technology) Root Cause of Tin Whisker Growth

P. Oberndorff, Philips CFT, The Netherlands; 1.1 Root Causes of Whisker Growth [18]

diffusion. At higher temperatures, bulk diffusion causes a homogeneous Cu6Sn5 layer, resulting in less stress. This also explains the observation that whiskers grow fastest at ambient temperature [28], [30], [31], [32]. Figure 2 presents a cross-sectional view, showing irregular growth of the Cu6Sn5 intermetallic in the grain boundaries of the columnar matte Sn deposit due to grain boundary diffusion at lower temperatures. By selectively etching away the Sn, the morphology of the intermetallic can be shown, see Figure 2and Figure 5. shows the intermetallic structure after the sample had been stored for 6 months at room temperature and subsequently the Sn had been etched away. Here it can be seen that the intermetallic grows predominantly at the grain boundaries, while almost no intermetallic grows in the centre.

Whisker formation with lead free plating is a known phenomenon. Whiskers are single crystals, protruding from electroplated layers, originating from diffusion under the influence of compressive stress. Figure 1 gives an example of a whisker. Long whiskers can have influence on quality of electronic devices as those can cause short circuits. It is therefore important to understand the root cause of whisker growth.

Figure 1: Example of a whisker showing stria tions along the length of the whisker [18] Knowledge of the growth mechanism of whiskers can be used to develop a whisker test. Until now, no standardized test is available for industry [18]. It is generally accepted that whiskers form because of compressive stress in the plating layer. Collected data on Cu based lead-frames support a hypothesis that the formation of irregular Cu6Sn5 intermetallics generate these compressive stresses. It can be calculated that the irregular growth of this intermetallic can introduce 58% additional volume in the plating layer, showing that the existence of compressive stress is plausible. This Cu6Sn5 is irregular after storage at lower temperatures, because at these temperatures grain boundary diffusion predominates over bulk

Figure 3: Individual grains of Sn in a cross-

section of a C19400 substrate plated with ~12 m Sn with irregular intermetallic at the grain boundaries. (the marker depicts 15 m) [18] If one compares the morphology of the intermetallic after 1 h at 150 oC and subsequent etching as in Figure 4 with the one shown in Figure 5,it is obvious that the intermetallic is much more regular at higher temperatures than at ambient. This is because at higher temperatures (> ~75oC), the predominating bulk diffusion forms a homogeneous Cu3Sn/Cu6Sn5 layer. This regular layer forms a diffusion barrier against further irregular growth of the Cu6Sn5 at lower temperatures. A further beneficial effect of a high temperature treatment is recrystallization of the Sn and annealing of al-

ready present stress. Therefore, a post bake treatment of 1h at 150 oC is introduced in several factories of component manufacturers to reduce whisker growth. The above mentioned theory holds for Cu based leadframe materials. For other materials such as FeNi42 whisker growth is caused by the mismatch of the coefficient of thermal expansion (CTE) of the leadframe material and the Sn plating. Therefore, whisker formation can be observed in these samples predominantly after temperature cycling. A quantitative explanation of the results will require a whisker model that recognizes more than the dominant effects. Finite element stress modeling, starting with the dedicated material property set, will support refinement and verification of the hypothesis. The goal is that this, ultimately, will result in an industry-wide accepted accelerated test for whisker growth.

Figure 5: Surface view of the intermetallic after

tive 1 hour at 150 oC and subsequent selecetching of Sn [18]

4.2

Development of Lead-free Fine Pitch Solder Paste [29]

EFSOT Europe develops a robust, easy to use lead-free fine pitch solder paste. The solder paste shall meet the requirements of the automotive electronics as well as that of the consumer electronics industry thus covering a broad range of widely different requirements. A test board was designed according to the requirements of the project partners. All the functional tests were performed to check and ensure good printing behavior, tack properties, electrical reliability, and wettability on different finishes: CU-Ni-Au Cu-Immersion-Sn Cu-immersion Ag Cu-OSP AgPt ink Copper (worst case)
Components with large heat sink pad

Solder balling test pattern

Figure 4: Surface view of the intermetallic after

Print capability pattern

Fine pitch components

storage at room temperature for 6 months and subsequent selective etching of Sn [18]

Surface isolation resistance pattern

Reflow behavior test pattern

Solder paste wetting test pattern

Figure 6: Test board for solder development

[29] The stencil thickness was 100 and 150m (electroformed), on FR4 and on ceramic base materials. The printing properties of the solder paste EFSOT 001 fully match the requirements. The printing properties of the solder paste EFSOT 001 fully match the requirements. The test board was soldered with different reflow profiles. The soldering results were good for all joints besides the small 0201 components. With long preheated profiles and 75 s over liquidus

temperature of the solder paste, the results were not satisfying. The next develo evelopment pment step focused on this temperature profile. The protection of the activators was improved, keeping all the other specifications and properties. Table 1: Functional Test Requirements [29]
FONCTIONNAL TEST
Copper mirror Chromate paper Solder balling test Cold and Hot slump Tack time test Wetting test Printing definition Smearing behaviour Rolling behaviour during printing or stencil life Rolling behaviour during printing or stencil life Abandon time Voids test Copper corrosion Surface insulation resistance and electro-migration Electro-migration Bellecore test Stencil cleaning Miss print cleaning PCB cleaning after reflow According to (test method) IPC TM 650 (2.3.32) IPC TM 650 (2.3.33) PROMOSOL (PR 01801) PROMOSOL (PR 10030) PROMOSOL (PR 10024) PROMOSOL (PR 10007) PHILIPS PHILIPS PROMOSOL PROMOSOL TEST PROMOSOL IPC TM 650 (2.6.15) IPC TM 650 (2.6.3.3) BELLECORE GR 78 PROMOSOL With electroformed stencil PROMOSOL Test pattern IPC B 36 PROMOSOL Test pattern IPC B 36

The new solder paste EFSOT 002 was soldered with different reflow temperature profiles and exhibited high resistance to long and high, nonlinear thermal profiles as described above. In the next step, partners will conduct reliability tests with the solder paste EFSOT 002.

Criteria pass pass Pass ( < or = 8) 0,4 (minimal pitch without bridging) 1,4g/mm2 after 16 h Class 2 ( 1 to 3) Class 3 - 4 For ratio speed/pressure 80/6 Class 4 with a linear profile >1000 printing i.e. no problem of evolution on stencil > 24h >20h i.e. no problem of evolution 2 hours for 0.4 pitch To determine pass > 10.8 ohms pass Using an environmental approved solvent and water base Using an environmental approved solvent and water base No residue and no microball Using an environmental approved solvent and water base No residue Ionic contamination SIR > 100 M

1.2

Reliability Testing of Lead-free Solder Joints [23]

Figure 15: Printing results [29]

The possible reliability and strength of solder joints is mainly determined by the creeping characteristics. A permanent pull or shear force will inevitably lead to the fracturing of solder joints. Fortunately, most stresses in soft solder joints are induced by thermal expansion and are relaxing in a short time. But the changing temperatures and stresses initiate fatigue processes and cracks which leads to defects and fracturing. For standard lead-containing solders we have a lot of experience to correlate thermo-mechanical data with practical results, not so for lead-free solutions. The available lead free solder alloys have very different thermo-mechanical and aging properties. For many applications, especially for elevated operating temperatures (e.g. automotive electronics) are these limitations very important. Beside standard reliability tests like thermal cycling of test boards, some special investigations of creeping properties of solder joints should help to find best correlation between measured data and test board failures. With the result of this in-

Figure 16: EFSOT 001 (left) and EFSOT 002 (right) solder paste with long preheat and long reflow zone over 217 C [29]

vestigation it will be possible to fill in relevant fields in a map of practical solutions and to recommend or disqualify materials and design rules for different applications. Thermo-mechanical and aging properties of joints are influenced by the interaction of the solders with component and board metallization. Especially the growth of intermetallic phases and the diffusion of metal from solder to base material and vice versa can create cracks and holes. A special measuring method for creeping properties of solder joints will be enhanced within this EFSOT project, to analyze the influences of solder joints dimensions, surface metallization and pretreatment for lead free solder joints. For the investigation it was necessary to do a typical selection with following parameters: solder alloys - Sn Pb Ag2, Sn Ag4 Cu0.5; surfaces - Cu/OSP, Imm.Sn, Imm.Ag, ENIG; dimensions - two different sizes; temperatures RT, 85C, 120C and ageing - as soldered; 16h/155C; 500 x 40/125C References

[1] DIEGNER, B. : Exzerpt of Fakten und Argumente zum Thema Bleiverbot in der Elektronikindustrie, Zentralverband der Elektrotechnik- und Elektronikindustrie (ZVEI); Status March 1999 and July/August 2001 [2] Hasegawa et al., Senju Metals, Japan: Interviews Oct. 2000 and Nov. 2002 [3] Sales data from 8 big European and US solder manufacturers covering about 50 % of the world market, last quarter of 2002 [4] Altendorf, Peter, Fraunhofer IZM: Recycling von Lotabfllen; Interviews with recyclers and electronics manufacturers, 2003; not published [5] Deubzer, Otmar, Fraunhofer IZM: Vergleich von Umweltbelastungen durch Reflowlt- un Leitklebeprozesse als Beispiel fr Verbindungstechniken in der Elektronikindustrie; Diplomarbeit an der TU Berlin, Fachgebiet Abfallwirtschaft, angefertigt am Fraunhofer IZM, Februar 1997. [6] European and Japanese secondary and primary (copper) smelters: Interviewed by Ot-

mar Deubzer, October 2000 and June to October 2003 [7] IPC, association connecting electronics industries, web-site [8] German Electronic recyclers, interviewed by Otmar Deubzer, June 2003 [9] Segsa: Spree Hybrid & Kommunikationstechnik GmbH, Berlin: Interview May 25, 2002 [10] Deubzer, Otmar; Griese, Hansjrg; Fraunhofer IZM, Berlin, Germany; Suga, Tadatomo, The University of Tokyo, Japan: Leadfree Soldering Future Aspects of Toxicity, Energy and Resource Consumption; Proceedings of Eco-Design Conference 2001, Tokyo, Japan [11] EFSOT: Next Generation EnvironmentFriendly Soldering Technology; an IMS project with participation of Japan, Korea and the European Union (see www.efsoteurope.info and www.ims.org) [12] Soldertec: Second European Lead-Free Soldering Roadmap, SolderTec, February 2003, http://download.leadfree.org/downloads/EU_roadmap_2003_ver2 _lab.pdf [13] http://download.leadfree.org/downloads/EU_roadmap_2003_ver2 _lab.pdf [14] United States Geological Survey, Mineral Commodity Report 2000, 2001 and 2002 (http://minerals.usgs.gov/minerals/pubs/mcs/ ) [15] Verhoef, E.V.; Reuter, M.A.; Scholte, A., Department of Applied Earth Sciences, Delft University of Technology: Keeping the Score of Lead in Electronics; The Minerals, Metals & Materials Society, 2003 [16] Verhoef, E.V.; Reuter, M.A.; Scholte, A., Department of Applied Earth Sciences, Delft University of Technology; Dijkema, P. J., Department of Technology, Policy and Management, Delft University of Technology: A Dynamic Model of Metal Production and Waste Management [17] Bundesanstalt fr Geowissenschaften und Ressourcen (BGR): Rohstoffwirtschaftliche Lnderstudien, Heft XXVII, Bundesrepublik

Deutschland, Rohstoffsituation, Hannover 2002 [18] Pascal Oberndorff, Philips CFT, Eindhoven, The Netherlands, EFSOT Europe; pascal.oberndorff@philips.com [19] Otmar Deubzer, TU Berlin, EFSOT Europe; otmar.deubzer@tu-berlin.de [20] Tsuyoshi Yamamoto, Fujitsu, EFSOT Japan; yanma@jp.fujitsu.com [21] H. Satoh, Tohoku University, EFSOT Japan; h.satoh@ehs.med.tohoku.ac.jp [22] Norihiro Itsubo, AIST, EFSOT Japan; itsubo-n@aist.go.jp [23] Mathias Nowottnick, TU Berlin, Germany, EFSOT Europe; mathias.nowottnick@izm.fraunhofer.de [24] Tadashi Takemoto, Osaka University, EFSOT Japan; takemoto@crcast.osakau.ac.jp [25] Iigo Cacho, Rafael Miguel, Fundacin Gaiker, Spain; cacho@gaiker.es, [26] Luis Irasarri, INDUMETAL RECYCLING, Spain, EFSOT Europe; lirasarri@indumetal.com [27] Irina Stobbe, TU Berlin, EFSOT Europe; Irina.stobbe@tu-berlin.de [28] Dittes, M; Oberndorff, P; Petit, L. Tin Whisker Formation Results, Test Methods and Countermeasures, Proc. 53. ECTC 2003, New Orleans, pp 822-826 [29] Anne Marie Lagt, Avantec, France; amlaugt@avantec.dehon.com, Jacob Klerk, Paul Evers, Philips CFT, The Netherlands; Peter Wilczek, AB Mikroelektronik, Salzburg, Austria; Didier Caban, Thomson, France [30] Oberndorff, P; Dittes, M; Petit, L; Chen, C.C.; Klerk, J; Kluizenaar, E.E de Tin Whiskers on Lead-Free Platings Proc. SEMI Technology Symposium, Advanced Packaging Technologies II, August 2003,Singapore, pp 51-55 [31] Oberndorff, P; Dittes, M; Petit, L. Intermetallic Formation in Relation to Tin Whiskers Proc. International Conference on Lead-Free Electronics 2003, Brussels [32] Dittes, M.; Oberndorff, P.; Crema, P.; Schroeder, V. The Effect of Temperature Cycling on Whisker Formation, IPC/JEDEC

4th Internation Conference on Lead-free Electronic Components and Assembly, October 2003, Frankfurt Germany [33] International Manufacturing Systems Website, www.IMS.org