Analog Behavioral Modeling With The Verilog-A Language

TE ANALOG BEHAVIORAL MODELING WITH THE VERILOG-A LANGUAGE by Dan FitzPatrick Apteq Design Systems, Inc. and Ira Miller Motorola KLUWER ACADEMIC PUBLISHERS Boston / Dordrecht London—— Distribatos for North, Central ané South America: Kluwer Academic Publishers 101 Philp Drive Assinippi Parke Norwell, Massachusetts 02061 USA Telephone (781) 871-6600 Fax (781) £71-6528 E-Mail Distributors for all ter counties ‘Kluwer Academie Pliers Group Pos Office Box 322 3300 AH Dordrecht, THE NETHERLANDS “Telephone 31 786576 000 Fax 31-78 6576475 E-Mail 9A ei Sori creping [Library of Congress Cataloging-in-Publication FitzPatrick, Dan, 1961— ‘Analog behavioral modeling with the Verilog-A language /by Dan FitzPatrick and Ia Miler, pcm. Includes bibliographical references and index ISBN 0-7923.2044-4 I. _Vetilg (Computer hardware description language) 2, Araiog electronic systems Computer simulation. 3. Lina integrated circults~Corapuersimslation 4, Mined signal creuis—Computersimlation. 5, Spice (Computer) Ira, 9143, Tile 138198 621.381°01'135369-4221 sr-sa105 cr ‘Copyright © 1998 by Kiower Academic Publishes. Third Printing 2003, ‘This pristng is a digial duplication ofthe original edition Allright reserved. No prt of this publication may be reproduced, sored in a retriev ‘system or ansited in any frm of by any mars, elsronic, mechanical, pho-copying, microfilming, recording, ot otherwise, witout the prior writen petiission of tee Bublsher, withthe exception of any material supplied special for he pupore of being fered and executed ona computer system, for exclave bythe purchaser of te Permission for books published inthe USA: permissions @wkapcom Permissions for books pblshd in Europe: permissions@iwhap Printed on acl fee pope Printed inthe United States of America Contents 1 Introduction LL Motivation 1.2 Product Design Methodologies. i 3 1.3 The Role of Standards 7 13.) Verilog: at an Extension of Spice . 5 9 0 14. The Role of Verilog-A. ns 141 Locking Ahead to Verilog AMS. ie 2. Analog System Description and Simulation 2.1 Inteoduetion 22 Representation of Systems svn 2.21 Anatomy of@ Module B 2.22 Siruemral Descriptions 4 1223 Behavioral Descriptions . n 16 23. Mixed-Level Descriptions. 19 2.3.1 Refining the Module 2 2.4 Types of Analog SyStEM8 cron 25 24.1 Conterotve Sytem. 25 24.2 Branches. 26‘Anslog Behavioral Modeling With the Verlog-A Language oe 243 Conservation Laws System Descriptions. 27 3.6.2 Indirect Contribution Statements... 7 81 2.44 Signal-Flow Systems. sD 3.6.3 Case Statements, 7 83 25 Signs naoy Ses > 34 teri Semen, — = 2B hen ucts u 37. Developing Beta Mol : wa 252 Inplici Branches. 2 2.71 Development Methodology. ~ a 25.3 Summary of Signal Acces. 33 3.72 System and Use Considerations. 85 26 roen Sues and Sig Agno 3 Made " ‘ Pal Polen a 2.6.3 Mustraied Examples. 37 Declarations and Structural Descriptions.. Fy * ifn eaten ae me _ 4.2, Module Overview. Sie eile 87 {21 recon rie Bers, % i ‘iptic 4.2.2 Introduction to Local Declarations. - veneer 3 Behavioral Descriptions. as aes eee Re ee 34 Inrodcon 43. Modules Decantons ne vga 32. Beavioal Decipions a {111 Pon Sa ern Diony ao 13) alg hat Pops # 123 Pentru : 8 33. ‘Shteont fr Behera Dasa s 44 eal Decarons % 31 fry Stee “3 43 Module sanaons —_ % 332 Conribation Statements, ” | 451 Positional and Named Association Example — 100 1223 Paar trate sips “ 132 Ault Poon i 234 Cota Sno nd pein 3 fos eee : fot 225 ny boc oI 34° Analog Operators 53 i : 34.1 Time Derivative Operator. 3 | Applications. ne Bf aa ttn 1 344 Transition Operator. 58 | 5.2. Behavioral Modeling of a Common Emitter Amplifier. 108 44.5 Slew Operator 62 | 5.2.1 Functional Model. 42 348 Lape Prt peas a 5323 Mose her Oe fic is 149 zinger bponce @ 525 Stents af ahr : i 258 iene if ies es ‘ S24 bono vout : iis 25 Amlog vena m4 $3 Aut Openon! Anita i 3.5.1 Cross Event Analog Operator. aS i 5.3.1 Model Development. 422 153 Ter nl ea ‘a Se atic 7 26 Adio Gonos : ” SA Nolage Reports : 129 11 hen in ns * J? fu Bown olen i — eg vi vil‘Analog Behavioral Modeling With the Verlog-A Language en 55 QPSK Modulator/Demodulator. 5.5. Modulator. 55.2 Demodulator... 5.6 Fractional N-Loop Frequency Synthesizer $6.1 Dighal VEO. so 5.62 Pale Remover one 383 Phase-Eror Adjucment. 56.4 Text Bench and Ress 5.7. Antenna Position Contrt System 571 Poteniomete. 5.72 DC Motor. $73 Geatbotecconrninnon 5.24 Antenna ——— e 575 Test Bench and Results Appendix A Lexical Conventions and Compiler Directives.. ALL Verilog-A Language Tokens. ALL White Space AI2 Comment A113 Operator vss : A Namberd. - ‘ALS Conversion — A168 ldenifers, Rewords and System Names, ALL? Escaped ldeifers. A Keywords. on A139 Verlog-A Keywords ‘A10Math Function Keywords A.LItAnalog Operator Keywords. ALLS tem Tas and Functions A2 Compiler Directives A2I define ond ‘nde. A22 le ‘hie ‘tnifossnrorsnonnnnvan 423 inca. 424 retell. 37 1B? 7 Bei) Ms “7 19 150 153 134 154 Iss 136 137 159 Contents Appendix B System Tasks and Functions. BA Introduction B2 Strobe Task nner B21 Examples 2 BB File Output ren Ba Simul BS Probabilistic Distibution BG Rando en BT Simulation Environment. ion Time. Appendix C Laplace and Discrete Filters... CA Introduction nn C2 Laplace Filters 2.1 leplocez. €2.2laplace_2d. 62.3 taplace-np 24 loplace-nd. C3 Discrete Fees non C31 a2. 32a ae ~ 3.3 2.19 Cad eind, CA. Verlog-A MATLAB Filter Speciation Scripts Appendix D Verilog-A Explorer IDE Dl Introduetion D2 Installation and Setup. D321 Overiew ofthe Distribution. D22Executable and Include Path Seti. D.23 Overview of the IDE Organization... D3. Using the Explorer IDE, (D.3.1 Opening ond Ruring an Existing Design (D.3.2Creaing a New Design. 169 N69 169 170 170 it m 1m 173‘Analog Behavioral Modeling With the Verlog-A Language ee AppendixE Spice Quick Reference. E.1 Introduction ve E2 Circuit Netlist Description E3 Component... E31 Bloments 3.2 Semiconductor Devices and Models E4 Anal 4.1 Operating Point Anas 4.2 DC Transfer Curve Anais B43 Transient Analys, EAS AC Smal signal Analysis, 199 Foreword \Verilog-A isa new hardware design language (HDL) for analog circuit and systems design. Since the mid-eightes, Verilog HDL has been used extensively inthe design and verification of digital systems. However, there have been no analogous high-level languages a cuits and systems, Verilog-A provides a new dimension of design and simulation capability for analog. electronic systems, Previously, analog simulation has been based upon the SPICE cit- uit simulator or some derivative of t. Digital simulation is primarily performed with ‘ hardware description language such as Verilog, whichis popular since itis easy to learn and use. Making Verilog more worthwhile isthe fact that several tools exist in the industry that complement and extend Verlog's capabilites. Although SPICE is very eecive inthe simulation of analog and digital integrated Circuit itis ited to the we of primitives sucha transistor restr, and capaci- tors: Hence, SPICE lacks the ese that Verilog HDL possess of dseribing and sim lating higher-level of abstraction ofthe desian Inthe past this Bap has been filed wih sich programs a Mathcad and Matlab tha allow description of eletone funetions based upon numeric computation and dat analysis. Although these programs src useful for tdying elestoie and non-electronic systems at higher levels of Abstraction, they 6 not eno oher ols such as SPICE and Verilog The Vrilog-A Tanguage enables desertion det using mathematica relationships, ths easily allowing system descriptions other han electrical, Adon, Vriog-A interfaces to numeric computation programs ich as SPICE and Verilog| ee Vertog-A HDL Analog Behavioral Modeling with the Verlg-A , th he Verilog Langue provides a good introdc- ton an saring pace srs nd racing engine with recs ‘Standing this new level of simulation technology. This book contains numerous — sorties Sieger, Preface ‘aes: The nt andthe simulation program fclded canbe used for nda study High vel ngs sch as esto Areva = Vig ue hing tbe simul comple kedanlgand aga bo crcl anlnocceeoneee a ‘get you started now. * a Dr. Thomas A. DeMassa Professor of Engineering Atizona State University ‘The Verilog HDL was introduced in 1984 as a means fr specifying digital systems at smany levels of abstraction, from behavioral to the srvtural. Accepted for standard- ization in 1995 by the IEEE, Verilog HDL continues to grow in acceptance and play ‘an increasing role inthe specification and design of digital systems. For analog systems analysis and desiga, Spice, developed by the University of California at Berke ley in 1971, became the defacto standard used to simulate the performance of j electronic circuits. While Spice provides a high-level of accuracy as a simulation tool, designs can only be represented ona structural evel. As such, the ability to handle t large analog and mixed-signal systems, as well as explore desig ideas atthe behav- i oral level is fairy limited. i ‘The Verilog-A language is derived from Verilog HDL for the description ofhigh-Level analog behaviors. Used in conjunction wth a Spice simulator, The Verilog-A lan- _guage expands the simulation capabilites for analog and mixed-signal systems to top- ) a a = FIGURE 14 Higher-Level representations ofthe design facilitate the functional and fabrication process portability ofthe design (here, design A from spec lon process y ta spec 2 on process x) ‘+ Among multiple groups participating inthe design, accuracy in the representation ofthe design is crucial as the complexity af the development, ac wall asthe diver- sity in the tools, becomes greater. ‘+ The sequential nature ofthe product development process has a two-fold impactin that steps within the process typically do nat occur concurrently and errors at any stage can require costly backtracking in terms of time and money. * High-level design methodologies enable concurrent activities inthe development flow, suchas in design, verification, and tes, enabling shorter product develop. ment eyces, ‘In addition to technical considerations, the business model dictates that the design information exchanged ean incorporate proprietary information - either from the foundry in terms of process libravies, the design house in terms of the design, or a third party vendor whose primary function is solely to provide intellectual propery, ‘The proprietary nature of the information is typically reflected in terms of iplemen- {ation - further emphasizing the need for different level of design abstraction, ‘One of the primary focus of the Verilog-A language is towards enhancing the portability of designs between suppliers and customers as wel a allowing for best in {ool solutions. high level of design abstraction such asthe Verilog-A language for analog and mixed-signal designs, maximizes the effectiveness of communication between different levels of designers within product design, verification, test, as well {IP providers and foundries. The high-level description can also be used for verity ing the implementation aguinst the original specifications. This capability has one of its most profound effects in minimizing the design iterations by simply allowing for system-level verification 1.3 The Role of Standards Representation of design information, including specifications, has evolved from spe- cialized tools targeted towards accomplishing specific roles in the product develop- ‘ment process. Generally speaking, these can be categorized based on the types of| {designs for which they represent and the level of abstraction in which those d are described as shown in Figure 15. Verilog HDL : Behavioral Asmracton oa over ——— FIGURE 15 The scope of Spice and Verilog HDL within the abstraction level/ ‘Analog Digital Description Domain FIGURE 146 The extended scope of Verilog-A encompassing that of traditional Spice as well as high-level behavioral representation of analog circu. Building onthe standards of Spice and Verilog HDL provides an opportunity not only to address product development needs ina technological sense, but also provide a ‘The Relea Verges transition path from current design methodologies and infrastructure, Based on traditional Spice design methodologies, the Verilog-A language allows utilization of existing frameworks, libraries, models, and taining. 1.4 The Role of Verilog-A ‘The Veritog-A language allows the description of analog and/or mixed-signal systems with varying amounts of detail. The analog behavioral capability allows the designer to span the abstraction levels, allowing direct access tothe underlying technology. hile maintaining the capability of system-level modelling and simulation, As such, the analog and mixed-signal system can be described and simulated ata high-level of abstraction early inthe design cycle to facilitate fll-chip architectural trade-offs. The resulting Verilog-A description, as an executable specification, promotes communication and consistency throughout the design process ({rom specification to implementation), [A standardized analog behavioral modeling language cuch athe Verilog-A language, with capabilites from the behavioral to cireuit-level provides: ‘+ An enabling technology for analog and mixed-signal top-down design ‘*Managing complexity and significant performance factors within the design + Specification, documentation, and simulation ‘+ A-compact and clear expression of design intent ‘Independent of the implementation ‘Behavioral model reuse enabling design reuse + Standardized form of communication of design information ‘Between tools within the design flow ‘*Between product development groups for exchange and reuse ‘Virtual component IP providers ‘*Semiconductor foundries ‘+ Concurrent development for shortening product development life cycles ‘Design, verification, and test program development 8 Introduction Introduction 91.4.1 Looking Ahead to Verilog-AMS ‘The Verilog-AMS specification, curently under development by Open Verilog Inter- ‘national, is targeted to be a single-language solution forthe specification and simulation of analog, digital, and mixed-signal systems, The objectives ofthe Verilog- AMS. specification are to facilitate portable mixed-signal system description and simulation, In addition, a design described withthe Verilog-AMS language will provide the capability to integrate system and cicuit-level aspects of the design allowing the ‘design intent tobe maintained throughout the entie mixed-signal design process. Veritog- AMS. Abstraction Level n> ———— Analog Digitat Description Domain FIGURE 17 The scope ofthe design descriptions targeted by Verilog-AMS. Full ‘mixed-signal specification, design, and simulation within a single language. ‘The Verilog-AMS specification, yet to be finalized a the time ofthis wr bbeyond the scope ofthis introductory book. 10 Introduction a ere eee ees CHAPTER? Analog System Description and Simulation 2.1 Introduction ‘The Verilog-A language gives designers the flexibility to describe systems at multiple levels of abstraction for architectural definition, verification, and analysis. The basis for both structural and behavioral descriptions inthe Verilog. A language are modules ‘A module definition can incorporate parametric and/or structural declarations (instan- liation or creation of other modules), behavioral descriptions, fall three. Structural descriptions allow system definition via pre-defined, user-defined, oF third part-defined components. The instantiation of a module definition in a lager system {defines a component or instance ofthat system. In an analog HDL such as Verilog-A, ral descriptions map diectly to the mathematical relationships of the system. Both the structural and behavioral abstractions of system definitions share the signals ‘ofthe system. Signal definitions in Verilog-A have thie basis in both the require- ‘ments of their usage for behavioral descriptions and the underlying requirements of analog simulation. ‘This chapter introduces the fundamental aspects ofthe representation of analog and ‘mixed-signal systems with the Veriog-A language. ‘Analog System Description and Simulation u—————————— ‘Analog Sytem Description and Simulation 2.2 Representation of Systems Jn gener sytem ae considered ob a collection of intcoaneced components that we aid upon ya stmuls and produce arp Ths Veen a noes slows analog and ied signa systems tobe Jesctbd ty tet oes Idle. The mode defntion dae he mechs y which heen eax wells the behavior that consibutes inthe sytem performance Each sins les in the system can be dsetited by speiing ty loon * Struc deripions in which a modules comprised tered mols Esch mode inthe stuctral definition ofthe poem come woe nase nal tiough he mode's ports or connection pases + Behavionl descriptions ina programmatic ation withthe Ve shion wth the Veritog- lang ‘The behavior of a module is defined in terms of the values for ‘each ena 7 + Mixd-evel escipions combine aspects of bath scr and beheioal seston ata vay ofeiferen sbarson ese ‘The behaviors comprising a system described in th Verilog-A language canbe a var ‘ious levels of abstraction depending upon the level of detai required. ‘An example of an analog and mixed-signal system is a modem, as shown in Figure 2- “1: A system-level simulation and verification would encompass not only simulation modem demodulator ofthe hardware comprising the system (modulator, demodulator, carrier recovery cr {ults, et.) but slo include eects ofthe envronmeht in which the system i 0 oper ‘ate In this particular example, s model ofthe channel is used lo determine the effect ‘of channel distortion on the transmission integrity, Represetaton a Sytem 22.1 Anatomy of a Module ‘A Verilog-A module definition not only defines the behavior ofthe component, but ‘must declare the interface necessary to configure and connect the component. ‘These interface declarations are used inthe composition of the structurl descriptions of systems. The interface declarations fora module include signal as well as parameter dec larations. We will be using the module definition of the modem as an example (Cistng 2.1). Later we will expand this module definition into a more detailed exam: ple using a 16-QAM (Quadrature Amplitude Modulation) architecture forthe modem of Figute 2-1. port signal declarations ‘and connections {LISTING 21 Example module defnit module modem(dout, din}; Anout dout, din; electrical dout, din: parameter declarations <_— // structural description (section 2.2.2) parameter real fc = 100.00 J1 behavioral description (section 2.2.3) endnoduie ‘The connection points of the module are defined by the port signal interface dectara- tions. The module defines the external ports or signals to which the module can con ‘ect as « component inthe system. In this example, these signals are the indicated by the identifiers dout and din, The module also defines any diectionality associated with those connection points (in Listing 2.1, the connection points dout and din are defined as Aout or bidirectional) as well a the type ofthe analog signals eee trical), ‘The other face of the interface declarations are parameter definitions which allow the characterization of the behavior of the component when i is used within a design. In the modem example of Listing 2.1, «real-valued parameter fc is declared with a default value of 100.066 Signa and parameter interface declarations are covered in In defining system suchas a modem, itis useful 10 encapsulate the. il . (encapsulate the components of more detail in Chapter 4 the system into manageable sub-components. Inthe Verilog-A language, the mrecha- : nism by which this is doae isthe moduie definition, 2 Verlog-A HDL ‘Analog System Description and Simulation 2BCena Analog System Description and Simulation Repression of Systems 2.2.2 Structural Descriptions Structural descriptions of a module for defining system behavior can also be done With the Verlog-A language. A structural description in Verilog-A is any description in which a module instantiates or creates another module within its definition. A structural definition forthe modem will define an explicit hierarchy, or parent-child relationship between modules in the system. The example 16-QAM modem has a pat- ‘ent-child relationship with its the modulator, channel, and demodulator instances (Figure 2.1), The module definition ofthe modem wil declare the names, and assign parameter values and connections for each ofits child-modules via instantiation statements ‘The structural definition of systems allows the designer to pass parametric specifca- tions, as well a connections, throughout the levels of hierarchy in the design. The assignment ofthe parameters and connections of child modules is done via parameter and port association. Te Verilog-A language allows parameters to be assigned and ports tobe connected by postion or name. Structural definitions such as for the 16 (QAM modem are derived from Verilog HDL, and are done in a programmatic fashion 2 illustrated in Listing 2.2 LUSTING 22 Verilog-A definition ofthe modem system in Figure 2-1, Mimetude *std.va* module modem(dout, din); Anout dout, din; electrical dout, din; parameter real fc = 100.026; electrical elk, cin, cout; ganmod #(.carrier_frea(fe)) mod(ein, din, clk); channel cl(cout, cin); ‘i gan.denod #(.carrier_freq(fc}} denod(dout, cout, elk 1, Verilog. language extends the Verilog HDL specification fr structural definition vie the ‘ution of named association for parameters, Thi is discussed in more detail inthe fllowing huge nao, ame ys con opin Vr Am opened ing te ‘ype of he ntiizesexpreston endmodule ‘A module instantiation in the Verilog-A language is similar toa variable declaration in programming languages, The module type name declares the module instance type, {ollowed by optional parameter settings (within the "W..)" construct), the instance name, and the connection list. From Listing 22, the following is used to illustrate the ‘module instantiation syntax: type of the module instance_name ofthe instance created gam_mod #(.carrier_fregife)) mod(ein, din, clk); parameter name in child (qar assigned as: carier_treq mod) module ‘The modile type name qam_mod creates the instance named mod, The mod instance is passed the value fc as the value forthe parameter carrier freq to the instance. The instance is connected to signals cin, din and clk within the defini ‘ion ofthe module modem, The instantiation forthe qam_mod instance mod, and the ‘ther two component instantiations within the modem module definition in Listing, 2.2 declares the design hierarchy of Figure 2.2 module: gam Instance: mod instance: ct instance: demod module: qam_mod module: channel module: qam_demod FicunE 22 Hierarchical view of the modem system, ‘Structural definitions inthe Verlog-A language facilitate the use of top-down design ‘methodologies. As architectural design progresses, structural and behavioral defi tions with finer details of description can be substitued for determining the system 14 Verlog-A HDL Analog System Description and Simulation 15‘Analg System Description and Simaton performance to specifications Utilizing this eapability requires no more than an "understanding ofthe parameter and port definitions of a module, 2.2.3 Behavioral Descriptions ‘The Verilog-A language provides for desribing the behavior of snalog and mixed- signal systems. The analog behavioral descriptions are encapsulated within analog Statemenis (or blocks) within a module definition. The behavioral descriptions are ‘mathematical mappings which relate the input signals ofthe module to output signals in terms ofa large-signal or time-domain behavioral description. The mapping uses the Verilog-A language contribution operator “<+" which assigns an expression to a signal. The assigned expression canbe linear, non-linear, algebraic and/or difere functions of the input signals, These large-signal behavioral des constitutive relationship ofthe module, and take the form output_signal <+ £( input_signal In signal contribution, the right-hand side expression, or £( input_signal ),is ‘evaluated and it value i assigned to the output signal. Consider, for instance, te ‘epresentation of a resistor connected between electrical nodes nl and n2 Hot.n2y me f Viotynay = FIGURE 23 Resistor model and reference directions. ‘The constitutive relationship ofthe element could be encapsulated as a module definition in the Verlog-A language as shown in the resistor module definition of List ing 2.3. LasTING 23 Verilog-A module ofthe resistor in Figure 2.3. module resistor (ni, n2); . Representtlon of Stems (nl, n2) <+ Vint, n2)/R; endnodule ‘where V(n2 2) i the voltage across the resistor connected between nodes n2 and 12 ofthe module, and (n1.,12) is the cutent through the branch connecting nodes ‘nl and n2. The behavior ofthe module is defined by the analog statement within the module definition. Inthe resistor of Listing 23, the analog statement isa single line description of the voltage and curent relationship ofthe resistor related by ‘the contribution operator. {tis important to note that the contribution operator i a concise description of the behavior ofthe element in terms of its terminal voltages and currents. The simulator bbecomes responsible for making sue thatthe relationship established by the contribution operator is satisfied at each point i the analysis, This is accomplished vie the strict enforcement of conservation laws that the Verilog-A language semantics out FIGURE 27 High-Level system schematic, ‘The behavior of Figure 2.7 can be expressed compactly in the Verilog-A language as (derived in txms of the signal at (out), V(out) <+ dae (Kutv(in) ~ KptV(out)); ‘where the behavior i formulated in terms of (out). Alternatively using other con: structs within the Verilog-A language, the behavior can also be expressed as, V(out) <+ laplacena(v(in), (Ku), (Kp, 20; ‘where Laplace _nd{) isa transfer function representation ofthe behavior. These ‘behavioral consruets willbe discussed in mote detail in Chapter 3 2.3 Mixed-Level Descriptions ‘The Verilog language allows the designer the flexibility to model components at various levels of abstraction. Mixed-level descriptions ean incorporate behavior and structure at various levels of abstraction. Flexibility in choosing the level of abstraction allows the designer to examine architectural trade-offs for design performance and physical implementation ‘Analog System Description and Simulation 19i Analog System Description and Simalation ‘Mixed -Level Desctiptons One of the techniques available to designers for mixing levels of abstractions are ‘ixed:-level descriptions themselves - module definitions that incorporate both siruc- tural and behavioral aspects. In addition to mixing structure and behavior, the Ver- ilog-A language is designed to accommodate the structural instantiation of Spice primitives and subcireuits, within the module definition This methodology provides ‘path to final verification within the design cycle, when detailed models ae necessary for insuring adherence to performance specification. For example, forthe 16-QAM modem system, a block diagram ofthe modulator ‘module, qam_mod, could be defined as shown in Figure 28 ‘cos (2H, 8/4) gam_mod mout At) 008 (2nf,6+ 809) mt dea [aq Asin (Qnf.t+n/4) FIGURE 28 Architecture ofthe 16.QAM modulator, ‘The definition of module qam_rod can include behaviocal and structural aspects. In Listing 24, the module definition instantites components that provide the serial to- Parallel conversion ofthe incoming digital data steam. The QAM modulation is, ‘defined behaviorally in terms ofits mathematica representation. The signals and Parameters declared within the module definition can be shared between both the structural and behavioral aspects within the same module, providing a high-degree of Alexibitty within the design process. For example, in Listing 2.4, the signals a3 and ‘aq are used within both the structural and behavioral aspects of the 16-QAM module definition, LASTING 24 Verilog-A definition of 16-QAM modulator sinelude “std.va" Minelude “const.va" module gam_mod(nout, din, elk); nowt mout, din, lk: electrical mout, din, elk: paraneter real fe = 100.026; electrical ait, 4i2, dg1, dq? electrical ai, aq; serin_parout sipo(dil, di2, dgl, dq2, din, clk); 2a daailai, ail. ai2. clk 2a dagiag, agi, aq2, clk); real phase; analog begin phase = 2.0*'M Prvéc*$realtine() + ‘M_PI_¢; ‘Vimout) <+ 0.5*(V(ai)*eon(phase) + V(aq) *ein (phase) ) ona, endnodule ‘The signals ai and aq are the outputs of the 2-it DIA converters, The behavioral an potential FIGURE 214 Associated potential and flow reference directions fo a branch, ‘The reference direction fora potential is indicated by the plus and minus symbols at cach end ofthe branch, Given the chosen reference direction, the branch potential is positive whenever the potential of the branch marked witha (+) sign is larger than the potential ofthe branch marked with a minus -) sign, Similarly, the flow is positive ‘Whenever it moves inthe direction of the arrow (inthis case from + to =) Inthe Ver- itog-A language, for an electrical device. the potential would be represented by ‘V(p,n), and the associated flow would be represented by ¥ (p.m) ve.) FIGURE 215 Associated potential (voltage) and flow (current) reference directions for a branch it an elecrical system ‘The potential ofa single node is given with respect toa reference node. The potential ofthe reference node, which is called ground in electrical systems, is always zero. 2.4.3 Conservation Laws In System Descriptions ‘There are two types of relationships used for defining conservative systems. The first ofthese are the constitutive relationships that describe the behavior of each instance ofthe design. Constitutive relationships fora component or module can be described in the Veilog-A language or built into a simulator a Spice-level primitives, ‘The second set of relationships for conservative systems are the interconnection rela tionships which describe the structure ofthe network. Interconnection relationships ‘contain information on how the components are connected to each other and are only 26 Verilog-A HDL ‘Analog System Description and Simulation 2Analog Sptem Description snd Simulation TT Sigais in Analg Systems 8 function ofthe system topology. The interconnection relationships define the conservation of energy within the analog system, KPL and KFL can be used to determine te interconnection relationships for any type | of system, KPL, i illustrated in Figure 2.15, where the sum of the potentials around potential, ‘enuajod potential, * potential; + potentials + potentials + potential FIGURE 216 Illustration of Kicchof's Potential La generalized form of rchol's Vole Law for conservative systems the loop are zero KFL, likewise, i ilusrated in Figure 2.16, in which the sum of the {}- flows flow, + flows + flowy =0 AGURE 247 Ilustration of Ktchof's Flow Law’ a generalization of Ktchoft's Current Law fr conservative systems. flows into a node is zero, Both KPL and KFL are used torelate the values on nodes snd branches. The application of both KPL and KFL imply that anode i infinitely small s0 that there is negligible difference in potential between any two points on the node and there i a negligible accumulation of flow. 2.44 Signal-Flow Systems Unlike conservative systems, sigal-low systems only have a potential associated with every node. Asa result signa-flow port must be unidirectional. t may either ‘ead the potential ofthe node input), or it may assign it (output). Signal-fow termi nals are either considered input ports if they pas the potential of the node into a eom- ponent, or output ports if hey specify the potential of anode. A typical signal-flow component is an amplifier (Figure 2-18) with an input port in out, FIGURE 218 Simple signal-flow gain block representation, ‘defined as in, and an output port defined as out. The behavior would be expressed Viout) <+ atviin) ‘Changes in potential of te in port would be reflected as A*V (An) on the port out. However, any changes on the output port out would not be seen by the input port ‘Signallow port support a subset of the functionality of conservative ports in that KF is not enforced. As uch, one can always use conservative semantics to represent signal-flow components 2.5 Signals in Analog Systems 7 “he Verilog-A language supports the description and simoltion of systems used in many disciplines suchas letical, mechani, uid dynamics, and thermodynamics. ‘To accomplish this, Verilog-A uses the concepts ofa @tucipiine and nature 28 Verlog-A HDL Analog System Description and Simulation 29Analog System Description and Silaion Sina in Analog Systems for encapsulating the characteristics and physical quantities associated withthe different types of analog signals. A nature definition defines the characteristics of quant tiesto the simulator, while a @i.sc4p1ine definition composes one ot more ‘ature definitions into the definition ofan analog signal In Vetilog-A, the primary motivation for providing this level of detail using @dwcd.~ lines and natures within the language i o support model portability amongst different analog simulators. Standard definition of disciplines and natures pre- i=gte no parameter real g - 1.0; analog T(pin) <+ g*Z(pe,ne); PP I endmodule os FIGURE 222 Module definition of a current-controlled current source and Schematic representation 36 Verlog-A HDL ‘Analog System Deseription and Simulation 37Analog System Description and Simulation module vove(p.n,pe,ne) Anout pny pe. ne! pot electrical p.n,pe.nc; [> veows paraneter real g = 1.0; analog Vipin) <+ g*Vipe,ne): ‘endnodule neo FIGURE223 Module definition ofa voltage-controed voltage source and schematic representation, module covs (p.n,pe,ne) ; Amout p,n,pe,ne; electrical pinposner parameter 1 analog pe Vipin) <+ g*r(pesne): endnoduie FIGURE 224 Module definition of a Voltge-contrlled curent source and schematic representation, 2.7 Analog System Simulation Analog simulation involves solving systems of ordinary differential equation that ‘describe the system. The system of equations that define the circuit is ofthe ————— ‘Analog System Simon form: Ft, xu) = 0, where xis a vector representing the unknowns, & the time rate of change ofthe unknowns, and u isa vector representing the external stimulus to the system, The system of equations is derived from both the behaviors describing the ‘components and the interconnection or strutute of the components as shown in Fig- ure 2-25, design behavior formulation fm ric = 0 structure system of equations FIGURE225 The formulation of a system of equations from the behavioral and structural aspects ofa design using via formulation based on KPL and KFL for conservative systems). Simulation of an analog system requires an analysis ofall nodes in the system to ena ‘The anadog statement encapsulates a large-signal behavior forthe model vali for alltime, The large-signal model of a component isthe behavior expressed inthe time domain, From this large-signal definition of the mode, representations required for the simulation of other types of snalyses can be derived (Figure 3.1). For example, the linearization of the large signal model about its operating pont allows sinal-signal [AC analysis to be performed! Description Analyses Large-signal module Time domain definition (DC transfer curve AC smal-signal a FIGURE 3.1 Mapping of a modules’ behavioral descriptions into representations suitable fr different types of analyses, . 1. Linearieation ofthe large-signal made! about the operating pot ithe same technique ui lied by Spice ‘The behavioral statements within the anaiog block can include contol-low or looping constructs for defining the behavior of the module, These statements are sim: ilar to those found in many programming languages. Additionally, the Verilog-A lan- {guage provides different language constructs that can be utilized for representing ‘equivalent behavior, For example, in Figure 3.2 three different ways of formulating the behavioral construct for assigning the maximum of two values toa variable are presented!. All ofthese are equivalent representations using statement, expression, statement expression functional if (x > y) ° ee Geom yl ery: 0 = mawtx, yz FIcURE 32 Equivalent statement, expression, and functional Verilog language representations of 0 f(t, 9) and functional techniques respectively for determining the maximum value and assigning ito a variable The Verilog-A language introduces a class of behavioral constructs known as analog ‘operators that are used in defining the large-signal behavioral characteristics ofthe ‘module, Because of mathematical and other properties associated with analog opera {ors, there are special considerations in their usage. These and other issues associated with the use of analog operators willbe discussed in Section 3.4 3.2.1 Analog Model Properties ‘The behavioral descriptions with the Verlog-A language can be used to represent dif ferent types of behaviors. These can include: + Linear + Nonlinear ‘+ Piecewise linear 1, Theres atleast one more, albeit more obscure, equivalent statement method of determining ‘he marimum of two values isthe Verilog language, az Verilog-A HDL Behavioral Descriptions 43i Behavior Descriptions ee + Integrosditferential + Bventdriven analog or combinations thereo. All behavioral models ely onthe understanding of the mod. ler in terms ofthe formulation ofthe model and the models’ valid regions of opera tion!. The model must also show stable and/or continuous behavior between its various regions of operation. For example, the behavior of a resistor connected between two electrical type nodes p and could be represented in one of two ways. Fits as, Vip, n) <+ res*tip, nl; Tp, n) <+ Vip, nl/zes: From a perspective ofthe description of behavior fora resistor, the two formulations are equivalent. However, note that forthe condition, res == 0.0 the frst formulation handles this cave worry, bu the second generates a divide by 2er0. Similar conditions can occur forthe signals from which the behavior is formu lated. For example, a volage divider could be represented behaviorally a3, V(out) <+ V(numer) /¥(denom) ; HV (denom) ever goes to 270, which can happen during the course of a simulation ‘Fat initialization, a similar divide by zero condition eaa occur. Ii upto the modeler, with an understanding ofthe tsk at hand, to insure thatthe model is mathemati cally vali ‘The model developer mst also insure the model i stable of well-behaved. This prop «ty is most obvious in the continuity in both ime and value thatthe model shows. For example, Af Ue > 2.5) (out) << 5.07 1. The teratve nature ofthe solation of the system of equations used in analog simulation sentially dictates that the model be valid or wel bhaved for any potential rion of opts tion or input signal valves, ————— ‘Statement for Behavioral Desrptions else Vout) <+ 0.0; for the variable x as some arbitrary function of time, is discontinuous atthe output about the condition x == 2.5 for Vout}, in both time and value. This may or ‘may not be a problem, depending upon the typeof network to which the output signal, V(out) is atached. For resistive loads, these (pes of discontinuities do not present problems. However, for capacitive or inductive loads, his type of behavior will potentially cause problems for the simulation. The Verlog-A language provides capabilities forthe mode! developer to effectively handle such eases but sill cies on the developer for recognizing and utilizing these capabilities ‘The mathematical validity and stability of the formulation of a model are important issues to consider when developing a behavioral model, particularly during the test and validation ofthe model 3.3 Statements for Rehaviaral Descriptions In the Verilog-A language, all analog behavior descriptions are encapsulated within the anaLog satoment The analog statement encompases the contribution state ‘ment() that are used to define the eeationships between the input and outpt signals of the module tlements within the Verilg-A language allows thse contribution tements used in defining the analog behaviors tobe sensive to procedural and/or timing conto. ‘This section describes the statements used in formulating analog behavioral descrip tions. 3.3.1 Analog Statement ‘The anaiog statement is used for defining the Behavior ofthe model in terms of eon- tribution statements, ontol-flow, and/er analog event statements. All the sate ‘men((s) comprising the analog statement ae evaluated at each point during an analysis, The analog statement isthe keyword analog followed by a valid Ver- log-A statement 44 Verlog-A HDL. Behavioral Descriptions 45 FO——————— Behavioral Descriptions analog ‘Where isa single statement in the Verilog-A language asin the module resistor of Listing 3.1 {asTING 31 Resistor module illustrating a single statement attached tothe ‘analog statement. module resistor (p, n); Amout p, nz electrical p, ns analog Vip, n) <+ res*z(p, nis endmodule ‘The stalementatached to an anaog statement is usually a hlack statement delim ited by abegin-ena pair. analog begin ena, ‘The block or compound statement defines the behavior of the module s a procedural sequence of statements, The block statement is a means of grouping two of more Statements together so that they act syntactically Ikea single statement. For example, the module resistor of Listing 3.1 could be re-written using a block statement ag in Listing 32. LisTING 32 Resistor module illustrating a block statement attached tothe analog statement module resistor (p, n); inout p, nz electrical p, nz paraneter real res = 1.0. real volte; analog begin volts = res*(p, n); Vip, nm) <+ volts: ona, endnodule ‘The group of statements within the analog block are processed sequentially inthe siven order and at each timepoint during a transient simulation, This aspect ofthe \Nerilog-A language allows the module develope the ability to define the low of contol within the behavioral description ‘Statements of any block statement are guaranteed to be evaluated ifthe block state- ‘ment is evaluated. This propery, in conjunction with properties of analog behaviors described inthe Verilog-A language to be discussed in Section 3.4, has implications in the formulation of the analog behaviors for stability and robustness. 3.3.2 Contribution Statements ‘The contribution statements within the anaog block of a module form the basis of the behavioral descriptions used to compute flow and potential values for the signals comprising the analog system. The behavioral or large-signal description isthe math ‘ematical relationships ofthe input signals to output signals. Tn the probe source model described in Section 2.6, the relationships between input and output signals is done with contribution statements of the form: output_signal <+ £(input_signals) ; Where output_signal isa branch potential or flow source that isthe target ofthe contribution operator (<+) assigned by the value of the right-hand side expression, £(input_signals). For example, V(pouti, nouti) <+ expri; T(pout2, nout2) <+ expr2: 4, The evaluation ofthe entire group of statements wihin the analog black a every time Bolot sa departure from the semantics of he alway statement in dial Verlog I dp etlog, the evaluation ofthe behavioral models determined by moniaring and beeing os evens ofthe (gil signals. 46 Veriog-A HDL. Behavioral Descriptions 47 CC ]_ es‘Statement for Behavioral Descriptions are examples of potential and flow branch contributions respectively, The right-hand Side expressions, expr and expr2, can be any combination of linear, nonlinear, algebraic, or dfferential expressions of module signals, constants and parameters ‘A contribution statement is formed such that the outputs isolate! For example, given the foliowing transfer function for #9) Ys) = His)-X() 2 1) = Fx) the transfer function relationship canbe formulated in terms of the output, 3) for the large-signal response as, =) dy 2009 0 = 9420) from which, the behavioral relationship can be expressed in the Veilog-A language contribution statement as, Viv) <+ aae(viy))/R + Via: ‘Where V(y1, the potential ofthe signal y, or (0. and V(x) is the potential ofthe signal x, or (9 - Note that Only a potential or low source branch canbe the target of ‘contribution operator, je, no ead or integer variables, 3.3.3 Procedural or Variable Assignments In the Verilog-A language, branch contributions and indirect branch contributions? ‘reused for modifying signals. The procedural assignments are used for modifying integer and real variables. A procedural assignment inthe Verilog-A language is sim iar to that in any programming language: 1. The probe-source formulation doesnot equ hat the tpt cannot sso appearon he "ight hand side ofthe contribution operate In addition, an alterstive equation formulation Constructs presen in Seetion 3.62 for such cates when its not cas to Iolate the ope 2, Described Iter in section 3.6 real x; real y[1:12); analog begin x5 5.05 yi) =x ona In general, the left-hand side ofthe assignment must bean integer ora real identifier ‘or a component of sn integer or eal aray. The right-hand side expression can be any aubitrary expression constituted from legal operands and operators inthe Verilog-A language 33.4.Con ional Statements and Expressions ‘The Veilog-A supports two primary methods of alteing contol-faw within the behavioral description of a module which ae the conditional statement and the tr nary ot ? operator. The control-flow constructs within the Verlog-A language are used for defining piece-wise behaviors (near or nonlinear). The conditional state- ‘ment (or 4£-e1.e siatement is used to make a decision as to whether a statement is executed or not. The syntax of a conditioal statement is as follows Ae ( expr ) one Where the el. branch of the 4£-e1.e statement is optional. Ifthe expression eval- tates to true (tha is, has a non-zero valve), the fst statement wil be executed. I it ‘evaluates to false (has a2er0 value), the firststalement will not be executed, I there is fn elLge statement and expression is false the ele siatement will be executed [As previously described, the 4£-e1.8e statement can be used to define an analog ‘behavior that determines the maximum of two input signals (or values) asin Listing 33, LUSTING 33 Module definition illustrating use of 4£-e19e statements 48 Veriog-A HDL Behavioral Descriptions 49 SO —ehavoeal Descriptions Statements for Behavioral Descriptions module maximun(out, int, in2); The ternary operator (?:) canbe used in place ofthe ££ statement when one of two | Amout out, int, ind; values isto be selected for assignment, The general form ofthe expression i: electrical out, ini, in? conditional_expr ? exprl 1 expr? comes Ifthe conditional_expr is non-zero, then the value ofthe ternary expression is expr, else the value is expr2, The maximum module definition of Listing 3.3 can analog begin be written much more compactly using the emary operator asin Listing 3.6 df (v(int) > v(ina)) vout = V(inl); LISTING 36 Module definition illustrating use of ternary operator. module maximum(out, inl, in?) imout out, int, ind; electrical out, inl, in? vout = V(in2); Vout) <+ vout, ona, analog endnodue Vout) <+ ((W(ini) > v(in2)) 2 viind) : viin2y) Because the else part of an {£-e1.8is optional, thee can be con: ‘ondmodule fision when an e1.e is omited from anested if sequence. This is resolved by always ‘The distinction between the 4-61.80 and the ternary operators that the teary associating the ele with the closest previous 4¢ that licks an ewe. In Listing 3, the alae goce wid telnet Afr as howe tp ee ‘operator can appear anywhere an expression is valid inthe Veilog-A language, Con, versely, the f-e1ge siatement can only appear in the body of an analog or a LisTING a4 Proper association of eee within a nested 4£, block statement, AE ( expr ) ie ( expr? ) 3.3.5 Multi-way Branching ete ‘The Verilog language provides two ways of creating multi-way branches in behav- oral descriptions; the 4-o18e-4£ and the ease statements The most general way ‘of writing a multi-way decision in Verilog-A is with an 4-03, If that association i not desired, atbegin-ena block statement must be used to force illustrated in Listing 3.7, the proper association, as shown in Listing 35. A€ construct as LISTING 3.7 Multi-way branching using the 4. -L€ statement construct, LisTING a5 Forced association of an} using block a oe 48 ( expr!) begin . | etse Lf ( expr? ) sf (expr?) aus ana Tatacement3> 50 Veriog-A HDL ee Behavioral Descriptions 51Behavioral Drips Analog Operitors ‘The expressions are evalvated in order; if any ofthe expressions are true (expe, expr2), the statement associated with it wil be executed, and this will terminate the whole chain. Each statement is citer a single statement oF a sequential block of stte- ‘ments. The last else part ofthe 4£~elge-L£ construct handles the none-of-the- above or default case where none ofthe other conditions are satisfied. Sometimes, there is no explicit action forthe default; in that cas, the trailing e2 8 statement can be omitted or itcan be used for error checking to catch an unexpected condition, For example, the behavior of a dead-band amplifier (Figure 3,3) using the 4. db_hign Vin) YiGURE33 Input-output relationship for a dead-band amplifies. ‘4 construct, the behavior can be represented in the Verlog-A language asin Listing [Note thal the variable vout, will be piece-wise continuous in value across the range of v(in), 3.4 Analog Operators Analog operators inthe Verlog-A language are used for formulating the large-signal ‘behavioral descriptions of modules. Used in conjunction withthe standard mathemat ‘cal and transcendental functions (Appendix A), with analog operators the modeler can define the components constitutive behavior. Similar to functions, analog opet tors take an expression as input and return a value. However, analog operators differ in tat they maintain internal state snd their output is a function of both the eurent input and ths internal state, ‘The Verilog-A language defines analog operators fr: + Time derivative + Time integral Linear time delay + Discrete waveform filters * Continuous waveform filters ‘+ Laplace transform filters ‘© Zransform filters 38. LisTING 34 Dead-band amplifier behavior using the 4. -1£ statement 3.41 Time Derivative Operator Ce ‘The dat operator computes the time derivative of its argument, analog begin Af (V(in) >© @b_high) aac (expr) vout = gain*(V(in) - db high); else {f (V(in) <= db_low) A vout = gaint (V(in) + db_low); Flora else vout = 0.0; FIGURE34 Prototype of at time derivative analog operator and mathematical viout) <+ vout: Ceo ena 52 Veriog-A HDL Behavioral Descriptions 33 ree... ... fl4a returns zero, Application of the €4t operator results in a zero at in. Consider the example module definition of Listing 3.9 taking the time derivative ofthe input signal LISTING 39 dat analog operator example, module aat_op(out, in}; Anout out, in; electrical out, in; parameter real scale = 1.0e-6; analog V(eut) <+ scaletade (V(in)); endmodule ‘The results of applying a 100KHz sinusoidal signal, with amplitude of 1.0V, tothe in signal of the module, with scale set o its default value of 1.0e-6 are shown in Fig- ure 3.5, 78 50 25 we 00 28 “5.0 78 ° Bu tou 150 20u FIGURE 3.5 Time-domain analysis with the @atanlog operator of Listing 3.9, {tis important to consider the input signal characteristics when doing when using the {4a operator (as with all analog operators). Without setng the parameter scale to |.06-6, the output ofthe module would have been 6.28e6 volts withthe same input ‘Analg Operators signal applied. The model developer should be aware that when differentiating an ‘unknown input signal, a fast varying ‘noise’ component can dominate the true derivative of the signal of interest 3.4.2 Time Integral Operator ‘The at operator computes the time-integral ofits argument. latexpr, ic, reset) Jew di vic FIGURE 36 Prototype of Lt time integral analog operator and its mathematical representation. ‘When specitied wit inital conditions, the 44 operator returns the value ofthe initial condition in DC. Without inital conditions, 14 multiplies i's argument by infin ity in DC analysis. Hence, without initial conditions, 44 must be used ina system description with feedback that forces its argument to zero!. The optional argument eset allows reseting of the integrator to the intial condition of ic value. Applica tion of the 44t operator results in a pole atthe origin. ‘The module definition of Listing 3.10 illustrates the use of L&t operators with differ ‘ent values of inital conditions specified LUSTING 340 dt analog operator example module idt_op(out1, out2, in}: Anout out), out2, in; electrical out, out2, in; parameter real scale = 1.0¢6; analog begin V(outi) <+ dae (scale*Viin), 0.0); 1, allure to do so wl aut ina ystem description hat snot solvable ie, convergence will ot Wely be ached, 54 Veriog-A HDL Behavioral Descriptions 55 Bi eemermmeememermemmemeeemmnmeeeeemensirs cag eee— ‘ebavoral Depts ‘Analg Operators Viout2) <+ 14e(scale*v(in), 2.0); 3.43 Delay Operator ona ‘The doday operator implements a ranspor, or liner time delay for continuous endmodule me i * ‘The results of applying V in) as a clock with a pulse period of 50m tothe input of the module of Listing 3.10 which die ony in the inital condition parameter (0.0 ‘and 2.0), are shown in Figute 3.7. Both integrator modules were applied scaie 60 50 40 30 20 10 00 a0! 200 on 600 ‘800 t00n FIGURE 37 Time domain analysis withthe 4a analog operator with and without initia conditions specified as per Listing 3.2 Parameter valves of 1.06, waveforms (similar to a tansmission line), delay(enpr, dt) em) = ouput -/- ‘ HAGURES Prototype of eLay analog operator and graphical representation ‘The parameter @t must be nonnegative and any changes tothe parameter dt are ‘ignored during simulation (the intially specified value for at is used). The effet of the @aLay operator in the ime domain isto provide a direct time-trastation ofthe input. An example of the delay analog operator is illustrated in Listing 3.11 LISTINGS: GeLay analog operator example module delay_op(out, in); Amout out, in; electrical out, in; analog Viout) <+ detay(viin), Son); endnodule 56 Verilog-A HDL Behavioral Descriptions 57 CC| ‘The results of applying a signal V (in) (Qwo-tone sinusoidal) tothe input ofthe mod- Lule of Listing 3.11 is shown in Figure 39. For AC smal 50 aol{| vow SS ~~ 20 10 ° 10 20 “30 oa vin) ° ‘500 100n 100 ‘2000, FIGURE 39 Time domain analysis with the deLay analog operator. ‘operator introduces 2? phase shift 3.44 Transition Operator ‘The transition operator smooths out piece-wise constant waveforms. The ‘transition ier is used to imitate transitions and delays on discrete signals. transition(expr, dt, tr, tf) expr) output) © [FIGURE 340 Prototype of tranadtion ar representation. Log operator and graphical ‘The input expr tothe transition operator must be defined in terms of discrete states!. The parameters dt, tr. and ¢£ are optional tothe transition analog ‘operator. If dis not specified, itis taken to be zero. I ony the tx valve is specified, the simulator uses it for both rise and fall times. In DC analysis, eranaition Passes the value ofthe expr directly to ite output Consider the example of Listing 3.12 illustating the effect ofthe transition time parameters versus the magnitude of different input step changes. LISTING a42 tranaitdon operators with different step changes. module transition_op(outi, out2, in); Anout outi, ou2, in; electrical outl, out2, in; real vin: analog begin // discretize the input into two states Af (VUin) > 0.5) vin = 1.0 a vin = 0.0; V(out1) <+ transitien(vin, 2n, Sn, Sn); V(out2) <+ transition(2*vin, 2n, Sn, Sn); ena endnodule ‘The input expression tothe transition operator, vin, is discretization of the ‘input signal and results inthe pulse shown in Figure 3.11 with the esulting outputs Note that the rise and fall times ae independent of the value being transitioned. In ‘ddition, the input to transition operators i best kept under the control ofthe modeler = in this example with a simple 4-e1.8e construct is aplied to some arbitrary input signal V(nn) to generate the discrete states that become the input tothe traned.— ‘elon operator. 1. For smoothing piece-wise continuous signals ee the slew analog operator. 58 Verilog-A HDL Peter Behavioral Descriptions 59‘Behavioral Dseriptons ‘Analg Operators 25 20 15 10 ne os Vloutt) Voouta) oo}-— 05, 0 200 aon on ‘0m 100n FLcURE 3.11 Time domain respons ofthe tzanadtion analog operator of Listing 3.12 to discontauous input changes of ferent magaitades, ‘Another characteristic ofthe transi tdon operator is exhibited when the rise and fall imes are longer than the specified delay If interupted ona transition, tranad~ ‘eon will try to complete the transition inthe specified time. ‘+ ICthe new final value level is below the value level atthe point ofthe interruption (the current value), transition uses the old destination asthe origi, + Ifthe new destination is above the current level, the first origin is retained, In Figure 3.12, arising transition is interrupted nes its midpoint, and the new destin tion level ofthe value is below the curent value. For the new origin and destination, ‘transition computes the slope that completes the transition from the origin (not the current value) in the specified transition tim. It then uses the computed slope to transition from the current value to the new destination Input change FIGURESA2 Response ofthe tanston anlog operator toa quckly-varyng input (less than tr and/or t £). - * a ‘Taking the module definition of Listing 3.12, the input signal is changed to create pulses of shorter duration. The result is shown in Figure 3.13. Because the tanaitdon function cannot be linearized in general, itis not possible ‘o accurately representa transition function in AC analysis. The AC transfer function is approximately modeled as having unit transmission forall frequencies in all situations. Because the transition function is intended to handle disrete-valued signals, the smal signals present in AC analysis rarely reach transition functions, 60 Verlog-A HDL Behavioral Descriptions 61 eee oeorl Deserpons ‘Analog Operators 10 Viouta) vin os Viout) 00 ° jon 200801 an SN FIGURE 3.3 Time domain response ofthe transition analog operator of Listing 3.12 to discontinuous input changes of different magnitudes asin Figure 3.12 but with pulse widths shorter than the rise ad fallanes ut tie teamed ton operator. 3.4 Slew Operator ‘The s.Lew operator bounds the rate of change (slope) ofthe waveform. A typical use for sew isto generate continuous signals from piece-wise continuous signals! slew (expr, mpsr, mast) expt) ouput) _ oy a to b FIGURE.3.16 Prototype of eiLew analog operator and graphical representation 0 Verlog-A HDL When applied, sew forces all transitions of the input expr faster than mpsz to change at mpsx for postive transitions and limits negative transitions toms .The ‘mp3 and nnsr arguments ae optional. The parameter mpsr must be greater than O and ms must be less than 0. Ifonly one rates specified, its absolute value is used {or both rates. If no rates are specified, slew passes the signal trough unchanged. f the rate of change of expr is less than the specified maximum slew rates, slew returns the value of expr, Consider the following example forthe effect of different slew rales on the slew analog operator: LISTING 313 Low analog operators with different slew rates module slew_op(out!, out2, in); Amout out, out2, in; electrical outl, out?, iny analog begin V(outl) <+ slew(Viin), 5e8, -5e8); v(out2) <+ slew(V(in), 169, -1e9); ondmodule ‘The results of applying a sinusoid of § Vpp anda frequency of 25MH2 (which defines ‘maximum slew rate of about 1.6e9 V/s) to the signal in are shown in Figure 3.15. In DC analysis, eLew simply passes the value of the destination tots output In AC ‘small-signal analyses, the sLew function has unity transfer function except when slewing, in which cae it has zero transmission through the sew operator. |. For dscrete-valued signals see transition, Behavioral Descriptions 63 2‘aera Davin Senominao ofthe user fnto ofthe fle. The numerator o denominator an ” becxpesed nthe fort: + tnptace. ap in whichthe sos nd pls ofthe eased a puso real nib peiyng he rea imainry components ofeach eat po + Aaptace_nain which ie zeros and ples ofthe er resected poh mM ial confit from lowest reer tote Mee + Anpace_e4in which the zo ofthe ie ae specified pir of eal am oo ber, specifying the el adimagiaycomponcras ofeach tse Me fe ete fe ate pelted polynomial corfcions om lowes ce tom he a 20 = + Aaptace_ap in whic te zt ofthe fie respected a yaoi oe 40 sins rom the lowest orm othe highest The pls ot fe fe ee feds paisa eal uber specijng eral and Sogiogy one cre chp, i eT Pol 3URE2.18 Time domain analysis of sLew analog operator with differing slew s specified as in Listing 34 3.4.6 Laplace Transform Operators ‘The Laplace transform operators implement lumped, continuous-time filters. Laplace _nd(expr, numer, denom) me HO = DG) FIGURE 3.16 Prototypes of diferent forms of he lplace analog operators andthe \ransferfunetion representation, ‘The laplace transform analog operators take vector arguments tha specify the coefi- cients ofthe filter. The vectors numer and denom represent the sumeralor and. ‘These diferent forms of specifications forthe numerator and denominator allow for {our diferent variants on specifying the filter coefficients." All ofthe laplace analog ‘operators represent linear time-invariant (LTD ters which requie thatthe values ef the filter coefficients cannot change during a simulation. Hence, only numeric literals Parameters or expressions of these are allowed for defining the filter coefficients. The ‘coefficients are arays specified using the Verilog HDL concatenation operator (_)) for creating arrays from these scalar constant expressions. For example, consider the pole locations ofa normalized S'th order Butterworth low ‘ass filter with 3-dB bandwidth of {rad/s as shown in Figure 3.17. ‘The Verilog-A numerator-poe laplace operator representation of Butterworth filter would be: LISTING 3.16 Laplace analog operator example using Laplace_np. module laplace_op(out, in); Anowt out, in; electrical out, in; analog 1. Appendix includes references to Maia scripts which ae useful for generating Veilog-A. Soninuous and discrete domain iter rom the ite: specications such at pastop band nd tipo and sampling ate Cor discrete ler). 64 Veriog-A HDL Behavioral Descriptions 65 Br s—s—CEE Behavioral Descriptions $F Anato Operators i analog Vout) <* laplace_na(viin), (1.0) -0.31+jo95 X €2.0, 3.236, 5.236, 5.236, 3.236, 1.0 1); 0.81 +j0.59 X endmodule “10. : ‘The coefficients ate specified from lowest to highestorder term (inthis case from s° to 5"), The laplace analog operators are valid for both transient and small-signal anal yses. Shown in Figure 3.18 i the step response for order = 2 to order = 6 for Butter. ‘worth low-pass filters wth 34B bandwidth of 1 rad/s. The Bode plots for the same -0.81 -j0.59 x " -0.31-j0.95 x FIGURE.17 Pole locations of Sth order Butterworth low-pass filter. Viout) <+ Laplace mp(v(in), (1), ( 0.62, 0.59, -0.81, -0.59, 0.31, 0.95, -0.31, -0.95, -1:0, 0.0); endnodule [Note that the real and imaginary pairs forthe zeros can be specified in any order. Con- versely, the laplace transform operator can be expressed inthe polynomial form, The corresponding Butterworth polynomial ofthe filter of Listing 3.14 is L HG) = > = ss 7 Sy 3.2365" + 52368" +5.236s"+ 3.236041 ‘The Butterworth polynomial can be expressed inthe polynomial or numerator: 0; i= 4-1) begin iregli] = dregli - i); ena ireg(0) = res; ena Viout) <+ transition (ires[width-1], In, 1m, in); ona, ‘The outputs of two peeudoandom bit aequence generators are shown in Figure 330 fora period of 100n. 60 50 40 @ 3° 10 to U U 49 60 50 40 30 © 30 +0 oo 49, 2u 4u eu 8u tou {FIGURE 3.30 Time domain results of pseudo-random bitstream generator using the tamer analog operator and tvo different shiftregiser widhhs and taps, (0 with wideh = 10.and tap =7 and (b) with width =9 and tap = 3 8 Veriog-A HDL Behavioral Descriptions 9Behaviors Desriptions ‘Addins Constructs 3.6 Additional Constructs ‘The Verilog-A language provides some additional behavioral constructs, especially ‘useful inthe definition of high-level behavioral models. These include access to the simulation environment, additional methods of formulating behaviors, and iterative statements. Some ofthese have already been introduced indirectly, but will be discussed in more detail in this section 3.6.1 Access to Simulation Environment ‘Access to the simulation environment can be necessary for describing behaviors that «an be dependent upon external simulation conditions. For example, the following Srealtine() Stemperature() fare Verilog-A defined system tasks that provide access tothe conditions under which the component is being evaluated. The Srealtdma() system tasks accesses the cur- ‘ent simulation time and allows custom independent sources to be defined inthe lan ‘guage. The ambient temperature, returned by the Seemperatuxe() system task, can bbe used to define temperature dependent models suchas semiconductor devices ‘The modeler has some degree of contol over the timestep utilized during the course ‘of a transient simulation via use ofthe Bound_step() function. The real-valued argument to bound_st.ep() indicates the maximum timestep that the module ‘equites for meeting its own accuracy constrains; the simulator can make a smaller timestep based on its own accuracy constraints of those of other modules. An exam: ple of the use of bound_st.ep() is provided in Section 55 ofthe applications ehap- ter, ‘Addltionaly, it ecomes useful to define behaviors conditionally upon the current ‘snalysis. Fo this purpose, the analyai.a() function is provided. anadyi.a() takes 8 string argument that js a descriptor of the analysis type to test for. For example, analysis (de") ‘returns 1 duting DC analysis, such as that prior to transient analy ‘mine the inital operating point, and O otherwise. Similatly, fetus 1 during a transient analysis, and 0 otherwise, An example of the use of ‘ana yi.) for inital conditions is provided in an example of Section 3.6.2. 3.6.2 Indirect Contribution Statements ‘The probe-source formulation is the primary method of formolating analog behaviors. lt provides clear and tractable description of inputs, outputs, and their relationships inthe module definition. However, in all cases i is not necessarily possible nor com, ‘venient to formulate behaviors asa function ofthe output signals. These cases occur commonly while developing purely mathematical models or modeling multi disc plinary components, Im these cases, the Verilog- language provides the indirect contribution statement. ‘The indirect contribution statement allows forthe specification ofa behavior in teras ‘of aconditon that must be solved for (as opposed to defining an output). The indirect contribution statement allows descriptions ofan analog behavior that implicitly spec. ites branch potential in fixed-point form. This oes not requite that behavioral rela. ‘ionships be formulated in terms of the outpus ‘The general form of the indirect contribution statement is: target : branch == £( signals ); ‘Where target represents the desired ouput, branch can be either of the following. + An implicit branch such as V (out) ‘+A derivative of an implicit branch suchas A€e (V (out) ‘+A imegral ofan implicit branch such as £at (Vout) ) ‘As with contribution statements, £( signals ) can be any combination of linear, Aontinear, algebraic, or differential expressions ofa modules input or output signals, cconstans, and parameters. For example, the ideal op amp, in which the output is riven tothe voltage that results in the input voltage being zero. Using indirect conti bution assignments, the opamp model could be written! V(out) = V(in) == 0.0; pate | The behavior can alto be expressed in he probe source formulation as: V(out) <+ vioue) + Vian) 80 Verlog-A HDL Behavioral Descriptions 81 eeDeserts lon Contr ‘which can be read as: “determine V (out) such hat V (in) == 0°. The indirect contribution statement indicates that the signal out should be driven wit a voltage source and the source voltage value should be solved such that the given equation is satisfied. Any branches referenced in the equation are ony probed and not driven For example, te following differential equation and inital condition has a known solution of sia (ayy) feo oa a gs % Using indirect contribution statements, the behavior would be represented as: LUSTING 321 Indiect contribution statement example, analog begin Af (analyais(*do")) Vax) <+ WO; else Vide) <+ ABE (V 00) Vix) + dae (vides) ona, =wO*WORV (x) For DC (which includes transient analysis initialization), the signal xis set tothe inital condition of w0 by using the analy #.0() function within the conditional of the 4felge statement Note that the ele statement branch ofthe 4£-el ge, statement contains at operator. This is permissible because the analy () statement has static properties (refer to Section 3.48). ‘The contribution statements and indirect contribution statement modelling methodol- gies provide similar functionality. Use of one or the other depends upon the particu lar modelting task at hand. However, asa generat rule, the two diferent methodologies are not mixed. 3.6.3 Case Statements As introduced in Section 3.3.5, the case statement is another statement-level con struct tat allows for mull-way decision tests, The statement tests whether an expres ion matches one of a numberof other expressions, and branches sceordingly. The ‘ease statement is generally used in the following form: case (pl) 0: Setrobe(*pi == 07); 1: Satrebe(*pl == 1"); default: Setrobe (“pi endcase. far, pls ‘The expression within the case statement (p1) is evaluated and compared in the ‘exact order to the came items (0, 1, and @efault) in which they are given, Dur ing the linear seach ofthe came items, if one of the cae item expressions matches the case expression given in parenthesis, then the statement associated with that ase item is executed. In this example, if pl == 0 or pl == 1, then we wil pint a message coresponding to heing either 0 or fall comparisons fail, and the default item is given, then the default item statement is executed. Ifthe default statement isnot given, and all ofthe comparisons fail, then none ofthe came item statements ae exectted. Inthe example, for any ‘ase other than pt being either 0 or 2, we print a message indicating the valve of pa 3.644 Iterative Statements ‘The Verilog-A language supports three kinds of iterative statements. These statements Provide means of controlling the execution ofa statement zero, one, or more times. Fepent executes a fixed numberof times. Evaluation ofthe constant Loop_ent_expr decides how many times a statement is executed repeat ( loop_ent_expr } wae executes a until the Lloop_test_expr becomes fal the Loop_test_expr stats out fale, the is not executed af 82 Veritg-A HDL Behavioral Descriptions 83 eeeBenaviorl Decrgtins Developing Behavioral Mod while ( loop_test_expr ) for is an iterative construct that uses a loop variable for ( init_expr ; loop_test_expr ; post_expr ) ‘ or controls execution ofits associated statement() by a three-step process as follows: ‘+ Execute init_expr, oran assignment which is normally used to initialize an integer that controls the numberof times the is executed ‘+ Evaluate Loop_test_expr - if the result is 2ro, the for-loop exits, and ‘ot zero, the for-loop executes the associated + Execute post_expr, or an assignment normally used fo update the value ofthe Toop-control variable, then continue ‘As the state associated with analog operators cannot be reliably maintained, analog. ‘operators are not allowed in any ofthe thee looping statements Developing Behavioral Models For both novice and seasoned mode! developers, a methodology for developing and validating behavioral models is essential. The process of developing a behavioral ‘model should provide fora development of an intuitive understanding ofthe model as ‘well asthe system in which i wll operate In contrast to digital simulation which is actvity-drected and the signal that eect a model can be easily isolated, behavioral ‘models defined for analog simulation must account forthe loading and timing (o lack thereof) in the whole system. 3.7.1 Development Methodology : ‘A methodology for developing behavioral models should encourage a process of step- “wise refinement from the concep, to implementation and validation of the model. The conceptual stage involves developing an understanding of what the behavioral mode! is to accomplish in terms of capabilites and performance and other specifications ‘The formulation, preferably beginning from an existing model, isthe factorization of Concept ‘iGUnE:331 Step-wise methodology for development and refinement of behavioral modes meinen ‘that specification into structural and behavioral components and its actual implemen tation. Verification and/or validation ofthe model includes the development o test benches that canbe used to test the Behavior of the module tothe original specificn- 9s. The methodology and development uted for verification and validation ofthe ‘model can also be applicable in the verification ofthe final circuitlevel implementa tion. 3.72 System and Use Considerations ‘A module defined in a behavioral language such as Verilog-A can be used as a com- PPoneat within diferent types of systems and ths should be reflected in the verfica tion phase ofthe module. For example, developing a behavioral model for use as a component within library would require much more rigorous formulation, as well as have more stringent criteria for validation, than a model developed strictly for we as a ‘component in one specific design. ‘Understanding the contest of use can also help the model developer make appropriate decisions for accuracy as well a for efficiency in simulation, The transition analog operator, which conversa discrete input toa piece-wise linear output, is charac~ terized in terms of rise (tx) and fall (:#) times ofthe output Pwl_output = transition(disc, ta, tr, tf); Using very small values for tr and tf, relative tothe overall length ofthe simulation ‘canbe very costly in terms of simulation time, Moreover, the resulting fast changing. 84 Verilog-A HDL Behavioral Descriptions 85 re‘Bevleal Descriptions ‘output will not necessarily reflect the physical system or the underlying implementa tion, Similar considerations can be made when defining the sensitivity of a model to its inputs asin the use of tolerances in the exoma operator 3.73 Style ‘One of the major benefits of HDL-based design isthe ability to convey and reuse designs that are represented at a high-level of abstraction. Tis ability to commu cate the design information effectively amongst a group of designer is enhanced by adopting consistent and agreed-upon techniques of style for the development of models, For example, the following are some ofthe common denominators in the devel- ‘opment of behavioral models that are easly defined ‘+ Port ordering convention inputs fist, then outputs o vce- versus) ‘+ Degree of parameterization ofthe model and naming convention. ‘+ Use ofthe Verilog pre-processor for enabling consistency and code documentation purposes, ‘+ Coding style (layout) conventions fr the module definitions. ‘The basic underlying theme is to plan for model reuse, 86 Verlog-A HDL os Declarations and Structural Descriptions CHAPTER 4 i 4.1 Introduction Structural definitions inthe Verilog-A language are the primary mechanism by which ‘hierarchical design methodology such as top-down is facilitated for analog and ‘mixed-signal designs. The Verilog-A language sllows analog and mixed-signal sy$- tems to be described by ase of components or modules andthe signals that intercon- ‘ect them. The connection of these modules is defined in terms ofthe parameters, a5, well asthe ports or connection points, declared within the module definitions. The ‘declaration of parameters and ports within the module definition define the interface. ‘The interface definition determines how the module will be instantiated as pat of a structural module definition or as a component within a Spice nels. ‘This chapter overviews the parameter, port, local variable and signal declarations, as well as module instantiations within the Verlog-A language. Ths chapter also looks at how module definitions relate to thei instantiations. 4.2 Module Overview ‘A module inthe Verilog-A language represents the fundamental user-defined type. A. ‘module definition can be an entire system, or only a component within a system. A. OO Declarations and Structural Descriptions 87 Fy Imnnrreeeneeeeenemmenemernrt cn ce— Deciaratins and Structural Desrptons ‘module definition can bean ative component inthe system in which it effects the signals in the system, either dependently or independently. Conversely, a module can be a passive component which only monitors activity in the system, performing Func- tions associated with test benches, (Other than adhering to the constructs ofthe Verilog-A language, there are no restric. tions on the typeof systems that can be represented and how the representation is ‘defined. Modile descriptions can include any number and type of parameters, be an entirely structural or behavioral description, or include aspects of both structure and behavior ‘The general constituents of a module definition include the interface declarations and the contents. The interface declarations consist of both the port and parametric decla ‘ations ofthe module. The module contents can be composed of structural instantiations, behavioral relationships or both Fo illustration purposes, the Verilog-A. | ampitier =| cain Stage Stage sow rate: £00) 5 ew rates ae”, FIGURE 58 Basic thre stage architecture ofan op amp. A differential input amplifier feeds a second gui stage that drives a cutent output stag. 53.1 Model Development ‘A variety of modeling lvels can be used to describe the operational amplifier, These ‘ange from a simple fonctional model with a gain equation to sophisticated models with pole and zero effets, as well as noise behavior, offset and drift effects “The first example uses a simple model useful for top-level architectural studies. The symbols to represent the behavior of the basic sages of the op amp ate shown in Fig ure 59. ee Vin Rin FIGURE S9 Conceptual mode! of the stages inthe behavioral model forthe ‘operational amplifier ‘The input impedance for the op amp is modeled witha simple resistor across the di {erential input. The frequency behavior ofthe fist gain stage is represented by pass= ing the signal through a laplace transform function fier. Te dominant pole introduced in the second gain stage is modeled using the analog operstor in conjunc tion with a esstor and acapacitorR,-C,. Note the slew ate of the model isthe rate at which the capacitor canbe charged! and discharged in tis RC low pass filter. The voltage-controlled voltage source is used lo create azero-impedance output stage with infinite sourcing capability. In higher-level models the output stage usually contains output impedance and output voltage swing limitation characteristics, These effects are not included in this model ‘The Vetilog-A module definition ofthe op amp using the conceptual model is shown in Listing 5S. LISTING Ss Verilog-A model ofthe operational amplifier ‘include ‘etd.va" “include “const.va" module opamp(inn, inp, out) Amout inm, inp, out electrical inm, inp, out; paraneter gain = 250k: rgm = 2.3: ce = 30D; rin = 2Meg: 122 Verilog-A HDL. 123‘ABase Operational Ampiter electrical vin, vor analog begin T(inp, inm) <+ V(inp, inm) /rgm: V(vin) <+ laplace_nd(gain*V(inp, inn), (1.0 9,€1.0, $.0a-7 1) I{vin, vo) <+ Vivin, vo) /xgm: Tivo) <+ Ade (ec*V(vo)}; viout) <+ Vive); ena endnodule For the purpose of the Verilog-A model development, atest structure symbol, as shown in Figure 5.10, is uilized to encapsulate the amplifir. In addition to develop- Gain = 250k GB=1 MHz FIGURE 10 Spice schematic ofthe operational aml Gevelop and characterize the model, er test bench used to {ng the behavioral model, the Verilog-A language i used in the characterization ofthe ‘operational amplifier. Here, we will develop a module that sets up te step input and ‘measures the setting time atthe output ofthe op amp, Listing 5.6 shows the circuit file forthe operational amplifier circuit used to test the model: LISTING &6 Spice netlist of the operational amplifier tet bench + basic operational amplifier -verilog “op_amp.va" Vb inp 0 de 0 Vin 10 de 0 ac 1 sin(0 10m 1k 0 0) xampi inn inp out 0 opamp Rin 1 inm 10k RE inm out 100k Rload out 0 100k Choad out 0 20p -p tac dec 100 0.1 10Meg Tevan 10u 3m send ‘The magnitude response of the op amp for AC small-signal simulation results of the operational amplifier are shown in Figure 5.11. The bode plot shows both the low and high-frequency poles ofthe op amp. 124 Verilog-A HDL 125108 tot unity gain 10? dominant ole 10° 102 secondary pole aca 1? 10? 0? 108 108 10° FIGURE S.1 AC small-signal magnitude response of the behavioral model ofthe ‘operational amplifir. “The op amp transient response toa sinusoidal input verifying the functionality ofthe ‘model is shown in Figure 5.12 0.10 Ving. 0.05 Carta 0.00 0.05 16 Tom 20m ‘am ‘FIGURE 5.12 Time domain response of the behavioral model of the operational 5.32 Settling Time Measurement ‘Measuring the settling time ofan operational amplifier can be automated by develop- ‘ment ofa Verlog-A module that acts as atest bench for the device under test. The conceptual approach i illustrate in Figuee 5.13. A measurement module sets up a stimulus ‘Measurement Module Device Under Test Tmeasurement FIGURE 13 Setup for measuring the s ng ime of an op amp. stimlus tothe Device Under Test (or DUT) under known conditions and records the results. At the end ofthe simulation, the measure results are summarized. ‘The modelo (Listing 5.7) performs the measurement using a tdmex analog opetatn {o inialize a step onthe stimulus signal that provides the input to the operational amplifier. The measurement module then senses the crossings of the output ofthe ‘module when they are within +/- 9 of the final state value, The times of the crossings are recorded, the setlng time being the difference between te latest crossing time and the start of the stimulus step input {LISTING 57 Verilog-A model of setling-time test bench measurement module settling_test (stim, meas) Anout stim, meas; electrical stim, meas; paraneter real vetep = 5.0; Paraneter real tetart = 1.04; Parameter real interval = 10,0u; Donte real vstin: " real last; analog begin 77 generate stimolus 126 velop AHDL 127 7”@(timer(estart)) begin vetim = vatep; last = tstart; ena V(stim) <+ transition(vstim, 0.0, 1.0n, 1.0); // measure results - op amp is in inverting G@(crows(V(meas) - 1.05*vetep, ~1.0)) begin last = Srealtime(); end G(cross(Vimeas) - 0.95*vatep, +1.0)) begin last = $realtime(); ona // report at end of measurement interval @(timer (interval) begin Satrobe(*settling time = tg s.*, last ~ tstart); ena ona endmogule 128 Verlog-A HDL ee ‘Vota Repoatr ‘The result of the measurement is printed tothe standard ouput sing the Setrobe 1.00 078 0.50 0.28, 0.00 0.25 bo You «20u~*S=C« USCC FIGURE 3.14 Schematic and waveforms showing the measurement process for the setlng time measurement ofthe op amp. system task, The results ofthe measurement simulation are shown in Figure 5.14. The results forthe simulation are recorded tothe standard output as settling time = 2.840-06 s. 5.4 Voltage Regulator ‘The architecture ofthe voltage regulator (Figure 5.15), is composed ofa bandgap rel erence model, the operational amplifier model from Section 5.3, a module to repre= sent the current of the op amp, and a switch model. The bandgap reference circuit ‘hich a curve-fitting equation to define the output voltage. The equation includes the effect of supply voltage and temperature variation. The equation was derived from, extrapolated data obtained from transistor-evel Spice simulations, raceabe to actual 129 es‘Votiage Reptatae FIGURE 15 Voltage regulator composed of modules fora bandgap reference, en ewitch opamp. and opanpecureat mona, = silicon behavior Te references connected an amplifies sabe tat buts the Yoltage (033 vols and provides the coment necessary to dive the Toa. A sich model connects the reference voltage tthe amplifier thatthe voltage can be "itched to zero fr power down applications, The switch model was reused inthe current load model that represents the curent equred by the amplifier This ils trates how another module canbe added to include the current loading requirements of behavioral models. Separate modes can be wed, or the behavior ean be included in the functional defisition ofthe module, depending pon design requirements and ‘modeling methodology Atthe heart of most voltage regulators in integrated circuit design is a bandgap voltage reference (Listing 5.8). The voltage is proportional 9 Vag the band-gap vollage of silicon, anda thermal voltage Vp evaluated at a given temperature. With careful design a low voltage drift with respect to temperature canbe maintained throughout a siven temperature range. Theoretical calculations can predict the fist order behavior of the generated voltage, but secondary effects due lo differing manufacturing processes must be considered, and the model tuned to match performance, LisTinc 54 Verilog-A model of bandgap reference 11 bandgap reference “include “std.va" “inelude “const.va" module bandgap(vee, vbg, temp): Amout vec, vbg, temp: electrical vee, vbg, temp; parameter real vby_nom = 1.0; parameter real icc_nom = 10.0e-6; Feal tempC_sup: real vec_appl; analog begin ‘tempC_swp =(V(temp) - 27.0)/27.0 vee_appl =(V(vec) - 5.0)/5.0; T(vec, gna) <+ (icc_nom - 2.78e-8*tempe)* (1.0 + (0.018(Vivee) = 2.0))); V(vbg) <+ vbg_nom - 0.0008 + L.Am*vec_appl - 0.5m*tenpC_swp*tempC_swp: end endmodule ‘The Verilog-A equation fo the voltage andthe cell current are: Tivee, gnd) <+ (icc_nom - 2.78e-8*tempc)* (1.0 + (0.01*(V(vec) = 2.0))); Vivbg) <+ vbg_nom - 0.0008 + 1.4m*vce_appl - 0,0005*tempc_swp*tempc_swp: ‘The switch model inthe voltage regulator uses control signal to change the characteristics of its output branch (Listing 5.9) The model monitors changes in the control signal with the use of the cross analog operator. The control signal is then compared to its threshold value to determine the state ofthe switch. The variable that is set is then used to set ether the voltage or curent condition atthe output branch, (vp, va} or V(vp, vn) depending upon te switch state, Note the use of preprocessor defines (“OPEN and *CLOSED) to help document the module description LASTING 89 Verilog-A simple switch model s@etine OPEN 1 s@etine CLOSED 0 130 Verlog-A HDL. 131 Sy eeeeeeeeeemeeeemecmeeiemmmmeeee eccomodule sw(vp, va, vetrip, vetrin): Anout vp, vn, vetrip, vetrin; electrical vp, vn, vetrip, vetrin; parameter real vth = 2.0; integer sw_stat analog begin @(erosa(Vivetrip, vetrin) - vth, 0.0, 1u)) : Ae ((v(vetrlp, vetria) ~ vth) > 0.0) aw_state = ‘CLOSED; alse ew_state = ‘OPEN; Af (ew_etate == ‘OPEN) vivp. va) <+ 0.0; ase Tlvp, va) <* 0.0; ena, endnodule ‘The op amp current load model is used to generate a cutent, Zc? to represent the cellcurtent ofthe amplifier. The curent load module, icc, is derived from the switch ‘module (Listing 5.10), excepting inthis case the objective isto sink 20.0u of current to represent the load of the op amp during the switching on condition. Listine S10 Curent load module, saefine OPEN 2 safine CLOSED 0 ‘i module icc(vec, vetrip, vetrin); Amout vec, vetrip, vetrin: electrical vec, vetrip, vetrin: parameter real vth = 2.0; integer sw_state; analog begin @leress(V(vetrip, vetrin) - vth, 0.0, 1.0u)) Af ((v(vetrip, vetrin) - veh) > 0.0) eu_state =" ‘CLOSED; else sw_state = ‘OPEN; Af (aw_state == ‘OPEN) Ive) <+ 0 else Tivee) <+ 20.0u ona endnodule ‘The icc module canbe part of the amplifier module or maintained separately, depending upon the design syle, reuse considerations, and model methodology. By including the cell current, we cen accurately capture the total amount of current used ‘within the system. For example, during architectural studies the curent can be moni tored to help select various configurations forthe system. The curent for the bandgap reference, Tce1, is included inthe bandgap model and is constant because the cell is ‘not switched off inthis application S.4.1 Test Bench and Results Circuit le fr the bandgap reference circuit used to test the model is shown in Listing 5.11, The circuit file includes tests for temperature, supply voltage, and the switching characteristics LASTING 6:1 Spice netlist of bandgap reference test bench, * voltage regulator circuit sverilog "bandgap.va tverilog ‘sw.va’ cvertiog ticc.vat 132 Verilog-A HDL mm pserr,e|eeeoeoeoew ae‘Voteage Regulator sverilog “op_amp.va" 180 degrees celsius is shown in Figure 5.16. The “bow in the voltage with respect to temperature isa typical characteristic for bandgap based voltage reference veel vee 0 de 3.0 ve entrl 0 de 2.5 pulse(0 2.5 0.1m 50u S0u 2.5m Sm) 1.260 veenp temp 0 dc 25:0 xog vee vbg temp bandgap vog_noml.295 {ce_nomel9u @) 1255 wee vee entr] 0 See vehe1.0 ms xew vbg inp cntrl 0 sw vthel.! Moa) Zamolinm inp vout Opa pi ina inp vout open +2899 a aio 7050 30.0 + anplitios biasing 20.80 RED inn vout, 100% we) Cf inn vou 150p 28.90 1 RE1 inm 0 61k (bo) Rinp inp 0 30k 2900 Rlosa vout 0 5k 94455 0 sia wT ——“T.9 op Tad veemp -40 140 1 ‘ioUns 0 Bandgap reference voliage (a) and toll curent(b) over “ae woe 4 6 tempernure forth Behaviorl model o Figure 5.17, shows the output voltage and the cll current as the supply voltage is vi vena, ply voltage is var ied over the expected range of usage from 4 106 volts, “The output volige is designed fora nominal bandgap voltage of 1,259 volts. The results of simulation using the Verilog-A model over a temperature range of -40 10 134 Verilog-A HDL. 135 oC(QPSK ModuatetDemoduator 5.5 QPSK Modulator/Demodulator 3.2980 Quadrature phase-shift keying, or QPSK. isan example of « modulation technique in 3.2975 which the information cared witin the signal i contained inthe phase. The phase @ ofthe signal can ake on one of four values, such as shown in the constellation dae 32970 4 sam of Figure 5.19. 3.2065) a5 30 SS 2 Bn = teu ie a . ‘sau 1 ) 38.90 39.20 99.445 a5 35 35 30 sf te icuRE S17 Regulator output voltage (a) and total current (b) over the operating supply range. Figur 5.18, eng the dynamic espns of model, Yes the ouput vokags Fees fhe sich cent betwoen he retence an tebe ample. 40 3° Viente) @) aa t 00 1805 802 oor 7006 40 = 3 Vivout) » * a 00 fo 18055 Tar 7005 T008 ‘igure sis Voltage regulator control signal (a) and output voltage (b). FIGURE 5.19 QPSK modulator constellation diagram showing the allowable ‘ates between the inphate and quadrature component 5.5.1 Modulator ‘As shown in the QPSK modulator schematic (Figure 5.20), the incoming binary ‘sequence i transformed into polar form by « noaretutn-o-zer0 (NRZ) encoder. Here, the binary 1 and Osymbols ae transformed into +1 and-I respectively. The NRZ data stream is de-multplexed into two separate binary sequences consisting of the odd- and even-numbered input bits. These binary sequences are used to modulate a pair of (quadrature carriers, which are added together to produce the QPSK signal ‘The QPSK modulator module consists of two primary components forthe polariza- tion ofthe input data sequence and the modulation of the quadrature components to produce the QPSK signal. The modulator samples the input data stream (Os and 1s) ‘and converts it to the corresponding -1 of +1 every period seconds using the ‘tdmor operator. An integer variable state is toggled to convert the serial data ‘stream into two parallel streams for modulating the quadrature carers. LISTING 412 Verilog-A module definition of QPSK modulator 136 Verlog-A HDL 137‘QPSK Modulator ‘Acos (27,0) Ss = mout encoder xy Asin (2mf,0) 29 Schematic representation ofthe QPSK modulator. The input data Tieton oat RG) enone: e-mstopexey ween he and Q ‘hhanels, modulated and summed for he output module qpsk.mod(out, in} Amout out, ins electrical out, in; parameter real offset = 0.0n; paraneter real period = 100.0n; parameter real oscfreq = 2.067; real an, bn, bani integer state: analog begin ‘ (timer (offset, period)) begin Af (state == 0) begin (tin) > 2.8) 71.0 1.0; (QPSK Modulator/Demoduator baal ena state = !state; end, (v(in) > 2.5) 2 1.0 -1.0; Vout) <+ (1.0/aqet(2.0))* (an*cos(2.0*'M_PI*oscfreq*$realtime()) + bn*sin(2.0*°N_Pr*oscfreq*Srealtime())); bound_step (0.05 /oscfreq) ; ena enanodule ‘To insure that an accurate representation ofthe QPSK signal i generated, the simula tion timestep is bounded to require a minimum of 20 points per oscillator period using the bound_step function. The Bound_step function acts to limit the timestep Utlized during the simulation, Is primary use is forthe accurate generation of inde- ppendent sources such as the modulator. In this case, bound_step(0.05/osctrea) ; limits the timestep used inthe representation ofthe modulated signal toa minimum of 20 points per the period of the oscillator (Figure 5.21. 10 < 0.05/osctreq 05 00 05 2, ‘Basu (246u ~~ aa7u abu «AOU OU FIGURE S21 Use of hound_atep for insuring accurate representation of custom 138 Verilog-A HDL 139 ed‘QPSK ModulatoerDemoduator “The output ofthe modulator (shown in Figure 5.22), shows the constant-envelope ‘modulator output with the phase transitions atthe changes in the input data sequence NN 1.00 180 2.00 FIGURE'S22 Time domain output ofthe QPSK module for some random bit input sequence 5.5.2 Demodulator “The OPSK demodulator, shown in Figure 5.23, consists of a pair of correlators supplied witha locally generated pairs of reference signals. The outputs of the corela- tors, ; and xq. re compared toa threshold of zero for their respective in-phase and ‘quadrature channel outputs. Forth in-phase channel, if; > 0, then a decision is made in favor of symbol 1. Likewise if x; <0, then a decision is made in favor ofthe symbol 0, A similar process occurs forthe quadrature channel. The wo binary eT sequences are combined ina parallel-to-srial converter to produce the original binary input sequence. ‘Acos (2Rf.0) bio ¥ Qsenat [] > A =a ae oa] Asin (2nf.1) une tanSchematc eesentaton of te QPSK demote The incoming Ena s mixed with two localy-generatedorogonal signal, ntegrated to ‘etermine the symbol ee LISTING 513 Verilog-A definition of QPSK demodulator. module qpsk_denod(out, in) Amout out, in; electrical out, in; parameter real offset = 0.0n; paraneter real period = 100.0n; parameter real oscfreg = 2.067; real xi, x4: real vi, voai real di, da real bout integer integreset; Anteger state, 140 Verlog-A HDL 141 adanalog begin vd = V(in) *cos (2.0*°M Prtoscfreq*$realtime()) ; vig = V(in) *ein(2,0*'M Prtoscfreq*$realtime()); integreset = 0; G(timer (offset, period)) begin integreset = 1; @4 = (Ki > 0.0) 75.0 : 0.0; ala = (xa > 0.0) 25.0 : 0.05 ona, xi = 4at(vi, 0.0, integreset); xg = dat vig, 0.0, integreset); (timer (offset, period) begin if (etate == 0) begin bout = 4 state = Istate; v(out) <+ transitien(bout, tn, in, In); ena, endnodule ‘The timer analog operator is used to sample the output ofthe quadrature correlators at the symbol period rate, The real variables _i and »_q ate used to store the correla: tor outputs from the previous evaluation time. At the same ime the correlator outputs are sampled, the variable integreset is set to 2, causing the correlators tobe reset to the specified inital condition (0-0). integreset = 0; . (timer (offset, period)) begin integreset = 1; ai = (xi > 0.0) 25.0 ala = Goa > 0.0) 75.0 ena Fractional N-Loop Frequency Spat XA = dae(v_i, 0.0, integreset); xq = dat (va, 0.0, integreset); ‘A more desiled mode! of the demodulator would extract the timing information from the incoming signal and use that to synchronize the symbol extraction. Resetting the integrators atthe symbol period implements an integrate-and-dump slgorthm for determining the symbol thresholds as shown in Figure 5.24 750 50n 25 00 250, -50n “750 ou tuStiAUS:*C*«‘a BSCS FIGURE S24 Output of demodulator integrators for some random bit sequence. 5.6 Fractional N-Loop Frequency Synthesizer ‘This example illustrates design and analysis of aN.F frequency synthesizer, where N is the integer multiple ofthe number and F i the fractional portion that the synthe sizer multiplies its input signal by. 142 Veriog-A HDL 143 ess“The architecture, shown in Figure 5.25, consists ofa divide-by-N frequency aynthe- sizer, augmented to provide fractional loop division. The fractional loop division is Carried out by removing pulses (module PR) prior tothe divide-by-N counter which Teds the phase detector. A pulse is removed whenever the accumulator (module ACCUM) detects thatthe number of reference clock pulses times the fractional part ‘exceed one. To adjust forthe phase error that occurs due tothe missing pulse, the ‘Seoumulator generates an offet term that i summed in withthe VCO control signal. FNES FIGURE S25 Schematic representation ofthe fractionalN frequency synthesizer. “The structural definition ofthe fractional n-loop frequency synthesizer is shown below. The resistor and capaci tor instanliations that constitute the low-pass filer use simulator built-in primitives (ee the test bench Listing 5.14 for their definitions). LISTING 514 Verilog-A definition forthe structural module ofthe frequency symbesizer *anciude *sed.va’ . “Aneiude “const.va" module fnfs(out, in, gné) fmout out, in, andy electrical out, in, ond parameter integer n = 1; parameter integer f = 1; accu #(.fract (£), .tdel(2n), .trise(2n), .tfal1(2n)) xaccu(phase offset, overflow, in); fpa #(.tdel(2n), .trise(2n), .tfall(2n)) xpd(in, ndivout, inc, dec): ep #(.omag(.2m), .tdeL(in), tr: xepline, dec, filtin, gnd); xsum(veo_in, £41¢_in, phase_offset); aveo #(.fc(2086), .gain(2e6), .tdel (10m). trise(an), .tfail(2n)) xvco(veo_in, out): pulrem #(.tdel(10n), .trise(2n), .tfal1(2n)) xpulrem(rem_out, out, overflow) : divbyn #(-ratio(n)) xdivbyn(ndiv_out, remot): (Sn), -tfal1(Sn)) capacitor #(.cap(S0p)) cl {filt_in, comm); Fesistor #{.resis(10K)) ri(com, ynd), capacitor #(.cap(5p)) €2(comm, gna): endnodule 56.1 Digital VCO “The digital vco defines relationship between its input voltage and output frequency as follows: T= feskvomae 144 Verilog-A HDL. 145, me mmmmmmmmmmmsmmmmammsammaasmaaaaaa sala‘The algorithm used must have two discernible states that can be used to drive the veo ‘output. Consider the algorithm represented graphically in Figure 5.26. os ineg_ Integ_dir=-1.0 00 FIGURE 526 The algorithm used to define the integration period ofthe voltage- controlled oscillate. ‘The period, 7, is defined by a full cycle ofthe integration - integrating the characteris: tic equation from 0.0 10.0.5 and then back to 0.0 agui. The direction ofthe inte- ration is set by the variable integ_Air, which is alenuted tn define the output (Gither 0 or 1). The implementation ofthis algorithm for the VCO is shown in Listing real vout; real period: real integ dir; initial begin intes_dir = 1.0; ond analog begin period « 4at(integ dirt (ce + kv*V(in)}; // catch rising transition (cross (period - 0.5, +1.0)) begin integ_dir = -1.0; ena // catch falling transition. G(eross (period, -1.0)) begin integ_dir = 1.0; ena vout = 0.5+vhigh* {integ_dir + 1.0); Viout) <+ tranaition(vout, tdel, trise, tfall); Sis ona LisriNc £18 Verlg-A defnion of the digital veo. “dnclude "std.va" endmodule “Enelude “const.va" Mzetude “logic .ve" ‘The variable period i used to ste the vale ofthe nega, Analg events are acnerted whenctes the vale of riod cones 0.5 inthe postive or pwd dre: eee ee ton. oF 0.0 nthenegavecr awnvard eto, At the generation ofthese evens, Howe in, outs the cuputis togled via the Steg” ax variable, andthe dection ofthe inte electrical in, out; seeceemenee paranster real fo + 200.0; 5.62 Pulse Remover Paranster zeal gain = 1.0) eee ee Tepe removg male eto moi veo sy om he scala Daraneter real trice = “LR GATE. 02, DRIVE DELAY: {ern rdet fo deeminc we remove «pls fromthe yoo pat ror the eee eet eatke Gas tance ttpeave Cea #77, sed to determine weno signal alan overflow condition See ene has been received This age cocked on tenet input nson- ifs that ans -GATE_LOGIC 5 toni effesivel ignored. The ue of fag versus dct leigh output, 146 erlog HDL 147 eeractonal N-Lowp Frequency Synbester _valu) allows that an entice pulse will be removed, and not partial pulses. The imple ‘mentation is shown in Listing 5.16 LisTING £16 Verlog-A definition of pulse-remover sinelude “std.va" ‘imelude *const.va" sinelude “logic.va" module pulrem(out, in, remove): Amout out, in, remove: electrical out, in, remove; parameter real tdel = ‘LE_GATE_PROP_DELAY: Parameter real trise = ‘LPGATE_01_DRIVE_DBLAY: Parameter real fall = ‘LF_GATE_10_DRIVE_DBLAY: Darameter real vthresh = ‘LF_MID_THRESH: real vout_val = 0.0; Anteger xn = 0; analog begin (lin) = vehresh, +1.0)) begin val = (zn) 70.0 : 5.0; (v(in) - vehresh, -1,0)) begin ona, J] see the rm (remove_next) flag on positive 47 transitions of the remove signal @{cress(V(remove) - vthresh, +1.0)) begin ena Yiout) <+ transition(vout_val, tdel, trise, fail) ona endmodule 5.6.3 Phase-Error Adjustment “The accumulator module is used to both determine the removal of pulses from the veo output forthe controt loop and to provide the phase-eror correction voltage that is fequied to offset the missing pulse Ateach edge of the reference input, a summation register vaum is incremented with the factional loop value. When tis value exceeds the equivalent value of 2.0, the overflow biti set and vetum is sett the remainder. ‘The overflow bits reset on the next clock cycle ofthe reference input LASTING $17 Verlog-A definition of phase adjustment accumulator vanelude “std.va sanclude ‘const.va" ‘anclude *logic.va" module accu(sum, ov, ref); Anout sum, ovf, ref; electrical sum, ovf, ref; paraneter tdel = ‘LF_GATE_PROP_DELAY; parameter teise = 'L?_CATE_01_DRIVE_DELAY: parameter téall = ‘LF_GATS_10_DRIVE_DELAY; parameter vehresh = ‘LP_MID_THRES! paraneter fract = 1-0; paraneter scale = 1.0 real voun = 0.0; real vovf = 0.0: analog begin @(crosa(V(ref) - vthresh, +1.0)) begin veun = vsun + fract; Af (vovf > 0.0) begin vovf = 0.0; end Af (veum > 10.0) begin vou = veun ~ 10.0; vové = 5.0 ena ena 148 Verilog-A HDL 149,Fractonal NLoop Frequency Sytner Viové) <+ trangition(vovt, tdel, trise, efall) Visum) <+ transition(0.1*scale*vsum, tdel trise, tfall); ena endmodule 5.64 Test Bench and Results Listing 5.18 isthe test bench designed for evaluating the system performance. The input reference clock is 4MHz. The loop multiplication factor i set to 5.4 (N=, F=8) and thus the veo output frequency should be at 21.6ME. LISTING &18 Spice netist of frequency synthesizer est bench, + Fractional N-loop frequency synthesizer sverdleg ‘accu.va" tveriieg “cpva" tverileg “dvco.va" ivarileg “divbyn.va srilog “Enfs.va" sverilog "fpa.va" tveriiog "pulren.va tverilog “sum.va" vref ref 0 dc 0 pulse(0 5 10n 2n 2n 100n 250n) xfnfs out ref 0 fnfa ne5 f=4 smodel capacitor ¢ tmodel resistor x stan .02u 10.00 ena ‘The tet beach setup defines two model definitions (for resistor and capaci- cor) which are simulator primitives instantiated from within the ffs structural description, Figure 5.27 shows the dynamic characteristics ofthe vo input signal, The phase- locked loop achieves lock after approximately five microseconds. 49 2.0 (a) 00 2.0 15 10 (b) os 00 40 @ 29 00 209 2 a0 eo or Tou FIGURE £27 Time domain setting response of frequency synthesizer (a) i output ‘of the lowpass iter, (b) the phase-error comectin signal, and () the input ‘contol signal tothe voltage-contolled oscillator. 150 Verilog-A HDL 151 etFiguite 5.28 shows the ouput signal ater the veo acquire lock. Not that or ve clock eels of the referene spn the ouput goes ough 27 cyles (S #5) 60 50 40 (a) 3° 20 10 reference cycles = § output cycles = 27 60 sof 40 30 © 20 } 10 oo u 10 7.80 8.0u su FIGURE 528 Measurement ofthe reference (a) and output (b) signals ofthe frequency synthesizer. Note the ratio ofthe eyeles is exactly 5.41 5.7 Antenna Position Control System ‘This example illustrates some of the multi-disciplinary modeling capabilis ofthe ‘Verlog-A language. The antenna postion control system, shown in Figure 5.29, consists ofboth electrical and mechanical (otaional) components antenna ditamp deo motor exeral_[potento- 2 ‘control Gal FIGURE 529 Schematic representation of the antenna position control system. ‘The position control system employs two potentiometers, one for converting the external postion contro into a Voltage and another for sensing the curent positon of the antenna, The outputs of the potentiometers fed into a differential amplifier which drives the motor. The antenna is driven by the output of the motor via a gearbox. ‘The potentiometers are defined in terms of electrical and rotational disci plines. The rotational discipline relates an angle to a torque and is used to sense the positon ofthe input shaft ofthe potentiometer. The motor, gearbox, and antenna ‘mechanical components ae defined in terms ofthe rotat iona}_omega discipline hich relates angular velocity to torque. Hence, we integrate the angular velocity of the antenna to determine its position 152 Verlog-A HDL 153 ——“Antenna Poston Control Sytem 5.7.1 Potentiometer “The potentiometer model conversa rotational position into a voltage. The module is ‘parameterized in terms of the minimum and maximum values ofthe potentiometer contol shaft. The coresponding output voltage scale is controlled by the value of the voltage across the input pins, inPos and integ. LASTING &:19 Verlog-A potentiometer definition. module potentioneter (out, shaft, infos, inNeg) output out; Amput shaft, inPos, inNeg: electrical out; rotational shaft; electrical inPos, inNeg: paraneter real min angle = -"M_PI; parameter real raxangle = ‘MPI: real scale, shaft_angle; analog begin A€ (Theta(shafe) > max_theta) shaft_angle = max_theta else 4 (Theta(shaft) < mintheta) shaft_angle = min theta: else shaft_angle = Theta(shaft); scale = V(inFos, inNeg) /(max_entr] - min_cntrl) V(out) <+ V(inNeg) + scaletctri_val; ona, endnodule 5.7.2. DC Motor ‘The core of any DC motors an electrical armature which converts between electrical ‘and mechanical power without any loss. The electrical properties ofthe motor include its resistance, R and inductance, Ly. The mechanical properties are the motos inertia, Jp and rotational friction, By. The back voltage generated by the motor is Ky times the angular frequency ofthe motor, 6, , and the torque is Ke times the current ‘through the motor, Ip, This is shown diagrammatically in Figure 5 30, FIGURE S30 Schematic representation ofthe de motor model ‘The equations describing the terminal and output characteristics of the motor become: Try = Ky Tq By Oy LB) oa 4 Rag Int Eig’ ba) +E Oe ‘Within the DC motor module, these equations representing the constitutive behavior ‘of the component are: Tau(shafe) <+ Ke*T(in) ~ BntOnega(shaft) - at (Jm*onega (shaft}) V(in) <+ RaPT(in) + dat (Lm*T(in)) + Km*Omega (shaft) ; 5.7.3 Gearbox ‘The motor translates torque tothe antenna via a gearbox. In addition to the transla tional affects of the gear ratios between the wo shafts, the model forthe gearbox ‘must be bidirectional in thatthe torque from the motor must affect the antenna, and ‘the inertial load ofthe antenna must be expressed on the load of the motor 154 Verilog-A HDL. 155 nd“Antenna Pein Control System ‘If we assume that the gears donot slip, then equating translational distance forthe ‘two gears in terms oftheir angular position yields: 8) = FO “The relationship between the torque onthe two shafsis related by the force atthe point of contact, F, = Fa, where ¢ = r- F. The total torque on the shaft isthe exter nally applied torque less the inertia ofthe gear. LASTING 630 Verilog-A gearbox model. module gearbox(shafti, shafe2): Amout shaftl, shaft?: rotational_omega shaftl, shaft?; paraneter real ri = 1 from (0:imf); Parameter real {i = im from (0:inf); paraneter real r? paraneter 2 analog begin ‘omega (shafti) <+ Omega(shage2) *(r2/r1) ; ‘Tau(shafe2) <+ i2*ade (omega (shaft2)) + (tau(shafel) - i1*4de (Omega (shaftt))) *x2/x1; ena, entnodule 8.74 Antenna “The antenna represents a rotational load onthe shaft of the gearbox which is chars terized in terms ofthe inertia LISTING 62 Verilog-A antenna model module antenna(shaft) ; dmout shaft; rotational_omega shaft paraneter real i= 1 analog begin ‘Tau(shagt) <+ iaae (Omega (shaft) ); ona endmogule 8.75 Test Bench and Results ‘The modules are assembled inthe Listing 5.22 as per the schematic of Figure 5.31 LisTING 522 Spice netlist of antenna position controller test bench + position controller sverilog “servo.va" veupply supply 05.0 vote] inpos 0 pwl(0 0 1 0 2 -1.0472 4 10 -1.0872 11 0.7854 20 0.7854) xinpot supply 0 inpos ittplus potentionerer + min_ctr]=-1.5708 max_ctrl=1,5708 xdiffanp innotor diffplus diftminus aiff_amp k = 24 xmotor innotor outangle metor_ée xgearbox outangle gearangle gearbox + r2=10 i190 420 xantenna gearengle antenna inerti xintgr8 igearpos gearangle intgr® pos_ic = 0 xoutpot supply 0 igearpos diffminus potentiometer 4 min_ctr] = -1.5708 max_ctrl = 1.5708 stean 0.01 20 ena, 156 Verilog-A HDL 187 Oerr ae In Figure 531, we show the applied postion tothe control system and the response for both light and heavy antennas. The position input to the system is in radians position control No light antenna heavy antenna 18 00 50 10.0) 16.0 20.0 ‘icURE.531 Time-domain trajectory of antenna position in response toa position ‘onto! signal for both light and heavy antennas. “The applied voltage tothe motor is shown in Figure $32 ‘Appendix A Lexical Conventions and Compiler Directives ae Ac] Verilog-A Language Tokens ‘Verilog-A source files ae a stream of lexical tokens. A lexical token consists of one cor more characters. Te layout of tokens in asoure fil is fee format - spaces and ‘newlines are not syntactically significant other than being token separators, except 00 Cecaped identifiers won “The types of lexical tokens inthe language ae a follows white pace 200 comment + operators 00 raber ting 4 Aight antenna a fo identifier 40.0 ae 00 30 yoo 150 ~~«200 rioune $2 Applied motor cive voltage insesponseoposition contol inal A. White Space Foros igh cd heavy amen. “White pace contains he characters for spaces, abs, newlines an form feeds, These ‘hurt are ignored except when they serve Yo separ cer lerical tokens 158, Verilog-A HDL Lexical Conventions and Compiler Directives 159 i ——Lexie Conventions and Comper Directives ‘erlogrA Language Tokens A.1.2 Comments = egal “The Verilog-A language has two forms to introduce comments. A one-line comments ae starts with two characters // and ends with a newline. A block comment statis with + oom /* andends witha */. Block comments can not be nested. The one-line comment %temary foken // does not have aay meaning within a block comment. A.14 Numbers A.13 Operators (Operators are single, double, or tiple character sequences and are used in expres sions. Unary operators appear tothe lft oftheir operand. Binary operators appear between their operands. A conditional operator has two operator characters that sepa rate three operands. Te following table lists the Verlog-A operators and their > tighe shit = ites << tessthan es > gremerthan a tes <= ess equal ier me greaerequal © ets rot equal 2 ters 160 Verilog-A HDL Lexical Conventions and Compiler Directives 161[No space is permitted between the number and the symbol. This form of floating. point number specification is provided in the Verlog-A language in addition tothe Daher methods for writing floating point numbers. A.L.5 Conversion ‘Real numbers are converted to integers by rounding the real number tothe nearest integer, rater than truncating it. Implicit conversion takes place when areal number is assigned to an integer. The ties are rounded away from ze, ‘A.1.6 Identifiers, Keywords and System Names “An identifiers used to give an object an unique name so that it canbe referenced. An Hdentier can be any sequence of letters, digits, and the underscore characters). “The fest character ofan identifier can not be a digit it can be a letter. Identifiers are case sensitive A.1:7 Escaped Identifiers Escaped identifiers start with the backslash character (\) and end with whitespace {pace tb, newline) They provide a means of including any ofthe printable ASCIL crrestiers in an identifier (the decimal values 33 through 126 or hexadecimal values 21 through TE). [Neither the leading back-slsh character nor the terminating white space is considered part ofthe identifier. A.L9 Verilog-A Keywords eee abet aes wnalog ‘erin case at aa natare Aefault Aicipline ese ond endcase enddisciptine _endmodule = endnature exclude flow tor from sat fat nature it fot ‘nat Inout input integer rmodile ature output o parameter potential real repeat volts white ‘A..10 Math Function Keywords “The following table contains the standard mathematical functions supported bythe Verilog-A language and their regions of validity. The operands must be numeric (inte- ferorteal) For min, sax, and abs, if either operand is real, both are converted to Fea as isthe result. Arguments to all other functions are converted to real A.B Keywords oo Keywords are predefined non escaped ienifers that ar sed to define language con Function Deseripton Domain srocts Al Keywords ar defined in Iowerease ony. * Ral gain ogo) ecial logan x0 ext) Exponential ret sat) Square rot 0 wing) ‘Minima atbeally sax. 9) Maxima analy abs) ‘Absaue ails 162 Verilog-A HDL Lexical Conventions and Compiler Directives 163 ee edLeaieat Convene and Compiler Diectves Funetion Description Domain pont Poee a a ‘The following table defines the wigonomeric and hyperbole functions supported by the Verilog-A language. All operands must be ofthe numeric ype (integer and real) and are converted to real if necessary, All arguments (othe trigonometric and hyper: bolic functions are specified in radians Function Description ne) Sas cox) Cosine tunis) Tangent sings) Aresine cos) Ae-cosne atan(s) Arccungent sinhis) Hyperbole sine coshis) Hyperbole cosine tants) Hyperotic tangent ssinhis) Archypesbotic sine scosh(2) Archypebolic cosine anh Are hyperbole tangent ‘As with any mathematical description language, the Verlog-A language requires that the model developer (and user ofthe mode!) understand the sage conditions. Almost all the mathematical nd trigonometric functions, by their definition, have some restrictions on their inputs. Consideration of these properties require that the modeler ‘understand the types and ranges of signals thatthe model willbe uted under and develop accordingly A.LA11 Analog Operator Keywords analysis ound sep aay laplace nd ——_taplace_np laplace_2p slew timer and amp aad ‘Analog operators are described in Chapter 3. ‘Compiler Directives A.1.12 System Tasks and Funetions ‘The (5) character introduces a language construct that enables development of user: b) ? a:b) @(cross(v(thr) ~*threshold, 0.0) Vout) <+ ‘ppmax(v(inl), v(in2)); ‘The macto text can be any arbitrary text specified on the same line asthe text macro ‘name, If more than one line is necessary to specify the text, the newline must be preceded by a backslash (\). The fist newline not preceded by a backslash will end the ‘macro text The newline preceded by a backslash is replaced inthe expanded macro ‘witha newtine (but without the preceding backslash character). For an argument-less macro, the textis substituted “as-is” for every occurrence of the ‘text macro, However, a text macro with one or more arguments must be expanded ‘by substituting each formal argument with the expression used asthe actual argument inthe macro usage. ‘The directive “undef undefines a previously defined text macro, An attempt to Undefine a text macro that was not previously defined using a “define compiler directive can result in a warning. ‘An undefined text macro as no value. A2.2 ‘ifdef, ‘else, ‘endif ‘These conditional compilation compiler directives are used to optionally include lines of a Verilog-A language source description during compilation. The “Af4ef_ compiler directive checks forthe definition ofa variable name. Ifthe variable name is defined, then the lines following the “4 #4ef directive are included. Ifthe variable ‘name is not defined and a *eliae directive exists then this source is compiled ‘These directives may appear anywhere inthe Veritog-A source description a The ‘itdes, “ei ‘endi¢ compiler directives workin the following manner: ‘+ When an *4#¢ef is encountered, the text macro name is tet to see iit is defined ss a text macro name using *dafine within the Verilog-A language source ) if you would lke to change the path from the default (¢: \vers.loga) ‘FIGURE D2 Installation dialog forthe Verlog-A Explorer IDE. sw of the Distribution ‘After successful installation, under you will find te following directory structure and fies: + File License. exe. * Directory bin executables for the IDE and simulator, ‘+ Directory book contains selected examples from the book. *+ Directory examples contains miscellaneous examples, * Directory inc1ude contains the Verilog-A standard definitions for disciplines and physical constants, *+ Directory Lib is orgenized in subdirectories for behaviorl models of analog, ‘communications, data acquisition, and digital. Circuit test bench files are also include. ‘+ Directory mat1ab includes the MATLAB scripts referenced in Appendix C. ‘+ Directory template has the template files for new * .ckt and * va files ere- ated from the Explore IDE, + Directory tutorial contains the behavioral models and circuit used for illustea- tion in this Appendix, Verilog-A Explorer IDE 187 [EeVerilog A Explorer IDE D.2.2 Executable and Include Path Setup From the program group that is created, you can check the installation by starting the Verilog-A Explorer IDE. From the Design->Settings menu (rom the main menu bat), raise the Sezings dialog: FIGURE D3 Settings dialog for defining Spice-SL executable, ouput directory, and include paths ‘The Settings dialog includes information regarding paths tothe Verilog-A Explorer ‘executables and include directories. These properties are defined as follows: ‘© Executable: Path tothe Spice simulator (shouldbe: \bin\epices!.exe) ‘Output Directory: Path to top-level directory where the results directory will be ‘reated. The default output directory isthe path of the input circuit le. Change this to point to an area where you would like al the simulation results tobe stored Maintaining a common output directory can help with the organization (and dele tion) of unneeded results directories. ‘+ Veritog-A Preprocessor Definitions: A comme-separated list of Verilog-A preprocessor directives to be passed tothe Verilog-A language compiler. An identifier, ‘vax, on ths line is passed tothe Veilog-A compiler with the same effect as Saiefine var in the Veilog-A source. = Verilog-A Preprocessor Include Directory: Path to a comma-separated list of dard (for “ata. va" and “const. va" definition ffs) and user-defined include directories (should at least have \include for the standard ude fies). Ifyou maintain your own Verilog-A module libraries in a separate ectory, adda path to that directory here. Ihutalaton and Stop D.2.3 Overview of the IDE Organization ‘The organization of the Verilog-A Explorer IDE is centered around the input circuit file (* .cke). The files containing the Verlog-A module definitions (*.va forthe ‘environment are referenced from the circuit fle wih the vex4.10g statement, For export flet.va sverdieg *£ile1.var—} mf fleava verilog "file2.va" >| FIGURE DA Circuit file, exp .ckt, referencing two Verilog-A module les, Filel.vaand file2.va, example, the circuit fle exp .ckt of Figure D.4 references two Verilog-A files, filel.va and £i162.va. When the Spice-SL simulator processes the input cit- cuit fle, it will pass these files off othe Verilog-A compiler. {A Verilog-A file can contain one or more definitions of Verilog-A modules. In exten aly all cases, module files include a least the standard discipline definitions file, ‘std. va", as well asa file of pre-defined physical constants, “const. va", 88, shown in Listing D.L LISTING D. Inclusion of standard discipline and constants definitions Mnelude *std.va" Mnelude “const.va* 188 Verilog-A HDL. Verilog-A Explorer IDE 189VerlogA Explorer IDE ‘stn the Explorer IDE Within the circuit fil, instantiations of Verlog-A modules is done via an extension of the Spice subcircuit instantiation mechanism. The subcircuit is instantiated as a °X" node connections parameter assignments Xinstnane nl n2 ... module_nane plevall p2eval2 \ device, as pat ofthe instance name, Followed are the circuit nodes attached to the ‘module in the order as defined in the modules’ por list. The Verlog-A module name identifies the typeof the module, followed by an optional list of parameter-value pairs, eee prefix of instance nam ‘Simulation ofa circuit file creates a results directory that stores the output results for all the analyses specified within the circuit file. The name ofthe results directory cre ated isthe same asthe cizcut file but with a rea extension. When you are asked to specify a results directory, itis this name. For example, in Figure D.5, expres is ‘the name ofthe results directory. ‘Within the results directory, each analysis type creates a results ile ofthe circuit name expckt de ran results directory: exp.res exp.deo. xp.acd exp. expart FIGURE DS Example circuit ile, exp ckt, with corespond results directory, ‘exp. res (al the same level in the filesystem hierarchy). Within the results ‘irectory, files are created for each of the analyses specified in the eieuit il, witha corresponding extension indicating the type of analysis. An index identifier is used in the sufix ofthe filename for differentiating the results files of different analysis ofthe same type. ‘You can change the destination ofthe results directory via the Design->Settings menu tobe another location such as a common temporary directory. This ean be used to simplify data management (see Section D.2, Installation and Setup) as unwanted eslls directories can be easily identified and removed, D.3 Using the Explorer IDE ‘This section proves simple walk-through examples ofthe Verilog-A Explorer IDE. ‘The ist example wil include opening and running an existing design and ploting results. The second example wil create a circuit file and Verilog-A module from scratch, 190 Verlog-A HDL Verilog Explorer IDE 191Verlg-A plorer IDE D.3:1 Opening and Running an Existing Design Fits start the Explorer IDE and from the main menu, selestFile->Open. From the Open File dialog, select te file p11.ckt from the \tuto- vial iectory a in Figure DS. FIGURED. Opening the pit .ckt circuit fie “This will load the circuit fie into the Explorer IDE workspace. As everything is already defined for this example circuit, ou can begin simulation, From the Explorer IDE toolbar, Figure D7, press the start simulation button, or from the Design->Start ‘Simulation menu entry. stop simulation start simulation. raise circut fle window ralse plot window: load results directory iGURE D7 Explorer IDE toolbar extensions. + Cuiput fom the Spice-SL simulation will be displayed i the Output Window (Figure .t) asthe simulation progresses. I there are errors inthe ciruit all information will be output to the Output Window. ye ‘stn the Explorer IDE ‘When the simulation completes successfully, ether ‘+ The output results ofthe simulation wll be auto-loaded into the workspace if there ‘was only one analysis in the circuit file. # Or, aLoad Results dialog willbe raised asking you to select the results you would Tike to look at if there were multiple analysis (.de, «am, .ac) performed (Fig- sure D3) results directory resuls directory browser resuits fles and__ descriptions FIGURE DS Load Results dislog and description “The Load Results dialog displays the availabe result files that can be loaded into the workspace. Ifthe results directory enty is empy, to the right ofthe results directory name is a button which rises a directory browser (Figure D.9) which allows you to specify the directory containing the output results files of interest. files (Figure ion ofthe ‘After the results directory i defined, you can choose one ofthe result .10), A results file willbe identified by name (p11 .tr0) and des type of corresponding analysis. When a results file is read into the environment, the Explorer IDE will use the infor- ‘mation in the result ie to fill ou the Project Navigator (Figure D1). The Project [Navigator allows you to plot signals (va the hierarchy browser) and manage the files associated with the design. 192 Verlog-A HDL Verilog-A Explorer IDE 193 ee‘une bo Results Dietry Browser dialog. Navigate filesystem ierachy unl the appropriate directory is high light ricURED.10 Load Results dalog with results directory specified and all results files enumerated Forp11.-ckt, loading the result file pL t20 results in the Project Navigator of Figure D.11. The Project Navigntor shows a hierarchical view ofboth signals and ‘components within the design, If there ia plus (+) box tothe lft ofan icon, that indicates that there is another level of hierarchy in the design below that component. “The Project Navigator is used for both traversing the hierarchy as well as specifying the output signals tobe plotted. Once a results file has been loaded into the Explorer 194 Verilog-A HDL ‘Using th Explorer IDE signal icon, and name component icon and name icume D.1 Project Navigator showing a hierarchical view of signals and components, ‘workspace, you can display simulation results with the waveform viewer. From the ‘main menu select View->Piot Window to raise the plot window (or use the toolbar shortcut - Figure D.7). To add signals othe plot window, simply double-click on a Verilog-A Explorer IDE 195Verlg-A Explore IDE, ‘Using the Explorer IDE, signal icon within the hierarchy view ofthe Project Navigator. For example, double: clicking on signal jean out results in shown in Figure D.12. ‘igure bata Plotting signls within the IDE. To plot signal, raise the plot twindow and doublesclck on the signal icon of interest inthe hierarchy navigator. ‘To delete a trace, click on a signal name in the plot legend to selec. Delete with the key. ‘Signals canbe deleted from the plot view by clicking on the signal within the plot leg- ‘end, This will select the signal by placing a box around the name. Ifa signal is selected, it can be deleted simply by pressing the key. Zooming in on a specific area ofthe plot view is accomplished by Ief-mouse button ‘drag operations. To zoom back out, press the right-mouse button inthe plot window and choose either Zoom To Fit or Zoom Out ‘After a plot has been selected, you can change is properties via the Plot Properties Now, which rates the following dialog box: Ifyou select a circuit file, the workspace will be cleared of any open files. If you select a Vrilog-A file it is assumed that it is associated with any existing circuit design open within the workspace. In both cases, a new file is created and initialized with a template file ofthe appropiate type. If you prefer your own template files, ‘change the pat ofthe template via the respective Editar Properties dialog accessible via the right mouse button, Appendix E Spice Quick Reference E.1 Introduction ‘Spice is a general-purpose citcut simulation program for nonlinear DC, nonlinear ‘transient, and linear AC analysis, Originating from the University of California at Berkely, is by far the best known and most widely used circuit simulator. Is availa- ‘ble in fora wide variety of computer platforms, in both commercial and proprietary isthe soutce through which the controlling curent is measured, Independent voltage and cutent sources are specified in Spice as: Yeenoo00 NP NN (DC) dctr_value] [AC {acmag [acphase]) Toovevx NP NW [[DC] dctr value} [AC [acmag [acphase] ] where detran_val isa constant value for times the following for time-dependent sources dependent sources, and one of pulse(vi v2 td tr tf pw per) va ut sin(v0 va froq td theta) oxp(-(ta)"thota) (y) For AC small-signal analyses, atleast one AC source must be defined inthe circuit E.3.2 Semiconductor Devices and Models For semiconductor devices, the large number of parameters requite thatthe device ‘model parameters be specified ona separate - MODEL, definition and assigned a unique mode! name. The device element cards in Spice then reference the model Each device element card contains the device name, the nodes to which the device is connected t, and the device model name. The standard semiconductor devices sup- posted by Spice include diodes (0), bipolar junction transistors (Q), junction field effect transistors (0), and mosfts(¥) devices DropoodK NP NN MNAME [area] Qrenouee NC NB NE MNAME (area) Ssooooc ND NG NS MNAME (area) Mronoode ND NG NS NB MNAME (0 fe) (Levalue} ‘Where MAME isthe model name, The model name is defined using 8 . MODEL card, assigning parameters by appending the parameter name forthe given model type with ‘an equal sign and the parameter value, Model parameters not given are assigned the default values forthe model. The general format of . MODE cards is: -MODEL MAME TYPE ( P: ALA P26VAL2 ... ) and TYPE is one ofthe following: NEN NPN je model PNP PNP bjt model Cs) D Diode model 202 Verilog A HDL Spice Quick Reference 203

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