CS2253 COMPUTER ORGANIZATION AND ARCHITECTURE PART - A

S.NO 1 2 3 4 5 6 7 QUESTIONS UNIT -1 Why is the data bus in most microprocessors bidirectional while the address bus is unidirectional? Perform 1010100 1000100 using 1s and 2s complement. What is a bus? What are the different buses in CPU? What are the four basic types of operations that need to be supported by an instructor set? What is the information conveyed by addressing modes? What are the various ways of representing signed integers in the system? Registers R1 and R2 of a computer contains the decimal values 1200 and 4600. What is the effective address of the memory operand in each of the following instructions? 1. Load 20(R1), R5 2. Add-(R2), R5. Give an example for zero-address, one-address, two-address and three-address instructions. Which data structures can be best supported using a) Indirect addressing b) Indexed addressing mode. What is the purpose of guard bits used in floating point operations.? The memory unit of a computer has 256K words of 32 bits each. The computer has an instruction format with four fields: an operation code field, a mode field to specify one of even addressing modes, a register address field to specify one of 60 processor registers, and a memory address. Specify the instruction format and the number of bits in each field if the instruction is in one memory word. Draw the structure of alternative two bus structure. What is meant by straight line sequencing? Draw the structure of 4-bit MSI ALU circuit block. Define IEEE floating point single and double precision standard. UNIT -2 1 2 3 1 2 3 4 What is the difference between hardwired control and micro programmed control? What are the advantages of hardwired control and micro programmed control? What is the principle of operation of a micro programmed control unit? UNIT -3 What is pipelining and what are the advantages of pipelining? What are the four situations under which a processor sets exception flag. What is meant by super scalar processor? What is data hazard in pipelining? What are the solutions?

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How do control instructions like branch, cause problems in a pipelined processor? What is the function of translation look-aside buffer. What is the ideal speedup expected in a pipelined architecture with n stages? Justify your answer. Draw the structure of two stage instruction pipeline. UNIT -4 List the difference between SRAM and DRAM? Define the terms: Spatial locality and temporal locality. What do you understand by hit ratio? Define locality of reference. What is virtual memory? Why is the wait-for-memory-function-completed step needed when reading form or writing to the main memory? Give the features of a ROM cell. An eight way set associative cache consists of a total of 256 blocks. The main memory, contains 8192 blocks, each consisting of 128 words. a) How many bits are there in the main memory address? b) How many bits are there in the TAG, SET and WORD fields. Define average memory access time for a computer system with two levels of cache. How do you construct a 8 M * 32 memory using 512 K* * memory chips? Draw the connection between main memory and CPU. What are advantages of MOS devices? UNIT -5 What factors influence the bus design decisions? What is priority interrupt? What is DMA operation? State its advantages. What is the necessity of an interface? What will be width of address and data busses for a 512K * 8 memory chip? Why do we need DMA? What is the difference between subroutine and interrupt? Write the sequence of control steps required for the three bus structure for the following instruction. 1. Add R4, R5, R6 What is bus arbitration? What are interrupt masks provided in any processor? How does bus arbitration typically work? What are the functions of a typical I/O interface? How does the processor handle an interrupt request? What are the necessary operations needed to start an I/O operation using DMA.

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PART B
S.NO 1. 2 3 4 5 6 7 What are the major instruction issues? (4) Explain various instruction format in detail.(8) Give the different instruction formats of a CPU in general. (6) Define addressing mode. Classify addressing modes and explain each type with examples. (10) Explain instruction set and instruction sequencing. (10) Explain in detail the different types of instructions that are supported in a typical processor. (10) Register R1 and R2 of a computer contain the decimal values 1200 and 2400 respectively. What is the effective address of the memory operand in each of the following instructions? 1) Load 20(R1), R5 2) Add (R2), R5 3) Move #3000, R5 4) Sub (R1)+, R5 (6) Explain in detail the principle of carry-look-ahead adder. Show how 16-bit CLAs can be constructed from 4-bit adders.(12) Perform the division on the following 5-bit unsigned integer using non-restoring division: 10101/00101 (4) Explain the working of a floating point adder/subtractor(12) Multiply the following pair of signed 2s complement numbers using bit-pair recording of the multipliers : A=010111, B=101100 (4) Explain in detail about functional unit and bus structures of computers (16) Describe various addressing modes with suitable examples (16) Explain in detail about instruction execution characteristics (16) What are the various types of Instruction Set Architectures (ISAs) possible? Discuss. (8) Discuss the various issues to be considered while designing the ISA of a processor. (8) UNIT -2 1 2 3 4 5 Explain the working of micro-programmed control unit.(16) Give the sequence of control signals to be generated to fetch an instruction from memory in a single bus organization. (4) Write a micro routine for the instruction, Add (Rsrc) + Rdst where the source and destination operands are specified in indexed and register addressing modes.(16) Explain micro programmed control unit. What are the advantages and disadvantages of it? (16) Give the organization of typical hard wired control unit and explain the functions performed by various blocks. Discuss the data flow for a sample instruction.(16) UNIT -3 1 What is branch hazard? Describe the methods for dealing with the branch hazards. (10) QUESTION UNIT -1

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With suitable diagram describe the sequence of micro operations involved in fetching and executing a typical instruction. (6) What is data hazard? Explain the methods for dealing with data hazards. (16) Explain how pipelining helps to speed up the processor. Discuss the hazards that have to be taken care of in pipelined processor. (16) Design a 4-stage instruction pipeline and show how its performance is improved over sequential execution.(8) Highlight the solutions of instructional hazards. (8) Discuss the various hazards that might arise in a pipeline. What are the remedies commonly adopted to overcome/minimize these hazards.(16) UNIT -4 Describe the functional characteristics that are common to the devices used to build main and secondary computer memories(6) Explain various mechanisms of mapping main memory address into cache memory addresses. (10) Explain how the virtual address is converted into real address in a paged virtual memory system. (10) Describe the working principle of a typical magnetic disk. (6) Draw a neat sketch of memory hierarchy and explain the need of cache memory. (8) Explain the virtual memory address translation and TLB with necessary diagram. (10) Discuss the concept of memory interleaving and give its advantages.(6) Discuss the address translation mechanisms and different page replacement policies used in a virtual memory system. (10) A byte addressable computer has a small data cache capable of holding eight 32 bit words. Each cache block contains one 32-bit word. When a given program is executed, the processor reads data from the following sequence of hex addresses 200, 204, 208, 20C, 2F4, 2F0, 200, 204, 218, 21C, 24C, 2F4. The pattern is repeated 4 times. Assuming that the cache is initially empty, show the contents of the cache at the end of each pass, and compute the hit rate for a direct mapped cache. (6) Discuss the various mapping schemes used in cache design. Compare the schemes in terms of cost and performance. (10) Consider a two-level cache with access times of 5ns, and 80ns respectively. If the hit rates are 95% and 75% respectively in the two caches, and the memory access time is 250ns, what is the average access time? (6) Give the structure of semiconductor RAM memories. Explain the Read and Write operations in detail. (16) Describe in detail about memory mapping between virtual and main memory with an example. (16) Write notes on static memories. (8) Explain the concept of memory hierarchy. (8) Write notes on : i. ROM technologies

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Memory Interleaving Set associative mapping of cache RAID disk arrays.

A computer system has a main memory consisting of 16 M words. It also has a 32K-word cache organized in the block-set-associative manner, with 4 blocks per set and 128 words per block. Calculate the number of bits in each of the TAG, SET and WORD fields of the main memory address format How will the main memory address look like for a fully associative mapped cache? (8) Explain the concept of virtual memory with any one virtual memory management technique. (8) Give the basic cell of an associative memory and explain its operation. Shoe how associative memories can be constructed using the basic cell. (8) UNIT -5 Draw the block diagram of a DMA controller and explain how it is used for direct data transfer between memory and peripherals. (16) Describe the working principles of USB. (8) Briefly compare the characteristics of SCSI with PCI. (8) Discuss the general steps involved in interrupt driven data transfer (6) Explain how DMA transfer is accomplished with a neat diagram. (10) Write short notes on : i. PCI. (8) ii. Advantages of USB over older I/O bus architectures (8) Explain the use of vectored interrupts in processors. Why is priority handling desired in interrupt controllers? How do the different priority schemes work? (10) Discuss the data transfer mechanism of the PCI bus. (6) Explain how data may be transferred from hard disk to memory using DMA including arbitration for the bus. Assume a synchronous bus, and draw a timing diagram showing the data transfer. (10) Discuss the salient features of the USB operation (6) Explain in detail about interrupt handling. (16) Explain in detail about standard I/O interfaces. (16) Explain the use of DMA controllers in a computer system with a neat diagram(16) Explain handshake protocol. Depict clearly how it controls data transfer during an input operation. (16) Explain how I/O devices can be interfaced with a block diagram (8) How do you connect multiple I/O devices to a processor using interrupts? Explain with suitable diagrams. (8) Write notes on : i. DMA ii. Bus arbitration iii. Printer-Processor Communication iv. USB (16)

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Explain the functions to be performed by a typical I/O interface with a typical input or output interface. (16) Discuss the DMA driven data transfer technique (8) Discuss the operation of any two input devices. (8)

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