EC410 A2 Fall 2012

Final

Name: ____________________________ UID: ____________________________

Relevant Equations
Diode:

I D = I S ! e(

VD /!VT )

"1

VT = Thermal Voltage

Approx. npn BJT DC Values:

kT VT = ! 25 mV @300 C q
p-type MOSFET (cut-off):

VBE(ACTIVE) = 0.7 V VCE(SAT) = 0.2 V

npn BJT (cut-off):

n-type MOSFET (cut-off):

VGS < VTN , I D = 0

n-type MOSFET (triode):

VSG < VTP , I D = 0

p-type MOSFET (triode):

VBE < VF = VBE(ACTIVE), IC = 0

npn BJT (saturation):

npn active mode values

VGS ! VTN & VDS < VGS " VTN

# 1 2& I D = K N ! % (VGS " VTN ) ! VDS " VDS ( $ 2 '

VSG ! VTP & VSD < VSG " VTP

# 1 2& I D = K P ! % (VSG " VTP ) ! VSD " VSD ( $ 2 '

VBE = VF = VBE ( ACTIVE )

iC = I S e
iB =

vBE VT
vBE

IC < ! ! I B
VCE = VCE ( SAT )

iB I S VT = e ! !

iE =

n-type MOSFET (saturation):

p-type MOSFET (saturation):

npn BJT (active):

iC I S VT = e ! !

vBE

VGS ! VTN & VDS ! VGS " VTN

ID = KN 2 ! (VGS " VTN ) ! (1 + ! ! VDS ) 2

VSG ! VTP & VSD ! VSG " VTP

ID =
2 KP ! (VSG " VTP ) ! (1 + ! ! VSD ) 2

VBE = VF = VBE ( ACTIVE )

gm =
r! =

IC = ! ! I B
VCE > VCE ( SAT )

IC VT " VT
gm = IB

gm = K N ! (VGS " VTN ) =

2 ! ID VGS " VTN

gm = K P ! (VSG " VTP ) =

2 ! ID VSG " VTP

re =

! 1 ! gm gm

Problem 1: Problem 2: Problem 3: Problem 4: Problem 5: Problem 6: Problem 7: Problem 8:

_________/ 10 _________/ 10 _________/ 10 _________ / 5 _________ / 5 _________/ 5 _________ / 5 _________/ 50

Total

_________/ 100

Problem 1-4 [10 points each] 1) [10 points] For the circuit below, find the voltage V2 that ensures that all diodes (D1, D2, and D3) are on (forward-biased) and also find the current flowing through each diode. Assume the diodes are ideal.
5V

D1 20 V

D3 5 k

VA

10 k 0V

VB
D2

5 k

V2

2) [10 points] Real op-amps have non-idealities that limit their functionality. Below is a nonexhaustive list of these non-idealities. Create a circuit that is affected by a non-ideality. Be sure to give a concise description of the non-ideality and the circuit.

Unity-Gain Bandwidth Slew-Rate Input Bias Current Finite Output Resistance Input-Offset Voltage

3) [10 points] A circuit is required with a maximum gain of 1000, a -20 dB/decade rolloff above 100 krads/s, and a +20 dB/decade rolloff below 100 rads/s. Specify an appropriate system function for the circuit.

4) [5 points] Explain why you cant increase the voltage across the Base to Emitter (VBE) of a BJT (npn) much beyond 0.7 Volts.

5) [5 points] Add the necessary components (such as independent sources, dependent sources, resistors, capacitors, inductors) so that the common-mode input (VCMI) is halfway between the power supply voltages. Additionally, integrate a 100 mV differential input (1 kHz sin-wave) independent source into the circuit schematic.

R 5V
+

VA

VOUT

VB

6) [5 points] Select the most appropriate statement regarding the small-signal MOSFET transconductance gm. a. Can be used anytime when calculating the current and voltages of MOSFETs when small input signals are applied. b. Defines the total current iD through the drain of the transistor c. Is equal to the slope of iD with respect to vGS at a particular VGS d. All the above e. None of the above

7) [5 points] Last year, Intel announced a break-through in transistor design, the tri-gate transistor, which that was introduced at the 22 nm line size. This new tri-gate transistor offers numerous enhancements to current planar transistors beyond the benefits normally associated with length and width scaling.
32 nm Planar Transistors 22 nm Tri-Gate Transistors

Qualitatively, interpret the impact of the following figure comparing supply voltage (VDD) vs transistor gate delay () for tri-gate transistors and planar transistors.
9

8) [50 points] (a-j) For the amplifier below, use VTN = 3.82 V, and KN =

!" !.!"!

mA/V2 = 555.5
! !!!"!!

mA/V2. You may assume that the Early voltage is infinite. Also, you can approximate 160 !"#. VDD = +10 V
R1 RD VD RX vin ~ rin RY R2 RS CS VX CG VG VS CD vout rout RL

VSS = -10 V a. Find the value for R1 such that the gate voltage of the transistor is 2 Volts, i.e. VG = -3 V. For the calculated value of R1, use R2 = 7 k.

b. If VGS = 4 Volts, what is the voltage at the source (VS) of the transistor?

c. If VGS = 4 Volts, what is the current ID assuming the transistor is in saturation? What must the drain voltage (VD) be to ensure the transistor is operating in the saturation region.

d. If VGS = 4 Volts and the drain voltage (VD) = 1 Volts, what value resistors must be used for RD and RS? What is the drain to source voltage (VDS)?
VDD = +10 V R1 RD VD RX vin ~ rin RY R2 VSS = -10 V RS CS VX CG VG VS CD vout rout RL

e. Draw the small-signal equivalent model.

f. Compute the small-signal mid-band gain vout/vin for RL = and RX = 200 , and RY = 200 .

g.

What is the AC steady-state input resistance (rin) of this circuit if RX = 200 , and RY = 200 ?

h.

What is the AC steady-state output resistance (rout) of this circuit excluding RL?

i.

If CG = 1 F, CS = 1 F, CD = 1 F, RX = 200 , RY = 200 , and RL = what is the lowfrequency cutoff value?

j. If the parasitic capacitance (CGS, CGD, CGB) of the MOSFET limits amplification beyond 100 kHz, draw the Bode plot for the magnitude of the amplifier? Be sure to label all relevant points.