Adc Converter For Audio Setup

PCM1804-Q1
www.ti.com SLES271A JUNE 2012 REVISED AUGUST 2012
FULL DIFFERENTIAL ANALOG INPUT 24-BIT, 192-kHz STEREO A/D CONVERTER

Check for Samples: PCM1804-Q1
1
FEATURES
Qualified for Automotive Applications AEC-Q100 Test Guidance With the Following Results: Device Temperature Grade 3: 40C to 85C Ambient Operating Temperature Range Device HBM ESD Classification Level H2 Device CDM ESD Classification Level C3B 24-Bit Delta-Sigma Stereo A/D Converter High Performance: Dynamic Range: 112 dB (Typical) SNR: 111 dB (Typical) THD+N: 102 dB (Typical) High-Performance Linear Phase Antialias Digital Filter: Pass-Band Ripple: 0.005 dB Stop-Band Attenuation: 100 dB Fully Differential Analog Input: 2.5 V Audio Interface: Master- or Slave-Mode Selectable Data Formats: Left-Justified, I2S, Standard 24Bit, and DSD Function: Peak Detection High-Pass Filter (HPF): 3 dB at 1 Hz, fS = 48 kHz Sampling Rate up to 192 kHz System Clock: 128 fS, 256 fS, 384 fS, 512 fS, or 768 fS

23
Dual Power Supplies: 5 V for Analog 3.3 V for Digital Power Dissipation: 225 mW Small 28-Pin SSOP DSD Output: 1 Bit, 64 fS
APPLICATIONS
AV Amplifier MD Player Digital VTR Digital Mixer Digital Recorder
DESCRIPTION
The PCM1804-Q1 device is a high-performance, single-chip stereo A/D converter with fully differential analog voltage input which uses a precision deltasigma modulator and includes a linear-phase antialias digital filter and high-pass filter (HPF) that removes DC offset from the input signal. The PCM1804-Q1 device is suitable for a wide variety of mid- to highgrade consumer and professional applications, where excellent performance and 5-V analog supply and 3.3-V digital power-supply operation are required. The PCM1804-Q1 device can achieve both PCM audio and DSD format due to the precision deltasigma modulator. The PCM1804-Q1 device is fabricated using an advanced CMOS process and is available in a small 28-pin SSOP package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. System Two, Audio Precision are trademarks of Audio Precision, Inc. All other trademarks are the property of their respective owners.
Copyright 2012, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
PCM1804-Q1
SLES271A JUNE 2012 REVISED AUGUST 2012 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
TA 40C to 85C PACKAGE SSOP - DB Reel of 2000 ORDERABLE PART NUMBER PCM1804S1IDBRQ1 TOP-SIDE MARKING PCM1804Q
FUNCTIONAL BLOCK DIAGRAM

OSR0 SCKI CLK Control OSR1 OSR2
VINL+ VINL VCOML AGNDL VREFL
Delta-Sigma Modulator (L)
Decimation Filter (L)
HPF
S/M FMT0 FMT1
VREFL Serial Output Interface VREFR LRCK/DSDBCK BCK/DSDL DATA/DSDR
VREFR AGNDR VCOMR VINR+ VINR
Delta-Sigma Modulator (R)
Decimation Filter (R)
HPF
OVFL OVFR BYPAS
Power Supply
RST
VCC AGND
DGND
VDD
B0029-01
PCM1804-Q1
PIN ASSIGNMENTS
PCM1804 PACKAGE (TOP VIEW)
VREFL AGNDL VCOML VINL+ VINL FMT0 FMT1 S/M OSR0 OSR1 OSR2 BYPAS DGND VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VREFR AGNDR VCOMR VINR+ VINR AGND VCC OVFL OVFR RST SCKI LRCK/DSDBCK BCK/DSDL DATA/DSDR
P0007-02
Pin Functions
PIN NAME AGND AGNDL AGNDR BCK/DSDL BYPAS DATA/DSDR DGND FMT0 FMT1 LRCK/DSDBCK OSR0 OSR1 OSR2 OVFL OVFR RST SCKI S/M VCC VCOML VCOMR VDD VINL VINL+ VINR (1) (2) (3) PIN 23 2 27 16 12 15 13 6 7 17 9 10 11 21 20 19 18 8 22 3 26 14 5 4 24 I/O I O I I I I I O O I I I I I I Analog ground Analog ground for VREFL Analog ground for VREFR
(1)
DESCRIPTIONS
I/O Bit clock input/output in PCM mode. Left-channel audio data output in DSD mode. HPF bypass control. High: HPF disabled. Low: HPF enabled.
(1)
Left-channel and right-channel audio data output in PCM mode. Right-channel audio data output in DSD mode. (DSD output, when in DSD mode) Digital ground Audio data format 0. See Table 5. Audio data format 1. See Table 5.
(2) (2) (1)
I/O Sampling clock input/output in PCM and DSD modes. Oversampling ratio 0. See Table 1 and Table 2. Oversampling ratio 1. See Table 1 and Table 2. Oversampling ratio 2. See Table 1 and Table 2.
(2) (2) (2)
Overflow signal of left-channel in PCM mode. This is available in PCM mode only. Overflow signal of right-channel in PCM mode. This is available in PCM mode only. Reset, power-down input, active-low
(2) (3)
System clock input; 128 fS, 256 fS, 384 fS, 512 fS, or 768 fS. Slave or master mode selection. See Table 4. Analog power supply Left-channel analog common-mode voltage (2.5 V) Right-channel analog common-mode voltage (2.5 V) Digital power supply Left-channel analog input, negative pin Left-channel analog input, positive pin Right-channel analog input, negative pin
(2)
Schmitt-trigger input Schmitt-trigger input with internal pulldown (51 k typically), 5-V tolerant. Schmitt-trigger input, 5-V tolerant. 3
PCM1804-Q1
Pin Functions (continued)

PIN NAME VINR+ VREFL VREFR PIN 25 1 28 I/O I Right-channel analog input, positive pin Left-channel voltage reference output, requires capacitors for decoupling to AGND Right-channel voltage reference output, requires capacitors for decoupling to AGND DESCRIPTIONS
ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted) (1)
VALUE MIN Supply voltage Ground voltage differences Supply voltage difference Digital input voltage Analog input voltage TA Tstg TJ VCC VDD AGND, AGNDL, AGNDR, DGND VCC, VDD FMT0, FMT1, S/M, OSR0, OSR1, OSR2, SCKI, RST BYPAS, DATA/DSDR, BCK/DSDL, LRCK/DSDBCK, OVFL, OVFR VREFL, VREFR, VCOML, VCOMR, VINL+, VINR+, VINL, VINR 0.3 0.3 0.3 V 40 55 0.3 0.3 MAX 6.5 4 0.1 V VCC VDD < 3 6.5 VDD + 0.3 VCC + 0.3 10 mA 125 150 150 260 260 2 750 C C C C, 5 s C kV V V V V V UNIT V V
Input current (any pins except supplies) Ambient temperature under bias Storage temperature Junction temperature Lead temperature (soldering) Package temperature (IR reflow, peak) ESD Rating (1) Human Body Model (HBM) AEC-Q100 Classification Level H2 Charged Device Model (CDM) AEC-Q100 750 V Classification Level C3B
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range
MIN Analog supply voltage, VCC Digital supply voltage, VDD Analog input voltage, full-scale (0 dB), differential input Digital input logic family Digital input clock frequency Digital output load capacitance Operating free-air temperature, TA (1) 10 System clock Sampling clock 8.192 32
(1)
NOM 5 3.3 5 TTL compatible
MAX 5.25 3.6
UNIT V V Vpp
4.75 3
36.864 192 10 70
MHz kHz pF C
If the VCC drops below the minimum recommended operating condition of 4.75 V, to avoid a brown out condition the VCC power must be cycled to 0 V and then to > 4.75 V to ensure continued device functionality.
PCM1804-Q1
ELECTRICAL CHARACTERISTICS
All specifications at TA = 25C, VCC = 5 V, VDD = 3.3 V, master mode, single-speed mode, fS = 48 kHz, system clock = 256 fS, 24-bit data, unless otherwise noted.
PARAMETER Resolution DATA FORMAT Audio data interface format Audio data bit length Audio data format DIGITAL INPUT/OUTPUT Logic family
(1) (2)
TEST CONDITIONS
PCM1804DB MIN TYP 24 Standard, I2S, left-justified 24 MSB first, 2s-complement, DSD TTL compatible 2 2 5.5 VDD 0.8 65 100 10 100 10 50 2.4 0.4 32 192 12.288 18.432 24.576 36.864 24.576 36.864 24.576 36.864 MAX
UNIT Bits
Bits
VIH VIL IIH
High-level input voltage Low-level input voltage High-level input current
(3) (1) (2) (3)
VDC VDC A
VIN = VDD VIN = VDD VIN = VDD IIL VOH VOL fS Low-level input current High-level output voltage Low-level output voltage Sampling frequency VIN = 0 V VIN = 0 V
(1) (2) (3) (1) (2) (3) (4)
A VDC VDC kHz
IOH = 1 mA IOL = 1 mA
(4)
CLOCK FREQUENCY 256 fS, single rate 384 fS, single rate 512 fS, single rate System clock frequency 768 fS, single rate 256 fS, dual rate 384 fS, dual rate 128 fS, quad rate 192 fS, quad rate DC ACCURACY Gain mismatch, channelto-channel Gain error (VIN = 0.5 dB) Bipolar zero error (1) (2) (3) (4) (5) (6) (7) HPF bypass 0.2 3 4 % of FSR % of FSR % of FSR
(5) (5) (5) (5)
(6) (6) (7) (7)
MHz
Pins 611, 19: FMT0, FMT1, S/M, OSR0, OSR1, OSR2, RST (Schmitt-trigger input with internal pulldown (51 k typically), 5-V tolerant) Pin 18: SCKI (Schmitt-trigger input, 5-V tolerant) Pins 12, 1617: BYPAS, BCK/DSDL, LRCK/DSDBCK (in slave mode, Schmitt-trigger input) Pins 1517, 20, and 21: DATA/DSDR, BCK/DSDL, LRCK/DSDBCK (in master mode), OVFR, OVFL Single rate, fS = 48 kHz Dual rate, fS = 96 kHz Quad rate, fS = 192 kHz
PCM1804-Q1
ELECTRICAL CHARACTERISTICS (continued)

PARAMETER DYNAMIC PERFORMANCE
(8)
TEST CONDITIONS
PCM1804DB MIN TYP 102 49 101 47 101 47 100 106 112 112 112 112 105 111 111 111 111 97 109 107 107 2.5 2.5 10 0.453 fS 0.547 fS 0.005 100 0.375 fS 0.49 fS 0.77 fS 0.005 135 37/fS 9.5/fS fS/48000 MAX 95
UNIT
VIN = 0.5 dB VIN = 60 dB VIN = 0.5 dB THD+N Total harmonic distortion plus noise VIN = 60 dB VIN = 0.5 dB VIN = 60 dB
fS = 48 kHz, system clock = 256 fS fS = 96 kHz, system clock = 256 fS fS = 192 kHz, system clock = 128 fS
dB
VIN = 0.5 dB DSD mode fS = 48 kHz, system clock = 256 fS Dynamic range (Aweighted) VIN = 60 dB DSD mode fS = 48 kHz, system clock = 256 fS SNR (A-weighted) fS = 96 kHz, system clock = 256 fS fS = 192 kHz, system clock = 128 fS DSD mode fS = 48 kHz, system clock = 256 fS Channel separation ANALOG INPUT Input voltage Center voltage Input impedance DIGITAL FILTER PERFORMANCE Pass-band edge Stop-band edge Pass-band ripple Stop-band attenuation Pass-band edge (0.005 dB) Pass-band edge (3 dB) Stop-band edge Pass-band ripple Stop-band attenuation Group delay Group delay HPF frequency response (8) Single rate, dual rate Single rate, dual rate Single rate, dual rate Single rate, dual rate Quad rate Quad rate Quad rate Quad rate Quad rate Single rate, dual rate Quad rate 3 dB Single-ended Differential input fS = 96 kHz, system clock = 256 fS fS = 192 kHz, system clock = 128 fS fS = 96 kHz, system clock = 256 fS fS = 192 kHz, system clock = 128 fS
dB
dB
dB
V VDC k Hz Hz dB dB Hz Hz Hz dB dB s s Hz
The fIN = 1 kHz, using System Two audio measurement system by Audio Precision in RMS mode, with 20-kHz LPF and 400-Hz HPF in calculation for single rate, or with 40-kHz LPF in calculation for dual and quad rates .
PCM1804-Q1
ELECTRICAL CHARACTERISTICS (continued)

PARAMETER POWER SUPPLY REQUIREMENTS VCC VDD ICC IDD Supply current Supply voltage range VCC = 5 V
(9) (10) (11) (9) (12) (10) (12) (11) (12) (9) (12) (10) (12) (11) (12)
TEST CONDITIONS
PCM1804DB MIN 4.75 3 TYP 5 3.3 35 15 27 18 225 265 235 5 10 100 70 290 MAX 5.25 3.6 45 20
UNIT
VDC
VDD = 3.3 V VDD = 3.3 V VDD = 3.3 V
mA
Operation, VCC = 5 V, VDD = 3.3 V PD Power dissipation Operation, VCC = 5 V, VDD = 3.3 V Operation, VCC = 5 V, VDD = 3.3 V
mW
Power down, VCC = 5 V, VDD = 3.3 V TEMPERATURE RANGE Operation temperature JA (9) (10) (11) (12) Thermal resistance Single rate, fS = 48 kHz Dual rate, fS = 96 kHz Quad rate, fS = 192 kHz Minimum load on DATA/DSDR (pin 15)
C C/W
PCM1804-Q1
TYPICAL PERFORMANCE CURVES - SINGLE RATE

All specifications at TA = 25C, VCC = 3.3 V, VDD = 5 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data, unless otherwise noted.
TOTAL HARMONIC DISTORTION + NOISE vs TEMPERATURE
THD+N Total Harmonic Distortion + Noise dB (0.5 dB) 90 35 THD+N Total Harmonic Distortion + Noise dB (60 dB)
DYNAMIC RANGE AND SNR vs TEMPERATURE

120
Dynamic Range and SNR dB
95
40
115 Dynamic Range
100 0.5 dB
45
110
SNR
105
60 dB
50
105
110 20
55 0 20 40 60 80 T Temperature C
100 20
20
40
60
80
G002
G001
T Temperature C
Figure 1. TOTAL HARMONIC DISTORTION + NOISE vs SUPPLY VOLTAGE

Figure 2. DYNAMIC RANGE AND SNR vs SUPPLY VOLTAGE

120
95
40
115 Dynamic Range
100 0.5 dB
45
110
SNR
105
60 dB
50
105
110 4.50
55 4.75 5.00 5.25 5.50 VCC Supply Voltage V
100 4.50
4.75
5.00
5.25
5.50
G004
G003
VCC Supply Voltage V
Figure 3.
Figure 4.
PCM1804-Q1
TYPICAL PERFORMANCE CURVES - SINGLE RATE (continued)

TOTAL HARMONIC DISTORTION + NOISE vs SAMPLING FREQUENCY
DYNAMIC RANGE AND SNR vs SAMPLING FREQUENCY

120
95
40
115 Dynamic Range
100
0.5 dB
45
110
SNR
105
60 dB
50
105
110 32 44.1 48 fS Sampling Frequency kHz
55
100 32 44.1 48
G006
G005
fS Sampling Frequency kHz
Figure 5. TOTAL HARMONIC DISTORTION + NOISE vs SIGNAL LEVEL

THD+N Total Harmonic Distortion + Noise dB 0
Figure 6.
20
40
60
80
100
120 100
80
60
40
20
0
G009
Signal Level dB
Figure 7.
PCM1804-Q1
TYPICAL PERFORMANCE CURVES - SINGLE RATE (continued)

AMPLITUDE vs FREQUENCY
0 20 40 Amplitude dB 60 80 100 120 140 160 0 12000 f Frequency Hz
G007
0
Output Spectrum: 0.5 dB, N = 8192
20 40 Amplitude dB 60 80 100 120 140 160 Output Spectrum: 60 dB, N = 8192
24000
12000 f Frequency Hz
24000
G008
Figure 8.
Figure 9.
TYPICAL PERFORMANCE CURVES - DUAL RATE

All specifications at TA = 25C, VCC = 3.3 V, VDD = 5 V, master mode, and 24-bit data, unless otherwise noted.
0 20 40 Amplitude dB fS = 96 kHz, System Clock = 256 fS
0 20 40 Amplitude dB fS = 96 kHz, System Clock = 256 fS
60 80 100 120 140 160 0
60 80 100 120 140 160
Output Spectrum: 60 dB, N = 8192
48000
G010
48000
G011
Figure 10.
Figure 11.
10
PCM1804-Q1
TYPICAL PERFORMANCE CURVES - QUAD RATE

All specifications at TA = 25C, VCC = 3.3 V, VDD = 5 V, master mode, 24-bit data, unless otherwise noted.
G012
0 fS = 192 kHz, System Clock = 128 fS
fS = 192 kHz, System Clock = 128 fS
20 40 Amplitude dB
60 80 100 120 140 160
96000
96000
G013
Figure 12.
Figure 13.
TYPICAL PERFORMANCE CURVES - DSD MODE

All specifications at TA = 25C, VCC = 3.3 V, VDD = 5 V, master mode, fS = 44.1 kHz, system clock = 16.9344 MHz, unless otherwise noted.
G014
0 20 40 Amplitude dB 60 80 100 120 140 160 22050 0 11025 f Frequency Hz
G015
22050
Figure 14.
Figure 15.
11
PCM1804-Q1
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER LINEAR PHASE ANTIALIAS DIGITAL FILTER FREQUENCY RESPONSE - Single Rate
OVERALL CHARACTERISTICS FOR SINGLE-RATE FILTER
50 fS = 48 kHz 0
STOP-BAND ATTENUATION CHARACTERISTICS FOR SINGLE-RATE FILTER

0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 fS = 48 kHz
Amplitude dB
50
100
150
Amplitude dB
200 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
G016
150 0.00
0.25
0.50
0.75
1.00
G017
Normalized Frequency y fS
Figure 16. PASS-BAND RIPPLE CHARACTERISTICS FOR SINGLE-RATE FILTER

0.02 fS = 48 kHz 0.00 0 1 2 3 Amplitude dB 4 5 6 7 8 9 0.10 0.0 10 0.45
Figure 17. TRANSIENT BAND CHARACTERISTICS FOR SINGLE-RATE FILTER

fS = 48 kHz
Amplitude dB
0.02
0.04
6.04 dB at 0.5 fS
0.06
0.08
0.1
0.2
0.3
0.4
0.5
0.6
G018
0.47
0.49
0.51
0.53
0.55
G019
Figure 18.
Figure 19.
12
PCM1804-Q1
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued) LINEAR PHASE ANTIALIAS DIGITAL FILTER FREQUENCY RESPONSE - Dual Rate
OVERALL CHARACTERISTICS FOR DUAL-RATE FILTER
50 fS = 96 kHz 0
STOP-BAND ATTENUATION CHARACTERISTICS FOR DUAL-RATE FILTER

0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 fS = 96 kHz
Amplitude dB
50
100
150
Amplitude dB
200 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Normalized Frequency y fS
G020
150 0.00
0.25
0.50
0.75
1.00
G021
Figure 20. PASS-BAND RIPPLE CHARACTERISTICS FOR DUAL-RATE FILTER

0.02 fS = 96 kHz 0.00 0 1 2 3 Amplitude dB 4 5 6 7 8 9 0.10 0.0 10 0.45
Figure 21. TRANSIENT BAND CHARACTERISTICS FOR DUAL-RATE FILTER

fS = 96 kHz
Amplitude dB
0.02
0.04
6.02 dB at 0.5 fS
0.06
0.08
0.1
0.2
0.3
0.4
0.5
0.6
G022
0.47
0.49
0.51
0.53
0.55
G023
Figure 22.
Figure 23.
13
PCM1804-Q1
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued) LINEAR PHASE ANTIALIAS DIGITAL FILTER FREQUENCY RESPONSE - Quad Rate
OVERALL CHARACTERISTICS FOR QUAD-RATE FILTER
50 fS = 192 kHz 0 0 10 20 30 40 Amplitude dB 50 Amplitude dB 50 60 70 80 90 100 110 150 120 130 140 200 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Normalized Frequency y fS
G024
STOP-BAND ATTENUATION CHARACTERISTICS FOR QUAD-RATE FILTER

fS = 192 kHz
100
150 0.00
0.25
0.50
0.75
1.00
G025
Figure 24. PASS-BAND RIPPLE CHARACTERISTICS FOR QUAD-RATE FILTER

0.02 fS = 192 kHz
Figure 25. TRANSIENT BAND CHARACTERISTICS FOR QUAD-RATE FILTER

0 1 fS = 192 kHz
0.00
2 3 Amplitude dB 4 5 6 7 8 9 3.9 dB at 0.5 fS
Amplitude dB
0.02
0.04
0.06
0.08
0.10 0.0
0.1
0.2
0.3
0.4
0.5
0.6
G026
10 0.45
0.47
0.49
0.51
0.53
0.55
G027
Figure 26.
Figure 27.
14
PCM1804-Q1
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued) HIGH-PASS FILTER (HPF) FREQUENCY RESPONSE
STOP-BAND CHARACTERISTICS
0 10 20 30 Amplitude dB 40 50 60 70 80 90 100 0.0 1.0 0.0 Amplitude dB 0.0 0.2
PASS-BAND CHARACTERISTICS
0.2
0.4
0.6
0.8
0.1
0.2
0.3
0.4
G028
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
G029
Normalized Frequency y fS/1000
Normalized Frequency y fS/1000
Figure 28.
Figure 29.
PRINCIPLES OF OPERATION THEORY OF OPERATION

The PCM1804-Q1 device consists of a band-gap reference, a delta-sigma modulator with full-differential architecture for L-channel and R-channel, a decimation filter with a high-pass filter, and a serial interface circuit. Figure 30 illustrates the total architecture of the PCM1804-Q1 device. An on-chip, high-precision reference with 10-F external capacitor(s) provides all the reference voltage needed in the PCM1804-Q1 device, and it defines the full-scale voltage range of both channels. Full-differential architecture provides a wide dynamic range and excellent power-supply rejection performance. The input signal is sampled at 128, 64, and 32 oversampling rates according to the overasmpling ratio control, OSR[0:2]. The single rate, dual rate, and quad rate eliminate the external sample-hold amplifier. Figure 31 illustrates how for each oversampling ratio the PCM1804-Q1 device decimates, the modulator outputs down to PCM data when the modulator is running at 6.144 MHz. The deltasigma modulation randomizes the modulator outputs and reduces the idle-tone level. The oversampled data stream from the delta-sigma modulator is converted to a 1-fS, 24-bit digital signal, while removing high-frequency noise components using a decimation filter. The DC components of the signal are removed by the HPF, and the HPF output is converted to a time-multiplexed serial signal through the serial interface, which provides flexible serial formats as well as master and slave modes. The PCM1804-Q1 device also has a DSD output mode. The PCM1804-Q1 device can output the signal directly from the modulators to DSDL (pin 16) and DSDR (pin 15).
15
PCM1804-Q1
PRINCIPLES OF OPERATION (continued)

OSR0 SCKI CLK Control OSR1 OSR2
VINL+ VINL VCOML AGNDL VREFL
Delta-Sigma Modulator (L)
Decimation Filter (L)
HPF
S/M FMT0 FMT1
VREFL Serial Output Interface VREFR LRCK/DSDBCK BCK/DSDL DATA/DSDR
VREFR AGNDR VCOMR VINR+ VINR
Delta-Sigma Modulator (R)
Decimation Filter (R)
HPF
OVFL OVFR BYPAS
Power Supply
RST
VCC AGND
DGND
VDD
B0029-01
Figure 30. Total Block Diagram of the PCM1804-Q1 Device
0
Quad-Rate Filter
20 40 Amplitude dB
Dual-Rate Filter
60 80 100 120 140 160 0 48 96 f Frequency kHz

G030
SingleRate Filter
Modulator
144
192
Figure 31. Spectrum of Modulator Output and Decimation Filter
16
PCM1804-Q1
PRINCIPLES OF OPERATION (continued) SYSTEM CLOCK INPUT

The PCM1804-Q1 device supports 128 fS, 192 fS (only in master mode at quad rate), 256 fS, 384 fS, 512 fS, and 768 fS as a system clock, where fS is the audio sampling frequency. The system clock must be supplied on SCKI (pin 18). Table 3 shows the relationship of typical sampling frequency and the system clock frequency, and Figure 32 shows system clock timing. In master mode, the system clock rate is selected by OSR2 (pin 11), OSR1 (pin 10), and OSR0 (pin 9) as shown in Table 1. In slave mode, the system clock rate is automatically detected. In DSD mode, OSR2 (pin 11), OSR1 (pin 10), OSR0 (pin 9), and the system clock frequency are fixed as shown in Table 1 and Table 3.
tw(SCKH) tw(SCKL) SCKI 2V SCKI 0.8 V
T0005B07
tw(SCKH) tw(SCKL)
PARAMETER System clock pulse duration, HIGH System clock pulse duration, LOW
MIN 11 11
UNIT ns ns
Figure 32. System Clock Input Timing
POWER-ON AND RESET FUNCTIONS

The PCM1804-Q1 device has both an internal power-on-reset circuit and RST (pin 19). For internal power-on reset, initialization (reset) is performed automatically at the time when the digital power supply exceeds 2 V (typical) and analog power supply exceeds 4 V (typical). RST accepts external forced reset, and a low level on RST initiates the reset sequence. Because an internal pulldown resistor terminates RST, no connection of RST is equivalent to a low-level input. Because the system clock is used as a clock signal for the reset circuit, the system clock must be supplied as soon as power is supplied; more specifically, at least three system clocks are required prior to VDD > 2 V, VCC > 4 V, and RST = high. While VDD < 2 V (typical), VCC < 4 V (typical), or RST = low, and 1 / fS (maximum) count after VDD > 2 V (typical),VCC > 4 V (typical) and RST = high, the PCM1804-Q1 device stays in the reset state and the digital output is forced to zero. The digital output is valid after the reset state is released and the time of 1116 / fS has passed. Figure 33 and Figure 34 illustrate the internal power-onreset and external-reset timing, respectively. Figure 35 illustrates the digital output for power-on reset and RST control. The PCM1804-Q1 needs RST = low when control pins are changed or in slave mode when SCKI, LRCK, and BCK are changed.
POWER-DOWN FUNCTION
The PCM1804-Q1 device has a power-down feature that is controlled by RST (pin 19). Entering the power-down mode is done by keeping the RST input level low for more than 65536 / fS. In the master mode, the SCKI (pin 18) is used as the clock signal for the power-down counter. While in the slave mode, SCKI (pin 18) and LRCK (pin 17) are used as the clock signal. The clock(s) must be supplied until the power-down sequence completes. As soon as RST goes high, the PCM1804-Q1 device starts the reset-release sequence described in the PowerOn and Reset Functions section.
OVERSAMPLING RATIO
The oversampling ratio is selected by OSR2 (pin 11), OSR1 (pin 10), and OSR0 (pin 9) as shown in Table 1 and Table 2. The PCM1804-Q1 device needs RST to equal low when logic levels on the OSR2, OSR1, and OSR0 pins are changed.
17
PCM1804-Q1
Table 1. Oversampling Ratio in Master Mode

OSR2 Low Low Low Low High High High High High High OSR1 Low Low High High Low Low High High Low Low OSR0 Low High Low High Low High Low High Low High OVERSAMPLING RATIO Single rate ( 128 fS) Single rate ( 128 fS) Single rate ( 128 fS) Single rate ( 128 fS) Dual rate ( 64 fS) Dual rate ( 64 fS) Quad rate ( 32 fS) Quad rate ( 32 fS) DSD mode ( 64 fS) DSD mode ( 64 fS) SYSTEM CLOCK RATE 768 fS 512 fS 384 fS 256 fS 384 fS 256 fS 192 fS 128 fS 384 fS 256 fS
Table 2. Oversampling Ratio in Slave Mode

OSR2 Low Low Low Low High High High High (1) OSR1 Low Low High High Low Low High High OSR0 Low High Low High Low High Low High OVERSAMPLING RATIO Single rate ( 128 fS) Dual rate ( 64 fS) Quad rate ( 32 fS) (1) Reserved Reserved Reserved Reserved Reserved SYSTEM CLOCK RATE Automatically detected Automatically detected Automatically detected
Only at the 128-fS system clock rate
Table 3. Sampling Frequency and System Clock Frequency

OVERSAMPLING RATIO SAMPLING FREQUENCY (kHz) 32 Single rate (2) 44.1 48 Dual rate (3) Quad rate (4) DSD mode (3) (1) (2) (3) (4) 88.2 96 176.4 192 44.1 SYSTEM CLOCK FREQUENCY (MHz) 128 fS 22.5792 24.576 192 fS 33.8688 36.864
(1)
256 fS 8.192 11.2896 12.288 22.5792 24.576 11. 2896
384 fS 12.288 16.9344 18.432 33.8688 36.864 16.9344
512 fS 16.384 22.5792 24.576
768 fS 24.576 33.8688 36.864
Only available in master mode at the quad rate Modulator is running at 128 fS. Modulator is running at 64 fS. Modulator is running at 32 fS.
18
PCM1804-Q1
VCC, VDD
4.4 V / 2.2 V 4V/2V 3.6 V / 1.8 V
Reset Internal Reset
Reset Removal
1024 System Clock + 1/fS (Max)
System Clock
T0014-07
Figure 33. Internal Power-On-Reset Timing
RST t(RST) RST Pulse Duration (t(RST)) = 40 ns (Min) Reset Internal Reset 1/fS (Max) System Clock
T0015-05
Reset Removal
Figure 34. External-Reset Timing

Power ON RST ON
Reset Removal
Internal Reset
Reset 1116/fS
Ready / Operation
Data(1)
Zero Data
Converted Data(2)
T0051-01
(1) (2)
In the DSD mode, DSDL is also controlled like DSDR. The HPF transient response appears initially.
Figure 35. ADC Digital Output for Power-On-Reset and RST Control
19
PCM1804-Q1
AUDIO DATA INTERFACE

The PCM1804-Q1 device interfaces the audio system through BCK/DSDL (pin 16), LRCK/DSDBCK (pin 17), and DATA/DSDR (pin 15). The PCM1804-Q1 device needs RST to equal low in the interface mode and/or if the data format is changed.
INTERFACE MODE
The PCM1804-Q1 device supports master mode and slave mode as interface modes, which are selected by S/M (pin 8) as shown in Table 4. In master mode, the PCM1804-Q1 device provides the timing of the serial audio data communications between the PCM1804-Q1 device and the digital audio processor or external circuit. While in slave mode, the PCM1804-Q1 device receives the timing for data transfer from an external controller. Slave mode is not available for DSD. Table 4. Interface Mode
S/M Low High MODE Master mode Slave mode
DATA FORMAT
The PCM1804-Q1 device supports four audio data formats in both master and slave modes, and these data formats are selected by FMT0 (pin 6) and FMT1 (pin 7) as shown in Table 5. Table 5. Data Format
FMT1 Low Low High High FMT0 Low High Low High
2
FORMAT PCM, left-justified, 24-bit PCM, I S, 24-bit PCM, standard, 24-bit DSD
MASTER Yes Yes Yes Yes
SLAVE Yes Yes Yes
20
PCM1804-Q1
INTERFACE TIMING FOR PCM

Figure 36 through Figure 38 show the interface timing for PCM. (1) Left-Justified Data Format; L-Channel = High, R-Channel = Low
1/fS LRCK BCK DATA 1 2 3 22 23 24 1 2 3 22 23 24 1 2 L-Channel R-Channel
(2) I2S Data Format; L-Channel = Low, R-Channel = High

1/fS LRCK BCK DATA 1 2 3 22 23 24 1 2 3 22 23 24 1 2 L-Channel R-Channel
(3) Standard Data Format; L-Channel = High, R-Channel = Low

1/fS LRCK BCK DATA 22 23 24 1 2 3 22 23 24 1 2 3 22 23 24
T0009-03
L-Channel
R-Channel
NOTE: LRCK and BCK work as outputs in master mode and as inputs in slave mode.
Figure 36. Audio Data Format for PCM
21
PCM1804-Q1
t(LRCP) LRCK tw(BCKL) tw(BCKH) t(CKLR) 0.5 VDD
BCK t(BCKP) t(CKDO) t(LRDO)
0.5 VDD
DATA
0.5 VDD
T0018-03
PARAMETERS t(BCKP) tw(BCKH) tw(BCKL) t(CKLR) t(LRCP) t(CKDO) t(LRDO) tr tf (1) (2) (3) BCK period BCK pulse duration, HIGH BCK pulse duration, LOW Delay time, BCK falling edge to LRCK valid LRCK period Delay time, BCK falling edge to DATA valid Delay time, LRCK edge to DATA valid Rising time of all signals Falling time of all signals Rising and falling times are measured from 10% to 90% of IN/OUT signal swing. The load capacitance of all signals is 10 pF. The t(BCKP) is fixed at 1 / (64 fS) in case of master mode.
MIN 32 32 5
TYP 1 / (64 fS)
MAX
UNIT ns ns
15 1 / fS 15 15 10 10
ns ns ns ns ns
5 5
Figure 37. Audio Data Interface Timing for PCM (Master Mode: LRCK and BCK Work as Outputs)
22
PCM1804-Q1
t(LRCP) LRCK tw(BCKL) tw(BCKH) t(LRHD) 1.4 V t(BCKP) t(CKDO) t(LRDO) t(LRSU) 1.4 V
BCK
DATA
0.5 VDD
T0017-03
PARAMETERS t(BCKP) tw(BCKH) tw(BCKL) t(LRSU) t(LRHD) t(LRCP) t(CKDO) t(LRDO) tr tf (1) (2) BCK period BCK pulse duration, HIGH BCK pulse duration, LOW LRCK setup time to BCK rising edge LRCK hold time to BCK rising edge LRCK period Delay time, BCK falling edge to DATA valid Delay time, LRCK edge to DATA valid Rising time of all signals Falling time of all signals Rising and falling times are measured from 10% to 90% of IN/OUT signals swing. The load capacitance of the DATA /DSDR signal is 10 pF.
MIN 1 / (64 fS) 32 32 12 12
TYP
MAX 1 / (48 fS)
UNIT ns ns ns ns
1 / fS 5 5 25 25 10 10 ns ns ns ns
Figure 38. Audio Data Interface Timing for PCM (Slave Mode: LRCK and BCK Work as Inputs)
INTERFACE TIMING FOR DSD

Figure 39 and Figure 40 show the interface timing for DSD.
DSDBCK DSDL Dn3 Dn2 Dn1 Dn Dn+1 Dn+2 Dn+3
DSDR
Dn3
Dn2
Dn1
Dn
Dn+1
Dn+2
Dn+3
T005201
Figure 39. Audio Data Format
23
PCM1804-Q1
tw(BCKH)
tw(BCKL)
t(CKDO)
DSDBCK t(BCKP)
0.5 VDD
DSDL DSDR
0.5 VDD
T005301
PARAMETERS t(BCKP) tw(BCKH) tw(BCKL) t(CKDO) tr tf (1) (2) DSDBCK period DSDBCK pulse duration, HIGH DSDBCK pulse duration, LOW Delay time DSDBCK falling edge to DSDL, DSDR valid Rising time of all signals Falling time of all signals Rising and falling times are measured from 10% to 90% of IN/OUT signal swing. The load capacitance of the DSDBCK, DSDL, and DSDR signal is 10 pF.
MIN
TYP 354 177 177
MAX
UNIT ns ns ns
15 10 10
ns ns ns
Figure 40. Audio Data Interface Timing for DSD (Master Mode Only)
SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM FOR PCM

In slave mode, the PCM1804-Q1 device operates under LRCK synchronized with the system clock SCKI. The PCM1804-Q1 device does not need a specific phase relationship between LRCK and SCKI, but it does require the synchronization of LRCK and SCKI. If the relationship between LRCK and SCKI changes more than 6 BCK during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1 / fS and digital output is forced into BPZ code until resynchronization between LRCK and SCKI is completed. For changes less than 5 BCK, resynchronization does not occur and the previously described digital output control and discontinuity do not occur. Figure 41shows the ADC digital output for loss of synchronization and resynchronization. During undefined data, the PCM1804-Q1 device may generate some noise in the audio signal. Also, the transition of normal to undefined data and undefined or zero data to normal causes a discontinuity of data on the digital output. This can generate noise in the audio signal. In master mode, synchronization loss never occurs.
HIGH-PASS FILTER (HPF) BYPASS CONTROL FOR PCM

The built-in function for DC component rejection can be bypassed by the BYPAS (pin 12) control. In bypass mode, the DC component of the input analog signal and the internal DC offset are also converted and output in the digital output data. Table 6. HPF Bypass Control
BYPAS PIN Low High HPF MODE Normal (high-pass) mode Bypass (through) mode
24
PCM1804-Q1
OVERFLOW FLAG FOR PCM

The PCM1804-Q1 device has two overflow flag pins, OVFR (pin 20) and OVFL (pin 21). The pins go to high as soon as the analog input goes across the full-scale range. The high level is held for 1.016 s at maximum, and returns to low if the analog input does not go across the full-scale range for the period.
Synchronization Lost Resynchronization
State of Synchronization
Synchronous
Asynchronous
Synchronous
1/fS DATA(1) Normal Data Undefined Data
90/fS Zero Data Converted Data(2)

T0020-06
(1) (2)
Applies only for slave mode; the loss of synchronization never occurs in master mode. The HPF transient response appears initially.
Figure 41. ADC Digital Output for Loss of Synchronization and Resynchronization
25
PCM1804-Q1
TYPICAL CIRCUIT CONNECTION DIAGRAM

Figure 42 shows a typical circuit connection diagram in the PCM data format operation.
PCM1804 C1 + 1 2 AGNDL C3 + 3 VCOML 4 + L-Channel In 6 FMT0 Format [1:0] 7 FMT1 8 Master/Slave 9 Control Oversampling Ratio [2:0] 10 11 12 HPF Bypass 13 3.3 V C5 + 14 VDD DATA/DSDR S/M OSR0 OSR1 OSR2 BYPAS DGND OVFL OVFR RST SCKI LRCK/DSDBCK BCK/DSDL VCC AGND 5 VINL+ VINL VINR+ VINR VCOMR AGNDR VREFL VREFR C2 28 + 27 C4 26 + 25 + 24 23 C6 22 21 20 19 Reset 18 17 L/R Clock 16 Data Clock 15 Data Out Audio Data Processor System Clock Overflow 5V + R-Channel In
S0058-01
A. B.
C1, C2, C5, and C6: Bypass capacitors, 0.1-F ceramic and 10-F tantalum, depending on layout and power supply C3, C4: Bypass capacitor, 0.1-F tantalum, depending on layout and power supply
Figure 42. Typical Circuit Connection Diagram for PCM
26
PCM1804-Q1
Figure 43 shows a typical circuit connection diagram in the DSD data format operation.
PCM1804 C1 + 1 2 AGNDL C3 + 3 VCOML 4 + L-Channel In 6 FMT0 Format [1:0] 7 FMT1 8 Master/Slave 9 Control Oversampling Ratio [2:0] 10 11 12 HPF Bypass 13 3.3 V C5 + 14 VDD DATA/DSDR S/M OSR0 OSR1 OSR2 BYPAS DGND OVFL OVFR RST SCKI LRCK/DSDBCK BCK/DSDL VCC AGND 5 VINL+ VINL VINR+ VINR VCOMR AGNDR VREFL VREFR C2 28 + 27 C4 26 + 25 + 24 23 C6 22 21 20 19 Reset 18 17 Data Clock 16 L-Channel Data Out 15 R-Channel Data Out Audio Data Processor System Clock Overflow 5V + R-Channel In
S0058-02
A. B.
C1, C2, C5, and C6: Bypass capacitors, 0.1-F ceramic and 10-F tantalum, depending on layout and power supply C3 and C4: Bypass capacitors, 0.1-F tantalum, depending on layout and power supply
Figure 43. Typical Circuit Connection Diagram for DSD
27
PCM1804-Q1
APPLICATION INFORMATION BOARD DESIGN AND LAYOUT CONSIDERATIONS

VCC and VDD Pins The digital and analog power supply lines to the PCM1804-Q1 device should be bypassed to the corresponding ground pins with 0.1-F ceramic and 10-F tantalum capacitors placed as close to the pins as possible to maximize the dynamic performance of the ADC. Although the PCM1804-Q1 device has two power lines to maximize the potential of dynamic performance, using one common power supply is recommended to avoid unexpected power-supply trouble like latch-up or the power-supply sequence. VIN Pins Using 0.01-F film capacitors between the left-channel analog input positive pin and left-channel analog input negative pin, and between right-channel analog input positive pin and right-channel analog input negative pin is strongly recommended to remove higher-frequency noise from the delta-sigma input section. VREFX and VCOMX Inputs Use 0.1-F ceramic and 10-F tantalum capacitors between the left-channel voltage reference output, rightchannel voltage reference output, and corresponding analog ground pins, to ensure low source impedance at ADC references. Use 0.1-F tantalum capacitors between left-channel analog common-mode voltage, rightchannel analog common-mode voltage and corresponding analog ground pins to ensure low source impedance of common voltage. These capacitors should be located as close as possible to the left-channel voltage reference output, right-channel voltage reference output, left-channel analog common-mode voltage, and rightchannel analog common-mode voltage pins to reduce dynamic errors on references and common voltage. The DC voltage level of these pins is 2.5 V. DATA/DSDR, BCK/DSDL, and LRCK/DSDBCK Pins The DATA/DSDR, BCK/DSDL, and LRCK/DSDBCK pins in master mode have large load drive capability. Locating the buffer near the PCM1804-Q1 device and minimizing the load capacitance, minimizes the digitalanalog crosstalk and maximizes the dynamic performance of the ADC. System Clock The quality of the system clock can influence dynamic performance because the PCM1804-Q1 device operates based on a system clock. Therefore, it might be necessary to consider the system clock duty, jitter, and the time difference between system clock transition and BCK/DSDL or LRCK/DSDBCK transition in slave mode. Reset Control If capacitors larger than 10 F are used on left-channel voltage reference output and right-channel voltage reference output, an external reset control with a delay time corresponding to the left-channel voltage reference output and right-channel voltage reference output response is required. Also, it works as a power-down control.
APPLICATION CIRCUIT FOR SINGLE-ENDED INPUT

An application diagram for a single-ended input circuit is shown in Figure 44. The maximum signal input voltage and differential gain of this circuit is designed as Vin(max) = 8.28 Vpp, Ad = 0.3. Differential gain (Ad) is given by R3 / R1(R4 / R2) in a circuit configured as a normal inverted-gain amplifier. Resistor R5 (R6) in the feedback loop gives low-impedance drive operation and noise filtering for the analog input of the PCM1804-Q1 device. The circuit technique using R5 (R6) is recommended.
28
PCM1804-Q1
R3 = 1 k 4.7 k 4.7 k Analog In _ + OPA2134 1/2 10 F + + OPA2134 1/2 VCOM 0.1 F R4 = 1 k C(1) 10 F + + OPA2134 1/2
S0059-01
C(1) PCM1804 R1 = 3.3 k _ R5 = 47 VIN
0.01 F
R2 = 3.3 k
R6 = 47
VIN+
(1)
A capacitor value of 1800 pF is recommended, unless an input signal greater than 6 dBFS at 100 kHz or higher is applied in the DSD mode. In that case, 3300 pF is recommended.
Figure 44. Application Circuit for Single-Ended Input Circuit (PCM)
VIN+ VIN
Modulator
_ BGR +
VCOM
VREF
_ +
S0060-01
Figure 45. Equivalent Circuit of Internal Reference (VCOM, VREF)
29
PCM1804-Q1
REVISION HISTORY
Changes from Original (June 2012) to Revision A Page
Changed part number from PCM1804-ME to PCM1804-Q1. ............................................................................................... 1 Added table note under recommended operating conditions table. ..................................................................................... 4
30
PACKAGE OPTION ADDENDUM
www.ti.com
5-Nov-2012
PACKAGING INFORMATION
Orderable Device PCM1804S1IDBRQ1
(1)
Status
(1)
Package Type Package Pins Package Qty Drawing SSOP DB 28 2000
Eco Plan
(2)
Lead/Ball Finish Call TI
MSL Peak Temp

(3)
Samples
(Requires Login)
ACTIVE
TBD
Call TI
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF PCM1804-Q1 :
Catalog: PCM1804
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Addendum-Page 1
MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
DB (R-PDSO-G**)
28 PINS SHOWN 0,65 28 0,38 0,22 15 0,15 M
PLASTIC SMALL-OUTLINE
0,25 0,09 5,60 5,00 8,20 7,40
Gage Plane 1 A 14 08 0,25 0,95 0,55
Seating Plane 2,00 MAX 0,05 MIN 0,10
PINS ** DIM A MAX
14
16
20
24
28
30
38
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30 4040065 /E 12/01
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as components) are sold subject to TIs terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TIs terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TIs goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or enhanced plastic are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such components to meet such requirements. Products Audio Amplifiers Data Converters DLP Products DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID OMAP Applications Processors Wireless Connectivity www.ti.com/audio amplifier.ti.com dataconverter.ti.com www.dlp.com dsp.ti.com www.ti.com/clocks interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com www.ti-rfid.com www.ti.com/omap TI E2E Community e2e.ti.com www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright 2012, Texas Instruments Incorporated Applications Automotive and Transportation Communications and Telecom Computers and Peripherals Consumer Electronics Energy and Lighting Industrial Medical Security Space, Avionics and Defense Video and Imaging www.ti.com/automotive www.ti.com/communications www.ti.com/computers www.ti.com/consumer-apps www.ti.com/energy www.ti.com/industrial www.ti.com/medical www.ti.com/security www.ti.com/space-avionics-defense www.ti.com/video

Adc Converter For Audio Setup

Caricato da

Informazioni sul documento

Titolo originale

Copyright

Formati disponibili

Condividi questo documento

Condividi o incorpora il documento

Opzioni di condivisione

Hai trovato utile questo documento?

Questo contenuto è inappropriato?

Copyright:

Formati disponibili

Adc Converter For Audio Setup

Caricato da

Copyright:

Formati disponibili

PCM1804-Q1

www.ti.com SLES271A JUNE 2012 REVISED AUGUST 2012

FULL DIFFERENTIAL ANALOG INPUT 24-BIT, 192-kHz STEREO A/D CONVERTER

FUNCTIONAL BLOCK DIAGRAM

VINL+ VINL VCOML AGNDL VREFL

Delta-Sigma Modulator (L)

Decimation Filter (L)

S/M FMT0 FMT1

VREFL Serial Output Interface VREFR LRCK/DSDBCK BCK/DSDL DATA/DSDR

VREFR AGNDR VCOMR VINR+ VINR

Delta-Sigma Modulator (R)

Decimation Filter (R)

OVFL OVFR BYPAS

Copyright 2012, Texas Instruments Incorporated

Copyright 2012, Texas Instruments Incorporated

Pin Functions (continued)

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

NOM 5 3.3 5 TTL compatible

MAX 5.25 3.6

Copyright 2012, Texas Instruments Incorporated

VIH VIL IIH

High-level input voltage Low-level input voltage High-level input current

(3) (1) (2) (3)

(1) (2) (3) (1) (2) (3) (4)

A VDC VDC kHz

(6) (6) (7) (7)

Copyright 2012, Texas Instruments Incorporated

ELECTRICAL CHARACTERISTICS (continued)

Copyright 2012, Texas Instruments Incorporated

ELECTRICAL CHARACTERISTICS (continued)

VDD = 3.3 V VDD = 3.3 V VDD = 3.3 V

Copyright 2012, Texas Instruments Incorporated

TYPICAL PERFORMANCE CURVES - SINGLE RATE

DYNAMIC RANGE AND SNR vs TEMPERATURE

Dynamic Range and SNR dB

115 Dynamic Range

Figure 1. TOTAL HARMONIC DISTORTION + NOISE vs SUPPLY VOLTAGE

Figure 2. DYNAMIC RANGE AND SNR vs SUPPLY VOLTAGE

Dynamic Range and SNR dB

115 Dynamic Range

55 4.75 5.00 5.25 5.50 VCC Supply Voltage V

VCC Supply Voltage V

Copyright 2012, Texas Instruments Incorporated

TYPICAL PERFORMANCE CURVES - SINGLE RATE (continued)

DYNAMIC RANGE AND SNR vs SAMPLING FREQUENCY

Dynamic Range and SNR dB

115 Dynamic Range

110 32 44.1 48 fS Sampling Frequency kHz

fS Sampling Frequency kHz

Figure 5. TOTAL HARMONIC DISTORTION + NOISE vs SIGNAL LEVEL

Copyright 2012, Texas Instruments Incorporated

TYPICAL PERFORMANCE CURVES - SINGLE RATE (continued)

Output Spectrum: 0.5 dB, N = 8192

20 40 Amplitude dB 60 80 100 120 140 160 Output Spectrum: 60 dB, N = 8192

TYPICAL PERFORMANCE CURVES - DUAL RATE

60 80 100 120 140 160 0

Output Spectrum: 0.5 dB, N = 8192

60 80 100 120 140 160

Output Spectrum: 60 dB, N = 8192

Copyright 2012, Texas Instruments Incorporated

TYPICAL PERFORMANCE CURVES - QUAD RATE

fS = 192 kHz, System Clock = 128 fS