742

IEEE TRANSACTIONS ON POWER APPARATUS AND SYSTEMS, VOL.

PAS-90,

NO.

2, MARCH/APRIL 1971

RELAYING A THREE PHASE TRANSMISSION LINE WITH A DIGITAL COMPUTER

B. J. Mann I. F. Morrison
N.S.W. Australia.

University of N.S.W., Kensington

ABSTRACT
The paper describes a digital computer programme for the protection of a three-phase transmission line. This programme detects the presence of a disturbance, classifies the fault into one of six fault types and, using a method of impedance calculation described in an earlier paper, determines the modulus and phase of the impedance of the faulted line. Accuracy of calculation and reliability of detection are determined from fault data for a model transmission line.
The method is shown to be suitable for extension to use in multi-line situtations.

With a view to establishing more firmly the feasibility of digital computer requirements for the protection, not only of a single line but also of a group of transmission lines in a substation, the programme described has also been coded for a somewhat more recent computer which incorporates some of the features found to be desirable. This translation is conisidered to be of considerable validity in the case of a single line but rather more speculative in the case of a group of lines (all those at a particular bus voltage level, for example).

THEORY
General Principles.
In conventional practice with analogue relays, the protection of a three-phase line against the range of possible fault types leads to the use of separate relays for phase and ground faults. In an analogous fashion a digital' computer could, upon detection of a likely disturbance, calculate impedances as if the fault were a phase fault and then as if it were a ground fault; in this fashion all eventualities are covered and one of these calculations will, in the presence of a fault, yield an unhealthy value and initiate tripping. This is essentially the scheme proposed in Ref. 2 which, as the author comments, places great strain on the computer hardware in terms of speed and storage requirements. The principle developed in this paper overcomes this difficulty in the following fashion - once the disturbance is detected, the type of fault (phase or ground) is determined and a suitable single phase set of relaying voltages and currents can then be chosen for subsequent impedance calculation. For extension to a multi-line substation, use of the impedance calculation technique developed in the previous paper (ref. 4) enables further simplifications. In a substation, one voltage is a common input to the relays for all the lines at any bus level. The techniques of Ref. 4 enable separation of the (common) voltage measurement from that of current, i.e. the method allows for the calculation of the peak voltage at the relevant bus level, followed by the peak current in each of the lines. Then, in order of decreasing peak current, the phase of each line is calculated until the faulted line is determined. This enables rapid sequential calculation of what previously has been an analogue parallel calculation.

INTRODUCTION
The possibility of utilising an on-line digital computer to perform the protection, switching and data collection functions of modem high-voltage substations is attracting increasing attention (refs. 1-5). Of these functions protective relaying is likely to be the most exacting in terms of computer hardware facilities and speed. Rockefeller (ref. 2) proposes a complete group of programmes for the protection both internal (transformers, busbars) and external (transmission lines) to the substation. The present authors have concentrated upon the protection of transmission lines by digital computer (refs. 3,4) as part of a larger project embracing a range of substation functions (ref. 1). Succeeding sections of this paper describe a programme developed for the type of small process control computer that is envisaged for eventual substation installations. The programme performs the relaying functions for a three-phase transmission line.
The mode of operation resembles that of a distance-type relay in that the complex impedance of the faulted line is calculated and this value used as the final criterion for the presence or absence of a fault and the allocation of any fault to one of several zones.
The method of impedance calculation used is described in an earlier paper (ref. 4). The extensions reported here lie in the methods of detection and fault classification, and in the proposed extension of the method for a single line to a group of lines at a single bus voltage
level.

Experimental results are also presented from a large number of faults of differing types and phase of incidence. The particular small computer used was not specifically designed for the protective task but was employed simply because of its availability. In the course of programme development, it was found to have some limitations which have placed restrictions on the ultimate capabilities of the programme. These restrictions are described and their implications in terms of the requirements for a more satisfactory computer for transmission line protection are outlined. Nevertheless it has been possible to establish the general principles and reliabilities of fault detection and classification, and the accuracy of impedance calculation. The all-important ,calculation times for various phases of the programme have also been determined.
Paper 70 TP 547-PWR, recommended and approved by the Power System Relaying Committee of the IEEE Power Group for presentation at the IEEE Summer Power Meeting and EHV Conference, Los Angeles, Calif., July 12-17, 1970. Manuscript submitted February 9, 1970; made available for printing April 23, 1970.

In both of these cases, the previously stringent computer requirements are ameliorated by processing only faulted information and avoiding working with healthy data. This concept has developed from an overall orientation towards fitting the problem to the machine rather than vice-versa.

EXISTING PROGRAMME This section describes the programme as developed on a Digital Equipment Corp. (DEC) PDP-8 computer. Reference throughout is to be made to the overall system flowchart of Fig. 1. For simplicity some of the mnemonics of the programme are used in explanation - these are defined in Appendix I. For a more detailed description of the PDP-8, see Appendix II.
Data Acquisition This is performed by subroutine SAMP6. The three line to ground voltages and the three line currents are sampled sequentially.

MANN AND MORRISON: RELAYING A TRANSMISSION LINE

743 The actual data transfer takes place by use of a programmed data transfer (ref 6 and App. II). This is the only way possible with the existing hardware for analogue to digital (A/D) conversion. The converter provides 11 bits and takes approximately 16 As for each conversion. Care was taken to scale the input signals to avoid the necessity for double precision routines for zero sequence calculation. Total subroutine time was 250 ,us.
Data Storage
The programme requires that very little data be stored. The detection phase (see next section) needs the most recent 40 samples of voltage while only the most recent 5 samples of current are required. In the PDP-8, storage was arranged in a ring; 1028 locations were allocated enabling the last three cycles of each voltage and current (including zero sequence) to be stored. Subroutine PUSH was used for housekeeping and for monitoring the locations in the ring in use at any time.

Computation of zero sequence voltage and current is interleaved with the sampling, and the subroutine stores these eight quantities each time it is called.

The sampling interval is set by an external 2kHz oscillator. On a 50Hz system, this gives 40 samples per cycle or a 500 ps sample interval. The oscillator communicates with the computer by setting a binary flag every 500 ps.

initializ-

Fault Detection or Relay Starting

This is performed using the cycle-by-cycle comparison scheme outlined previously (ref. 3). On a three phase basis, this operates in the following manner (text to be read in conjunction with flowchart of fig. 2 and glossary Appendix I). A counter is assigned to each phase voltage NOFR for red, NOFY for yellow and NOFB for blue. The method of detection of a disturbance on each phase is the same, but each phase operates independently.

Each voltage sample is compared to the corresponding sample in the previous cycle. If the values differ in excess of a tolerance EPSV, the counter for that particular phase is incremented. When any of the counters NOFR, NOFY or NOFB exceeds a value CNOFV, the computer jumps into the fault determination subroutines.
If the comparison of the voltage samples yields a difference less than EPSV, (i.e. the comparison is healthy) the counter is decremented for that phase, if it is not already zero. It can thus be seen that such a detection scheme would not detect sharp spikes or gradual fluctuations, yet allows for positive detection for one cycle of values (i.e. after the 40th post fault sample, comparisons are made between two faulted samples rather than between healthy and faulted samples). If it is desired to maintain positive detection for a longer time, e.g. two cycles, the scheme is simply adapted by performing the comparison between voltage samples two cycles apart. There are several variable parameters to be set in this scheme, the settings being dependent on the fault levels at any particular location. The values of EPSV used was 6% p.u. and for CNOFV, 5. At 500 ps per sample interval therefore, the first 2.5 ms of the fault are taken up by detection. The subroutine used to perform the above is COMP and calculation time was 158 ps max.

NOTE ON SYMBOLS: SAMP6 COMP PUSH

460

within

Subroutines to be executed
one

sample interval

The subroutine COMP jumps into the following fault determination subroutines only when at least one of the counters NOFR, NOFY or NOFB has a value 5.

Fault Type Determination

Execution time inr,osec must be less than 500/lS

Fig. 1. Flowchart - existing PDP-8 programme.

Subroutines FTYPE and SELCT are used here. The following impedance calculation stage requires an equivalent single phase relaying quantity. The aim of these subroutines is to determine which two of the red, yellow or blue phases or ground are to be used to derive this equivalent single phase quantity.

744

IEEE TRANSACTIONS ON POWER APPARATUS AND SYSTEMS,

MARCH/APRIL 1971

of the same value as the ground counter are to be selected in preference to it since subsequent impedance calculations are more accurate when working with delta values on multi-phase to ground faults i.e. it is preferable to calculate a RYG fault as an RY fault rather than an RG or a YG.

SELCT could be reached with one of NOFR, NOFB or NOFY at value 5 with the other two and NOFG all less than 4. In this case more information is considered necessary, and, as shown in fig. 1 flowchart branch C, return is made to subroutine COMP to further increment the counters. Eventually, provided the values of tolerances EPSV and EPSZ are chosen appropriately, SELCT must yield a positive exit along one of the six paths, RY, RB, YB, RG, YG or BG. The calculation times for FTYPE and SELCT are 230 As and 50 ,us respectively. Calculation of Impedance from an Equivalent Single Phase Relaying Quantity In the manner of existing distance relays, it is proposed to work with delta quantities for phase faults and phase voltages and zerosequence compensated phase currents for ground faults. If desired, sound phase compensation could be used instead of zero sequence compensation.

Thus, if subroutine SELCT exit was along paths RY, YB, RB, subsequent impedance is calculated from the equivalent single phase delta values, forned by subtraction of the appropriate line to ground voltages and currents. If exit was via paths RG, YG or BG, the impedance is calculated from the phase voltages and currents with compensated currents where required. It is because of the additional complexity of compensation for single phase to ground faults and the errors which arise if this compensation is not made adequately (Chap. 11 of Ref. 9 provides a good summary, while more detail can be found in Refs. 7 to 11), that subroutine SELCT is oriented to detect multi-phase to ground faults as phase faults rather than ground faults.
The impedance calculation was performed in the manner described in Ref. 4. For convenience, the main results are summarized here.

Fig. 2. Flowchart - subroutine COMP.

A counter for zero-sequence values, NOFG, is determined by FTYPE in a manner similar to that in which the red, yellow and blue counters were determined. The last five (the same value as CNOFV) zero sequence voltage samples are examined - for each value exceeding a specified tolerance EPSZ, the counter NOFG is incremented. EPSZ is chosen to be large enough to avoid increments due to any slight steady state unbalance of the three phases. Thus after exit from FTYPE, NOFG, like NOFR, NOFY and NOFB, is in the range 0 to 5, with at least one of NOFR, NOFY or NOFB equal to 5.

Using values of v, v', i, i' derived from averaging of three samples and by use of a central difference expression for derivatives,

Peak Voltage:
Peak Current:

Vp2 Vpk2

V2+ v2+()
j2
2

(VI

Ip2
V0

Point on cycle of voltage sample:

= arctan

the values of these counters. If a counter has value 4 or 5, then the phase it represents is considered to be involved in the fault; if a counter has value 0 or 1, the phase is not involved in the fault. If the value is 2 or 3, the result is undetermined. The object of SELCT is to determine two of the counters for subsequent work e.g. if a RYG fault occurs, it would suffice to treat it as a RY, RG or YG; but in any case, only two of the red phase, yellow phase or ground need be considered as being involved in the fault. Counters of value 5 are to be selected in preference to those of value 4. The red, yellow or blue phase counters

Subroutine SELCT then determines whether any of the red, yellow or blue phases or ground is involved in the fault on the basis of

-V

Point on cycle of current sample:

IO
Impedance modulus: z2 Impedance argument: Z0

= arctan

wil.

V2pk/I2pk
= Io - Vo

Stable values of Z, 0 are available after the 8th post-fault sample.

MANN AND MORRISON: RELAYING A TRANSMISSION LINE

745
required for impedance calculation - these may include those required for detection. Thirdly, the impedance calculation itself will require an additional time.

In order to use fixed point arithmetic with the 11 bits output from the A/D converter, double precision arithmetic was found to be necessary for these calculations.
At the completion of this stage, values of impedance, peak voltage, peak current etc. were output on teletype. Timing of the calculations was achieved by the generation and display of suitable binary step voltages within the computer.

RESULTS FROM EXISTING PROGRAMME

Detection On final debugging, the programme was tested on 1000 faults via the magnetic tape facility described in Ref. 4. The quantitative aspects of these are described later. All of these faults "detected" satisfactorily i.e. in no case did the programme falsely indicate R, Y, B or G involvement in a fault. This was despite quite severe switching noise in some faults originating from the rather erratic behaviour of the contactor used to close the faults onto the model line. Differences of up to I ms occurred between the closure of the first and last poles. Figs. 3,4,5 are three representative faults illustrating operation of the detection phase. The time scale for each is 2 ms/division. The step waveform shown in each case is generated by the computer when detection occurs i.e. when one of counters NOFR, NOFY, NOFB had value of 5 on completion of subroutine COMP. Fig. 3 shows a RYB fault which detected as a RB fault. The R and B poles closed just under I ms before the Y pole, consequently NOFR and NOFB were already advanced before NOFY had increased from zero. Fig. 4 shows a BG fault which detected satisfactorily despite severe noise on the R phase. Fig. 5 shows an RYG fault which detected as a YG fault. Here the Y phase faulted before R. Furthermore, the R phase was close to a zero crossing and may have yielded one healthy sample comparison because of this. In this case, NOFR would be decremented and NOFG would have a higher value.
Block C in the flowchart (fig 1) provides for the case where SELCT was entered with insufficient information to classify the fault i.e. only one of the counters NOFR, NOFY, NOFB or NOFG has value 4 or 5. In the debugging stage before this block was provided, 17 in a run of 800 faults failed fault classification for this reason. Block C was then added to provide one return to COMP. It was then found that a second try to SELCT was satisfactory - i.e. the return to COMP was sufficient to bring a second counter up to the value 4.

Fig. 3. Model transmission line R YB fault, detected as RB.

Fig. 4. Model transmission line BG fault, detected as BG.

Impedance Calculation
The model line provided faults of constant impedance only. Thus on execution of the programme for 1000 faults, it is possible to statistically estimate the overall accuracy of the calculation procedure. The 1000 faults were divided approx. equally into 10 of the 11 basic faults (no RB faults) i.e. approx. 100 each of RYBG, RYB, RY, YB, RYG, YBG, BRG, RG, YG and BG faults. The results are shown in Table I, where it can be seen that for 99% of faults the peak values of current and voltage will be accurate to within less than 10%, the Z modulus to within 10% and the argument of Z to within 7.
The time required to calculate impedance within these accuracies is determined by three considerations. Firstly, five samples are required for detection of a disturbance. Secondly, eight samples are

Fig. 5. Model transmission line R YG fault, detected as YG.

746

IEEE TRANSACTIONS ON POWER APPARATUS AND SYSTEMS, MARCH/APRIL 1971

TABLE I: Statistical results from 1000 faults

Peak voltage

Peak current

Imped. Mod
0.291 0.304 4.3%

Imped. phase
-5.8

322 Actual 323 Mean Variance about mean 2.8% +21%,-17% Max. errors about mean Values 5% of mean 95.1% Values+ 1%oof mean 99.4% Values 15% of mean 99.8% * These are no. of values within 5 of mean. ** These are no. of values within 70 of mean.

1105. 1059 2.8%

-4.30
2.90

93.4% 100% 10o0%

+9.6%,-5.9%

+22%,-19%
77.5% 98.5% 99.6%

* 93.7% ** 99.1%

+20.20,-7.20

The overall worst calculation time assuming the programme does not enter loop C was found to be 5.4 ms. This was for phase-phase relaying quantities - these were longest because the delta voltages and currents had to be calculated then scaled. Of this time, the five samples for detection occupied 2.5 ms, the three additional samples for impedance calculation a further 1.5 ms and the actual impedance calculation itself occupied 1.4 ms. Thus the impedance calculation time here is only 25% of the total time consumed.

Storage should of necessity be increased to at least 8K words; the entire 4K of core of the PDP-8 was filled by the existing programme. Inclusion of extra routines possible with a faster cycle-time machine will require extra storage.

Core Utiliiation
The computer core storage was utilised in the following manner. The PDP-8 has 4096 word core which is broken down to 32 pages; 10 pages were used for input/output routines, display, debugging, reader and disk linkages; 14 pages were used for actual programme, 2 of these being for the executive programme. The remaining 8 pages were used for storage of voltage and current values.

Restrictions on Existing Programme

The capabilities of the programme described in previous sections were found to be restricted by limitations of the equipment and especially the particular computer used in development. It is important to note these restrictions, for they help to clarify the computer requirements for ultimate substation implementation.

The combined effects of the above-mentioned limitations of the PDP-8 has meant that the existing programme does not operate entirely in real time. As mentioned earlier, it is necessary to accumulate at least 8 post fault samples for an accurate value of Z (ref.4). Thus the fault classification logic is the only other section after detection which can be resolved before the 8th sample is in memory for impedance calculation. The classification logic must therefore be interleaved with sampling. It would be desirable to perforn the impedance calculation of loop D (fig. 1) in a similar manner, so that if the impedance does calculate satisfactorily, return can be made to the cycle-by-cycle comparison stage of loop A without losing samples. It is important that no samples be lost so as not to affect subsequent comparisons. As the PDP-8 is not the machine ultimately suitable for substation application, no attempt was made to return to the comparison stage after the calculation of impedance.

PROPOSED SCHEME FOR RELAYING A THREE-PHASE LINE

The hardware features mentioned in previous sections are available in several of the current group of small general purpose computers. The PDP-8 programme has established the efficacy of fault detection and analysis and the accuracies of impedance calculation. It remains to establish that a basically similar programme for a more suitable computer could be executed in real time, on-line. The Honeywell DDP-5 16 computer was selected for this purpose, not because it was necessarily more attractive than others in the same general class, but because detailed information on the machine was immediately available and furthermore, the instruction code and organization is similar to the PDP-8. This last feature enabled the majority of the PDP-8 subroutines to be coded into DDP-5 16 language virtually on a one-to-one instruction basis. The programme for the DDP-516 is flow-charted in Fig. 6 (the symbols used are as for fig.1). The detailed improvements in each subroutine are summarized in Table II and itemized below. Times referred to are those estimated for a DDP-5 16. Data Acquisition As outlined in the section on restrictions, this is organized by hardware external to the machine and input is via a DMA channel.

entered the PDP-8 under the slow, programmed, data transfer mode described in Appendix II. A data-break or direct memory access (DMA) facility, commonly available in this class of computer would be much more satisfactory (see Appendix II). With this type of facility, if A/D conversion is available at the rate of the computer cycle time, the values as converted could be entered directly into core via the DMA channel with very little buffer storage. If a slower A/D converter (still less than 10 ,us conversion time) is to be used, all the voltages and currents would have to be stored in buffers and subsequently read into core in one batch in order to use the DMA channel as efficiently as possible. This would entail more buffer storage. The 12 bit word length of the PDP-8 was also found to be a serious limitation. Since the accuracy of the calculation technique requires at least 10 bits (ref. 4), unnecessary allowance had to be made for time-consuming double precision arithmetic routines. It would be desirable to have a 16 or 18 bit word machine in practice; this would remove the necessity for all the double precision routines except those for squaring the peak current and voltage values.

interface to perform the data acquisition. During development, data

The major restriction was perhaps the lack of special purpose

Improvements in cycle time over that of the PDP-8 are available and would be desirable.- The actual impedance value will not be available more quickly. Rather there will be more time free during sample intervals for inclusion of extra computations.

Allowing for initialisation of the DMA range and address counters plus actual transfer of data, SAMP6 would occupy 25 ,us. This assumes that zero sequence values are entered in an analogous fashion to the line quantities.

MANN AND MORRISON: RELAYING A TRANSMISSION LINE

747

TABLE II: Comparative Subroutine Execution Times

Subroutine
SAMP6 COMP PUSH FTYPE SELCT VPEAK worst case phase faults IPEAK worst case ground faults ZMOD PHASE

Honeywell DDP-516
25 Ms 1 O0s 32 ,us 155 ,us 17 ,us 220 ps

DEC PDP-8
250,us 158 ps

230 fs 50 s

50ups

250,us
60 ,us 120 ps

770

very approx.

1400,us

Data Storage and Fault Detection

Organization as for PDP-8. The speed improvements in PUSH, COMP, FTYPE are largely due to the cycle time improvement (See Table II). Fault Type Determination

Subroutine SELCT is considerably different. The availability of a three-way jump instruction on the DDP-516 reduces subroutine time from 55 Ms to 17 ps.
Calculation of Impedance
It is proposed to organize these sections of the programme somewhat differently. Basically, whereas in the existing programme all the impedance calculations are lumped into one block (fig. 1, block D), it is now necessary to split this up into the following:

VPEAK: Working with the last five samples in core, perform digital smoothing, estimate v and v', square and add these to calculate Vpk2 Include a test for Vpk2 at the end to enable branching back if wrong detection. Worst case time estimate for VPEAK is 220 ps.
IPEAK: Performs the same calculations as VPEAK but on the currents. Extra calculations enabling zero-sequence compensation would extend this subroutine to 250 ps.
ZVAL: Divides Vpk2 by lpk2. Time taken is variable depending on scaling required to preserve fixed point calculations. A reasonable estimate for data from the model transmission line is 60 ,us.

PHASE: Almost the same as the PDP-8 arctan subroutine. Time required 114 ps. This would have to be performed twice to yield point-on-cycle phase for voltage and current with subsequent subtraction to yield arg. Z.
Features of the overall flowchart are:
The normal healthy mode loop E, only uses 175 ps compared with 460 ps previously. This would permit some other mode of detection to be incorporated - overcurrent detection for example could provide useful backup.

Fig. 6. Flowchart - proposed real-time on-line programme (Legend as for fig. 1).

Provision is now made to loop back at branch F, for the case in which the fault is not immediately classifiable. The loop could be entered more than once. Appropriate selection of tolerances EPSV and EPSZ should always ensure a positive exit. A return could be made to loop E if branch F is entered more than a specified number of times.

Sampling is continued throughout the calculation stage. If any of the tests for peak current, voltage and impedance proved satisfactory, return can readily be made to the healthy mode, loop E. Such a case could arise if the disturbance detected occurred on a substantial surge and subsequent calculations proved everything normal.

748

IEEE TRANSACTIONS ON POWER APPARATUS AND SYSTEMS,

MARCH/APRIL 1971

Return must be made to ioop E before 35 sample intervals after the initial disturbance have elapsed. The cycle-by-cycle detection scheme compares each sample with the corresponding sample of the preceding cycle. Return to this loop must be such that this detection can still perform, i.e. before one faulted cycle has been read in, with allowance made for 5 or 6 samples to enable detection.

Using an available small process control computer (PDP-8) and fault data from a model transmission line, the programme and the detection and classification stages have been shown to be reliable on 1000 faults. For these faults the impedance has calculated to within 10% of its value in 98.5% of cases; the variance of the impedance value for these faults is 4.3%.
The programme calculates both modulus and argument of the complex impedance, allowing the possibility of more flexible relay characteristics and more sophisticated zero sequence compensation for ground faults.

The estimated subroutine times circled on the flowchart (fig.6) are expected to be accurate to within 10%. Assuming the worst case, and also assuming that additional routines have to be included upon implementation, it can be seen that there is still adequate time available between sample intervals to perform extra computations.

EXTENSIONS TO A "BUS LEVEL COMPUTER"

The obvious extension of the foregoing is to include the protection of more than one line. The scheme as proposed very readily adapts to protection of all the lines at the one bus voltage level.

It has further been shown that this basic method of protection of a single three-phase line is, in principle, simply extended to a number of lines at the same bus-voltage level.

Since all the lines at a bus level have the same voltage, the detection, fault classification and peak voltage calculation stages of the programme would remain the same.
When peak current is to be calculated, this would have to be performed for all the lines at that bus voltage level. Assume for simplicity that each peak current takes one sampling interval to compute, so with all the peak line currents calculated, there follows a priority scheme to calculate 0. For severe close-up faults, the line with the highest peak current would be the faulted one, in which case the 0 value for this line would be compted first. For these faults therefore if there were say 6 lines at the bus, calculation of impedance would require an extra 5 sample intervals i.e. total time of 8.5 ms as opposed to the present 6 ms. Thus the inclusion of extra lines into the protection programme is straight-forward in principle. The extra cost involved would be in storage for data and in buffer storage for interface. It must be noted that, for 6 lines, the SAMP6 subroutine would now take longer (50 gs). Furthermore the subroutines after the fault has been verified would be more complicated. The computer still has to protect the other five lines while providing fault diagnostics and checking on breaker operation for the faulted line. Housekeeping routines would in general be more lengthy. Thus it is not certain as yet whether such a scheme is feasible. The continual advances in computer technology, especially in the reduction of cycle times and costs seem to be helpful.
The problem of protection of mutually coupled lines is relatively difficult with existing analogue devices. The digital scheme proposed could offer accurate protection for the case of mutually coupled lines, as it would be possible first to discriminate which of the pair were faulty on the basis of their peak currents and then compensate for mutuals accordingly.

Experience accumulated during the development of the basic programme has revealed the shortcomings of the particular hardware used and has clarified the computer requirements for projected substation installation.
Some minimum basic requirements for such a computer have been found to be, an 8K basic m/c, a 16 bit word and cycle time less than I ,us. An A/D converter and associated interface linked through a DMA channel are required for input/output. These requirements are available in several of the current group of small general purpose digital computers. The analogue-to-digital interface could well be the only non-standard item required. The need for custom-built hardware has therefore almost entirely been avoided.

The basic programme as developed has been rewritten for one of the available computers which incorporates the desirable features. The feasibility of running the existing programme in real time has thus been demonstrated.
APPENDIX I

Glossary of Mnemonics
SAMP6 - Subroutine name. Samples the three voltages and currents sequentially; calculation of the zero sequence voltage and current is interleaved with the sampling; the eight quantities so derived are stored.

COMP - Subroutine. Performs the cycle-by-cycle comparison on the voltages. Used in the detection stage to start the relay.
PUSH - Subroutine. Performs housekeeping on the registers used for memory reference in SAMP6 and COMP. FTYPE - Subroutine. Used to calculate the value of NOFG and to prepare NOFR, NOFY, NOFB for the subroutine SELCT.

CONCLUSIONS
A working digital computer programme has been developed for the protection of a single three-phase transmission line.

Two basic concepts have facilitated the operation of the protection in times fess than one-half of a cycle (10 ms). Firstly the complexity of calculation has been reduced by converting the essentially parallel operation of analogue relays into serial digital computations. Secondly, no data from healthy phases is involved in the calculation of impedance. These have required the development of a flexible scheme. which, upon detection of a disturbance, isolates the phases involved and selects an appropriate set of relaying currents and voltages for subsequent impedance calculation.

SELCT - Selects the 2 quantities (from red, yellow or blue phase or ground) from which the equivalent single phase relaying quantity is to be derived.
NOFR - Red phase counter used in detection or relay starting phase. Indicates likelihood of red phase being involved in the fault. Value 4 or 5, definitely faulted; value 0 or 1 definitely not, value 2 or 3 not determined.

NOFY, NOFB - Similar to NOFR but for yellow and blue phases.
NOFG - Equivalent counter to NOFR but for zero seq. voltage.

MANN AND MORRISON: RELAYING A TRANSMISSION LINE

749
ACKNOWLEDGEMENTS

EPSV -Tolerance used in cycle-by-cycle comparison on voltage, change must exceed this value to register as an "unhealthy" comparison. CNOFV - Value of NOFR etc. required for fault detection.
EPSZ - Tolerance used in determining if a zero seq. value is excessive.

Commission of N.S.W. Discussions with Mr. W. Linn of the Electricity Commission and Mr. A. D. McInnes have proved particularly helpful.

financial support of the Electrical Research Board and the Electricity

The work described in this paper has been made possible by the

APPENDIX II
TABLE III: Some Machine Fundamentals.

Further, the authors wish to acknowledge the support and encouragement of their colleagues, Associate Professor G. C. Dewsnap and Mr. G. H. Couch.

REFERENCES
1. 1. F. Morrison, "Prospects of on-line computer control in transmission systems and substations," Elec. Eng. Trans. I.E. Aust., Vol. EE3, pp. 234-6, Sept. 1967. 2. G. D. Rockefeller, "Fault protection with a digital computer," I.E.E.E. Trans. Power Apparatus and Systems, Vol. 88, pp. 438-464, April 1969.

3. B. J. Mann, "Real time computer calculation of the impedance of a faulted single-phase line," Elec. Eng. Trans. I.E. Aust., Vol. EE4, pp. 26-8, March 1969.
4. B. J. Mann and I. F. Morrison, "Digital calculation of impedance for transmission line protection," Paper No. 70 TP 165-PWR, presented at the I.E.E.E. Winter Power Meeting, New York, N.Y., Jan. 25-30, 1970. 5. P. E. Mantey, "Computer requirements for event recording, digital relaying and substation monitoring," 6th P.I.C.A. Conference Proceedings, 1969, pp. 262-272.
Table of comparative features of the two computers used in text. Further information from appropriate handbooks.
Reference in the text has been made to programmed data transfer and to DMA channels. Under programmed data transfer an instruction is issued to start the A/D converter. The computer then samples a busy/done flag to await conversion completion. When complete, the computer instruction reads the digital number into the accumulator where it is usually stored indirectly in some location. Each of these instructions take up to three cycle times and when followed by an increment multiplexer command (to change the analogue signal at the input to the A/D converter), 15 cycle times have elapsed apart from actual A/D conversion time. This data entry mode was used in the existing programme with the PDP-8. The data-break facility on the other hand, allows direct access to memory much more quickly. The external device, here the A/D converter, issues a signal which interrupts the programme, stealing a number of cycles of machine time during which a group of digital numbers is entered into core. The programme then continues. Hardware registers indicate where the information is to be stored (the address register) and the number of items in the group (the range counter). Two cycles of machine time are usually required for initializing and entering the first number, while subsequent numbers require one cycle each. It can be seen that a considerable speed increase over the previous method is achieved.

6. Digital Equipment Corporation, 1966-67.

Small Computer Handbook,

7. W. A. Lewis and L. S. Tippett, "Fundamental Basis for distance relaying on 3-phase systems," A.I.E.E. Trans., Vol. 66, pp. 694-709, 1947.

8. A. R. van C. Warrington, Protective Relays their theory and practice - Vol. 1, London: Chapman & Hall, 1962.
9. A. R. van C. Warrington, Protective Relays their theory and practice - Vol. II, London: Chapman & Hall, 1969.

10. E. B. Davison and A. Wright, "Some factors affecting the accuracy of distance-type protective equipment under earth fault conditions," Proc. I.E.E., Vol. 110, No. 9, pp. 1678-1688, Sept.

1963.

11. C. Adamson and A. Tureli, "Errors of sound-phase-compensation and residual compensation systems in earth-fault distance relaying," Proc. I.E.E., Vol. 112, No. 7, pp. 1369-1382, July 1965.

12. Honeywell Inc., Programmers reference manual DDP-516 General purpose computer, April 1969.

H316 and

750

IEEE

TRANSACTIONS ON POWER APPARATUS AND

SYSTEMS, MARCH/APRIL 1971

Discussion

B. J. Mann and I. F. Morrison: We are grateful to Messrs. Agrawal and Swift for pointing out our misleading value of impedance angle. In fact the model transmission line itself had

XL/RL = 7.22,
and the line-plus-source

A. Agrawal and G. W. Swift (University of Manitoba, Winnipeg, Canada): We have found the authors' paper very enlightening and would like to ask some questions and present some ideas in a spirit of cooperation rather than criticism. We note that the model line impedance was 0.291 /-43 ohms. Is there some reason why a more typical impedance phase angle was not used, e.g. +700? The reason we ask this question is in connection with current dc offset transients, which decay slowly for high L/R ratios of line-plus-source impedance. The impedance calculation method outlined in the paper results in large errors if any dc offset is present. The method in the paper uses i and it at time t to compute lpk and Io. What we have had some success with is the use of i1'and i2 'at times t, and t2 to compute I pk and 1I. These current derivatives are relatively unaffected by the dc offset. They come simply from successive differences of three consecutive current samples. The expressions (left as an exercise the reader will undoubtedly wish to carry out for himself) are relatively complex, so the calculation time is higher. A related question concerns the authors' assumption that the calculated value of Z "stabilizes" after eight samples (four milliseconds). It does for the model line, but some Manitoba Hydro staged fault tests and other results (ref. 13) indicate that voltage or current high frequency transients may last a cycle or more. Do the authors propose any analog or digital filtering in connection with their
scheme?

XS/R, = 10.9.
The measured value of angle (Table I) appears to be small and negative because, as in Ref. 4, the DC offset in the current signals has been largely removed by use of a "mimic impedance" in the CT secondary, i.e. an impedance with an X/R ratio close to that of the line-plussource impedance. This results in a phase shift of the secondary current signal by an angle close to 90 relative to the voltage signal. As to the second point raised by Messrs. Agrawal and Swift regarding the effect of long-lived high frequency transients in the current and voltage, the same query was raised in the discussion of Reference 4 and we would direct their attention to our closure of that discussion. There we commented that inaccuracies in impedance measurement due to the presence of noise (of all types, not that due to the effects of line capacitance only) need to be evaluated. Although we applied no deliberate analogue filtering to our signals we foresee the necessity for this in some practical situations. Such filtering may well introduce additional delays in calculation. We estimate that an input channel 3db point around 200Hz would be appropriate.

Manuscript received September 8, 1970.

[13] G. R. Slemon, S.T.D. Robertson, and M. Ramamoorty, "High Speed Protection of Power Systems based on Improved Power System Models," CIGRE, Paper No. 31-09, vol. 2, 1968.

B. J. Mann (M'68), for a photograph and biography, please see page 388 of the January/February 1971 issue of this TRANSACTIONS.

Manuscript received August

13, 1970.

I. F. Morrison (M'68), for a photograph and biography, please see page 389 of the January/February 1971 issue of this TRANSACTIONS.