Go

Script started on Tue 05 Mar 2013 09:08:00 AM CST [root@localhost 32]# cd /simplesim-3.0/ <<.
/sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 i l2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb:dtlb none ./benc hmarks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 il2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb :dtlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:06 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
false false false false 1 false <null> <null>
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:l # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:l # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
<null> # profile stat(s) against text addr's (mult uses o
The cache config parameter <config> has the following format:
<name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708115 # total number of hits il1.misses 1206 # total number of misses il1.replacements 298 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0017 # miss rate (i.e., misses/ref) il1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 1206 # total number of accesses il2.hits 105 # total number of hits il2.misses 1101 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9129 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186469 # total number of hits dl1.misses 10209 # total number of misses dl1.replacements 8161 # total number of replacements dl1.writebacks 7362 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0519 # miss rate (i.e., misses/ref)
dl1.repl_rate 0.0415 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0374 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 17571 # total number of accesses dl2.hits 8304 # total number of hits dl2.misses 9267 # total number of misses dl2.replacements 124 # total number of replacements dl2.writebacks 60 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5274 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0071 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0034 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 i l2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb:dtlb none ./benc hmarks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 il2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb :dtlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:06 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # load configuration from a file # dump configuration to a file
# -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)
# # # # # # # #
print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:f # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:f # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds
sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708115 # total number of hits il1.misses 1206 # total number of misses il1.replacements 298 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0017 # miss rate (i.e., misses/ref) il1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 1206 # total number of accesses il2.hits 105 # total number of hits il2.misses 1101 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9129 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186469 # total number of hits dl1.misses 10209 # total number of misses dl1.replacements 8161 # total number of replacements dl1.writebacks 7362 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0519 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0415 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0374 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 17571 # total number of accesses dl2.hits 8304 # total number of hits dl2.misses 9267 # total number of misses dl2.replacements 124 # total number of replacements dl2.writebacks 60 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5274 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0071 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0034 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 i
l2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb:dtlb none ./benc hmarks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 il2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb :dtlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:06 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:r # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:r # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> - name of the cache being defined <nsets> - number of sets in the cache
<bsize> - block size of the cache <assoc> - associativity of the cache <repl> - block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random Examples: -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708115 # total number of hits il1.misses 1206 # total number of misses il1.replacements 298 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0017 # miss rate (i.e., misses/ref) il1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 1206 # total number of accesses il2.hits 105 # total number of hits il2.misses 1101 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9129 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186469 # total number of hits dl1.misses 10209 # total number of misses dl1.replacements 8161 # total number of replacements dl1.writebacks 7362 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0519 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0415 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0374 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 17571 # total number of accesses
dl2.hits 8304 # total number of hits dl2.misses 9267 # total number of misses dl2.replacements 124 # total number of replacements dl2.writebacks 60 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5274 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0071 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0034 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 i l2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:dtlb none ./benchm arks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 il2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:d tlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:06 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # # # # # # -config -dumpconfig -h -v -d -i # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger
false false false false
-seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)
1 false <null> <null>
# # # #
random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:l # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:l # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708115 # total number of hits il1.misses 1206 # total number of misses
il1.replacements 298 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0017 # miss rate (i.e., misses/ref) il1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 1206 # total number of accesses il2.hits 105 # total number of hits il2.misses 1101 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9129 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186469 # total number of hits dl1.misses 10209 # total number of misses dl1.replacements 8161 # total number of replacements dl1.writebacks 7362 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0519 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0415 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0374 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 17571 # total number of accesses dl2.hits 8334 # total number of hits dl2.misses 9237 # total number of misses dl2.replacements 28 # total number of replacements dl2.writebacks 11 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5257 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0016 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 i l2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:dtlb none ./benchm arks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass
2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 il2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:d tlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:06 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:f # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:f # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random
Examples:
-cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708115 # total number of hits il1.misses 1206 # total number of misses il1.replacements 298 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0017 # miss rate (i.e., misses/ref) il1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 1206 # total number of accesses il2.hits 105 # total number of hits il2.misses 1101 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9129 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186469 # total number of hits dl1.misses 10209 # total number of misses dl1.replacements 8161 # total number of replacements dl1.writebacks 7362 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0519 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0415 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0374 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 17571 # total number of accesses dl2.hits 8334 # total number of hits dl2.misses 9237 # total number of misses dl2.replacements 28 # total number of replacements dl2.writebacks 11 # total number of writebacks
dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5257 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0016 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 i l2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:dtlb none ./benchm arks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 il2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:d tlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:06 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:r # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:r # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708115 # total number of hits il1.misses 1206 # total number of misses il1.replacements 298 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0017 # miss rate (i.e., misses/ref)
il1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 1206 # total number of accesses il2.hits 99 # total number of hits il2.misses 1107 # total number of misses il2.replacements 22 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9179 # miss rate (i.e., misses/ref) il2.repl_rate 0.0182 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186469 # total number of hits dl1.misses 10209 # total number of misses dl1.replacements 8161 # total number of replacements dl1.writebacks 7362 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0519 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0415 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0374 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 17571 # total number of accesses dl2.hits 8310 # total number of hits dl2.misses 9261 # total number of misses dl2.replacements 846 # total number of replacements dl2.writebacks 803 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5271 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0481 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0457 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:06 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
Cache levels can be unified by pointing a level of the instruction cache
hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708115 # total number of hits il1.misses 1206 # total number of misses il1.replacements 298 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0017 # miss rate (i.e., misses/ref) il1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186469 # total number of hits dl1.misses 10209 # total number of misses dl1.replacements 8161 # total number of replacements dl1.writebacks 7362 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0519 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0415 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0374 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 18777 # total number of accesses dl2.hits 8429 # total number of hits dl2.misses 10348 # total number of misses dl2.replacements 430 # total number of replacements dl2.writebacks 213 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5511 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0229 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0113 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC)
ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:06 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ
ivalents # -pcstat k)
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708115 # total number of hits il1.misses 1206 # total number of misses il1.replacements 298 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0017 # miss rate (i.e., misses/ref) il1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186469 # total number of hits dl1.misses 10209 # total number of misses dl1.replacements 8161 # total number of replacements dl1.writebacks 7362 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0519 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0415 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0374 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 18777 # total number of accesses
dl2.hits 8429 # total number of hits dl2.misses 10348 # total number of misses dl2.replacements 430 # total number of replacements dl2.writebacks 213 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5511 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0229 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0113 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:06 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # # # # # # -config -dumpconfig -h -v -d -i # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger
-seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
il1.replacements 298 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0017 # miss rate (i.e., misses/ref) il1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186469 # total number of hits dl1.misses 10209 # total number of misses dl1.replacements 8161 # total number of replacements dl1.writebacks 7362 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0519 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0415 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0374 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 18777 # total number of accesses dl2.hits 8429 # total number of hits dl2.misses 10348 # total number of misses dl2.replacements 430 # total number of replacements dl2.writebacks 213 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5511 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0229 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0113 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored...
sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:06 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l
Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 sim_num_refs 196640 sim_elapsed_time 1 sim_inst_rate 709321.0000 il1.accesses 709321 il1.hits 708115 il1.misses 1206 il1.replacements 298 il1.writebacks 0 il1.invalidations 0 il1.miss_rate 0.0017 il1.repl_rate 0.0004 il1.wb_rate 0.0000 il1.inv_rate 0.0000 dl1.accesses 196678 dl1.hits 186469 dl1.misses 10209 dl1.replacements 8161 dl1.writebacks 7362 dl1.invalidations 0 dl1.miss_rate 0.0519 dl1.repl_rate 0.0415 dl1.wb_rate 0.0374 dl1.inv_rate 0.0000 dl2.accesses 18777 dl2.hits 8440 dl2.misses 10337 dl2.replacements 6 dl2.writebacks 5 dl2.invalidations 0 dl2.miss_rate 0.5505 dl2.repl_rate 0.0003 dl2.wb_rate 0.0003 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 376832 ld_data_base 0x0140000000 ld_data_size 612032 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x0120007bb0 ld_environ_base 0x011ff97000 ld_target_big_endian 0 big endian mem.page_count 111 mem.page_mem 888k mem.ptab_misses 1866 # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs
# program stack segment base (highest addres # # # # program initial stack size program entry point (initial PC) program environment base address address target executable endian-ness, non-zero if
# total number of pages allocated # total size of memory pages allocated # total first level page table misses
mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:06 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format:
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708115 # total number of hits il1.misses 1206 # total number of misses il1.replacements 298 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0017 # miss rate (i.e., misses/ref) il1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186469 # total number of hits dl1.misses 10209 # total number of misses dl1.replacements 8161 # total number of replacements dl1.writebacks 7362 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0519 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0415 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0374 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 18777 # total number of accesses dl2.hits 8440 # total number of hits dl2.misses 10337 # total number of misses dl2.replacements 6 # total number of replacements dl2.writebacks 5 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5505 # miss rate (i.e., misses/ref)
dl2.repl_rate 0.0003 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0003 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32:1:l -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:l -cache:dl1 dl1:2048:32 :1:l -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:06 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file
-nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708115 # total number of hits il1.misses 1206 # total number of misses il1.replacements 298 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0017 # miss rate (i.e., misses/ref) il1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref)
il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186469 # total number of hits dl1.misses 10209 # total number of misses dl1.replacements 8161 # total number of replacements dl1.writebacks 7362 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0519 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0415 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0374 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 18777 # total number of accesses dl2.hits 8425 # total number of hits dl2.misses 10352 # total number of misses dl2.replacements 374 # total number of replacements dl2.writebacks 222 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5513 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0199 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0118 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 i l2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb:dtlb none ./benc hmarks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 il2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb :dtlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:06 2013, options follow:
sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:l # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:l # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 sim_num_refs 196640 sim_elapsed_time 1 sim_inst_rate 709321.0000 il1.accesses 709321 il1.hits 708115 il1.misses 1206 il1.replacements 298 il1.writebacks 0 il1.invalidations 0 il1.miss_rate 0.0017 il1.repl_rate 0.0004 il1.wb_rate 0.0000 il1.inv_rate 0.0000 il2.accesses 1206 il2.hits 105 il2.misses 1101 il2.replacements 0 il2.writebacks 0 il2.invalidations 0 il2.miss_rate 0.9129 il2.repl_rate 0.0000 il2.wb_rate 0.0000 il2.inv_rate 0.0000 dl1.accesses 196678 dl1.hits 186469 dl1.misses 10209 dl1.replacements 8161 dl1.writebacks 7362 dl1.invalidations 0 dl1.miss_rate 0.0519 dl1.repl_rate 0.0415 dl1.wb_rate 0.0374 dl1.inv_rate 0.0000 dl2.accesses 17571 dl2.hits 8304 dl2.misses 9267 dl2.replacements 124 dl2.writebacks 60 dl2.invalidations 0 dl2.miss_rate 0.5274 dl2.repl_rate 0.0071 dl2.wb_rate 0.0034 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 376832 ld_data_base 0x0140000000 ld_data_size 612032 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x0120007bb0 ld_environ_base 0x011ff97000 ld_target_big_endian 0 # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs
big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 i l2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb:dtlb none ./benc hmarks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 il2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb :dtlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:06 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:f # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:f # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708115 # total number of hits il1.misses 1206 # total number of misses il1.replacements 298 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0017 # miss rate (i.e., misses/ref) il1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 1206 # total number of accesses il2.hits 105 # total number of hits il2.misses 1101 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9129 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186469 # total number of hits dl1.misses 10209 # total number of misses
dl1.replacements 8161 # total number of replacements dl1.writebacks 7362 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0519 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0415 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0374 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 17571 # total number of accesses dl2.hits 8304 # total number of hits dl2.misses 9267 # total number of misses dl2.replacements 124 # total number of replacements dl2.writebacks 60 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5274 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0071 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0034 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 i l2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb:dtlb none ./benc hmarks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 il2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb :dtlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:06 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing
information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:r # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:r # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call...
sim: ** simulation statistics ** sim_num_insn 709321 sim_num_refs 196640 sim_elapsed_time 1 sim_inst_rate 709321.0000 il1.accesses 709321 il1.hits 708115 il1.misses 1206 il1.replacements 298 il1.writebacks 0 il1.invalidations 0 il1.miss_rate 0.0017 il1.repl_rate 0.0004 il1.wb_rate 0.0000 il1.inv_rate 0.0000 il2.accesses 1206 il2.hits 105 il2.misses 1101 il2.replacements 0 il2.writebacks 0 il2.invalidations 0 il2.miss_rate 0.9129 il2.repl_rate 0.0000 il2.wb_rate 0.0000 il2.inv_rate 0.0000 dl1.accesses 196678 dl1.hits 186469 dl1.misses 10209 dl1.replacements 8161 dl1.writebacks 7362 dl1.invalidations 0 dl1.miss_rate 0.0519 dl1.repl_rate 0.0415 dl1.wb_rate 0.0374 dl1.inv_rate 0.0000 dl2.accesses 17571 dl2.hits 8304 dl2.misses 9267 dl2.replacements 124 dl2.writebacks 60 dl2.invalidations 0 dl2.miss_rate 0.5274 dl2.repl_rate 0.0071 dl2.wb_rate 0.0034 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 376832 ld_data_base 0x0140000000 ld_data_size 612032 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x0120007bb0 ld_environ_base 0x011ff97000 ld_target_big_endian 0 big endian mem.page_count 111 mem.page_mem 888k mem.ptab_misses 1866
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs
mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 i l2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:dtlb none ./benchm arks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 il2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:d tlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:06 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:l # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:l # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
dl1.repl_rate 0.0415 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0374 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 17571 # total number of accesses dl2.hits 8334 # total number of hits dl2.misses 9237 # total number of misses dl2.replacements 28 # total number of replacements dl2.writebacks 11 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5257 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0016 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 i l2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:dtlb none ./benchm arks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 il2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:d tlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:06 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # load configuration from a file # dump configuration to a file
# -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)
# # # # # # # #
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:f # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:f # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708115 # total number of hits il1.misses 1206 # total number of misses il1.replacements 298 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0017 # miss rate (i.e., misses/ref) il1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 1206 # total number of accesses il2.hits 105 # total number of hits il2.misses 1101 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9129 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186469 # total number of hits dl1.misses 10209 # total number of misses dl1.replacements 8161 # total number of replacements dl1.writebacks 7362 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0519 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0415 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0374 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 17571 # total number of accesses dl2.hits 8334 # total number of hits dl2.misses 9237 # total number of misses dl2.replacements 28 # total number of replacements dl2.writebacks 11 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5257 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0016 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 i
l2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:dtlb none ./benchm arks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 il2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:d tlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:07 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:r # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:r # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
dl2.hits 8310 # total number of hits dl2.misses 9261 # total number of misses dl2.replacements 846 # total number of replacements dl2.writebacks 803 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5271 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0481 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0457 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:07 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # # # # # # -config -dumpconfig -h -v -d -i # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger
-seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
il1.replacements 298 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0017 # miss rate (i.e., misses/ref) il1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186469 # total number of hits dl1.misses 10209 # total number of misses dl1.replacements 8161 # total number of replacements dl1.writebacks 7362 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0519 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0415 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0374 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 18777 # total number of accesses dl2.hits 8429 # total number of hits dl2.misses 10348 # total number of misses dl2.replacements 430 # total number of replacements dl2.writebacks 213 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5511 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0229 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0113 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored...
sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:07 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:07 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format:
dl2.repl_rate 0.0229 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0113 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:07 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
-nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186469 # total number of hits dl1.misses 10209 # total number of misses dl1.replacements 8161 # total number of replacements dl1.writebacks 7362 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0519 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0415 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0374 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 18777 # total number of accesses dl2.hits 8440 # total number of hits dl2.misses 10337 # total number of misses dl2.replacements 6 # total number of replacements dl2.writebacks 5 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5505 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0003 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0003 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:07 2013, options follow:
sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708115 # total number of hits il1.misses 1206 # total number of misses il1.replacements 298 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0017 # miss rate (i.e., misses/ref) il1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186469 # total number of hits dl1.misses 10209 # total number of misses dl1.replacements 8161 # total number of replacements dl1.writebacks 7362 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0519 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0415 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0374 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 18777 # total number of accesses dl2.hits 8440 # total number of hits dl2.misses 10337 # total number of misses dl2.replacements 6 # total number of replacements dl2.writebacks 5 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5505 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0003 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0003 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32:1:f -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>>
Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:f -cache:dl1 dl1:2048:32 :1:f -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:07 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> name of the cache being defined number of sets in the cache block size of the cache associativity of the cache
<repl> Examples:
- block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708115 # total number of hits il1.misses 1206 # total number of misses il1.replacements 298 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0017 # miss rate (i.e., misses/ref) il1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186469 # total number of hits dl1.misses 10209 # total number of misses dl1.replacements 8161 # total number of replacements dl1.writebacks 7362 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0519 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0415 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0374 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 18777 # total number of accesses dl2.hits 8425 # total number of hits dl2.misses 10352 # total number of misses dl2.replacements 374 # total number of replacements dl2.writebacks 222 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5513 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0199 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0118 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base
ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 i l2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb:dtlb none ./benc hmarks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 il2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb :dtlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:07 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:l # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2
-cache:il2 il2:16384:32:1:l # l2 instruction cache config, i.e., {<config> |dl2|none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708115 # total number of hits il1.misses 1206 # total number of misses il1.replacements 298 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0017 # miss rate (i.e., misses/ref) il1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 1206 # total number of accesses il2.hits 105 # total number of hits il2.misses 1101 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks
il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9129 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186469 # total number of hits dl1.misses 10209 # total number of misses dl1.replacements 8161 # total number of replacements dl1.writebacks 7362 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0519 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0415 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0374 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 17571 # total number of accesses dl2.hits 8304 # total number of hits dl2.misses 9267 # total number of misses dl2.replacements 124 # total number of replacements dl2.writebacks 60 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5274 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0071 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0034 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 i l2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb:dtlb none ./benc hmarks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 il2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb
:dtlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:07 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:f # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:f # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1):
-cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708115 # total number of hits il1.misses 1206 # total number of misses il1.replacements 298 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0017 # miss rate (i.e., misses/ref) il1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 1206 # total number of accesses il2.hits 105 # total number of hits il2.misses 1101 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9129 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186469 # total number of hits dl1.misses 10209 # total number of misses dl1.replacements 8161 # total number of replacements dl1.writebacks 7362 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0519 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0415 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0374 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 17571 # total number of accesses dl2.hits 8304 # total number of hits dl2.misses 9267 # total number of misses dl2.replacements 124 # total number of replacements dl2.writebacks 60 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5274 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0071 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0034 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack)
ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 i l2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb:dtlb none ./benc hmarks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 il2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb :dtlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:07 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:r # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:r # l2 instruction cache config, i.e., {<config> none # instruction TLB config, i.e., {<config>|none} none # data TLB config, i.e., {<config>|none}
-flush -cache:icompress ivalents # -pcstat k)
false # flush caches on system calls false # convert 64-bit inst addresses to 32-bit inst equ <null> # profile stat(s) against text addr's (mult uses o
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708115 # total number of hits il1.misses 1206 # total number of misses il1.replacements 298 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0017 # miss rate (i.e., misses/ref) il1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 1206 # total number of accesses il2.hits 105 # total number of hits il2.misses 1101 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9129 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref)
il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186469 # total number of hits dl1.misses 10209 # total number of misses dl1.replacements 8161 # total number of replacements dl1.writebacks 7362 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0519 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0415 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0374 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 17571 # total number of accesses dl2.hits 8304 # total number of hits dl2.misses 9267 # total number of misses dl2.replacements 124 # total number of replacements dl2.writebacks 60 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5274 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0071 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0034 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 i l2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:dtlb none ./benchm arks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 il2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:d tlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:07 2013, options follow:
sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:l # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:l # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 sim_num_refs 196640 sim_elapsed_time 1 sim_inst_rate 709321.0000 il1.accesses 709321 il1.hits 708115 il1.misses 1206 il1.replacements 298 il1.writebacks 0 il1.invalidations 0 il1.miss_rate 0.0017 il1.repl_rate 0.0004 il1.wb_rate 0.0000 il1.inv_rate 0.0000 il2.accesses 1206 il2.hits 105 il2.misses 1101 il2.replacements 0 il2.writebacks 0 il2.invalidations 0 il2.miss_rate 0.9129 il2.repl_rate 0.0000 il2.wb_rate 0.0000 il2.inv_rate 0.0000 dl1.accesses 196678 dl1.hits 186469 dl1.misses 10209 dl1.replacements 8161 dl1.writebacks 7362 dl1.invalidations 0 dl1.miss_rate 0.0519 dl1.repl_rate 0.0415 dl1.wb_rate 0.0374 dl1.inv_rate 0.0000 dl2.accesses 17571 dl2.hits 8334 dl2.misses 9237 dl2.replacements 28 dl2.writebacks 11 dl2.invalidations 0 dl2.miss_rate 0.5257 dl2.repl_rate 0.0016 dl2.wb_rate 0.0006 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 376832 ld_data_base 0x0140000000 ld_data_size 612032 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x0120007bb0 ld_environ_base 0x011ff97000 ld_target_big_endian 0 # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs
big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 i l2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:dtlb none ./benchm arks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 il2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:d tlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:07 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:f # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:f # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708115 # total number of hits il1.misses 1206 # total number of misses il1.replacements 298 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0017 # miss rate (i.e., misses/ref) il1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 1206 # total number of accesses il2.hits 105 # total number of hits il2.misses 1101 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9129 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186469 # total number of hits dl1.misses 10209 # total number of misses
dl1.replacements 8161 # total number of replacements dl1.writebacks 7362 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0519 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0415 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0374 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 17571 # total number of accesses dl2.hits 8334 # total number of hits dl2.misses 9237 # total number of misses dl2.replacements 28 # total number of replacements dl2.writebacks 11 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5257 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0016 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 i l2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:dtlb none ./benchm arks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 il2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:d tlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:07 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing
information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:r # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:r # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** simulation statistics ** sim_num_insn 709321 sim_num_refs 196640 sim_elapsed_time 1 sim_inst_rate 709321.0000 il1.accesses 709321 il1.hits 708115 il1.misses 1206 il1.replacements 298 il1.writebacks 0 il1.invalidations 0 il1.miss_rate 0.0017 il1.repl_rate 0.0004 il1.wb_rate 0.0000 il1.inv_rate 0.0000 il2.accesses 1206 il2.hits 103 il2.misses 1103 il2.replacements 17 il2.writebacks 0 il2.invalidations 0 il2.miss_rate 0.9146 il2.repl_rate 0.0141 il2.wb_rate 0.0000 il2.inv_rate 0.0000 dl1.accesses 196678 dl1.hits 186469 dl1.misses 10209 dl1.replacements 8161 dl1.writebacks 7362 dl1.invalidations 0 dl1.miss_rate 0.0519 dl1.repl_rate 0.0415 dl1.wb_rate 0.0374 dl1.inv_rate 0.0000 dl2.accesses 17571 dl2.hits 8312 dl2.misses 9259 dl2.replacements 857 dl2.writebacks 825 dl2.invalidations 0 dl2.miss_rate 0.5269 dl2.repl_rate 0.0488 dl2.wb_rate 0.0470 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 376832 ld_data_base 0x0140000000 ld_data_size 612032 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x0120007bb0 ld_environ_base 0x011ff97000 ld_target_big_endian 0 big endian mem.page_count 111 mem.page_mem 888k mem.ptab_misses 1866
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs
mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:07 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format:
dl2.repl_rate 0.0229 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0113 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:07 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
-nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186469 # total number of hits dl1.misses 10209 # total number of misses dl1.replacements 8161 # total number of replacements dl1.writebacks 7362 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0519 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0415 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0374 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 18777 # total number of accesses dl2.hits 8429 # total number of hits dl2.misses 10348 # total number of misses dl2.replacements 430 # total number of replacements dl2.writebacks 213 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5511 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0229 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0113 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:07 2013, options follow:
sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708115 # total number of hits il1.misses 1206 # total number of misses il1.replacements 298 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0017 # miss rate (i.e., misses/ref) il1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186469 # total number of hits dl1.misses 10209 # total number of misses dl1.replacements 8161 # total number of replacements dl1.writebacks 7362 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0519 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0415 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0374 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 18777 # total number of accesses dl2.hits 8429 # total number of hits dl2.misses 10348 # total number of misses dl2.replacements 430 # total number of replacements dl2.writebacks 213 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5511 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0229 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0113 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>>
Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:07 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> name of the cache being defined number of sets in the cache block size of the cache associativity of the cache
<repl> Examples:
ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:08 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2
-cache:il2 |none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)
dl2 # l2 instruction cache config, i.e., {<config>|dl2 none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708115 # total number of hits il1.misses 1206 # total number of misses il1.replacements 298 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0017 # miss rate (i.e., misses/ref) il1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186469 # total number of hits dl1.misses 10209 # total number of misses dl1.replacements 8161 # total number of replacements dl1.writebacks 7362 # total number of writebacks
dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0519 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0415 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0374 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 18777 # total number of accesses dl2.hits 8440 # total number of hits dl2.misses 10337 # total number of misses dl2.replacements 6 # total number of replacements dl2.writebacks 5 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5505 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0003 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0003 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32:1:r -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:2048:32:1:r -cache:dl1 dl1:2048:32 :1:r -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:08 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated.
# -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:2048:32:1:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed
sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708115 # total number of hits il1.misses 1206 # total number of misses il1.replacements 298 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0017 # miss rate (i.e., misses/ref) il1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186469 # total number of hits dl1.misses 10209 # total number of misses dl1.replacements 8161 # total number of replacements dl1.writebacks 7362 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0519 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0415 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0374 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 18777 # total number of accesses dl2.hits 8431 # total number of hits dl2.misses 10346 # total number of misses dl2.replacements 350 # total number of replacements dl2.writebacks 201 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5510 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0186 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0107 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 i l2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb:dtlb none ./benc hmarks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 il2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb :dtlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:08 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:l # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:l # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708211 # total number of hits il1.misses 1110 # total number of misses il1.replacements 86 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0016 # miss rate (i.e., misses/ref) il1.repl_rate 0.0001 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 1110 # total number of accesses il2.hits 9 # total number of hits il2.misses 1101 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9919 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186670 # total number of hits dl1.misses 10008 # total number of misses dl1.replacements 7960 # total number of replacements dl1.writebacks 7287 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0509 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0405 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0371 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 17295 # total number of accesses dl2.hits 8039 # total number of hits dl2.misses 9256 # total number of misses dl2.replacements 113 # total number of replacements dl2.writebacks 45 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5352 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0065 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0026 # writeback rate (i.e., wrbks/ref)
dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 i l2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb:dtlb none ./benc hmarks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 il2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb :dtlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:08 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute
-cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)
dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:f # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:f # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708211 # total number of hits il1.misses 1110 # total number of misses il1.replacements 86 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0016 # miss rate (i.e., misses/ref) il1.repl_rate 0.0001 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 1110 # total number of accesses
il2.hits 9 # total number of hits il2.misses 1101 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9919 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186670 # total number of hits dl1.misses 10008 # total number of misses dl1.replacements 7960 # total number of replacements dl1.writebacks 7287 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0509 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0405 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0371 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 17295 # total number of accesses dl2.hits 8039 # total number of hits dl2.misses 9256 # total number of misses dl2.replacements 113 # total number of replacements dl2.writebacks 45 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5352 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0065 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0026 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 i l2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb:dtlb none ./benc hmarks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com).
warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 il2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb :dtlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:08 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:r # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:r # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2):
-cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708211 # total number of hits il1.misses 1110 # total number of misses il1.replacements 86 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0016 # miss rate (i.e., misses/ref) il1.repl_rate 0.0001 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 1110 # total number of accesses il2.hits 9 # total number of hits il2.misses 1101 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9919 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186670 # total number of hits dl1.misses 10008 # total number of misses dl1.replacements 7960 # total number of replacements dl1.writebacks 7287 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0509 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0405 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0371 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 17295 # total number of accesses dl2.hits 8039 # total number of hits dl2.misses 9256 # total number of misses dl2.replacements 113 # total number of replacements dl2.writebacks 45 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5352 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0065 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0026 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base
ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 i l2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:dtlb none ./benchm arks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 il2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:d tlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:08 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:l # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2
-cache:il2 il2:8192:32:2:l # l2 instruction cache config, i.e., {<config>| dl2|none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708211 # total number of hits il1.misses 1110 # total number of misses il1.replacements 86 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0016 # miss rate (i.e., misses/ref) il1.repl_rate 0.0001 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 1110 # total number of accesses il2.hits 9 # total number of hits il2.misses 1101 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks
il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9919 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186670 # total number of hits dl1.misses 10008 # total number of misses dl1.replacements 7960 # total number of replacements dl1.writebacks 7287 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0509 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0405 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0371 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 17295 # total number of accesses dl2.hits 8058 # total number of hits dl2.misses 9237 # total number of misses dl2.replacements 28 # total number of replacements dl2.writebacks 11 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5341 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0016 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 i l2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:dtlb none ./benchm arks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 il2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:d
tlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:08 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:f # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:f # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708211 # total number of hits il1.misses 1110 # total number of misses il1.replacements 86 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0016 # miss rate (i.e., misses/ref) il1.repl_rate 0.0001 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 1110 # total number of accesses il2.hits 9 # total number of hits il2.misses 1101 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9919 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186670 # total number of hits dl1.misses 10008 # total number of misses dl1.replacements 7960 # total number of replacements dl1.writebacks 7287 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0509 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0405 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0371 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 17295 # total number of accesses dl2.hits 8058 # total number of hits dl2.misses 9237 # total number of misses dl2.replacements 28 # total number of replacements dl2.writebacks 11 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5341 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0016 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack)
ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 i l2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:dtlb none ./benchm arks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 il2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:d tlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:08 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:r # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:r # l2 instruction cache config, i.e., {<config>| none # instruction TLB config, i.e., {<config>|none} none # data TLB config, i.e., {<config>|none}
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708211 # total number of hits il1.misses 1110 # total number of misses il1.replacements 86 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0016 # miss rate (i.e., misses/ref) il1.repl_rate 0.0001 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 1110 # total number of accesses il2.hits 7 # total number of hits il2.misses 1103 # total number of misses il2.replacements 22 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9937 # miss rate (i.e., misses/ref) il2.repl_rate 0.0198 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref)
il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186670 # total number of hits dl1.misses 10008 # total number of misses dl1.replacements 7960 # total number of replacements dl1.writebacks 7287 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0509 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0405 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0371 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 17295 # total number of accesses dl2.hits 8032 # total number of hits dl2.misses 9263 # total number of misses dl2.replacements 804 # total number of replacements dl2.writebacks 758 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5356 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0465 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0438 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:08 2013, options follow:
sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708211 # total number of hits il1.misses 1110 # total number of misses il1.replacements 86 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0016 # miss rate (i.e., misses/ref) il1.repl_rate 0.0001 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186670 # total number of hits dl1.misses 10008 # total number of misses dl1.replacements 7960 # total number of replacements dl1.writebacks 7287 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0509 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0405 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0371 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 18405 # total number of accesses dl2.hits 8061 # total number of hits dl2.misses 10344 # total number of misses dl2.replacements 426 # total number of replacements dl2.writebacks 207 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5620 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0231 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0112 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>>
Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:08 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> name of the cache being defined number of sets in the cache block size of the cache associativity of the cache
<repl> Examples:
ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:08 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2
dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0509 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0405 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0371 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 18405 # total number of accesses dl2.hits 8061 # total number of hits dl2.misses 10344 # total number of misses dl2.replacements 426 # total number of replacements dl2.writebacks 207 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5620 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0231 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0112 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:08 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated.
# -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708211 # total number of hits il1.misses 1110 # total number of misses il1.replacements 86 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0016 # miss rate (i.e., misses/ref) il1.repl_rate 0.0001 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186670 # total number of hits dl1.misses 10008 # total number of misses dl1.replacements 7960 # total number of replacements dl1.writebacks 7287 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0509 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0405 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0371 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 18405 # total number of accesses dl2.hits 8068 # total number of hits dl2.misses 10337 # total number of misses dl2.replacements 6 # total number of replacements dl2.writebacks 5 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5616 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0003 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0003 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:08 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32:2:l -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:l -cache:dl1 dl1:1024:32 :2:l -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:08 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:l # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ
dl2.hits 8056 # total number of hits dl2.misses 10349 # total number of misses dl2.replacements 346 # total number of replacements dl2.writebacks 203 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5623 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0188 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0110 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 i l2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb:dtlb none ./benc hmarks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 il2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb :dtlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:08 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # # # # # # -config -dumpconfig -h -v -d -i # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger
-seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)
# # # #
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:l # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:l # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
il1.replacements 89 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0016 # miss rate (i.e., misses/ref) il1.repl_rate 0.0001 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 1113 # total number of accesses il2.hits 12 # total number of hits il2.misses 1101 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9892 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186660 # total number of hits dl1.misses 10018 # total number of misses dl1.replacements 7970 # total number of replacements dl1.writebacks 7281 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0509 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0405 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0370 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 17299 # total number of accesses dl2.hits 8037 # total number of hits dl2.misses 9262 # total number of misses dl2.replacements 119 # total number of replacements dl2.writebacks 48 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5354 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0069 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0028 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 i l2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb:dtlb none ./benc hmarks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass
2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 il2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb :dtlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:08 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:f # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:f # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
Examples:
dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5354 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0069 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0028 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 i l2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb:dtlb none ./benc hmarks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 il2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb :dtlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:08 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:r # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:r # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
il1.repl_rate 0.0001 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 1113 # total number of accesses il2.hits 12 # total number of hits il2.misses 1101 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9892 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186660 # total number of hits dl1.misses 10018 # total number of misses dl1.replacements 7970 # total number of replacements dl1.writebacks 7281 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0509 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0405 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0370 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 17299 # total number of accesses dl2.hits 8037 # total number of hits dl2.misses 9262 # total number of misses dl2.replacements 119 # total number of replacements dl2.writebacks 48 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5354 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0069 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0028 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 i l2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:dtlb none ./benchm arks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 il2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:d tlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:08 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:l # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:l # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708208 # total number of hits il1.misses 1113 # total number of misses il1.replacements 89 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0016 # miss rate (i.e., misses/ref) il1.repl_rate 0.0001 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 1113 # total number of accesses il2.hits 12 # total number of hits il2.misses 1101 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9892 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186660 # total number of hits dl1.misses 10018 # total number of misses dl1.replacements 7970 # total number of replacements dl1.writebacks 7281 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0509 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0405 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0370 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 17299 # total number of accesses dl2.hits 8062 # total number of hits dl2.misses 9237 # total number of misses dl2.replacements 28 # total number of replacements dl2.writebacks 11 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5340 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0016 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref)
dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 i l2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:dtlb none ./benchm arks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 il2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:d tlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:09 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
-cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)
dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:f # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:f # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708208 # total number of hits il1.misses 1113 # total number of misses il1.replacements 89 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0016 # miss rate (i.e., misses/ref) il1.repl_rate 0.0001 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 1113 # total number of accesses
il2.hits 12 # total number of hits il2.misses 1101 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9892 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186660 # total number of hits dl1.misses 10018 # total number of misses dl1.replacements 7970 # total number of replacements dl1.writebacks 7281 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0509 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0405 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0370 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 17299 # total number of accesses dl2.hits 8062 # total number of hits dl2.misses 9237 # total number of misses dl2.replacements 28 # total number of replacements dl2.writebacks 11 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5340 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0016 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 i l2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:dtlb none ./benchm arks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com).
warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 il2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:d tlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:09 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:r # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:r # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708208 # total number of hits il1.misses 1113 # total number of misses il1.replacements 89 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0016 # miss rate (i.e., misses/ref) il1.repl_rate 0.0001 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 1113 # total number of accesses il2.hits 11 # total number of hits il2.misses 1102 # total number of misses il2.replacements 20 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9901 # miss rate (i.e., misses/ref) il2.repl_rate 0.0180 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186660 # total number of hits dl1.misses 10018 # total number of misses dl1.replacements 7970 # total number of replacements dl1.writebacks 7281 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0509 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0405 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0370 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 17299 # total number of accesses dl2.hits 8032 # total number of hits dl2.misses 9267 # total number of misses dl2.replacements 826 # total number of replacements dl2.writebacks 780 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5357 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0477 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0451 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base
ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:09 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2
dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0509 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0405 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0370 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 18412 # total number of accesses dl2.hits 8068 # total number of hits dl2.misses 10344 # total number of misses dl2.replacements 426 # total number of replacements dl2.writebacks 207 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5618 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0231 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0112 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:09 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated.
# -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708208 # total number of hits il1.misses 1113 # total number of misses il1.replacements 89 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0016 # miss rate (i.e., misses/ref) il1.repl_rate 0.0001 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186660 # total number of hits dl1.misses 10018 # total number of misses dl1.replacements 7970 # total number of replacements dl1.writebacks 7281 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0509 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0405 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0370 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 18412 # total number of accesses dl2.hits 8068 # total number of hits dl2.misses 10344 # total number of misses dl2.replacements 426 # total number of replacements dl2.writebacks 207 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5618 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0231 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0112 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:09 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:09 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ
dl2.hits 8075 # total number of hits dl2.misses 10337 # total number of misses dl2.replacements 6 # total number of replacements dl2.writebacks 5 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5614 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0003 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0003 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:09 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # # # # # # -config -dumpconfig -h -v -d -i # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger
-seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
il1.replacements 89 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0016 # miss rate (i.e., misses/ref) il1.repl_rate 0.0001 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186660 # total number of hits dl1.misses 10018 # total number of misses dl1.replacements 7970 # total number of replacements dl1.writebacks 7281 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0509 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0405 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0370 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 18412 # total number of accesses dl2.hits 8075 # total number of hits dl2.misses 10337 # total number of misses dl2.replacements 6 # total number of replacements dl2.writebacks 5 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5614 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0003 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0003 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32:2:f -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored...
sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:f -cache:dl1 dl1:1024:32 :2:f -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:09 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:f # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 i l2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb:dtlb none ./benc hmarks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 il2:16384:32:1:l -cache:dl2 dl2:16384:32:1:l -tlb:itlb none -tlb :dtlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:09 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:l # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:l # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
dl1.repl_rate 0.0431 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0387 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 18133 # total number of accesses dl2.hits 8883 # total number of hits dl2.misses 9250 # total number of misses dl2.replacements 107 # total number of replacements dl2.writebacks 48 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5101 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0059 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0026 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 i l2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb:dtlb none ./benc hmarks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 il2:16384:32:1:f -cache:dl2 dl2:16384:32:1:f -tlb:itlb none -tlb :dtlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:09 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # load configuration from a file # dump configuration to a file
# -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)
# # # # # # # #
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:f # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:f # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim_inst_rate 709321.0000 # simulation speed (in insts/sec) il1.accesses 709321 # total number of accesses il1.hits 708145 # total number of hits il1.misses 1176 # total number of misses il1.replacements 239 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0017 # miss rate (i.e., misses/ref) il1.repl_rate 0.0003 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 1176 # total number of accesses il2.hits 75 # total number of hits il2.misses 1101 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9362 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186162 # total number of hits dl1.misses 10516 # total number of misses dl1.replacements 8469 # total number of replacements dl1.writebacks 7617 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0535 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0431 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0387 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 18133 # total number of accesses dl2.hits 8883 # total number of hits dl2.misses 9250 # total number of misses dl2.replacements 107 # total number of replacements dl2.writebacks 48 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5101 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0059 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0026 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 i
l2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb:dtlb none ./benc hmarks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 il2:16384:32:1:r -cache:dl2 dl2:16384:32:1:r -tlb:itlb none -tlb :dtlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:09 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 |dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} dl2:16384:32:1:r # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:16384:32:1:r # l2 instruction cache config, i.e., {<config> none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
dl2.hits 8781 # total number of hits dl2.misses 9256 # total number of misses dl2.replacements 113 # total number of replacements dl2.writebacks 51 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5132 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0063 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0028 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 i l2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:dtlb none ./benchm arks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 il2:8192:32:2:l -cache:dl2 dl2:8192:32:2:l -tlb:itlb none -tlb:d tlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:09 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # # # # # # -config -dumpconfig -h -v -d -i # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger
-seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)
# # # #
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:l # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:l # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
il1.replacements 239 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0017 # miss rate (i.e., misses/ref) il1.repl_rate 0.0003 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 1176 # total number of accesses il2.hits 75 # total number of hits il2.misses 1101 # total number of misses il2.replacements 0 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9362 # miss rate (i.e., misses/ref) il2.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186162 # total number of hits dl1.misses 10516 # total number of misses dl1.replacements 8469 # total number of replacements dl1.writebacks 7617 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0535 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0431 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0387 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 18133 # total number of accesses dl2.hits 8896 # total number of hits dl2.misses 9237 # total number of misses dl2.replacements 28 # total number of replacements dl2.writebacks 11 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5094 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0015 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 i l2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:dtlb none ./benchm arks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass
2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 il2:8192:32:2:f -cache:dl2 dl2:8192:32:2:f -tlb:itlb none -tlb:d tlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:09 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k) # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:f # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:f # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
Examples:
dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5094 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0015 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0006 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 i l2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:dtlb none ./benchm arks/go.alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 il2:8192:32:2:r -cache:dl2 dl2:8192:32:2:r -tlb:itlb none -tlb:d tlb none ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:09 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 |none} -cache:il2 dl2|none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} dl2:8192:32:2:r # l2 data cache config, i.e., {<config>|none} il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 il2:8192:32:2:r # l2 instruction cache config, i.e., {<config>| none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
il1.repl_rate 0.0004 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 1183 # total number of accesses il2.hits 78 # total number of hits il2.misses 1105 # total number of misses il2.replacements 21 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.9341 # miss rate (i.e., misses/ref) il2.repl_rate 0.0178 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186194 # total number of hits dl1.misses 10484 # total number of misses dl1.replacements 8437 # total number of replacements dl1.writebacks 7595 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0533 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0429 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0386 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 18079 # total number of accesses dl2.hits 8749 # total number of hits dl2.misses 9330 # total number of misses dl2.replacements 912 # total number of replacements dl2.writebacks 818 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5161 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0504 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0452 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:09 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:09 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ
dl2.hits 8964 # total number of hits dl2.misses 10345 # total number of misses dl2.replacements 427 # total number of replacements dl2.writebacks 192 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5358 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0221 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0099 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 d l2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 dl2 -cache:dl2 dl2:32768:32:1:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:09 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # # # # # # -config -dumpconfig -h -v -d -i # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger
-seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
il1.replacements 238 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0017 # miss rate (i.e., misses/ref) il1.repl_rate 0.0003 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186223 # total number of hits dl1.misses 10455 # total number of misses dl1.replacements 8408 # total number of replacements dl1.writebacks 7591 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0532 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0428 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0386 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 19233 # total number of accesses dl2.hits 8884 # total number of hits dl2.misses 10349 # total number of misses dl2.replacements 431 # total number of replacements dl2.writebacks 191 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5381 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0224 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0099 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored...
sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:l -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:10 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:f -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:10 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format:
dl2.repl_rate 0.0003 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0003 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32:2:r -cache:il2 d l2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./benchmarks/go.alp ha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 il1:1024:32:2:r -cache:dl1 dl1:1024:32 :2:r -cache:il2 dl2 -cache:dl2 dl2:16384:32:2:r -tlb:itlb none -tlb:dtlb none ./ benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:10 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
-nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:1024:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 il1:1024:32:2:r # l1 inst cache config, i.e., {<config>|dl1|dl2 |none} -cache:il2 dl2 # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 196678 # total number of accesses dl1.hits 186196 # total number of hits dl1.misses 10482 # total number of misses dl1.replacements 8437 # total number of replacements dl1.writebacks 7605 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0533 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0429 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0387 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 19275 # total number of accesses dl2.hits 8925 # total number of hits dl2.misses 10350 # total number of misses dl2.replacements 365 # total number of replacements dl2.writebacks 197 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.5370 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0189 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0102 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:10 2013, options follow:
sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) dl1.accesses 905999 # total number of accesses dl1.hits 894915 # total number of hits dl1.misses 11084 # total number of misses dl1.replacements 6988 # total number of replacements dl1.writebacks 5703 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0122 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0077 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0063 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 16787 # total number of accesses dl2.hits 6404 # total number of hits dl2.misses 10383 # total number of misses dl2.replacements 465 # total number of replacements dl2.writebacks 240 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.6185 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0277 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0143 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com).
warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:10 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) dl1.accesses 905999 # total number of accesses dl1.hits 894915 # total number of hits dl1.misses 11084 # total number of misses dl1.replacements 6988 # total number of replacements dl1.writebacks 5703 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0122 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0077 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0063 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 16787 # total number of accesses dl2.hits 6404 # total number of hits dl2.misses 10383 # total number of misses dl2.replacements 465 # total number of replacements dl2.writebacks 240 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.6185 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0277 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0143 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass
2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:10 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random
Examples:
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 sim_num_refs 196640 sim_elapsed_time 1 sim_inst_rate 709321.0000 dl1.accesses 905999 dl1.hits 894915 dl1.misses 11084 dl1.replacements 6988 dl1.writebacks 5703 dl1.invalidations 0 dl1.miss_rate 0.0122 dl1.repl_rate 0.0077 dl1.wb_rate 0.0063 dl1.inv_rate 0.0000 dl2.accesses 16787 dl2.hits 6404 dl2.misses 10383 dl2.replacements 465 dl2.writebacks 240 dl2.invalidations 0 dl2.miss_rate 0.6185 dl2.repl_rate 0.0277 dl2.wb_rate 0.0143 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 376832 ld_data_base 0x0140000000 ld_data_size 612032 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x0120007bb0 ld_environ_base 0x011ff97000 ld_target_big_endian 0 big endian mem.page_count 111 mem.page_mem 888k mem.ptab_misses 1866 # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs
mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:10 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format:
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) dl1.accesses 905999 # total number of accesses dl1.hits 894915 # total number of hits dl1.misses 11084 # total number of misses dl1.replacements 6988 # total number of replacements dl1.writebacks 5703 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0122 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0077 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0063 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 16787 # total number of accesses dl2.hits 6450 # total number of hits dl2.misses 10337 # total number of misses dl2.replacements 6 # total number of replacements dl2.writebacks 5 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.6158 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0003 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack)
ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:10 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 ne} -cache:il2 |none} -tlb:itlb -tlb:dtlb # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:4096:32:1:l # l1 data cache config, i.e., {<config>|none} dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no none # l2 instruction cache config, i.e., {<config>|dl2 none # instruction TLB config, i.e., {<config>|none} none # data TLB config, i.e., {<config>|none}
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) dl1.accesses 905999 # total number of accesses dl1.hits 894915 # total number of hits dl1.misses 11084 # total number of misses dl1.replacements 6988 # total number of replacements dl1.writebacks 5703 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0122 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0077 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0063 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 16787 # total number of accesses dl2.hits 6450 # total number of hits dl2.misses 10337 # total number of misses dl2.replacements 6 # total number of replacements dl2.writebacks 5 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.6158 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0003 # writeback rate (i.e., wrbks/ref)
dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:l -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:10 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
-cache:dl1 dl1:4096:32:1:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) dl1.accesses 905999 # total number of accesses dl1.hits 894915 # total number of hits dl1.misses 11084 # total number of misses dl1.replacements 6988 # total number of replacements dl1.writebacks 5703 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0122 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0077 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0063 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 16787 # total number of accesses
dl2.hits 6418 # total number of hits dl2.misses 10369 # total number of misses dl2.replacements 365 # total number of replacements dl2.writebacks 214 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.6177 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0217 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0127 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:10 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # # # # # # -config -dumpconfig -h -v -d -i # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger
-seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) dl1.accesses 905999 # total number of accesses dl1.hits 894915 # total number of hits dl1.misses 11084 # total number of misses
dl1.replacements 6988 # total number of replacements dl1.writebacks 5703 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0122 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0077 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0063 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 16787 # total number of accesses dl2.hits 6404 # total number of hits dl2.misses 10383 # total number of misses dl2.replacements 465 # total number of replacements dl2.writebacks 240 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.6185 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0277 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0143 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:10 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing
information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) dl1.accesses 905999 # total number of accesses dl1.hits 894915 # total number of hits dl1.misses 11084 # total number of misses dl1.replacements 6988 # total number of replacements dl1.writebacks 5703 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0122 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0077 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0063 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 16787 # total number of accesses dl2.hits 6404 # total number of hits dl2.misses 10383 # total number of misses dl2.replacements 465 # total number of replacements dl2.writebacks 240 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.6185 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0277 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0143 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb non
e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:10 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) dl1.accesses 905999 # total number of accesses dl1.hits 894915 # total number of hits dl1.misses 11084 # total number of misses dl1.replacements 6988 # total number of replacements dl1.writebacks 5703 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0122 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0077 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0063 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 16787 # total number of accesses dl2.hits 6404 # total number of hits dl2.misses 10383 # total number of misses dl2.replacements 465 # total number of replacements dl2.writebacks 240 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.6185 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0277 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0143 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:10 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) dl1.accesses 905999 # total number of accesses dl1.hits 894915 # total number of hits dl1.misses 11084 # total number of misses dl1.replacements 6988 # total number of replacements dl1.writebacks 5703 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0122 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0077 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0063 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 16787 # total number of accesses dl2.hits 6450 # total number of hits dl2.misses 10337 # total number of misses dl2.replacements 6 # total number of replacements dl2.writebacks 5 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.6158 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0003 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache:il2 dl2 -cache:dl
2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:10 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> - name of the cache being defined <nsets> - number of sets in the cache
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 sim_num_refs 196640 sim_elapsed_time 1 sim_inst_rate 709321.0000 dl1.accesses 905999 dl1.hits 894915 dl1.misses 11084 dl1.replacements 6988 dl1.writebacks 5703 dl1.invalidations 0 dl1.miss_rate 0.0122 dl1.repl_rate 0.0077 dl1.wb_rate 0.0063 dl1.inv_rate 0.0000 dl2.accesses 16787 dl2.hits 6450 dl2.misses 10337 dl2.replacements 6 dl2.writebacks 5 dl2.invalidations 0 dl2.miss_rate 0.6158 dl2.repl_rate 0.0004 dl2.wb_rate 0.0003 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 376832 ld_data_base 0x0140000000 ld_data_size 612032 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x0120007bb0 ld_environ_base 0x011ff97000 ld_target_big_endian 0 # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs
big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:f -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:10 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) dl1.accesses 905999 # total number of accesses dl1.hits 894915 # total number of hits dl1.misses 11084 # total number of misses dl1.replacements 6988 # total number of replacements dl1.writebacks 5703 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0122 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0077 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0063 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 16787 # total number of accesses dl2.hits 6418 # total number of hits dl2.misses 10369 # total number of misses dl2.replacements 365 # total number of replacements dl2.writebacks 214 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.6177 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0217 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0127 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base
ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:10 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 ne} # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:4096:32:1:r # l1 data cache config, i.e., {<config>|none} dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no
none # l2 instruction cache config, i.e., {<config>|dl2 none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) dl1.accesses 905999 # total number of accesses dl1.hits 894915 # total number of hits dl1.misses 11084 # total number of misses dl1.replacements 6988 # total number of replacements dl1.writebacks 5703 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0122 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0077 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0063 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 16787 # total number of accesses dl2.hits 6404 # total number of hits dl2.misses 10383 # total number of misses dl2.replacements 465 # total number of replacements dl2.writebacks 240 # total number of writebacks
dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.6185 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0277 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0143 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:10 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) dl1.accesses 905999 # total number of accesses dl1.hits 894915 # total number of hits dl1.misses 11084 # total number of misses dl1.replacements 6988 # total number of replacements dl1.writebacks 5703 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0122 # miss rate (i.e., misses/ref)
dl1.repl_rate 0.0077 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0063 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 16787 # total number of accesses dl2.hits 6404 # total number of hits dl2.misses 10383 # total number of misses dl2.replacements 465 # total number of replacements dl2.writebacks 240 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.6185 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0277 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0143 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:11 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # load configuration from a file # dump configuration to a file
# -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim_inst_rate 709321.0000 # simulation speed (in insts/sec) dl1.accesses 905999 # total number of accesses dl1.hits 894915 # total number of hits dl1.misses 11084 # total number of misses dl1.replacements 6988 # total number of replacements dl1.writebacks 5703 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0122 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0077 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0063 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 16787 # total number of accesses dl2.hits 6404 # total number of hits dl2.misses 10383 # total number of misses dl2.replacements 465 # total number of replacements dl2.writebacks 240 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.6185 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0277 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0143 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:11 2013, options follow:
sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) dl1.accesses 905999 # total number of accesses dl1.hits 894915 # total number of hits dl1.misses 11084 # total number of misses dl1.replacements 6988 # total number of replacements dl1.writebacks 5703 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0122 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0077 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0063 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 16787 # total number of accesses dl2.hits 6450 # total number of hits dl2.misses 10337 # total number of misses dl2.replacements 6 # total number of replacements dl2.writebacks 5 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.6158 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0003 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com).
warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:11 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) dl1.accesses 905999 # total number of accesses dl1.hits 894915 # total number of hits dl1.misses 11084 # total number of misses dl1.replacements 6988 # total number of replacements dl1.writebacks 5703 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0122 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0077 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0063 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 16787 # total number of accesses dl2.hits 6450 # total number of hits dl2.misses 10337 # total number of misses dl2.replacements 6 # total number of replacements dl2.writebacks 5 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.6158 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0003 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass
2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:4096:32:1:r -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:11 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:4096:32:1:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random
Examples:
mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:11 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format:
ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:11 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 ne} -cache:il2 |none} -tlb:itlb -tlb:dtlb # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:2:l # l1 data cache config, i.e., {<config>|none} dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no none # l2 instruction cache config, i.e., {<config>|dl2 none # instruction TLB config, i.e., {<config>|none} none # data TLB config, i.e., {<config>|none}
dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:11 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
-cache:dl1 dl1:2048:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
dl2.hits 5640 # total number of hits dl2.misses 10372 # total number of misses dl2.replacements 454 # total number of replacements dl2.writebacks 234 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.6478 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0284 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0146 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:11 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # # # # # # -config -dumpconfig -h -v -d -i # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger
-seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) dl1.accesses 905999 # total number of accesses dl1.hits 895521 # total number of hits dl1.misses 10478 # total number of misses
dl1.replacements 6382 # total number of replacements dl1.writebacks 5534 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0116 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0070 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0061 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 16012 # total number of accesses dl2.hits 5675 # total number of hits dl2.misses 10337 # total number of misses dl2.replacements 6 # total number of replacements dl2.writebacks 5 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.6456 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0003 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:11 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing
information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) dl1.accesses 905999 # total number of accesses dl1.hits 895521 # total number of hits dl1.misses 10478 # total number of misses dl1.replacements 6382 # total number of replacements dl1.writebacks 5534 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0116 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0070 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0061 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 16012 # total number of accesses dl2.hits 5675 # total number of hits dl2.misses 10337 # total number of misses dl2.replacements 6 # total number of replacements dl2.writebacks 5 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.6456 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0003 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:l -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb non
e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:11 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:l # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) dl1.accesses 905999 # total number of accesses dl1.hits 895521 # total number of hits dl1.misses 10478 # total number of misses dl1.replacements 6382 # total number of replacements dl1.writebacks 5534 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0116 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0070 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0061 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 16012 # total number of accesses dl2.hits 5652 # total number of hits dl2.misses 10360 # total number of misses dl2.replacements 372 # total number of replacements dl2.writebacks 219 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.6470 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0232 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0137 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:11 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) dl1.accesses 905999 # total number of accesses dl1.hits 895473 # total number of hits dl1.misses 10526 # total number of misses dl1.replacements 6430 # total number of replacements dl1.writebacks 5535 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0116 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0071 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0061 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 16061 # total number of accesses dl2.hits 5689 # total number of hits dl2.misses 10372 # total number of misses dl2.replacements 454 # total number of replacements dl2.writebacks 234 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.6458 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0283 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0146 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache:il2 dl2 -cache:dl
2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:11 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> - name of the cache being defined <nsets> - number of sets in the cache
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 sim_num_refs 196640 sim_elapsed_time 1 sim_inst_rate 709321.0000 dl1.accesses 905999 dl1.hits 895473 dl1.misses 10526 dl1.replacements 6430 dl1.writebacks 5535 dl1.invalidations 0 dl1.miss_rate 0.0116 dl1.repl_rate 0.0071 dl1.wb_rate 0.0061 dl1.inv_rate 0.0000 dl2.accesses 16061 dl2.hits 5689 dl2.misses 10372 dl2.replacements 454 dl2.writebacks 234 dl2.invalidations 0 dl2.miss_rate 0.6458 dl2.repl_rate 0.0283 dl2.wb_rate 0.0146 dl2.inv_rate 0.0000 ld_text_base 0x0120000000 ld_text_size 376832 ld_data_base 0x0140000000 ld_data_size 612032 s' size in bytes ld_stack_base 0x011ff9b000 s in stack) ld_stack_size 16384 ld_prog_entry 0x0120007bb0 ld_environ_base 0x011ff97000 ld_target_big_endian 0 # # # # # # # # # # # # # # # # # # # # # # # # # # # # total number of instructions executed total number of loads and stores executed total simulation time in seconds simulation speed (in insts/sec) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs
big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:11 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) dl1.accesses 905999 # total number of accesses dl1.hits 895473 # total number of hits dl1.misses 10526 # total number of misses dl1.replacements 6430 # total number of replacements dl1.writebacks 5535 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0116 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0071 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0061 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 16061 # total number of accesses dl2.hits 5689 # total number of hits dl2.misses 10372 # total number of misses dl2.replacements 454 # total number of replacements dl2.writebacks 234 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.6458 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0283 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0146 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base
ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:11 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 ne} # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:2:f # l1 data cache config, i.e., {<config>|none} dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no
none # l2 instruction cache config, i.e., {<config>|dl2 none none false false # # # # instruction TLB config, i.e., {<config>|none} data TLB config, i.e., {<config>|none} flush caches on system calls convert 64-bit inst addresses to 32-bit inst equ
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) dl1.accesses 905999 # total number of accesses dl1.hits 895473 # total number of hits dl1.misses 10526 # total number of misses dl1.replacements 6430 # total number of replacements dl1.writebacks 5535 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0116 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0071 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0061 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 16061 # total number of accesses dl2.hits 5724 # total number of hits dl2.misses 10337 # total number of misses dl2.replacements 6 # total number of replacements dl2.writebacks 5 # total number of writebacks
dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.6436 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0003 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:11 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) dl1.accesses 905999 # total number of accesses dl1.hits 895473 # total number of hits dl1.misses 10526 # total number of misses dl1.replacements 6430 # total number of replacements dl1.writebacks 5535 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0116 # miss rate (i.e., misses/ref)
dl1.repl_rate 0.0071 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0061 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 16061 # total number of accesses dl2.hits 5724 # total number of hits dl2.misses 10337 # total number of misses dl2.replacements 6 # total number of replacements dl2.writebacks 5 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.6436 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0004 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0003 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:f -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:11 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # load configuration from a file # dump configuration to a file
# -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:f # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim_inst_rate 709321.0000 # simulation speed (in insts/sec) dl1.accesses 905999 # total number of accesses dl1.hits 895473 # total number of hits dl1.misses 10526 # total number of misses dl1.replacements 6430 # total number of replacements dl1.writebacks 5535 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0116 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0071 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0061 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 16061 # total number of accesses dl2.hits 5696 # total number of hits dl2.misses 10365 # total number of misses dl2.replacements 353 # total number of replacements dl2.writebacks 200 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.6454 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0220 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0125 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:11 2013, options follow:
sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) dl1.accesses 905999 # total number of accesses dl1.hits 895131 # total number of hits dl1.misses 10868 # total number of misses dl1.replacements 6910 # total number of replacements dl1.writebacks 5918 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0120 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0076 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0065 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 16786 # total number of accesses dl2.hits 6410 # total number of hits dl2.misses 10376 # total number of misses dl2.replacements 458 # total number of replacements dl2.writebacks 202 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.6181 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0273 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0120 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com).
warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:11 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:f # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
sim: ** starting functional simulation w/ caches ** warning: partially supported sigprocmask() call... sim: ** simulation statistics ** sim_num_insn 709321 # total number of instructions executed sim_num_refs 196640 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 709321.0000 # simulation speed (in insts/sec) dl1.accesses 905999 # total number of accesses dl1.hits 895131 # total number of hits dl1.misses 10868 # total number of misses dl1.replacements 6910 # total number of replacements dl1.writebacks 5918 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0120 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0076 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0065 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 16786 # total number of accesses dl2.hits 6410 # total number of hits dl2.misses 10376 # total number of misses dl2.replacements 458 # total number of replacements dl2.writebacks 202 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.6181 # miss rate (i.e., misses/ref) dl2.repl_rate 0.0273 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.0120 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache:il2 dl2 -cache:dl 2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass
2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache: il2 dl2 -cache:dl2 dl2:32768:32:1:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:11 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:32768:32:1:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random
Examples:
mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:l -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:12 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt <null> # restore EIO trace execution from <fname> # -redir:sim <null> # redirect simulator output to file (non-interacti ve only) # -redir:prog <null> # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:2048:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:l # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format:
ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:f -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:12 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst -cache:dl1 -cache:dl2 -cache:il1 ne} -cache:il2 |none} -tlb:itlb -tlb:dtlb # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
<null> # redirect simulated program output to file 0 # simulator scheduling priority 0 # maximum number of inst's to execute dl1:2048:32:2:r # l1 data cache config, i.e., {<config>|none} dl2:16384:32:2:f # l2 data cache config, i.e., {<config>|none} dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no none # l2 instruction cache config, i.e., {<config>|dl2 none # instruction TLB config, i.e., {<config>|none} none # data TLB config, i.e., {<config>|none}
dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x0120000000 # program text (code) segment base ld_text_size 376832 # program text (code) size in bytes ld_data_base 0x0140000000 # program initialized data segment base ld_data_size 612032 # program init'ed `.data' and uninit'ed `.bs s' size in bytes ld_stack_base 0x011ff9b000 # program stack segment base (highest addres s in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x0120007bb0 # program entry point (initial PC) ld_environ_base 0x011ff97000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 111 # total number of pages allocated mem.page_mem 888k # total size of memory pages allocated mem.ptab_misses 1866 # total first level page table misses mem.ptab_accesses 2780602 # total page table accesses mem.ptab_miss_rate 0.0007 # first level page table miss rate >>> <<./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache:il2 dl2 -cache:dl 2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb none ./benchmarks/go .alpha -O ./benchmarks/1stmt.i>> Error is: <<< 1 B pass 2 W pass Game over sim-cache: SimpleScalar/Alpha Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). warning: section `.comment' ignored... sim: command line: ./sim-cache -cache:il1 dl1 -cache:dl1 dl1:2048:32:2:r -cache: il2 dl2 -cache:dl2 dl2:16384:32:2:r -cache:il2 none -tlb:itlb none -tlb:dtlb non e ./benchmarks/go.alpha -O ./benchmarks/1stmt.i sim: simulation started @ Tue Mar 5 09:08:12 2013, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # -dumpconfig # -h # -v # -d # -i -seed # -q # -chkpt # -redir:sim ve only) # -redir:prog -nice -max:inst # # # # # # # # # # load configuration from a file dump configuration to a file print help message verbose operation enable debug message start in Dlite debugger random number generator seed (0 for timer seed) initialize and terminate immediately restore EIO trace execution from <fname> redirect simulator output to file (non-interacti
-cache:dl1 dl1:2048:32:2:r # l1 data cache config, i.e., {<config>|none} -cache:dl2 dl2:16384:32:2:r # l2 data cache config, i.e., {<config>|none} -cache:il1 dl1 # l1 inst cache config, i.e., {<config>|dl1|dl2|no ne} -cache:il2 none # l2 instruction cache config, i.e., {<config>|dl2 |none} -tlb:itlb none # instruction TLB config, i.e., {<config>|none} -tlb:dtlb none # data TLB config, i.e., {<config>|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equ ivalents # -pcstat <null> # profile stat(s) against text addr's (mult uses o k) The cache config parameter <config> has the following format: <name>:<nsets>:<bsize>:<assoc>:<repl> <name> <nsets> <bsize> <assoc> <repl> Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r
dl2.hits 6467 # dl2.misses 10360 # dl2.replacements 339 # dl2.writebacks 155 # dl2.invalidations 0 # dl2.miss_rate 0.6157 # dl2.repl_rate 0.0201 # dl2.wb_rate 0.0092 # dl2.inv_rate 0.0000 # ld_text_base 0x0120000000 # ld_text_size 376832 # ld_data_base 0x0140000000 # ld_data_size 612032 # s' size in bytes ld_stack_base 0x011ff9b000 # s in stack) ld_stack_size 16384 # ld_prog_entry 0x0120007bb0 # ld_environ_base 0x011ff97000 # ld_target_big_endian 0 # big endian mem.page_count 111 # mem.page_mem 888k # mem.ptab_misses 1866 # mem.ptab_accesses 2780602 # mem.ptab_miss_rate 0.0007 # >>> [root@localhost simplesim-3.0]# exit exit
total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., repls/ref) writeback rate (i.e., wrbks/ref) invalidation rate (i.e., invs/ref) program text (code) segment base program text (code) size in bytes program initialized data segment base program init'ed `.data' and uninit'ed `.bs program stack segment base (highest addres program initial stack size program entry point (initial PC) program environment base address address target executable endian-ness, non-zero if total total total total first number of pages allocated size of memory pages allocated first level page table misses page table accesses level page table miss rate
Script done on Tue 05 Mar 2013 10:48:29 AM CST

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Script started on Tue 05 Mar 2013 09:08:00 AM CST [root@localhost 32]# cd /simplesim-3.0/ <<.

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format:

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

false false false false

1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

-cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

Cache levels can be unified by pointing a level of the instruction cache

<null> # profile stat(s) against text addr's (mult uses o

false false false false

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

The cache config parameter <config> has the following format:

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

false false false false

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file

false false false false 1 false <null> <null>

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

-cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l

false false false false 1 false <null> <null>

-flush -cache:icompress ivalents # -pcstat k)

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false <null> <null>

<null> # redirect simulated program output to file

false false false false 1 false <null> <null>

-cache:il2 |none} -tlb:itlb -tlb:dtlb -flush -cache:icompress ivalents # -pcstat k)

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

Cache levels can be unified by pointing a level of the instruction cache

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false <null> <null>

<null> # profile stat(s) against text addr's (mult uses o

false false false false 1 false <null> <null>

false false false false 1 false <null> <null>