Fractional-N Synthesizers: Dynamic Scheme of Fractional Spurs Suppression

Author(s): Motorola
Muhammad Douban Abdul Rahman Yu Kok Hoong Anwar Faizd Osman

IP.com number: Original Publication Date: IP.com Electronic Publication: Copyright:

IPCOM000160375D November 16, 2007 November 16, 2007 2007 Motorola, Inc.

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Fractional-N Synthesizers: Dynamic Scheme of Fractional Spurs Suppression

Authors: Muhammad Douban Abdul Rahman, Yu Kok Hoong, Anwar Faizd Osman

Abstract Fractional-N synthesizers have been used for many years to improve the performance of indirect frequency synthesizers. The Fractional-N synthesizer has been acknowledged with the ability to decrease phase noise, provide increased loop speed for a given small step size, and provide reduced reference spurs level. However, one major stigma attached to Fractional-N synthesizer is their poor spurious performance. The most phenomenal spurs found on the Fractional-N synthesizers are fractional spurs. They appear all around the Voltage Controlled Oscillator (VCO) carrier regardless of the frequency to which it is programmed. The spacing of these spurs is usually equal to the channel step size of the Fractional-N synthesizer. The exact mechanism that precipitates these spurs is not entirely understood. The spurs tend to lessen when the VCO drive level into the divider port is lowered. This paper will discuss on some of the fundamentals of the Fractional-N synthesizers and the dynamic scheme of the fractional spurs suppression at which it uses the technique of varying the reference divider, and charge pump currents to attenuate the spurs. This paper explores the fundamentals and the theory of Fractional-N synthesizers, how to hunt for the fractional spurs, and finally discusses on how different reference dividers and charge pump current settings help on the fractional spurs suppression improvement, which is the main agenda of this paper. Keywords- Fractional N spur suppression, synthesizers, VCO, dynamic scheme. I. INTRODUCTION

are compared in a phase and frequency detector (PFD). Any phase difference will be converted into a voltage by the means of a charge pump. A succeeding loop filter extracts the DC component of this voltage, which is then used to control the output signal frequency of a Voltage Controlled Oscillator (VCO). A PLL provides high output frequency accuracy at reasonable short settling time.

Figure 1: Basic Frequency PLL Block Diagram Several different frequency synthesizers architectures have been designed, implemented, and populated in the market today. One of the examples is the integer-N type, where a programmable divider in the feedback path divides the oscillator frequency by an integer value. These loops are characterized by a straightforward circuit implementation, but they suffer from large channel spacing and slower settling time due to loop bandwidth limitations. Fractional-N phase locked loops (PLLs) promise a theoretical performance edge over integer-N, but historically they have struggled to achieve this breakthrough [1]. Now, a new design has resulted in a Fractional-N PLL that lives up to its theoretical performance. Fractional-N loops overcome much of the integer-N types problems, as the output channel spacing can be a small (not only integer) fraction of the reference frequency. In practice, the division ratio is an average, placed between two integers, says N and N+1. As the reference frequency can now be higher, the loop bandwidth increases which reduces the settling time. However, the fractional-N PLLs exhibit spectral output spurs (fractional spurs). Their distance from the target frequency depends on the changing rate between N and N+1. This paper discusses a

Frequency synthesizers are an essential part of any modern transceiver system. They generate clocks and oscillator signals required for up and down conversion. The communication standards today, demand both high frequency accuracy and fast frequency settling time. One of the most frequently used synthesizer types is the phase-locked loop (PLL). Phases of two signals, for instances, from an external reference and a feedback signal from an oscillator,

2007 Motorola, Inc.

Therefore, a brief description on calculating the fractional divider of dynamic scheme of the fractional spurs suppression by randomizing or varying the reference division ratio, and also the charge pump current settings. The idea on this paper is different from other known solutions in terms of fractional spurs suppression at which, typically the Sigma-Delta noise shaping technique is employed for fractional spurs suppression. Fractional-N synthesizer will serve as a building block on understanding the operation of synthesizer ICs. The Fractional-N synthesizers divider calculation for the synthesizer IC is given by equation (3).

N f FVCO = M + 3 + ref D R
At which, M = MAINND N = MAINNUM D = 224 fref = Fr MHz, Reference frequency R = Reference frequency divider ranges from 1 to 7 IV. HOW TO HUNT FOR FRACTIONAL SPURS?

(2)

Figure 2: Fractional-N PLL Block Diagram II. FRACTIONAL-N SYNTHESIZERS BASIC THEORY

It is important and equally crucial to understand and realize that NOT all the frequencies possess fractional spurs [3]. IC designers have streamlined certain guidelines which can be used as guidance on hunting for the fractional spurs frequencies. A frequency is deemed to possess fractional spurs when it falls under any of the two conditions outlined below:

In a PLL, the VCO output frequency, fVCO is determined by the reference frequency, fref and the division ratio N, such that

(1) In conventional frequency synthesizers, the division ratio N is an integer. In order to achieve a fine frequency resolution, small reference frequency and a narrow loop bandwidth are needed. However, narrow loop bandwidth will cause a poor locking time (longer settling time). Fractional-N frequency synthesizer as shown on Figure2 is capable of achieving finer frequency resolution than the reference frequency. Dualmodulus pre-scaling technique has been implemented in order to obtain the fractional divider in the frequency synthesizer. In a fractional divider, the division ratio is periodically altered from N to N+1 [4]. V. DYNAMIC SCHEME OF FRACTIONAL SPURS SUPPRESSION Typically, when the fractional spurs suppression issue is a topic of discussions, engineers tends to bind their thoughts and consideration more III. DIVIDER CALCULATIONS OF FRACTIONAL-N SYNTHESIZERS towards layout considerations and good layout practice [5]. Among the good layout practice includes avoid routing long prescaler runner, and sandwiching all the dirty runners (clock runners, digital runners, and etc) with the ground planes. Holding tight with the good layout practice and principles helps a lot (3) By utilizing the equation given above, Fc= 403.125MHz contains the fractional N-spurs while Fc=403.54MHz free from fractional spurs.

This section will mainly focus on calculating the divider for synthesizer IC, currently implemented on some new radio products. The key concept of divider calculations on this IC is similar to any Fractional-N synthesizer.

2007 Motorola, Inc.

of the fractional spurs suppression with the R value of 7. At 6.25 kHz channel on the spurs suppression. However, it is interesting to notice that even after employing a very good layout practice on the design, there are still a lot more stubborn and nasty spurs appearing on the circuit, which consume most of the engineering effort and time on suppressing these spurs. This paper on the other hand, discusses a dynamic scheme of spurs suppression, namely fractional spurs. This particular scheme utilizes method of varying the reference frequency divider to avoid or bypass the fractional spurs. It is known fact that there are 2 conditions govern the fractional spurs frequencies, at which N is the main contributing factor whereas D is a fixed value. spacing, the fractional spurs suppression is -69dB whereas at the 12.5 kHz channel spacing, the fractional spurs suppression is -70.74dB, which undoubtedly meets the specifications.

(Prescal.Freq.) (Prescal.Freq.) 224 N = INT INT f ref f ref R R

(4) Figure 3: Fractional Spurs Performance Using the R=2

Taking a closer look at (4), most of the parameter is unchangeable except for the R value, which ranges from 1 to 7 (for this synthesizer IC case). Changing the R values significantly transform given carrier frequency from falling into fractional spurs region to a fractional spurs free region. Consider the sample calculation 1, by using the R value of 2, the carrier frequency of 403.125MHz falls under the fractional spurs region. However, by iterative calculations, it is determined that the R value of 7 transformed this carrier frequency from fractional spurs region to a fractional spurs free region. Changing the value of R to 7 dynamically changes the ratio of N over D to 0.97. Following Figure3 and Figure4 illustrates these changes graphically. Based on the Figure3, while using the R value of 2, the fractional spurs suppression at 6.25 kHz channel spacing is -48.56dB and at 12.5 kHz channel spacing, it is -49.46dB. Comparing these values against the specifications, typically, for 6.25 kHz channel spacing, the fractional spurs suppression required is -60dB whereas for the 12.5 kHz channel spacing, fractional spurs suppression needed is -70dB. The performance of the fractional spurs suppression shown on Figure3 is a way off, roughly about 10dB to 20dB off from the specifications. Optimizations and rework would be a very tough effort and almost impossible to attain improvement up to 10dB. Significant improvement on the fractional spurs suppression can be attained by varying Rs value from 2 to 7. Figure4 illustrates the performance From these series of graphical examples, it can be said that the dynamic scheme of fractional spurs suppression technique offered on this paper is a viable and practical fractional spurs suppression methodology. One of the most common as well as important questions arose pertaining to the idea proposed on this paper is on how to keep track of Rs value whether it is suitable or not for a given carrier frequency? The answer for this question is that, the software coding on the radio controller that is capable to cater and keep track of best R value for a given frequency. Figure8 shows the proposed software programming sequences flowchart in order to obtain a suitable R value. Figure 4: Fractional Spurs Performance Using R=7

2007 Motorola, Inc.

Figure 5: Effect of R on Loop Filter Bandwidth The loop bandwidth becomes narrower with the increase of the R value. Narrower loop bandwidth is a phenomenal for the lock time performance. Lock time (settling time) increases as the loop bandwidth gets narrower. The impact of increase on the R value upon the loop bandwidth is illustrated on the simulation results of Figure5. However, the loop bandwidth can be still attained back to its typical value by increasing the charge pump currents [2]. The effect of increasing charge pump current settings while using the higher R value is shown on the simulation results of Figure7. Realizing that by varying the Rs value, it has the direct effect towards the loop bandwidth hence may jeopardy the lock time performance. Therefore, the proposed software flowchart needs to ensure both of these parameters are well versed. One method the designer should employ to handle this issue is by simulating the loop bandwidth for all the R values, such that the design loop bandwidth is maintained throughout the frequency band. In order to maintain the loop bandwidth, it may require the designer to subdivide their frequency band into a number of segments with a different charge pump current settings. Figure 7: Loop Bandwidth, R=6 with 320uA Charge Pump Current By practicing this, for instance, if the R value of 3 is chosen on a given frequency, the required value of the charge pump current settings is readily known. Flowchart below demonstrates the changes on the proposed software programming sequences, emphasizing the charge pump current settings. Analyzing the simulation results, it can be well said that the dynamic scheme introduced on this paper is practical and viable solution for the fractional spurs suppression. In order to compensate the narrower loop bandwidth due to the increase in R values, one can readily adjust (increase) the charge pump current settings. By doing this, the typical loop bandwidth is attainable, and this has been proved by the simulation. Figure 6: Loop Bandwidth, R=2 with 160uA Charge Pump Current

2007 Motorola, Inc.

Figure 8: Proposed Software Programming Sequences Flowchart with Charge Pump Current Settings VI. CONCLUSIONS

In conclusion, the dynamic scheme for fractional spurs suppression discussed on this paper takes a fresh approach for a fractional spurs solution, with the focus firmly on performance and adaptability. By paying particular attention to the way in which this approached can be implemented and its impact, this flexibility solutions (software coding and charge pump current settings) can be offered as a programmable optimization solution, rather than a fixed design. The approach outlined on this paper is a new, novel and viable solutions, which has not been used yet to cater for the fractional spurs suppression. REFERENCES [1] KING N.J.R, Phase-Locked Loop Variable Frequency Generator. US Patent 4204174, 20 May 1980. [2] Dean Banerjee, PLL Performance, Simulation and Design, National Semiconductor. [3] Jedi UHF Fractional-N Synthesizer Closing Report by Christine Ng, October 10, 1993. [4] Brendan Daly, A New Approach to Fractional-N PLL Design Yields Performance Breakthrough, Analog Devices, April 2003. [5] RF Circuit Design by Chris Bowick.

2007 Motorola, Inc.