PROJECT Assignment ECE 534 Power Electronics

Design of Three-stage Full-bridge Converter Presented by Abhijit Kuvar (001081139) Unity ID: akuvar

Requirements: 1. Output Voltage = 120 V 2. Pmax = 1440 W Schematic Diagram of Three-Stage Full Bridge Rectifier:

Following specifications must be satisfied:

6. Controller Design and Implementation:

a. The following control scheme i.e. Voltage Controlled Control of the converter is used for the closed loop control of the Three-Stage Full-Bridge Converter.

b. We take into account for the control of the single module of the Full-Bridge Converter circuit and design the control scheme for that.

PROPOSED ALGORITHM FOR DESIGN OF CONTROLLER: 1. Determine the Gvd(s) i.e. Control-to-Output TF of the single module for different values of input voltage (Vg) and load current (I load). 2. Find out the uncompensated loop Tu(s), by selecting the Sensor Gain H(s) and magnitude of PWM waveform VM accordingly. 3. =
0 1+ 1
2 + 0 2 0

4. Plot the magnitude and phase of Bode diagrams for combination of values of Vg and ILOAD . 5. Determine for what values of Vg and ILOAD , the least phase margin is obtained. 6. For value of Gvd(s) at those values of Vg and ILOAD , find the controller design for the given circuit using SISOTOOL in MATLAB. Specify the required bandwidth and phase margin while designing the controller. 7. Implement the controller and find out the closed loop gain of the control system, T(s) using following expression. = 0 1 1+
0

2
2 0

8. Check for the stability of the control scheme by sketching bode diagrams of T(s) for every value of Vg and ILOAD.

Following values and equations are considered for implementation of the controller. 1. Gd0 = nVg 2. 0 = 3. Q = R
1

4. H (s) = (1/24) (i.e. Vref = 5V) 5. VM = 20 V 6. n = 6 ; Vg = (30 50V) ; C = 0.521 F ; L = 1.5 mH 7. R = (Vg) / (ILOAD/3) (since we are implementing for single module only)

Following MATLAB Code is written to get the bode plots for the uncompensated system.
s = tf('s'); V = 120; % Output voltage Vg = 50; % Insert Input Voltage (or Vg = 30) n = 6; L = 1.5e-3; % Inductor C = 0.521e-6; % Capacitor Vm = 20; H = (1/24); Gc = 1; % Uncompensated System I_load = (1/3); % I_load = (1/3) for light load % I_load = (12/3) for heavy load R = V/I_load; W = 1/(sqrt(L*C)); Q = R*sqrt(C/L);
num = n*Vg*H*Gc/Vm; den = 1 + (s*(1/(Q*W))) + (s^2*(1/W^2)); T = num/den ; margin(T);

We get bode diagrams for uncompensated system as follows:

For Vg = 30 V ; ILOAD = 1 A

For Vg = 50 V; ILOAD = 1A

For Vg = 30 V ; ILOAD = 12 A

For Vg = 50 V; ILOAD = 12 A

Conclusion: As seen from above bode plots, we get the least phase margin (2.51 deg) at input voltage of 50 V and light load current of 1 A.

SISOTOOL Design
1. Implement Gvd(s) for input voltage of 50V and ILOAD = 1 A as Plant in SISOTOOL compensator design. 2. Set bandwidth of system to be equal to 20khz (< fSW = 60 kHz) i.e. ` BW(=fc) = 20 kHz ~ 125000 rad/s 3. Input the phase margin parameter as PM = 60 deg 4. Using automated PID tuning, the controller obtained is the PID controller having following TF: 1 + 10.9 5 + (2.838 9) 2 = 51424 + (2.2 6) 2 Bode diagram of controller:

5. We now find the closed loop transfer function T(s) after implementing controller

Following MATLAB Code is written to get the bode plots for the Compensated system.
s = tf('s'); V = 120; % Output voltage Vg = 50; % Insert Input Voltage (or Vg = 30) n = 6; L = 1.5e-3; % Inductor C = 0.521e-6; % Capacitor Vm = 20; H = (1/24); Gc = tf([1.459e-4 5.605 51424],[2.2e-6 1 0]) % Compensator I_load = (1/3); % I_load = (1/3) for light load % I_load = (12/3) for heavy load R = V/I_load; W = 1/(sqrt(L*C)); Q = R*sqrt(C/L); num = n*Vg*H*Gc/Vm; den = 1 + (s*(1/(Q*W))) + (s^2*(1/W^2)); T = num/den ; margin(T);

We get bode diagrams for Compensated system as follows:

For Vg = 30 V ; ILOAD = 1 A

For Vg = 50 V ; ILOAD = 1 A

For Vg = 30 V ; ILOAD = 12 A

For Vg = 50 V ; ILOAD = 12 A

Conclusion: PHASE MARGIN: We get the improved phase margin for every given case of input voltage and load current, thus ensuring the stability of the system for all the point of operation. Bandwidth: The desired bandwidth i.e. 20kHz is obtained for input voltage of 50V and light load of 1A. This bandwidth tends to decrease for input voltage 30 V up to 9.88 kHz which seems an acceptable bandwidth given the switching frequency of 60kHz

7. Simulation Using PLECS/Simulink

Three-stage full-bridge converter is simulated using combination of PLECS and Simulink, by including all the CALCULATED values of the parameters Following diagram shows the schematic of circuit:

Simulink Part:

 Working: 1. Sensor gain H(s) is selected as (1/24) thus lowering output voltage to 5V, which is the standard voltage to apply to any Op-Amp logic circuit. 2. We apply a step change in Vref from 5V to 5.1V after 6ms to analyze its effect on the output voltage. 3. The pulses generated from PWM are the gating pulses which are divided using logical circuitry and are given to gating of Q1,Q4 and Q2,Q3 Waveforms: Waveforms shown below are for Vg = 50 V and ILOAD = 12 A 1. Output Voltage Waveform

As seen from waveform, the rise time of voltage with no reference step is approximately 0.1 ms which is substantially less.

With change in reference voltage from 5 V to 5.1 V, we get no overshoot and undershoot, also the rise time is only approximately 0.2ms.

Voltage ripple around 120 V

As seen from the waveform, the maximum voltage value observed is around 121 V, whereas minimum voltage value is 119 V, thus satisfying the voltage ripple requirement of 2% i.e. (+ 2.4 V)

2. Output Current Waveform

As seen from the waveform, the output current value fluctuates around 12A, with maximum value being 12.6 A and minimum being 11.4 A, thus ensuring that ripple current condition of + 10% (+ 1.2 A ) is satisfied. 3. Diode Current Waveform:

4. Switch Current Waveform (from FET1 and FET4)

Conclusion: The project has satisfied all the required specifications of design for the ThreeStage Full Bridge Converter. The simulation guarantees the performance of the converter in regards to given constraints and closed-loop specifications. Simulation Files have been E-mailed.