PROJECT REPORT ON

DESIGN OF MATRIX CONVERTER USING CARRIER BASED MODULATION TECHNIQUE

PRESENTED BY ABHIJIT KUVAR 001081139

Configuration of Matrix Converter (Fsw = 5kHz) [1]

Objectives of the Project: 1) Determine the switching states of switches SaA, SaB,, ScC in order to implement the operation of Matrix Converter. 2) Implement the Output Voltage Synthesis in order to achieve sinusoidal output voltage. 3) Implement Input Current Synthesis in order to achieve sinusoidal input source currents. 4) Check for overmodulation case in which Matrix Converter achieves output voltage to input voltage ratio = 1.

PART 1: Output Voltage Synthesis

PART 2: Overmodulation

PART 3: Input Current Synthesis

Approach: Part 1: Output Voltage Synthesis 1. Design of Matrix Converter in PLECS Values of source resistance and source reactance (Rs and Ls) are not given. They are calculated with the assumption that, XLs = 0.5-2%. We do not know VA rating of the converter so the following approach is employed to calculate these, 1 ( = 60 ) 2 = = = 10 =

= 0.05 = 0.1 We get the values as Rs = 10.61 m and Ls = 50 H

2. Calculation of Maximum, Minimum and Mid supply voltages. As the paper describes, the calculation of MAX, MIN and MID voltages in the given Ts = (1/Fsw) = 200 s is done using a MATLAB function which accepts inputs as three phase line-neutral supply voltages. The output voltage references are generated using function in PLECS and then they are compared through MATLAB function to give outputs as max and min voltages.

The Logic circuit above uses Sample-and-Hold technique in order to retain the input supply voltages for given switching period Ts = 200 s. MATLAB functions used for Calculation of MAX, MID and MIN voltages and for calculation of max and min of reference voltages are as given in Appendix as Code-1 and Code-2 respectively.

3. Timing Circuit Implementation using PLECS In part 1, the time period Ts is divided equally into two periods. The generation of timing signals is done as follows:

Triangular wave with frequency 5kHz and maximum amplitude of 0.0002 is generated and used for comparison in subsequent functions. T1 and T2 are the equally divided periods which are also used in subsequent functions for calculations. 4. Carrier and Pole Voltages Generation The discontinuous carrier generation follows continually changing slope technique which basically is dependent on presence of max and min of reference voltages. For carrier generation following logic is used. During period T1 (from 0 to t1), H1 = MAX and L1 = MIN Slope of carrier = (L1 H1)/ T1 Equation of carrier = (slope) t + H1 During period T2 (from t1 to Ts), H2 = MAX and L2 = MID (if MAX MID > MID MIN) or H2 = MID and L2 = MIN (if MID MIN > MAX MID) Slope of carrier = (H2 L2)/(Ts t1) Equation of carrier = (slope) (t Ts1) + L2

The pole voltage references Van1, Vbn1, Vcn1, Van2, Vbn2, Vcn2 are generated as given in [1]. Code-3 in Appendix is written for Generation of Carrier and Pole Voltages 5. Generation of Switching States By comparing pole voltages with carrier, appropriate switching states [1] for phases a,b,c are generated using Code-4 in Appendix. 6. Generation of Switching Sequence By comparing switching states of each phase with the status (MAX,MID,MIN) of the input phase supply the switching is done accordingly i.e. if phase x is at MAX and phase y switching state is MAX as well, then switching state of switch connecting x and y is 1. This is generated using Code-5 in Appendix. 7. Output Voltage and Input Current waveforms The waveforms are passed through 2nd order filter with appropriate cutoff frequency.

COMPLETE CIRCUIT IMPLEMENTATION FOR PART 1

POLE VOLTAGES and TIMING CIRCUIT

Part 2: Overmodulation (q = 1) Steps 1 and 2 for part 1 remain the same for this case. There would be change in timing circuit implementations. 1. Timing Circuit Implementation for Overmodulation: i = phase angle of voltage of phase A Given the variation in i, the new angle i is calculated using following waveform.

To calculate i, Code-6 is implemented as in Appendix. Now times T1 and T2 are calculated using following formula, 1 = 2 3 sin + 2 cos 3

2 = 1 To calculate, T1 and T2 Code-7 is implemented in Appendix. Simulink Implementation for Timing Circuit

2. Pole Voltages Generation: In the overmodulation technique, to produce q = 1, we need to change the reference voltages by factor of . This can be calculated as given in [1]. If >1, then limit =1. Saturator with maximum output of 1 is implemented for that in Simulink Implementation. The code for calculation of is as given in Code-8 of the Appendix. The output voltage references are multiplied with factor of and then added to the respective offset voltages in order to get pole voltage references. The Code-9 in Appendix gives the pole voltages required for comparison with carrier. Carrier generation occurs in the same way as in step 4 in Part 1, rest of the steps in the part 1 remaining the same to generate the switching sequences accordingly. COMPLETE CIRCUIT IMPLEMENTATION FOR PART 2

POLE VOLTAGES and TIMING CIRCUIT

Part 3: Input Current Synthesis For the input current synthesis, Steps 1-2 in Part 1 Remain the same. Timing Circuit is as same as in step 1 in Part 2. We have to use i concept here to generate the timings. Steps 4-7 remain the same as in Part 1.

COMPLETE CIRCUIT IMPLEMENTATION FOR PART 3

POLE VOLTAGES and TIMING CIRCUIT

References: [1] Y.-D. Yoon and S.-K. Sul, Carrier-based modulation technique for matrix converter, IEEE Trans. Power Electron., vol. 21, no. 6, pp. 1691 1703, Nov. 2006.

PART 1: Output Voltage Synthesis

Line-Line Supply Voltages

Isa (Input Phase Current) Unfiltered

Isa (Input Phase Current) Filtered

Output Voltages (Line-Line) Unfiltered

Output Voltages (Line-Line) Filtered

Output Current (IA)

Spectrum of Output Voltages Waveform

Spectrum

Spectrum of Input Current Waveform

Spectrum

Spectrum of Output Current (IA) Waveform

Spectrum

PART 2 : Overmodulation
Isa (Input Phase Current) Unfiltered

Isa (Input Phase Current) Filtered

Output Voltages (Line-Line) Unfiltered

Output Voltages (Line-Line) Filtered

Output Current (IA)

THD of Output Voltage (L-L), Input Current and Output Current (Respectively)

Tabulated THD from Waveform Variable Output Voltage Input Current Output Current THD (avg %) 55 150 2

SWITCH STRESS WAVEFORM

Switch Stress: 1) From the waveform, it can be seen that the switch stress = (Vavg.Irms) ranges from 2.6kW in positive direction to 2.9kW in negative direction. 2) This indicates that there almost occurs a power flow reversal of approximately 6kW across the switch within the time period of 0.14 sec, thus indicating that there is large amount of switch stress present on the switches.

PART 3: Input Current Synthesis

Isa (Input Phase Current) Unfiltered

Isa (Input Phase Current) Filtered

Output Voltages (Line-Line) Unfiltered

Output Voltages (Line-Line) Filtered

Output Current (IA)

THD of Output Voltage (L-L), Input Current and Output Current (Respectively)

Tabulated THD from Waveform Variable Output Voltage Input Current Output Current THD (avg %) 0.4 0.5 1.5

SWITCH STRESS WAVEFORM

Switch Stress: 1) From the waveform, it can be seen that the switch stress = (Vavg.Irms) ranges from 2.4kW in positive direction to 2.6kW in negative direction. 2) This indicates that there almost occurs a power flow reversal of approximately 5kW across the switch within the time period of 0.14 sec, thus indicating that there is large amount of switch stress present on the switches.

APPENDIX
Code-1: Calculation of MAX, MID and MIN Voltages
% Function To Generate MAX MID MIN of Input Supply Voltage function [mx,mn,md,A,B,C] = fcn(Ean,Ebn,Ecn,t,Ts) mx = 0; mn = 0; md = 0; A = 0; B = 0; C = 0; if ((t/Ts)==0) if (Ean>Ebn && Ean>Ecn) mx = Ean; A = 3; if (Ebn>Ecn) mn = Ecn; C = 1; md = Ebn; B = 2; else mn = Ebn; B = 1; md = Ecn; C = 2; end end if (Ebn>Ean && Ebn>Ecn) mx = Ebn; B = 3; if (Ean>Ecn) mn = Ecn; C = 1; md = Ean; A = 2; else mn = Ean; A = 1; md = Ecn; C = 2; end end if (Ecn>Ebn && Ecn>Ean) mx = Ecn; C = 3; if (Ean>Ebn) mn = Ebn; B = 1; md = Ean; A = 2; else mn = Ean; A = 1; md = Ebn;

B = 2; end end end end

Code -2: Calculation of max and min of reference voltages

function [max,min] = fcn(Vas,Vbs,Vcs,t,Ts) max = 0; min = 0; if ((t/Ts)==0) if (Vas>Vbs && Vas>Vcs) max = Vas; if (Vbs>Vcs) min = Vcs; else min = Vbs; end end if (Vbs>Vas && Vbs>Vcs) max = Vbs; if (Vas>Vcs) min = Vcs; else min = Vas; end end if (Vcs>Vbs && Vcs>Vas) max = Vcs; if (Vas>Vbs) min = Vbs; else min = Vas; end end end end

Code-3: Generation of Carrier and Pole Voltage References

function [y,Van1,Vbn1,Vcn1,Van2,Vbn2,Vcn2,flag] = fcn(mx,mn,md,max,min,Vas,Vbs,Vcs,t1,t2,Ts,t_comp) h1 = 0; l1 = 0; h2 = 0; l2 = 0; slope = 0; y = 0; Vsn1 = 0; Vsn2 = 0; Van1 = 0; Vbn1 = 0; Vcn1 = 0; flag = 0;

Van2 = 0; Vbn2 = 0; Vcn2 = 0; if (t_comp>=0) && (t_comp<t1) h1 = mx; l1 = mn; slope = (l1-h1)/t1; y = (slope*t_comp) + h1; Vsn1 = ((h1+l1)-(max+min))/2; Van1 = Vas + Vsn1; Vbn1 = Vbs + Vsn1; Vcn1 = Vcs + Vsn1;

end if (t_comp>=t1) && (t_comp<Ts) if (mx-md)>(md-mn) h2 = mx; l2 = md; flag = 1; end if (md-mn)>(mx-md) h2 = md; l2 = mn; flag = 0; end slope = (h2-l2)/(Ts-t1); y = (slope*(t_comp-t1)) + l2; Vsn2 = ((h2+l2)-(max+min))/2; Van2 = Vas + Vsn2; Vbn2 = Vbs + Vsn2; Vcn2 = Vcs + Vsn2; end

Code-4: Generation of Switching States

% Generation of Switching States function [Sa,Sb,Sc] = fcn(y,Van1,Vbn1,Vcn1,Van2,Vbn2,Vcn2,t1,t2,t_comp,flag) %#codegen Sa = 0; Sb = 0; Sc = 0; if (t_comp>=0) && (t_comp<t1) if (y>=Van1) Sa = 1; end if y<Van1 Sa = 3; end if (y>=Vbn1) Sb = 1; end if y<Vbn1 Sb = 3; end

if (y>=Vcn1) Sc = 1; end if y<Vcn1 Sc = 3; end end if (t_comp>=t1) && (t_comp<(t1+t2)) if flag==1 if (y>=Van2) Sa = 2; end if (y<Van2) Sa = 3; end if (y>=Vbn2) Sb = 2; end if (y<Vbn2) Sb = 3; end if (y>=Vcn2) Sc = 2; end if (y<Vcn2) Sc = 3; end end if flag==0 if (y>=Van2) Sa = 1; end if (y<Van2) Sa = 2; end if (y>=Vbn2) Sb = 1; end if (y<Vbn2) Sb = 2; end if (y>=Vcn2) Sc = 1; end if (y<Vcn2) Sc = 2; end end

end end

Code-5: Generation of Switching Sequence

% Generation of Switching Sequence function [SwA,SwB,SwC] = fcn(Sa,Sb,Sc,A,B,C) %#codegen SwA = [0 0 0]; SwB = [0 0 0]; SwC = [0 0 0]; if (Sa==A) SwA = [1 0 0]; end if (Sa==B) SwA = [0 1 0]; end if (Sa==C) SwA = [0 0 1]; end if (Sb==A) SwB = [1 0 0]; end if (Sb==B) SwB = [0 1 0]; end if (Sb==C) SwB = [0 0 1]; end if (Sc==A) SwC = [1 0 0]; end if (Sc==B) SwC = [0 1 0]; end if (Sc==C) SwC = [0 0 1]; end end

Code-6: Calculation i
function beta_i = fcn(beta) %#codegen beta_i = 0; m = 1; if (beta>=0)&&(beta<(pi/6)) beta_i = m*beta; end

if (beta>=(pi/6))&&(beta<(pi/3)) beta_i = -m*(beta-(pi/6))+(pi/6); end if (beta>=(pi/3))&&(beta<(pi/2)) beta_i = m*(beta-(pi/3)); end if (beta>=(pi/2))&&(beta<(2*pi/3)) beta_i = -m*(beta-(pi/2))+(pi/6); end if (beta>=(2*pi/3))&&(beta<(5*pi/6)) beta_i = m*(beta-(2*pi/3)); end if (beta>=(5*pi/6))&&(beta<pi) beta_i = -m*(beta-(5*pi/6))+(pi/6); end if (beta>=pi)&&(beta<(7*pi/6)) beta_i = m*(beta-pi); end if (beta>=(7*pi/6))&&(beta<(4*pi/3)) beta_i = -m*(beta-(7*pi/6))+(pi/6); end if (beta>=(4*pi/3))&&(beta<(3*pi/2)) beta_i = m*(beta-(4*pi/3)); end if (beta>=(3*pi/2))&&(beta<(5*pi/3)) beta_i = -m*(beta-(3*pi/2))+(pi/6); end if (beta>=(5*pi/3))&&(beta<(11*pi/6)) beta_i = m*(beta-(5*pi/3)); end if (beta>=(11*pi/6))&&(beta<2*pi) beta_i = -m*(beta-(11*pi/6))+(pi/6); % end end

Code-7: Generation of Timing Signals:

function T1 = fcn(beta_i,Ts) %#codegen T1 = ((2/sqrt(3))*sin(beta_i+(2*pi/3))*cos(beta_i))*Ts; end

Code-8: Generation of
function Gam = fcn(h1,l1,h2,l2,max,min,Ts,t1) %#codegen Gam = ((h1-l1)*(h2-l2)*Ts)/(t1*(h2-l2)+(Ts-t1)*(h1-l1))*(1/(max-min)); end

Code-9: Generation of pole voltage references for Part 2

function [Van1,Vbn1,Vcn1,Van2,Vbn2,Vcn2] = fcn(Gam,Vas,Vbs,Vcs,Vsn1,Vsn2,t1,t_comp,Ts) %#codegen Van1 = 0; Vbn1 = 0; Vcn1 = 0; Van2 = 0; Vbn2 = 0; Vcn2 = 0; if (t_comp>=0)&&(t_comp<t1) Van1 = Gam*Vas + Vsn1; Vbn1 = Gam*Vbs + Vsn1; Vcn1 = Gam*Vcs + Vsn1; end if (t_comp>=t1)&&(t_comp<Ts) Van2 = Gam*Vas + Vsn2; Vbn2 = Gam*Vbs + Vsn2; Vcn2 = Gam*Vcs + Vsn2; end end