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UXGA Interface
Dual Full-Speed
10/100/1000Base-T
Ethernet Interfaces
Power & Backplane I/O Connector C PCI Express™ Connector B PCI Express™ Connector A
Chassis Plans’ NLT system host board 400 memory channels. Data bottlenecks are reduced by the three PCI PCI EXPRESSTM CONFIGURATION AND BUS
turns the promise of PCI ExpressTM into ExpressTM interfaces that provide high bandwidth (4GB/s) connections SPEEDS:
a reality. The high-speed SHB-to-back- between the ports on the Memory Controller Hub (MCH) and external
I/O devices or option cards. PCI Express - Edge Connectors A & B - Two x8 links, one x4 link
plane PCI Express links employed on - Five reference clocks
the NLT strip away parallel bus band- PCI EXPRESS INTERFACES:
TM
PCI Express - (on-board only) - One x4 link
width limitations while unleashing PCI-X (on-board only) - 64-bit/66MHz
High-speed serial links that make up PCI Express interfaces typically PCI (on-board only) - 32-bit/33MHz
the processing power of the next have data rates twice that of PCI interfaces. A basic PCI Express link Hub Link 1.5 - 266MB/s
generation Intel® XeonTM processors. consists of at least one pair of differentially driven transmit and receive System or FSB - 800MHz
The NLT features the Intel® E7520 signal lines. PCI Express link bandwidth is increased linearly by adding
chipset, an 800MHz system bus, dual signal pairs to form multiple lanes or wider lane widths. The most SERIAL ATA/150 PORTS (DUAL):
common PCI Express links used today are configured to have lane
DDR2-400 memory interfaces, dual widths of x1, x4, x8 or x16. Chassis Plans’ NLT system host board The primary and secondary Serial ATA (SATA) ports on the NLT boards
Gigibit Ethernet ports and advanced provides two x8 PCI Express links, one x4 PCI Express link and five PCI comply with the SATA 1.0 specification and support two independent
video. PCI Express, PCI and PCI-X Express reference clocks on edge connectors A and B. These PCI SATA storage devices such as hard disks and CD-RW devices. SATA
option card support makes the NLT an Express links are used on SHB ExpressTM backplanes to support PCI technology provides lower-pin counts, reduced signaling voltages,
Express option cards and bridge chips that provide PCI/PCI-X option simplified cabling, CRC error detection and hot-plug device support.
ideal choice for current as well as SATA produces higher performance interfacing by providing data transfer
future industrial computing applica- card support. During system initialization the NLT automatically nego-
tiates with the PCI Express cards connected to the PCI Express links in rates up to 150MB per second on each port.
tions. order to set up communication between the devices. The net result is
that the NLT system host board supports communication to x1, x4,
DUAL ETHERNET INTERFACES -
PROCESSORS: x8, x16 PCI Express boards as well as PCI/PCI-X cards via PCI 10/100/1000BASE-T:
Dual Intel® XeonTM Processors at 2.8GHz to 3.6GHz* Express-to-PCI/PCI-X bridge chip technology on the backplane. The NLT uses an internal PCI-X bus to connect the I/O Controller hub
Processor Package: FC-mPGA4 (604-pin) to the Ethernet controller chip. This design feature provides high-speed
DDR2-400 MEMORY: dual Gigabit Ethernet on LAN ports 1 and 2. The SHB also supports
*Higher speeds as available
The DDR2-400 interface is a dual channel interface originating at the 10Mb/s or 100Mb/s Ethernet networks. RJ-45 connectors on the
The Intel® Xeon processors used on the NLT support an 800MHz system Memory Controller hub with each channel terminating at two DIMM I/O bracket provide the mechanical interface to the Ethernet networks.
bus as well as the Intel® NetBurst™ micro-architecture. These new module sockets, for a total of four memory sockets. The NLT uses ECC
processors support both 64-bit and 32-bit applications. Intel® Extended registered PC2-3200 DIMMs and supports a maximum memory
Memory 64 Technology (Intel® EM64T) is the processor feature that capacity of 8GB and a minimum memory interface bandwidth of
allows 64-bit application support. Other processor features: 3.2GB/s per channel. The total effective memory interface bandwidth
• Hyper-Threading Technology increases to 6.4GB/s when at least one PC2-3200 DIMM is used in
• Streaming SIMD Extensions 2 & 3 (SSE2 & SSE3) each of the channels.
• Hyper-Pipelined technology
STANDARDS:
• 1M Advanced Transfer Cache (L2) (2M L2 Cache - Future)
• 16K Level 1 data cache (L1) • PCI ExpressTM Base Specification 1.0a
• SHB ExpressTM System Host Board PCI Express Specification -
CHIPSET: PCI Industrial Computer Manufacturers Group (PICMG®) 1.3
Increased system performance is made possible by the Intel E7520
®
TM
chipset's ability to support an 800MHz system bus. The chipset The Original Industrial Computer Source
configuration on Chassis Plans NLT board supports two registered DDR2-
CHASSIS PLANS • 8295 Aero Place, San Diego, CA 92123 • Phone: (858) 571-4330 • Fax: (858) 571-6146
E-mail: saleseng@chassisplans.com • Web: www.chassisplans.com
PRODUCT DATA SHEET
DDR-B MCH
Xeon Xeon
™ ™
Channel B
DDR2-400 Memory Controller Hub
3200MB Processor 1 Processor 2
Bandwidth*
Intel
® Socket 604 Socket 604
DIMM Module Sockets E7520
1A & 2A DDR-A
Channel A Hub Link 1.5
DDR2-400 800MHz Front Side Bus
PCI Express x8
*Single Channel operations.
SMBus Memory bandwidth typically doubles
PCI Express x8 Edge Connectors
in dual channel operations.
A and B
Controlled Impedance PCI Express x4
Connector
Board Intel
®
LAN 1
82802 PCI-X Ethernet
SMBus PCI-X 64-bit/66MHz Controller 10/100/1000
SMBus Base-T
Intel
To Edge 82546EB
Connector A IDE E6300ESB Serial ATA LAN 2
Primary Primary
I/O
IDE Controller Serial ATA Optional
Secondary Hub Secondary Backplane Routing
I/O USB 0 USB 2
NLT Edge Connector C
USB 1 USB 3 Headers USB Ports
Bracket Intel
FW80001ESB
EN61000-4-11:1994
CHASSIS PLANS • 8295 Aero Place, San Diego, CA 92123 • Phone: (858) 571-4330 • Fax: (858) 571-6146
E-mail: saleseng@chassisplans.com • Web: www.chassisplans.com