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LABORATORY 1 EE 476
Lab 1: Introduced to the Cadence suit of IC design tools
GROUP 8 09ECE Danang University of Technology, Faculty of Electronics and Telecommunications, COE center
Danang University of Technology, Faculty of Electronics and Telecommunications EE 476 Lab 1: Introduced to the Cadence suit of IC design tools TA. Vo Tuan Minh
MEMBER OF GROUP 8: L Mai Trung L Huy L Quang Tun
Table of Contents
LABORATORY 1 EE 476
GROUP 8 09ECE
From Figure 1, a CMOS circuit is composed of two MOSFETs. The top FET (MP) is a PMOS type device while the bottom FET (MN) is an NMOS type. The body effect is not present in either device since the body of each device is directly connected to the devices source. Both gates are connected to the input line. The output line connects to the drains of both FETs. Take a look at the VTC in Figure 2. The curve represents the output voltage taken from node 3. We can easily see that the CMOS circuit functions as an inverter by noting that when VIN is five volts, VOUT is zero, and vice versa. Thus when inputting a high we get a low and when input a low we get a high as is expected for any inverter.
The active PMOS load device is a PMOS transistor, wherein the source of the PMOS transistor is connected to the power supply voltage and the drain of the PMOS transistor is connected to the amplifying unit wherein the second load device further comprises: a compensation unit which is connected to the negative feedback buffering unit and compensates for both a gain and a frequency characteristics in the high frequency range. The gate of the NMOS transistor of the negative feedback load buffering unit is connected to the drain of the PMOS transistor, the source of the NMOS transistor of the negative feedback load buffering unit is connected to the gate of the PMOS transistor, and the drain of the NMOS transistor is connected to the power supply voltage.
LABORATORY 1 EE 476 GROUP 8 09ECE
LABORATORY 1 EE 476
GROUP 8 09ECE
LABORATORY 1 EE 476
GROUP 8 09ECE
LABORATORY 1 EE 476
GROUP 8 09ECE
LABORATORY 1 EE 476
GROUP 8 09ECE
Let zoom in for more detail, at this time: 1 Redline 2 Yellow line Check the graph from low to high (raising era):
3 Blue line
At we can see, the yellow line (as known as PMOS with W/L = 6um/100nm and NMOS with W/L = 2um /100 nm) raises first then the red line (PMOS with W/L = 3um/100nm and NMOS with W/L = 1um /100 nm) and finally the blue line (PMOS with W/L = 1.5um/100nm and NMOS with W/L = 0.5um /100 nm). By the principle operation, PMOS has many holes and NMOS has many charges, charges from NMOS will go in PMOS to fulfill the holes. PMOS and NMOS have width increases that
LABORATORY 1 EE 476 GROUP 8 09ECE
W/L is increase then tpLH decreases. Or the tpLH (Low to High) of output = 6um is lowest and tpLH of output = 1.5um is highest. Check the graph from high to low (falling era) 1 Redline 2 Yellow line
3 Blue line
LABORATORY 1 EE 476
GROUP 8 09ECE
To create AND gate CMOS, we have to create NAND gate CMOS first then use INVERTER CMOS to fulfill the operation of AND gate CMOS.
LABORATORY 1 EE 476
GROUP 8 09ECE
LABORATORY 1 EE 476
GROUP 8 09ECE
Combining NAND gate CMOS and INVERTER CMOS to create AND gate CMOS
LABORATORY 1 EE 476
GROUP 8 09ECE
LABORATORY 1 EE 476
GROUP 8 09ECE
LABORATORY 1 EE 476
GROUP 8 09ECE
LABORATORY 1 EE 476
GROUP 8 09ECE
LABORATORY 1 EE 476
GROUP 8 09ECE
Period: 2 us, rise time = fall time = 100n s, delay time = 0, pulse width = 400ns
LABORATORY 1 EE 476
GROUP 8 09ECE
delay time = 500n s Period: 2 us, rise time = fall time = 100n s, delay time = 0, pulse width = 400ns
LABORATORY 1 EE 476
GROUP 8 09ECE
Input A: delay time 500n s Period: 2 us, rise time = fall time = 100n s, delay time = 0, pulse width = 400ns
LABORATORY 1 EE 476
GROUP 8 09ECE