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5/6/2013

LABORATORY 1 EE 476
Lab 1: Introduced to the Cadence suit of IC design tools

GROUP 8 09ECE Danang University of Technology, Faculty of Electronics and Telecommunications, COE center

DESIGN CMOS INVERTER 1

Danang University of Technology, Faculty of Electronics and Telecommunications EE 476 Lab 1: Introduced to the Cadence suit of IC design tools TA. Vo Tuan Minh
MEMBER OF GROUP 8: L Mai Trung L Huy L Quang Tun

Table of Contents

A. Design CMOS Inverter


1. 2. 3. 4. CMOS inverter basics Design Layout in Cadence Results of Testbench Explanation

B. Design AND gate


1. Introduction the principle operation 2. Design Layout in Cadence 3. Results of Testbench

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DESIGN CMOS INVERTER 2 A. DESIGN CMOS INVERTER


1. CMOS Inverter basics:

From Figure 1, a CMOS circuit is composed of two MOSFETs. The top FET (MP) is a PMOS type device while the bottom FET (MN) is an NMOS type. The body effect is not present in either device since the body of each device is directly connected to the devices source. Both gates are connected to the input line. The output line connects to the drains of both FETs. Take a look at the VTC in Figure 2. The curve represents the output voltage taken from node 3. We can easily see that the CMOS circuit functions as an inverter by noting that when VIN is five volts, VOUT is zero, and vice versa. Thus when inputting a high we get a low and when input a low we get a high as is expected for any inverter.

The active PMOS load device is a PMOS transistor, wherein the source of the PMOS transistor is connected to the power supply voltage and the drain of the PMOS transistor is connected to the amplifying unit wherein the second load device further comprises: a compensation unit which is connected to the negative feedback buffering unit and compensates for both a gain and a frequency characteristics in the high frequency range. The gate of the NMOS transistor of the negative feedback load buffering unit is connected to the drain of the PMOS transistor, the source of the NMOS transistor of the negative feedback load buffering unit is connected to the gate of the PMOS transistor, and the drain of the NMOS transistor is connected to the power supply voltage.
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DESIGN CMOS INVERTER 3


2. Design Layout in Cadence: Inverter schematic:

- PMOS with W/L = 3um/100nm - NMOS with W/L = 1um /100 nm

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Sympol of the inverter:

Schematic of Inverters testbench:

Adding a 20f F Capacitor in the schematic of testbench.


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DESIGN CMOS INVERTER 5


3. Results of testbench: Input is a Voltage pulse with period = 1us. Rise time = 100ns. Fall time = 100ns. Pulse width = 400ns Voltage peak to peak from 0 to 1V And voltage source VDC = 1V. Set up for 2u of simulation time. The result: Input and Output show in the same graph

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DESIGN CMOS INVERTER 6

Only the output:

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The input and output show in the graph is opposite amplitude, because output and input is reverse. 4. Explanation: Changing the W/L on PMOS and CMOS to get a new output. 1. Design PMOS with W/L = 3um/100nm and NMOS with W/L = 1um /100 nm 2. PMOS with W/L = 6um/100nm and NMOS with W/L = 2um /100 nm 3. PMOS with W/L = 1.5um/100nm and NMOS with W/L = 0.5um /100 nm 1 Green line 2 Red line 3 Yellow line

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Let zoom in for more detail, at this time: 1 Redline 2 Yellow line Check the graph from low to high (raising era):

3 Blue line

At we can see, the yellow line (as known as PMOS with W/L = 6um/100nm and NMOS with W/L = 2um /100 nm) raises first then the red line (PMOS with W/L = 3um/100nm and NMOS with W/L = 1um /100 nm) and finally the blue line (PMOS with W/L = 1.5um/100nm and NMOS with W/L = 0.5um /100 nm). By the principle operation, PMOS has many holes and NMOS has many charges, charges from NMOS will go in PMOS to fulfill the holes. PMOS and NMOS have width increases that
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DESIGN CMOS INVERTER 9


leads to the movement of charges increases. The inverter is more active, the delay time is smaller. We have

W/L is increase then tpLH decreases. Or the tpLH (Low to High) of output = 6um is lowest and tpLH of output = 1.5um is highest. Check the graph from high to low (falling era) 1 Redline 2 Yellow line

3 Blue line

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DESIGN CMOS INVERTER 10


At this falling time, opposite to raising era, the blue line falls first then the red line and finally the yellow line. The increase width of gate increases the delay time from high to low. The greater width, the greater value of total capacitance (intrinsic capacitance plus load capacitance) is because width length in proportion to intrinsic capacitance. Thus, discharging time increases. This explain why increasing W, tphl (high to low) increases.

B. Design AND gate


1. Introduction the principle operation:

To create AND gate CMOS, we have to create NAND gate CMOS first then use INVERTER CMOS to fulfill the operation of AND gate CMOS.

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DESIGN CMOS INVERTER 11


2. Design Layout in Cadence NAND GATE CMOS schematic

PMOS with W/L = 3um/100nm NMOS with W/L = 1um /100 nm

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DESIGN CMOS INVERTER 12


Symbol of NAND gate CMOS:

Combining NAND gate CMOS and INVERTER CMOS to create AND gate CMOS

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Symbol of AND gate CMOS:

Schematic of testbench AND gate:

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DESIGN CMOS INVERTER 14


3. Results of Testbench: Set up the period, rise time, fall time, delay time of the two inputs like the image below.

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DESIGN CMOS INVERTER 15

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DESIGN CMOS INVERTER 16


The results:

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DESIGN CMOS INVERTER 17


The other results when setting up the different period, rise time, fall time, delay time of the two inputs.

Period: 2 us, rise time = fall time = 100n s, delay time = 0, pulse width = 400ns

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delay time = 500n s Period: 2 us, rise time = fall time = 100n s, delay time = 0, pulse width = 400ns

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DESIGN CMOS INVERTER 19

Input A: delay time 500n s Period: 2 us, rise time = fall time = 100n s, delay time = 0, pulse width = 400ns

LABORATORY 1 EE 476

GROUP 8 09ECE