1.

Lo que hay que hacer es sacar el tiempo de establecimiento a partir de las grficas que tomo hacindole estadstica. 2. Despus que usted tiene el tiempo de establecimiento observa que la respuesta del motor corresponde a un de ms o menos 0.8 a 0.9 entonces toca escoger uno entonces como usted miro la velocidad que es de segundo orden osea :

Entonces como tiene el cita y tiempo de establecimiento saca el Wn .

3. Usted se pregunta y el K como lo hallo entonces resulta que si usted le mete 10 Voltios y revisa la salida del otro motor y tiene 8 voltios osea un ejemplo:

Ese resulta siendo la ganancia que debe tener el sistema para ajustarse a la entrada.

Shows the block diagram of a digitally controlled dc motor. The output of the D/A converter is proportional to the binary equivalent of its digital inputs. The differential amplifier compares the D/A converter output with the output voltage of the F/V converter. The resulting difference voltage is an input to the power amplifier/driver stage. The output of the power amplifier/driver then drives the dc motor. The speed sensor converts the motors speed into a pulse waveform, which is in turn converted into a proportional voltage by the F/V converter since the output of the F/V converter is processed using a negative feedback formed with the differential amplifier, the motor is kept at a constant speed corresponding to the setting of the digital inputs. In fact, the key to the operation of the circuit is that the differential amplifier maintains a specific difference between two input voltages so that motor speed is constant at the selected digital input setting.

Since the output of the D/A converter is directly proportional to the binary equivalent of its digital inputs, the output voltage of the D/A converter will be maximum positive when all the inputs are logic 1. This means that when all inputs are logic 1 the motor will run at a maximum speed. Now suppose that the motor is initially running at a certain speed and digital inputs have just been set to lower the speed. This action will reduce the output voltage of the D/A converter, which in turn

reduces the difference between the two input voltages of the differential amplifier, resulting in a reduced drive for the motor. Therefore, the speed of the motor will be lowered until the output of the F/V converter is such that a specific input difference voltage for the differential amplifier, which is required to keep the motor running at a constant speed, is reached. The difference voltage necessary to maintain the constant motor speed is a function of the physical dimensions and electrical characteristics of the motor. These include torque, speed, inertia, and current and voltage ratings of the motor. Thus the constant difference voltage and, in turn, a constant motor speed is maintained through the use of negative feedback. The digital inputs may be calibrated in terms of revolutions per minute (rpm). In addition, the output of the speed sensor may be applied to the frequency meter/indicator to monitor the motors speed.

implementation in proteus was conducted through a DAC 0800.The DAC0800 series are monolithic 8-bit high-speed current-output digital-to-analog converters (DAC) featuring typical settling times of 100 ns. When used as a multiplying DAC, monotonic performance over a 40 to 1 reference current range is possible.

The Block Diagram of DAC is show in the figure 5.

this datasheet show a typical application from which we obtain the analog output of the diagram above:

From this block diagram we find the need to implement a similar stage of power, for this purpose we resort to a class power amlificator B Push-Pull.

In order to be able to rotate the motor in both clockwise and counterclockwise directions we should be capable of providing a negative current to the motor. This can be achieved using a pushpull amplifier. A push pull amplifier is a Class B type of amplifier that either drives a positive or a negative current into a load. It consist of a pair of complimentary transistors, in our case NPN and PNP BJT transistors, connected in common collector configuration.

When +Vcc>Vin>Vbe the upper transistor (NPN) is in active region and the lower transistor (PNP) would be in cutoff region. When -Vcc<Vin<-Vbe the lower transisor (PNP) will be in active region and the upper one will be in cutoff. The same theory developed in the previous section can be applied in here. In order to be able to drive the transistors from a high output impedance source (potentiometer - DAC etc.) we need an impedance matching device. This can be achieved using a UA741 op-amp. The feedback for the op-amp needs to be implemented depending on the gain needed. In our case unity gain is required.

We notice from this plot that there is a dead zone around 0V. This dead zone is called "crossover distortion" in the literature. This is obviously due to base-emitter voltage necessary for the NPN transistor to be in the active region (in the case of positive Vin) and for the PNP transistor to be in the active region (in the case of negative Vin). In the case of TIP31 and TIP32 this crossover distortion is of about 2Vbe=2*1.8=3.6volts. This is not desirable at all since it provides nonlinearity that will cause the frequency response analysis or the closed loop control to fail.