International Journal of Engineering Research and Development e-ISSN: 2278-067X, p-ISSN: 2278-800X, www.ijerd.

com Volume 6, Issue 10 (April 2013), PP. 101-106

A Novel Method for the Elimination of Dead Time in Two Level Voltage Source Inverter
M.S.Sivagamasundari1, Dr.P.Melba Mary2
1

(Assistant Professor , Department of EEE,V V College of Engineering,Tisaiyanvilai 2 (Principal , Department of EEE,V V College of Engineering,Tisaiyanvilai)

Abstract: - Dead time is a short delay introduced between the gating signals of the upper and lower switches in an inverter leg to prevent the short circuit of dc link. Such dead time results in a change in f undamental voltage and also causes low frequency distortion. In this paper , a novel method for the elimination of dead time in two level voltage source inverter is proposed and implemented. This method reduces the low frequency distortion and results in a steady fundamental voltage. The validity of this method has been studied by the PSPICE Simulation and prototype experiment. Keywords: - Dead-time, harmonic, phase-leg, gate drive, voltage source inverter (VSI)

I.

INTRODUCTION

To avoid shoot-though in PWM controlled voltage source inverters (VSI), dead-time, a small interval during which both the upper and lower switches in a phase leg are off, is introduced into the control of the standard VSI phase leg. However, such a blanking time can cause problems such as output waveform distortion and fundamental voltage loss inVSIs.[1-4].Fig. 1(a) shows the dead-time effect in a voltage source inverter.

(a)

(b) Fig.1.Effect of dead time

Fig 1 (b) shows the output voltage waveform distortion caused by dead-time effect. To overcome deadtime effects, most solutions focus on dead-time compensation [1-4] by introducing complicated PWM controller and expensive current detection hardware. In practice, the dead-time varies with the devices and output current, as well as temperature, which makes the compensation less effective, especially at low output current, low frequency, and zero current crossing. [5] proposed a new switching strategy for PWM power converters. [6] presented an IGBT gate driver circuit to eliminate the dead-time effect. [7] proposed a phase leg configuration topology which prevented shoot through. However, an additional diode in series in the phase leg increases complexity and causes more loss in the inverter. Also, this phase leg configuration is not suitable for high power inverters because the upper device gate turn off voltage is reversely clamped by a diode turn on voltage. Such a low voltage, usually less than 2 V, is not enough to ensure that a device is in off state during the activation of its complement device.[7]

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A Novel Method for the Elimination of Dead Time in Two Level Voltage II. PRINCIPLE OF DEAD TIME ELIMINATION

Fig. 2. A generic phase leg of VSIs. To explain the principle of the proposed dead-time elimination method, we refer to a generic phase leg of VSIs, as shown in figure 2. Assuming the output current flows out of the phase leg, in each switching cycle, the current comes out from the upper device when Kp is on and freewheels through diode Dn when Kp is off. Here this current direction is defined as positive. Under this condition, the generic phase leg can be equivalently expressed as a P type switching cell. Similarly when load current flows into the phase leg, defined as negative, the current goes into the lower device when Kn is on and freewheels through diode Dp when Kn is off. Under this condition, the generic phase leg can be equivalently expressed as a N type switching cell . Actually a generic phase leg is a combination of one P switch cell and one N switch cell. There is no question that deadtime is not required for either a P switch cell or a N switch cell because both cells are configured with a controllable switch in series with a uncontrollable diode.[8].

III.

TWO LEVEL VOLTAGE SOURCE INVERTER

Fig.3.Full-bridge inverter feeding an RL load The full-bridge circuit feeding an inductive (RL) load is shown in fig.3. A simple scheme of controlling the gating of the four switches is also shown. Although each switch is gated to be on for one-half the time period, each switch may not conduct for one-half the time period due to the constraints imposed by the load. The arrow-head shows the direction in which the current can flow through each switch. When a switch is gated on but the current is in the opposite direction, the freewheeling diode placed in anti parallel with the switch will provide the path for the current. Note that there are two intervals during which the output voltage is zero. During the time interval between a and b, the current i(t) circulates in the top-half of the circuit through S1 and D3 and the voltage across the load is zero assuming the diode and the switch are ideal. Likewise, the current completes it path through S4 and D2 in the bottom half of the circuit during the time interval from c to d and the voltage across the load is zero.

Fig. 4. Waveform for the gating scheme of the 4 switches

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A Novel Method for the Elimination of Dead Time in Two Level Voltage

IV.

SIMULATION RESULTS

In this paper, the simulation model is developed with PSPICE tool which contains a dc source, four MOSFETs , inductor, capacitor and a resistive load. The MOSFET is driven by the gate signal of frequency of 50KHZ. The circuit is designed for an output of 40V with an input of 48V. The simulation circuit of the proposed method and the output voltage waveform is shown in fig.5. and fig.6.

DEAD TIME ELIMINATION 2

V2 V1 = 0 V2 = 5 TD = 0 TR = 1ns TF = 1ns PW = 10ms PER = 20ms V1 M1 M2N6757 D6 V1 = 0 V2 = 5 TD = 10ms TR = 1ns MUR150 TF = 1ns PW = 10m PER = 20ms M3 D1 M2N6757 MUR150

V7 48V
VV+

V1 = 0 V2 = 5 TD = 10ms TR = 1ns TF = 1ns PW = 10ms PER = 20ms

V1 = 0 V2 = 5 TD = 0 TF = 1ns TR = 1ns PW = 10m M2 D4 M2N6757 MUR150 PER = 20ms

V4 M6 D5 M2N6757 MUR150

L1 1 100mH 2 C3 100u
V+

R5 1k
V-

Fig.5.Simulation circuit of the proposed method

60V

40V

20V

-0V

-20V

-40V

-60V 0s 10ms V(M2:d,V2:-) 20ms 30ms 40ms 50ms Time 60ms 70ms 80ms 90ms 100ms

Fig.6. Output Voltage Waveform

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A Novel Method for the Elimination of Dead Time in Two Level Voltage
In this proposed method, the dead time effect has been dramatically minimized and the output distortion also reduces.

V.
1 2 7805 1 2
1000U-35V

HARDWARE IMPLEMENTATION
7805 VIN
GND

1 220 TO 1K 3 VIN
GND

VOUT

VOUT

D7 10U LED

R4 2 10K TX3 TN33_20_11_2P90

U5 C9 10U 0 1 RST/VPP 1
20

U4

VCC

U2 12 13 6 P1.2 P1.3 14 8 15 10 1 2 4 1A1 VCC 1A2 1Y1 1Y2 1A3 1Y3 1A4 1Y4 GND 1G 74HC244 20 18

10

HIN

HO VCC

7
1

230-15V
C8 33P 33P

P1.0/AIN0 5 X1 12.00 4 XTAL1 P1.1/AIN1 XTAL2

3 2 6 5 1 47U 10U

22 1N4500
2

12 16 14 12 C3 9 47U 13

LIN

COM VB VS

VDD LO VSS IR2110

M1 22 IRF840

M3 IRF840 L1

10

GND

16 17 AT89C2051/SO

2200U-63

M5 IRF840 V1 30 M4 M2 10 HIN HO VCC 12 C3 9 47U 13 VDD LO VSS IR2110 LIN COM VB VS 7

1

10uH C12 333P M6 IRF840

IRF840 22 1N4500 10U 47U 22

2

IRF840

3 2 6 5 1

D7

D7

220 LED TO 1K

220 LED TO 1K

U7 MCT2E

10U 7805

10U 7805 22 2 U8 MCT2E 10K

VOUT

GND
VIN

GND
VIN

1000U-35V

VOUT

1000U-35V 1k 10K

TX1 TN33_20_11_2P90

TX2 TN33_20_11_2P90

230-15V

230-15V

Fig.7.Hardware circuit diagram The hardware circuit for the proposed method is shown in fig.7. The hardware circuit consists of the following major parts such as power supply unit, microcontroller circuit, buffer circuit and isolation circuit. Fig.8. shows the power and control circuit.

Fig.8.Power and control circuit

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A Novel Method for the Elimination of Dead Time in Two Level Voltage

Fig.9.Experimental waveform of the proposed method

Fig.10.Hardware Setup The proposed dead elimination circuit is incorporated into a single phase H-Bridge inveter as shown in fig.10. The MOSFETS used are IRF840.The inverter is loaded with a R-L load resistances of 1K and 100mH. The dc bus voltage is 48V and the frequency of modulation is 50HZ. In addition, the proposed deadtime elimination control scheme can be implemented, contained in the at AT89C2051microcontroller software to reduce hardware cost.

VI.

CONCLUSION

In the present work, a novel method for the elimination of dead time in two level voltage source inverter is proposed and implemented. This method reduces the low frequency distortion and results in a steady fundamental voltage. The validity of this method has been studied by the PSPICE Simulation and prototype experiment. Compared to the conventional method , this method has simple control logic, low cost and flexible implementation.

REFERENCES
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[2]. [3].

[4]. [5].

[6].

[7]. [8] [9]

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A Novel Method for the Elimination of Dead Time in Two Level Voltage
[10] D. G. Holmes and T. A. Lipo, Pulse Width Modulation for Power Converters:Principles and Practice . New York: Wiley, 2003. [11] N.Mohan,T.M.Undeland, andW.P. Robbins,Power Electronics- Converters, Applications and Design, 3rd ed. NewYork:Wiley, 2003. [12] C. M. Wu, W. Lau, and H. S. Chung, Analytical technique for calculating the output harmonics of an H-bridge inverter with dead time, IEEE Trans. Circuits Syst., vol. 46, no. 5, pp. 617627, May 1999. [13] F. Z. Peng, J. Wang, F. Zhang, and Z. Qian, Development of a 1.5 MVA universal converter mo dule for ship propulsion, traction drive and utility applications, in Proc. IEEE Power Electronics SpecialistsConf., 2005, pp. 22902295.

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