ELETRONICA DIGITAL - PRCTICA TEMA: TRABAJO DE PROGRAMACION VHDL INTEGRANTES:

CCORAHUA SANTO, NACEAN OSCAR CORNEJO CONDORI, CARLOS MARIO

AREQUIPA- 2012

PROBLEMAS

PROYECTO N 1 Realice la descripcin logartmica en VHDL de un biestable D cerrojo. Luego emplee esta entidad en el control de un motor elctrico por medio de un botn. El motor pasa de encendido a apagado y viceversa cada vez que se pulsa el botn. Se pide:

a. Algoritmo de solucin para el biestable D b. Esquema solucin para el encendido/apagado del motor. c. Algoritmo solucin para el control de E/A

d. Codificacin en VHDL del algoritmo del item d e. Pruebas de simulacin para el sistema propuesto. Esquema para el encendido y apagado del motor

Tengamos en cuenta que para un BIESTABLE D

D 0 1

Q 0 1

Q 1 0

Donde:

D= pulso del botn Q= funcionamiento del botom

El algoritmo (comportamental) a usar es el siguiente:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --practica electronica digital , jueves 4.00;5.30 --nombres: ccorahua santo oscar -cornejo condori carlos entity biestabled is Port ( c : in STD_LOGIC; d : in STD_LOGIC; q : out STD_LOGIC); end biestabled; architecture Behavioral of biestabled is begin process (c,d) begin if (c='1') then q<=not d; end if; if (c='0') then q<=c and d; end if; end process; end Behavioral;

Simulacin:

PROYECTO N 2 Implemente en cdigo VHDL un multiplexor de 8 bits y 4 entradas. Utilice una descripcin comportamental. Detalle su procedimiento y considere en su solucin lo siguiente:

a. Anlisis y algoritmo para el multiplexor. b. Codificacin en VHDL del algoritmo del multiplexor. c. Pruebas de simulacin.

Algoritmo.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux8bitsy4entradas is Port ( S : in BIT_VECTOR(1 DOWNTO 0); D01 : in STD_LOGIC; D11 : in STD_LOGIC; D21 : in STD_LOGIC; D31 : in STD_LOGIC; Y1 : out STD_LOGIC; D12 : in D22 : in D32 : in Y2 : out D13 : in D23 : in D33 : in Y3 : out D14 : in D24 : in D34 : in Y4 : out D15 : in D25 : in D35 : in Y5 : out D16 : in D26 : in D36 : in Y6 : out D17 : in D27 : in D37 : in Y7 : out D02 : in STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; D03 : in STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; D04 : in STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; D05 : in STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; D06 : in STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; D07 : in STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC;

D08 : in STD_LOGIC; D18 : in STD_LOGIC; D28 : in STD_LOGIC; D38 : in STD_LOGIC;

Y8 : out STD_LOGIC ); end mux8bitsy4entradas; architecture comportamental of mux8bitsy4entradas is begin PROCESS (D01,D11,D21,D31,D02,D12,D22,D32,D03,D13,D23,D33,D04,D14,D24,D34,D05,D15 ,D25,D35,D06,D16,D26,D36,D07,D17,D27,D37,D08,D18,D28,D38,S) BEGIN CASE S IS WHEN "00" WHEN "01" WHEN "10" WHEN "11" END CASE; CASE S IS WHEN "00" WHEN "01" WHEN "10" WHEN "11" END CASE; CASE S IS WHEN "00" WHEN "01" WHEN "10" WHEN "11" END CASE; CASE S IS WHEN "00" WHEN "01" WHEN "10" WHEN "11" END CASE; CASE S IS WHEN "00" WHEN "01" WHEN "10" WHEN "11" END CASE; CASE S IS WHEN "00" WHEN "01" WHEN "10" WHEN "11" END CASE; => => => => Y1 Y1 Y1 Y1 <= <= <= <= D01; D11; D21; D31;

=> => => =>

Y2 Y2 Y2 Y2

<= <= <= <=

D02; D12; D22; D32;

=> => => =>

Y3 Y3 Y3 Y3

<= <= <= <=

D03; D13; D23; D33;

=> => => =>

Y4 Y4 Y4 Y4

<= <= <= <=

D04; D14; D24; D34;

=> => => =>

Y5 Y5 Y5 Y5

<= <= <= <=

D05; D15; D25; D35;

=> => => =>

Y6 Y6 Y6 Y6

<= <= <= <=

D06; D16; D26; D36;

CASE S IS WHEN "00" => Y7 <= D07; WHEN "01" => Y7 <= D17; WHEN "10" => Y7 <= D27;

WHEN "11" => Y7 <= D37; END CASE; CASE S IS WHEN "00" WHEN "01" WHEN "10" WHEN "11" END CASE; => => => => Y8 Y8 Y8 Y8 <= <= <= <= D08; D18; D28; D38;

END PROCESS; end comportamental;

Simulacin.

PROYECTO N 3 Realice en cdigo VHDL la descripcin estructural de un codificador decimal cuyas salidas son activas en un cero lgico. Se pide: Anlisis del problema Codificacin en VHDL del decodificador decimal Pruebas de simulacin para el sistema propuesto Algoritmo.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --practica electronica digital. jueves 4.00;5:30 --nombres; ccorahua santo oscar -cornejo condori carlos entity decodif is Port ( x : in STD_LOGIC_VECTOR (3 downto 0); a : out STD_LOGIC; b : out STD_LOGIC; c : out STD_LOGIC;

d : out STD_LOGIC; e : out STD_LOGIC; f : out STD_LOGIC; g : out STD_LOGIC; h : out STD_LOGIC; i : out STD_LOGIC; j : out STD_LOGIC); end decodif; architecture Behavorial of decodif is begin process (x) begin a <= '1'; b <= '1'; c <= '1'; d <= '1'; e <= '1'; f <= '1'; g <= '1'; h <= '1'; i <= '1'; j <= '1'; if X = "0000" then a <= '0'; elsif X = "0001" then b <= '0'; elsif X = "0010" then c <= '0'; elsif X = "0011" then d <= '0'; elsif X = "0100" then e <= '0'; elsif X = "0101" then f <= '0'; elsif X = "0110" then g <= '0'; elsif X = "0111" then h <= '0'; elsif X = "1000" then i <= '0'; else j <= '0'; end if; end process; end Behavorial;

Simulacin.

PROYECTO N4 Realice en cdigo VHDL la descripcin de un flujo de datos de un sumador completo. Se pide:

a. Anlisis del problema.

b. Codificacin en VHDL del sumador total. c. Pruebas de simulacin para el sistema propuesto

VHDL: ---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; -- Practica electronica digital , jueves 4.00-5.30 -- Cornejo Condori Carlos, -- Ccorahua Santo Oscar entity SUM_COM is Port ( x : in STD_LOGIC; y : in STD_LOGIC; z : in STD_LOGIC; s : out STD_LOGIC; c : out STD_LOGIC); end SUM_COM; architecture Flujo_de_datos of SUM_COM is begin S<= X xor Y xor Z; C<= (X and Y) or ((X xor Y) and Z); end Flujo_de_datos;

Simulacin:

CONCLUSIONES y OBSERVACIONES. -

Al usar estas compuertas lgicas se hace ms fcil el trabajo. Podemos comprobar las simulaciones hechas con ejercicios descritos en la prctica. Se logr conocer ms el uso de todas las compuertas logicas