3D TRANSISTORS-FINFETs

CHAPTER 1 INTRODUCTION
Since the fabrication of MOSFET, the minimum channel length has been shrinking continuously. The motivation behind this decrease has been an increasing interest in high speed devices and in very large scale integrated circuits. The sustained scaling of conventional bulk device requires innovations to circumvent the barriers of fundamental physics constraining the conventional MOSFET device structure. The limits most often cited are control of the density and location of dopants providing high Ion /I off ratio and finite sub threshold slope and quantummechanical tunneling of carriers through thin gate from drain to source and from drain to body. The channel depletion width must scale with the channel length to contain the off-state leakage I off. This leads to high doping concentration, which degrade the carrier mobility and causes junction edge leakage due to tunneling. Furthermore, the dopant profile control, in terms of depth and steepness, becomes much more difficult. The gate oxide thickness tox must also scale with the channel length to maintain gate control, proper threshold voltage VT and performance. The thinning of the gate dielectric results in gate tunneling leakage, degrading the circuit performance, power and noise margin. Alternative device structures based on silicon-on-insulator (SOI) technology have emerged as an effective means of extending MOS scaling beyond bulk limits for mainstream high-performance or low-power applications .Partially depleted (PD) SOI was the first SOI technology introduced for high-performance microprocessor applications. The ultra-thin-body fully depleted (FD) SOI and the non-planar FinFET device structures promise to be the potential future technology/device choices. In these device structures, the short-channel effect is controlled by geometry, and the offstate leakage is limited by the thin Si film. For effective suppression of the off-state leakage, the thickness of the Si film must be less than one quarter of the channel length. The desired VT is achieved by manipulating the gate work function, such as the use of midgap material or polySiGe. Concurrently, material enhancements, such as the use of a) high-k gate material and b) strained Si channel for mobility and current drive improvement have been actively pursued.

Dept of ECE, VJCET

3D TRANSISTORS-FINFETs

CHAPTER 2 WORKING OF A TYPICAL n-CHANNEL MOSFET

The n-type Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) consists of a source and a drain, two highly conducting n-type semiconductor regions which are isolated from the p-type substrate by reversed-biased p-n diodes. A metal (or poly-crystalline) gate covers the region between source and drain, but is separated from the semiconductor by the gate oxide. The basic structure of an n-type MOSFET and the corresponding circuit symbol are shown in Fig.2.1.

Fig.2.1: Cross section and circuit symbol of MOSFET As can be seen on the figure the source and drain regions are identical. It is the applied voltages which determine which n-type region provides the electrons and becomes the source, while the other n-type region collects the electrons and becomes the drain. The voltages applied to the drain and gate electrode as well as to the substrate by means of a back contact are referred to the source potential, as also indicated on the figure. A top view of the same MOSFET is shown in Fig.2.2, where the gate length, L, and gate width, W, are identified. Note that the gate length does not equal the physical dimension of the gate, but rather the distance between the sources and drain regions underneath the gate. The overlap between the gate and the source and drain region is required to ensure that the inversion layer forms a continuous conducting path between the source and drain region. Typically this overlap is made as small as possible in order to minimize its parasitic capacitance.

Dept of ECE, VJCET

3D TRANSISTORS-FINFETs

Fig.2.2: Top view of N - type MOSFET The flow of electrons from the source to the drain is controlled by the voltage applied to the gate. A positive voltage applied to the gate, attracts electrons to the interface between the gate dielectric and the semiconductor. These electrons form a conducting channel between the source and the drain, called the inversion layer. No gate current is required to maintain the inversion layer at the interface since the gate oxide blocks any carrier flow. The net result is that the current between drain and source is controlled by the voltage which is applied to the gate.

Fig.2.3: V-I Characteristics of n-type MOSFET

Dept of ECE, VJCET

3D TRANSISTORS-FINFETs

CHAPTER 3 MOORES LAW

Fig.3.1: Agreement with Moores law Moore's law is the observation that over the history of computing hardware, the number of transistors on integrated circuits doubles approximately every two years. The law is named after Intel co-founder Gordon E. Moore, who described the trend in his 1965 paper. The paper noted that the number of components in integrated circuits had doubled every year from the invention of the integrated circuit in 1958 until 1965 and predicted that the trend would continue "for at least ten years". His prediction has proven to be uncannily accurate, in part because the law is now used in the semiconductor industry to guide long-term planning and to set targets for research and development. The capabilities of many digital electronic devices are strongly linked to Moore's law: processing speed, memory capacity, sensors and even the number and size of pixels in digital cameras. All of these are improving at (roughly) exponential rates as well. This exponential improvement has dramatically enhanced the impact of digital electronics in nearly every segment of the world economy This trend has continued for more than half a century. Sources in 2005 expected it to continue until at least 2015 or 2020. However, the 2010 update to the International Technology Roadmap for Semiconductors has growth slowing at the end of 2013, after which time transistor counts and densities are to double only every three years. Dept of ECE, VJCET
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3D TRANSISTORS-FINFETs

CHAPTER 4 TRANSISTOR SCALING

Over the past decades, the MOSFET has continually been scaled down in size; typical MOSFET channel lengths were once several micrometers, but modern integrated circuits are incorporating MOSFETs with channel lengths of tens of nanometers. Intel began production of a process featuring a 32 nm feature size (with the channel being even shorter) in late 2009. The semiconductor industry maintains a "roadmap", the ITRS, which sets the pace for MOSFET development. Historically, the difficulties with decreasing the size of the MOSFET have been associated with the semiconductor device fabrication process, the need to use very low voltages, and with poorer electrical performance necessitating circuit redesign and innovation (small MOSFETs exhibit higher leakage currents, and lower output resistance, discussed below).

4.1 Reasons for MOSFET scaling

Smaller MOSFETs are desirable for several reasons. The main reason to make transistors smaller is to pack more and more devices in a given chip area. This results in a chip with the same functionality in a smaller area, or chips with more functionality in the same area. Since fabrication costs for a semiconductor wafer are relatively fixed, the cost per integrated circuits is mainly related to the number of chips that can be produced per wafer. Hence, smaller ICs allow more chips per wafer, reducing the price per chip. In fact, over the past 30 years the number of transistors per chip has been doubled every 23 years once a new technology node is introduced.

Fig.4.1: Scaling of gate length w.r.t Moores law Dept of ECE, VJCET
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3D TRANSISTORS-FINFETs It is also expected that smaller transistors switch faster. For example, one approach to size reduction is a scaling of the MOSFET that requires all device dimensions to reduce proportionally. The main device dimensions are the transistor length, width, and the oxide thickness, each (used to) scale with a factor of 0.7 per node. This way, the transistor channel resistance does not change with scaling, while gate capacitance is cut by a factor of 0.7. Hence, the RC delay of the transistor scales with a factor of 0.7. While this has been traditionally the case for the older technologies, for the state-of-theart MOSFETs reduction of the transistor dimensions does not necessarily translate to higher chip speed because the delay due to interconnections is more significant.

4.2 Difficulties arising due to MOSFET size reduction

Producing MOSFETs with channel lengths much smaller than a micrometer is a challenge, and the difficulties of semiconductor device fabrication are always a limiting factor in advancing integrated circuit technology. In recent years, the small size of the MOSFET, below a few tens of nanometers, has created operational problems. 4.2.1 Higher subthreshold conduction As MOSFET geometries shrink, the voltage that can be applied to the gate must be reduced to maintain reliability. To maintain performance, the threshold voltage of the MOSFET has to be reduced as well. As threshold voltage is reduced, the transistor cannot be switched from complete turn-off to complete turn-on with the limited voltage swing available; the circuit design is a compromise between strong current in the "on" case and low current in the "off" case, and the application determines whether to favor one over the other. Subthreshold leakage (including subthreshold conduction, gate-oxide leakage and reverse-biased junction leakage), which was ignored in the past, now can consume upwards of half of the total power consumption of modern high-performance VLSI chips. 4.2.2 Increased gate-oxide leakage The gate oxide, which serves as insulator between the gate and channel, should be made as thin as possible to increase the channel conductivity and performance when the transistor is on and to reduce subthreshold leakage when the transistor is off. However, with current gate oxides with a thickness of around 1.2 nm (which in silicon is ~5 atoms thick) the quantum phenomenon Dept of ECE, VJCET
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3D TRANSISTORS-FINFETs of electron tunneling occurs between the gate and channel, leading to increased power consumption. Silicon dioxide has traditionally been used as the gate insulator. Silicon dioxide however has a modest dielectric constant. Increasing the dielectric constant of the gate dielectric allows a thicker layer while maintaining a high capacitance (capacitance is proportional to dielectric constant and inversely proportional to dielectric thickness). All else equal, a higher dielectric thickness reduces the quantum tunneling current through the dielectric between the gate and the channel. Insulators that have a larger dielectric constant than silicon dioxide (referred to as high-k dielectrics), such as group IVb metal silicates e.g. hafnium and zirconium silicates and oxides are being used to reduce the gate leakage from the 45 nanometer technology node onwards. On the other hand, the barrier height of the new gate insulator is an important consideration; the difference in conduction band energy between the semiconductor and the dielectric (and the corresponding difference in valence band energy) also affects leakage current level. For the traditional gate oxide, silicon dioxide, the former barrier is approximately 8 eV. For many alternative dielectrics the value is significantly lower, tending to increase the tunneling current, somewhat negating the advantage of higher dielectric constant. The maximum gate-source voltage is determined by the strength of the electric field able to be sustained by the gate dielectric before significant leakage occurs. As the insulating dielectric is made thinner, the electric field strength within it goes up for a fixed voltage. This necessitates using lower voltages with the thinner dielectric. 4.2.3 Increased junction leakage To make devices smaller, junction design has become more complex, leading to higher doping levels, shallower junctions, "halo" doping and so forth, all to decrease draininduced barrier lowering (see the section on junction design). To keep these complex junctions in place, the annealing steps formerly used to remove damage and electrically active defects must be curtailed increasing junction leakage. Heavier doping is also associated with thinner depletion layers and more recombination centers that result in increased leakage current, even without lattice damage.

Dept of ECE, VJCET

3D TRANSISTORS-FINFETs

Fig.4.2: MOSFET version of gain osted current mirror; M1 and M2 are in active mode, while M3 and M4 are in Ohmic mode, and act like resistors. The operational amplifier provides feedback that maintains a high output resistance.

4.2.4 Lower output resistance For analog operation, good gain requires high MOSFET output impedance, which is to say, the MOSFET current should vary only slightly with the applied drain-to-source voltage. As devices are made smaller, the influence of the drain competes more successfully with that of the gate due to the growing proximity of these two electrodes, increasing the sensitivity of the MOSFET current to the drain voltage. To counteract the resulting decrease in output resistance, circuits are made more complex, either by requiring more devices, for example the cascode and cascade amplifiers, or by feedback circuitry using operational amplifiers, for example a circuit like that in the adjacent figure. 4.2.5 Lower transconductance The transconductance of the MOSFET decides its gain and is proportional to hole or electron mobility (depending on device type), at least for low drain voltages. As MOSFET size is reduced, the fields in the channel increase and the dopant impurity levels increase. Both changes reduce the carrier mobility, and hence the transconductance. As channel lengths are reduced without proportional reduction in drain voltage, raising the electric field in the channel, the result is velocity saturation of the carriers, limiting the current and the transconductance. 4.2.6 Interconnect capacitance Traditionally, switching time was roughly proportional to the gate capacitance of gates. However, with transistors becoming smaller and more transistors being placed on the chip, interconnect capacitance (the capacitance of the metal-layer connections between different parts of the chip) is becoming a large percentage of capacitance. Signals have to travel through the interconnect, which leads to increased delay and lower performance. Dept of ECE, VJCET
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3D TRANSISTORS-FINFETs 4.2.7 Heat production

Fig.4.3: Large heat sinks to cool power transistors in aTRM-800 audio amplifier.

The ever-increasing density of MOSFETs on an integrated circuit creates problems of substantial localized heat generation that can impair circuit operation. Circuits operate more slowly at high temperatures, and have reduced reliability and shorter lifetimes. Heat sinks and other cooling devices and methods are now required for many integrated circuits including microprocessors. Power MOSFETs are at risk of thermal runaway. As their on-state resistance rises with temperature, if the load is approximately a constant-current load then the power loss rises correspondingly, generating further heat. When the heat sink is not able to keep the temperature low enough, the junction temperature may rise quickly and uncontrollably, resulting in destruction of the device. 4.2.8 Process variations With MOSFETS becoming smaller, the number of atoms in the silicon that produce many of the transistor's properties is becoming fewer, with the result that control of dopant numbers and placement is more erratic. During chip manufacturing, random process variations affect all transistor dimensions: length, width, junction depths, oxide thickness etc., and become a greater percentage of overall transistor size as the transistor shrinks. The transistor characteristics become less certain, more statistical. The random nature of manufacture means we do not know which particular example MOSFETs actually will end up in a particular instance of the circuit. This uncertainty forces a less optimal design because the design must work for a great variety of possible component MOSFETs. See process variation, design for manufacturability, reliability engineering, and statistical process control.

Dept of ECE, VJCET

3D TRANSISTORS-FINFETs

CHAPTER 5 SHORT CHANNEL EFFECTS

A MOSFET device is considered to be short when the channel length is the same order of magnitude as the depletion-layer widths (xdD, xdS) of the source and drain junction. As the channel length L is reduced to increase both the operation speed and the number of components per chip, the so-called short-channel effects arise.

5.1 Various Short-Channel Effects

The short-channel effects are attributed to two physical phenomena: 1. The limitation imposed on electron drift characteristics in the channel, 2. The modification of the threshold voltage due to the shortening channel length. In particular five different short-channel effects can be distinguished: 1. Drain-induced barrier lowering and punchthrough 2. Surface scattering 3. Velocity saturation 4. Impact ionization 5. Hot electrons 5.1.1 Drain-induced barrier lowering and punchthrough The expressions for the drain and source junction widths are:

And

where VSB and VDB are source-to-body and drain-to-body voltages. When the depletion regions surrounding the drain extends to the source, so that the two depletion layer merge (i.e., when xdS + xdD = L), punchthrough occurs. Punchthrough can be minimized with thinner oxides, larger substrate doping, shallower junctions, and obviously with longer channels. Dept of ECE, VJCET
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3D TRANSISTORS-FINFETs The current flow in the channel depends on creating and sustaining an inversion layer on the surface. If the gate bias voltage is not sufficient to invert the surface (VGS<VT0), the carriers (electrons) in the channel face a potential barrier that blocks the flow. Increasing the gate voltage reduces this potential barrier and, eventually, allows the flow of carriers under the influence of the channel electric field. In small-geometry MOSFETs, the potential barrier is controlled by both the gate-to-source voltage VGS and the drain-to-source voltage VDS. If the drain voltage is increased, the potential barrier in the channel decreases, leading to drain-induced barrier lowering (DIBL). The reduction of the potential barrier eventually allows electron flow between the source and the drain, even if the gate-to-source voltage is lower than the threshold voltage. The channel current that flows under this conditions (VGS<VT0) is called the sub-threshold current. 5.1.2 Surface scattering As the channel length becomes smaller due to the lateral extension of the depletion layer into the channel region, the longitudinal electric field component y increases, and the surface mobility becomes field-dependent. Since the carrier transport in a MOSFET is confined within the narrow inversion layer, and the surface scattering (that is the collisions suffered by the electrons that are accelerated toward the interface by x) causes reduction of the mobility, the electrons move with great difficulty parallel to the interface, so that the average surface mobility, even for small values of y, is about half as much as that of the bulk mobility.

Fig.5.1: Surface scattering 5.1.3 Velocity saturation The performance short-channel devices are also affected by velocity saturation, which reduces the transconductance in the saturation mode. At low y, the electron drift velocity vde in the channel varies linearly with the electric field intensity. However, as y increases above 104 Dept of ECE, VJCET
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3D TRANSISTORS-FINFETs V/cm, the drift velocity tends to increase more slowly, and approaches a saturation value of vde(sat)=107 cm/s around y =105 V/cm at 300 K. Note that the drain current is limited by velocity saturation instead of pinch off. This occurs in short channel devices when the dimensions are scaled without lowering the bias voltages. Using vde(sat), the maximum gain possible for a MOSFET can be defined as gm WCox vde(sat) 5.1.4 Impact ionization Another undesirable short-channel effect, especially in NMOS, occurs due to the high velocity of electrons in presence of high longitudinal fields that can generate electron-hole (e-h) pairs by impact ionization, that is, by impacting on silicon atoms and ionizing them. It happens as follow: normally, most of the electrons are attracted by the drain, while the holes enter the substrate to form part of the parasitic substrate current. Moreover, the region between the source and the drain can act like the base of an npn transistor, with the source playing the role of the emitter and the drain that of the collector. If the aforementioned holes are collected by the source, and the corresponding hole current creates a voltage drop in the substrate material of the order of .6V, the normally reversed-biased substrate-source pn junction will conduct appreciably. Then electrons can be injected from the source to the substrate, similar to the injection of electrons from the emitter to the base. They can gain enough energy as they travel toward the drain to create new eh pairs. The situation can worsen if some electrons generated due to high fields escape the drain field to travel into the substrate, thereby affecting other devices on a chip. 5.1.5 Hot electrons Another problem, related to high electric fields, is caused by so-called hot electrons. These high energy electrons can enter the oxide, where they can be trapped, giving rise to oxide charging that can accumulate with time and degrade the device performance by increasing VT and affect adversely the gates control on the drain current.

Fig.5.2: Hot Electrons Dept of ECE, VJCET

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3D TRANSISTORS-FINFETs

CHAPTER 6 INTRODUCTION TO DOUBLE GATE CMOS

Innovative device architectures will be necessary to continue the benefits that previously acquired through rote scaling. Double-gate CMOS (DGCMOS) offers distinct advantages for scaling to very short gate lengths. Furthermore, adoption of gate dielectrics with permittivity substantially greater than that of SiO2 (so-called high-k materials) may be deferred if a DGCMOS architecture is employed. Previously, serious structural challenges have made adoption of DGCMOS architecture untenable. Recently, through use of the delta device, now commonly referred to as the FinFET, significant advances in DGCMOS device technology and performance have been demonstrated. Fabrication in FinFET-DGCMOS is very close to that of conventional CMOS process, with only minor disruptions, offering the potential for a rapid deployment to manufacturing. Planar product designs have been converted to FinFET DGCMOS without disruption to the physical area, thereby demonstrating its compatibility with todays planar CMOS design methodology and automation techniques.

6.1 Overcoming Obstacles By Doubling Up

CMOS technology scaling has traversed many anticipated barriers over the past 20 years to rapidly progress from 2 m to 90nm rules. Currently, two obstacles, namely subthreshold and gate-dielectric leakages, have become the dominant barrier for further CMOS scaling, even for highly leakage-tolerant applications such as microprocessors. Double-gate (DG) FETs, in which a second gate is added opposite the traditional (first) gate, have better control over short-channel effects [SCEs]. SCE limits the minimum channel length at which an FET is electrically well behaved.

Fig.6.1: Schematically illustrates the advantage of DG-FETs. Dept of ECE, VJCET

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3D TRANSISTORS-FINFETs As the channel length of an FET is reduced, the drain potential begins to strongly influence the channel potential, leading to an inability to shut off the channel current with the gate. This short-channel effect is mitigated by use of thin gate oxide (to increase the influence of the gate on the channel) and thin depletion depth below the channel to the substrate, to shield the channel from the drain. Gate oxide thickness has been reduced to the point where, at 90 nm CMOS, the power drain from gate leakage is comparable to the power used for switching of circuits. Thus, further reduction of the thickness would lead to unreasonable power increases. Alternatively, further decrease of the depletion region XD degrades gate influence on the channel and leads to a slower turn on of the channel region. In DG-FETs, the longitudinal electric field generated by the drain is better screened from the source end of the channel due to proximity to the channel of the second gate, resulting in reduced short-channel effects, in particular, reduced drain induced- barrier lowering (DIBL) and improved subthreshold swing (S). Therefore, as CMOS scaling becomes limited by leakage currents, DGCMOS offers the opportunity to proceed beyond the performance of single-gate (SG) bulk-silicon or PDSOI CMOS. Both the DIBL and subthreshold swing for the DG device are dramatically improved relative to those of the bulk-silicon counterpart. From a bulk-silicon device design perspective, increased body doping concentration could be employed to reduce DIBL; however, at some point it would also increase the subthreshold swing, thereby requiring higher threshold voltage VT to keep the subthreshold current adequately low.

Fig.6.2: V-I characteristics of DG and Bulk (SG) MOSFETS

Dept of ECE, VJCET

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3D TRANSISTORS-FINFETs Similarly, decreasing the body doping concentration could improve the subthreshold swing but degrade DIBL. Hence a compromise is necessary for the bulk-silicon device design In Fig.6.2, simulations of the IDSVGS characteristics of DG and SG FETs shows the steeper turn on of the DG-FET, which results from the gate coupling advantage. This property enables the use of lower threshold voltage for the DG-FET for a given off-current. As a direct result, higher drive currents at lower power-supply voltages VDD are attainable.

6.2 Double Gate Threshold Voltage

The very thin silicon body associated with fully depleted DG-FETs suggests that the centering of VT could be a challenging proposition. Three basic techniques have been explored both theoretically and experimentally, namely, use of body doping, use of asymmetric gate work function, and use of symmetric mid-gap work-function gate-electrodes. Adequate body doping can be achieved by directly doping the silicon body or by use of halo (also known as pocket) ion implants introduced laterally from the gate edges, or a combination of these two techniques. One technique uniquely available to DG- FETs is the use of asymmetric gates, wherein the two gate electrodes are of materials of differing work functions. Body doping has been the technique of choice for VT centering in both bulk and PD-SOI planar CMOS technologies. Adequate body doping can be achieved by directly doping the silicon body or by use of halo ion implants introduced laterally from the gate edges, or a combination of these two techniques. Metal gates offer the possibility of centering threshold voltage with a single work function for both gate electrodes without relying on body doping. Many metals with work functions near the middle of the silicon band gap exist. Use of these metals in SG-FETs is problematic since the VT of such devices is typically above 0.5 V, which is too high for most CMOS applications. Lower VT may be achieved by counter-doping the body, which results in buried conduction channels in the off-state, thus degrading short channel effects. Metal gates on DG-FETs, on the other hand, naturally achieve the VTs in the vicinity of 0.2 V (the exact value depending on the details) and good short channel characteristics. Dept of ECE, VJCET
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6.3 Double gate taxonomy

6.3.1 Type I, the Planar DG-FET: This is a direct extension of a planar CMOS process with a second, buried gate

Fig.6.3: Type I, the Planar DG-FET

6.3.2 Type II, the Vertical DGFET: Here the silicon body has been rotated to a vertical orientation on the silicon wafer with the source and drain on the top and bottom boundaries of the body, and the gates on either side.

Fig.6.4: Type II, the Vertical DGFET

6.3.3 Type III, the Non Planar DG-FET (FinFET): In FinFET the silicon body has been rotated on its edge into a vertical orientation so only the source and drain regions are placed horizontally about the body, as in a conventional planar FET. Referred to as FinFET as the silicon resembles the dorsal fin of a fish.

Fig.6.5: Type III, the Non Planar DG-FET (FinFET) Dept of ECE, VJCET
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3D TRANSISTORS-FINFETs

CHAPTER 7 FINFET
Type 3 DG-FETs are called FinFETs. Even though current conduction is in the plane of the wafer, it is not strictly a planar device. Rather, it is referred to as a quasi-planar device, because its geometry in the vertical direction (viz. the fin height) also affects device behavior. Amongst the DG-FET types, the FinFET is the easiest one to fabricate. Its schematic is shown in Fig.15

Fig.7.1: Structure of a FinFET

Because of the vertically thin channel structure, it is referred to as a fin because it resembles a fishs fin; hence the name FinFET. A gate can also be fabricated at the top of the fin, in which case it is a triple gate FET. Or optionally, the oxide above the fin can be made thick enough so that the gate above the fin is as good as not being present. (This helps in reducing corner effects, discussed later in this report) It should be noted that while the gate length L of a

Dept of ECE, VJCET

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3D TRANSISTORS-FINFETs FinFET is in the same sense as that in a conventional planar FET, the device width W is quite different. W is defined as:
W 2 H fin T fin

where Hfin and Tfin are the fin height and thickness respectively (see Fig.15 above. Some literature refers to the fin thickness as the fin width). The reason for this is quite clear when one notices that W as defined above is indeed the width of the gate region that is in touch with (ie. in control of) the channel in the fin (albeit with a dielectric in between). This fact can especially be seen if one unfolds the gate (ie. unwraps it).The above definition of device width is for a triple gate FinFET. If the gate above the fin is absent/ineffective, then the Tfin term in the above definition is taken out. On the surface, this freedom in the vertical direction (of increasing H fin) is a much desired capability since it lets one increase the device width W without increasing the planar layout area. (Increasing W increases the Ion, a desirable feature). However, it will be seen in subsequent sections in this report, that there is a definite range (in relation to Tfin) beyond which Hfin should not be increased, else one encounters SCE.

7.1 Features of FinFET

Finfet consists of a vertical Si fin controlled by self aligned double gate. Main Features of Finfet are, 1) Ultra thin Si fin for suppression of short channel effects. 2) Raised source/drain to reduce parasitic resistance and improve current drive. 3) Gate last process with low T, high k gate dielectrics. 4) Symmetric gates yield great performance, but can built asymmetric gates that target VT. Finfets are designed to use multiple fins to achieve larger channel widths. Source/Drain pads connect the fins in parallel. As the number of fins is increased, the current through the device increases. For e.g.: A 5 fin device 5 times more current than single fin device.

Dept of ECE, VJCET

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7.2 FinFET fabrication process

The key challenges in FinFET fabrication are the thin, uniform fin; and also in reducing the source-drain series resistance. Finfets have broadly been reported to be fabricated in 2 ways: Gate-first process: Here the gate stack is patterned/formed first, and then the source and drain regions are formed Gate-last process (also called replacement gate process): Here source and drain regions are formed first and then the gate is formed

Fig.7.2: High level FinFET fabrication steps; (a-b): Gate-first process, (c-f): Gate last process Dept of ECE, VJCET
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3D TRANSISTORS-FINFETs FinFETs are usually fabricated on an SOI substrate. It starts by patterning and etching thin fins on the SOI wafer using a hard mask. The hard mask is retained throughout the process to protect the fin. The fin thickness is typically half or one third the gate length, so it is a very small dimension. It is made by either e-beam lithography or by optical lithography using extensive linewidth trimming. In the gate-first process, fabrication steps after the fin formation are similar to that in a conventional bulk MOSFET process. In the gate-last process, the source/drain is formed immediately after fin patterning. To protect the fin while forming the other regions, doped poly or poly SiGe or even doped amorphous Silicon is deposited on the fin. Then the S/D fan-out pads are patterned, leaving a thin slot between the source and the drain. This distance determines the gate length, which can be further reduced using a dielectric sidewall spacer. Finally the gate oxide is grown and the gate material is deposited and patterned.

Fig.7.3: The sidewall image transfer (SIT) technique Dept of ECE, VJCET
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3D TRANSISTORS-FINFETs To create thin fins very close to each other, the sidewall image transfer (SIT) technique can be used. This technique can help obtain a fin pitch that is half the lithography pitch, which is desirable because: It improves device layout density (done by creating very close fins and using a trim level to break the gate continuity, thus separating devices), and It enables having the fin pitch smaller than the fin height, which is desirable because it make the FinFET have a greater effective device width than a planar conventional FET.

7.3 Recent Fabrication efforts on FinFETs

Ultra thin fins result in reduced SCE, but increased series resistance. So a fine balance has to be achieved between the two goals. Also, the fabrication process has to be easily integrateable into conventional CMOS process to the extent possible. Keeping such considerations in mind and others, there have been many efforts to fabricate and characterize FinFETs. Some of them are listed below. Hisamoto et al reported a gate-last process where they made FinFETs with10nm thick and 50nm tall fins, and 30nm gate length. The fins were patterned using e-beam lithography. The gate material was boron-doped Si0.4Ge0.6, which has the advantage that it is compatible with poly-Si process and its work function is continuously controllable by the mole fraction of Ge. Boron-doped Si0.4Ge0.6 results in a mid-gap work function. The gate was self-aligned to S/D, which was a raised source drain (RSD) structure to reduce series resistance. As was reported, a S/D first, gate-last process can be advantageous when used with a high-k gate dielectric, which mostly have thermal stability issues. Using a gate-first process, Collaert, et al fabricated FinFETs having (poly, not metal) gate lengths (Lpoly) of 25nm for nFETs and 35nm for pFETs, with 60-80nm tall fins, each being 10nm thick with a 1.6nm gate oxide EOT. The fins were patterned using e-beam lithography. The wafers underwent a H2 anneal to smoothen the fin surface and a 15nm oxidation to round the corners (more on corner effects later in this report). Selective epitaxy to create RSD was not used just to simplify the fabrication process, even though they would have lowered the series resistance. Dept of ECE, VJCET
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3D TRANSISTORS-FINFETs Kedzierski, et al also fabricated a FinFET using a gate-first process where they made symmetric as well as asymmetric FinFETs. Polysilicon gates were used. The symmetric FinFETs were smaller and had dimensions of Lpoly=60nm (Leff = 30nm), Tfin=10nm and Hfin=65nm. The thin fin was fabricated using optical lithography and a hard mask trimming technique, whose further details are unavailable. The asymmetric FinFETs had p+ and n+ poly gates. They were realizable using gate implant shadowing, because they had a taller 120nm fin. Selective epitaxy was used to create RSD to create devices with low series resistance. Fig.7.4 and Fig.7.5 show the Id-Vg curves obtained.

Fig.7.4: Id-Vg plot of asymmetric FinFETs

Fig.7.5: Id-Vg plot of symmetric FinFETs

7.4 Effects due to imperfections in fabrication

There are basically three reasons for the adverse effects on the performance characteristics of the FinFETs due to improper fabrication as follows: a) non vertical fin side wall b) corner effects c) channel width quantization problem 7.4.1 Effect of non-vertical fin sidewall The fabrication of the uniform, ultra thin fin is one of the key challenges in FinFET fabrication. Due to non ideal anisotropic over etch, the fins can end up having a slightly Dept of ECE, VJCET
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3D TRANSISTORS-FINFETs triangular or trapezoidal shape. Concave and convex surfaces can also end up during the reactive ion etching (RIE) process. In, Wu et al assumed a trapezoidal shape and studied the effect of the various parameters of the trapezoid (slope of the sidewall, fin height, etc) on the subthreshold slope S and VT rolloff, using 3D device simulations. Assuming a constant top thickness (of the fin), S and VT rolloff worsens as the fin height is increased. This is because the thickness at the bottom increases, resulting in worsened SCE. It was reported that more than 50% profit from suppression of SCE can be gained, if the sidewall angle (w.r.t. horizontal) is controlled between 75 to 85. 7.4.2 Corner effects In ultra thin triple gate (TG) FinFETs with a doped fin, the corners of the fin get inverted before the sidewalls of the fin get inverted. This is because the corners are under the influence of 2 gates (the top gate and one of the sidewall gates). This also makes the corners turn off later, as the gate voltage is ramped down. As a result, there is increased subthreshold leakage at the corners. There have been many efforts to study these corner effects and see how they can be minimized. The unanimous conclusion in all these efforts has been that to minimize these corner effects, we need FinFETs with: Undoped fins Metal gates with appropriate work function for VT control Corners of fins should be rounded as much as possible (i.e. not sharp) In the papers reviewed, it wasnt categorically mentioned but it is felt (by the author of the current report) that corner effects can also be minimized if double gate FinFETs were used (ie. make the gate oxide over the fin very thick). Simulations were done, where devices with identical top and bottom corner radii as well as different top and bottom corner radii were considered. The device cross sections considered are shown in Fig.7.6. The gate material was N+ polysilicon with a ms = -0.9V. The fin was therefore highly doped in order to get a workable threshold voltage. The fin thickness T fin (shown as W in Fig.7.6) was 30nm, and the gate oxide thickness was 2nm. Simulations were done as the doping was varied from 1018 to 5x1018 cm-3. It was found that corner effects degrade Dept of ECE, VJCET
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3D TRANSISTORS-FINFETs the subthreshold slope S when the fin doping is increased and/or the radius of curvature of the corners is low (ie. sharp curvature).

Fig.7.6: Corner effects 7.4.3 Channel width quantization problem Because Weff varies in integral multiples of 2HFin + TFin, FinFET circuits inherently have a device width quantization problem. To illustrate this, suppose HFin and TFin are 30nm and 10nm respectively. Thus, Weff can be 70nm, 140nm, 210nm, etc. This renders it hard to get W/L ratios of say, 2.5 between 2 devices (eg. pFET and nFET in an inverter are usually sized such, to account for the mobility differences, in order to get equal rise/fall times). It is not clear how this is tackled in the literature. To cater to the cases where the fractional W/L ratio requirements are simply due to mobility differences as in the above example, there have been unpublished proposals to lighten this requirement by enhancing the mobility of pFETs in an alternate way, such as fabricating them in a <110> direction. Another way to solve the problem is to increase the gate length, which is lithographically controlled and hence doable. However this potentially reverses the benefits of shrinking.

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CHAPTER 8 APPLICATIONS OF FINFETs

DG devices like Fin FETs offer unique opportunities for microprocessor design. Compared to a planar process in the same technology node, FinFETs have reduced channel and gate leakage currents. This can lead to considerable power reductions when converting a planar design to FinFET technology. Utilizing FinFETs would lead to a reduction in total power by a factor of two, without compromising performance. Another possibility to save power arises when both gates can be controlled separately. The second gate can be used to control the threshold voltage of the device, thereby allowing fast switching on one side and reduced leakage currents when circuits are idle. Finally, separate access to both gates could also be used to design simplified logic gates. This would also reduce power, and save chip area, leading to smaller, more cost-efficient designs. However chip designs using FinFETs must cope with quantization of device width, since every single transistor consists of an integral number of fins, each fin having the same height. Recently Intel has put forth a new generation of microprocessors codenamed the Ivy Bridge which incorporates 22nm FinFET technology. These new generation chips are claimed to be 50% more power efficient and 37% faster than its 35nm predecessor, the Sandy Bridge which is based on the traditional MOSFET technology.

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3D TRANSISTORS-FINFETs

CHAPTER 9
CONCLUSION FinFETs appear to be the device of choice in sub-50nm designs, because of their reduced short channel effects (SCE) and relative ease of integration into existing fabrication processes. They seem well suited to help us stay on track with Moores law, for a little while longer. A gate-first method of fabricating FinFETs is advantageous in that it is more akin to the conventional CMOS process. This is probably the reason why there is more literature on this method. On the other hand, a gate-last method of fabricating FinFETs is advantageous from a thermal stability point of view when introducing metal gates and high-k gate dielectrics. Tall, thin fins help minimize SCE, but tend to increase series resistance. For best SCE, keeping manufacturability in mind, the ideal dimensions reported are a fin thickness of one third the channel length. Tall fin heights are desirable because they yield higher ON currents (increased Weff), but it gets more difficult to manufacture them with uniformly steep sidewalls. So a fine balance needs to be struck. FinFETs need to be used with metal gates with appropriate work function, for yielding desired VT. Also, undoped fins need to be used to minimize corner effects Fabrication techniques need to be improved to create thin fins with uniform thickness (uniformity across devices) as well as smooth, vertical sidewalls. These are necessary for consistent and high ON currents.

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3D TRANSISTORS-FINFETs

REFERENCES
1. Burenkov and J. Lorenz , Corner Effect in Double and Triple Gate FinFETs, ESSDERC 2003, pp. 135-138 2. P.M. Solomon et al, Two Gates are better than one, IEEE Circuits and Devices Magazine, Jan 2003, pp. 48-62 3. Xusheng Wu et al, Impact of Non-Vertical Sidewall on Sub-50nm FinFET, SOIC 2003, pp. 151-152 4. Gen Pei et al, FinFET Design Considerations Based on 3-D Simulation and Analytical Modeling, IEEE Trans. Electron Devices, vol. 49, pp. 1411-1419, Aug 2002 5. H.-S.P Wong, Beyond the conventional transistor, IBM Journal of Research and Development (http://www.research.ibm.com/journal/rd/462/wong.html) 6. http://en.wikipedia.org/wiki/FinFET#FinFETs 7. http://en.wikipedia.org/wiki/MOSFET#MOSFET_scaling 8. Dr.Chenmin Hus video presentation on FinFETs,www.synopsis.com.

Dept of ECE, VJCET