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Documenti di Cultura
Document ID: 1MRK 502 027-UUS Issued: December 2012 Revision: A Product version: 1.2
Copyright
This document and parts thereof must not be reproduced or copied without written permission from ABB, and the contents thereof must not be imparted to a third party, nor used for any unauthorized purpose. The software and hardware described in this document is furnished under a license and may be used or disclosed only in accordance with the terms of such license.
Trademarks
ABB and Relion are registered trademarks of the ABB Group. All other brand or product names mentioned in this document may be trademarks or registered trademarks of their respective holders.
Warranty
Please inquire about the terms of warranty from your nearest ABB representative.
ABB Inc. 1021 Main Campus Drive Raleigh, NC 27606, USA Toll Free: 1-800-HELP-365, menu option #8
ABB Inc. 3450 Harvester Road Burlington, ON L7N 3W5, Canada Toll Free: 1-800-HELP-365, menu option #8
ABB Mexico S.A. de C.V. Paseo de las Americas No. 31 Lomas Verdes 3a secc. 53125, Naucalpan, Estado De Mexico, MEXICO Phone: (+1) 440-585-7804, menu option #8
Disclaimer
The data, examples and diagrams in this manual are included solely for the concept or product description and are not to be deemed as a statement of guaranteed properties. All persons responsible for applying the equipment addressed in this manual must satisfy themselves that each intended application is suitable and acceptable, including that any applicable safety or other operational requirements are complied with. In particular, any risks in applications where a system failure and/or product failure would create a risk for harm to property or persons (including but not limited to personal injuries or death) shall be the sole responsibility of the person or entity applying the equipment, and those so responsible are hereby requested to ensure that all measures are taken to exclude or mitigate such risks. This document has been carefully checked by ABB but deviations cannot be completely ruled out. In case any errors are detected, the reader is kindly requested to notify the manufacturer. Other than under explicit contractual commitments, in no event shall ABB be responsible or liable for any loss or damage resulting from the use of this manual or the application of the equipment.
Conformity
This product complies with the directive of the Council of the European Communities on the approximation of the laws of the Member States relating to electromagnetic compatibility (EMC Directive 2004/108/EC) and concerning electrical equipment for use within specified voltage limits (Low-voltage directive 2006/95/EC). This conformity is the result of tests conducted by ABB in accordance with the product standards EN 50263 and EN 60255-26 for the EMC directive, and with the product standards EN 60255-1 and EN 60255-27 for the low voltage directive. The product is designed in accordance with the international standards of the IEC 60255 series and ANSI C37.90.
Table of contents
Table of contents
Section 1 Introduction..........................................................................27
Introduction to the technical reference manual.......................................27 About the complete set of manuals for an IED..................................27 About the technical reference manual...............................................28 This manual.......................................................................................29 Introduction...................................................................................29 Principle of operation....................................................................29 Input and output signals...............................................................33 Function block..............................................................................33 Setting parameters.......................................................................34 Technical data..............................................................................34 Intended audience.............................................................................34 Related documents............................................................................34 Revision notes...................................................................................35
Section 2
Analog inputs.......................................................................37
Introduction.............................................................................................37 Operation principle..................................................................................37 Function block.........................................................................................38 Setting parameters.................................................................................39
Section 3
Local HMI............................................................................47
Human machine interface ......................................................................47 Medium size graphic HMI.......................................................................48 Medium..............................................................................................48 Design................................................................................................49 Keypad....................................................................................................51 LED.........................................................................................................52 Introduction........................................................................................52 Status indication LEDs......................................................................52 Indication LEDs.................................................................................53 Local HMI related functions....................................................................54 Introduction........................................................................................54 General setting parameters...............................................................54 Status LEDs.......................................................................................54 Design..........................................................................................54
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Function block..............................................................................55 Input and output signals...............................................................55 Indication LEDs.................................................................................55 Introduction...................................................................................55 Design..........................................................................................56 Function block..............................................................................64 Input and output signals...............................................................64 Setting parameters.......................................................................65
Section 4
Table of contents
Principle of operation.........................................................................92 Function block...................................................................................93 Input and output signals....................................................................93 Setting parameters............................................................................93 Test mode functionality TEST.................................................................93 Introduction........................................................................................93 Principle of operation.........................................................................94 Function block...................................................................................96 Input and output signals....................................................................96 Setting parameters............................................................................96 IED identifiers.........................................................................................97 Introduction........................................................................................97 Setting parameters............................................................................97 Product information.................................................................................97 Introduction........................................................................................97 Setting parameters............................................................................98 Factory defined settings....................................................................98 Signal matrix for binary inputs SMBI.......................................................98 Introduction........................................................................................98 Principle of operation.........................................................................99 Function block...................................................................................99 Input and output signals....................................................................99 Signal matrix for binary outputs SMBO ................................................100 Introduction......................................................................................100 Principle of operation.......................................................................100 Function block.................................................................................101 Input and output signals..................................................................101 Signal matrix for mA inputs SMMI........................................................101 Introduction......................................................................................101 Principle of operation.......................................................................102 Function block.................................................................................102 Input and output signals..................................................................102 Signal matrix for analog inputs SMAI....................................................103 Introduction......................................................................................103 Principle of operation.......................................................................103 Frequency values............................................................................103 Function block.................................................................................105 Input and output signals..................................................................105 Setting parameters..........................................................................106 Summation block 3 phase 3PHSUM....................................................108
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Introduction......................................................................................108 Principle of operation.......................................................................108 Function block.................................................................................109 Input and output signals..................................................................109 Setting parameters..........................................................................109 Authority status ATHSTAT....................................................................110 Introduction......................................................................................110 Principle of operation.......................................................................110 Function block.................................................................................111 Output signals..................................................................................111 Setting parameters..........................................................................111 Denial of service DOS..........................................................................111 Introduction......................................................................................111 Principle of operation.......................................................................111 Function blocks................................................................................112 Signals.............................................................................................112 Settings............................................................................................113
Section 5
Differential protection........................................................115
Generator differential protection GENPDIF (87G)................................115 Introduction......................................................................................115 Principle of operation.......................................................................116 Function calculation principles....................................................117 Fundamental frequency differential currents..............................117 Supplementary criteria................................................................122 Harmonic restrain.......................................................................125 Cross-block logic scheme...........................................................125 Function block.................................................................................129 Input and output signals..................................................................129 Setting parameters..........................................................................130 Technical data.................................................................................132 Transformer differential protection T2WPDIF (87T) and T3WPDIF (87T).....................................................................................................132 Introduction .....................................................................................133 Principle of operation.......................................................................135 Function calculation principles....................................................137 Logic diagram.............................................................................161 Function block.................................................................................167 Input and output signals..................................................................168 Setting parameters..........................................................................172
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Technical data.................................................................................177 Restricted earth-fault protection, low impedance REFPDIF (87N).......178 Introduction......................................................................................178 Operation principle..........................................................................179 Fundamental principles of the restricted groundfault protection....................................................................................179 Restricted earth-fault protection, low impedance differential protection....................................................................................182 Calculation of differential current and bias current.....................183 Detection of external ground faults.............................................184 Algorithm of the restricted ground fault protection......................186 Function block.................................................................................187 Input and output signals..................................................................188 Setting parameters..........................................................................188 Technical data.................................................................................189 1Ph High impedance differential protection HZPDIF (87).....................189 Identification....................................................................................190 Introduction......................................................................................190 Principle of operation.......................................................................190 Logic diagram.............................................................................190 Function block.................................................................................191 Input and output signals..................................................................191 Setting parameters..........................................................................192 Technical data.................................................................................192
Section 6
Table of contents
Introduction......................................................................................214 Principle of operation.......................................................................214 Directional impedance element for mho characteristic ZDMRDIR (21D).........................................................................214 Function block.................................................................................217 Input and output signals..................................................................218 Setting parameters..........................................................................218 Pole slip protection PSPPPAM (78)......................................................218 Introduction......................................................................................219 Principle of operation.......................................................................220 Function block.................................................................................225 Input and output signals..................................................................225 Setting parameters..........................................................................226 Technical data.................................................................................227 Loss of excitation LEXPDIS(40)...........................................................227 Introduction......................................................................................227 Principle of operation.......................................................................228 Function block.................................................................................232 Input and output signals..................................................................233 Setting parameters..........................................................................233 Technical data.................................................................................234 Sensitive rotor earth fault protection, injection based ROTIPHIZ (64R).....................................................................................................235 Introduction......................................................................................235 Principle of operation.......................................................................235 The injection unit REX060..........................................................237 Rotor Earth Fault Protection function.........................................238 General measurement of ground fault impedance.....................239 Simplified logic diagram..............................................................241 Commissioning tool ICT.............................................................243 Description of input signals..............................................................246 Description of output signals...........................................................246 Function block.................................................................................248 Input and output signals..................................................................249 Setting parameters..........................................................................250 Technical data.................................................................................251 100% stator earth fault protection, injection based STTIPHIZ (64S).....................................................................................................251 Introduction......................................................................................251 Principle of operation.......................................................................252
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Configuration principle................................................................252 Generator system grounding methods.......................................255 100% Stator earth fault protection function................................259 General measurement of ground fault impedance.....................264 Measuring reference impedance................................................266 Simplified logic diagram..............................................................270 The commissioning tool ICT.......................................................271 Description of input signals..............................................................273 Description of output signals...........................................................274 Function block.................................................................................276 Input and Output signals..................................................................276 Setting parameters..........................................................................277 Technical data.................................................................................278
Section 7
Current protection..............................................................279
Instantaneous phase overcurrent protection 3-phase output PHPIOC (50).........................................................................................279 Introduction......................................................................................279 Principle of operation.......................................................................279 Function block.................................................................................280 Input and output signals..................................................................280 Setting parameters..........................................................................281 Technical data.................................................................................281 Four step phase overcurrent protection OC4PTOC (51/67).................281 Introduction......................................................................................282 Principle of operation.......................................................................282 Function block.................................................................................288 Input and output signals..................................................................288 Setting parameters..........................................................................290 Technical data.................................................................................295 Instantaneous residual overcurrent protection EFPIOC (50N).............296 Introduction......................................................................................296 Principle of operation.......................................................................296 Function block.................................................................................297 Input and output signals..................................................................297 Setting parameters..........................................................................298 Technical data.................................................................................298 Four step residual overcurrent protection, zero, negative sequence direction EF4PTOC (51N/67N).............................................................298 Introduction......................................................................................299
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Principle of operation.......................................................................299 Operating quantity within the function........................................300 Internal polarizing.......................................................................301 External polarizing for ground-fault function...............................303 Base quantities within the protection..........................................303 Internal ground-fault protection structure....................................303 Four residual overcurrent steps..................................................304 Directional supervision element with integrated directional comparison function...................................................................305 Second harmonic blocking element............................................308 Switch on to fault feature............................................................309 Function block.................................................................................311 Input and output signals..................................................................312 Setting parameters..........................................................................313 Technical data.................................................................................318 Four step directional negative phase sequence overcurrent protection NS4PTOC (46I2)..................................................................319 Introduction......................................................................................319 Principle of operation.......................................................................320 Operating quantity within the function........................................320 Internal polarizing facility of the function.....................................321 External polarizing for negative sequence function....................322 Base quantities within the function.............................................322 Internal negative sequence protection structure.........................322 Four negative sequence overcurrent stages..............................322 Directional supervision element with integrated directional comparison function...................................................................324 Function block.................................................................................327 Input and output signals..................................................................327 Setting parameters..........................................................................328 Technical data.................................................................................333 Sensitive directional residual overcurrent and power protection SDEPSDE (67N)...................................................................................334 Introduction......................................................................................334 Principle of operation.......................................................................335 Function inputs...........................................................................335 Function block.................................................................................342 Input and output signals..................................................................342 Setting parameters..........................................................................343 Technical data.................................................................................345
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Thermal overload protection, two time constants TRPTTR (49)...........346 Introduction......................................................................................346 Principle of operation.......................................................................347 Function block.................................................................................351 Input and output signals..................................................................351 Setting parameters..........................................................................352 Technical data.................................................................................353 Breaker failure protection CCRBRF (50BF)..........................................353 Introduction......................................................................................353 Principle of operation.......................................................................354 Function block.................................................................................357 Input and output signals..................................................................357 Setting parameters..........................................................................358 Technical data.................................................................................358 Pole discrepancy protection CCRPLD (52PD).....................................359 Introduction......................................................................................359 Principle of operation.......................................................................359 Pole discrepancy signaling from circuit breaker.........................362 Unsymmetrical current detection................................................362 Function block.................................................................................363 Input and output signals..................................................................363 Setting parameters..........................................................................364 Technical data.................................................................................364 Directional underpower protection GUPPDUP (37)..............................364 Introduction......................................................................................365 Principle of operation.......................................................................366 Low pass filtering........................................................................368 Calibration of analog inputs........................................................368 Function block.................................................................................370 Input and output signals..................................................................370 Setting parameters..........................................................................371 Technical data.................................................................................372 Directional overpower protection GOPPDOP (32)................................372 Introduction......................................................................................373 Principle of operation.......................................................................374 Low pass filtering........................................................................376 Calibration of analog inputs........................................................376 Function block.................................................................................378 Input and output signals..................................................................378 Setting parameters..........................................................................379
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Technical data.................................................................................380 Negativ sequence time overcurrent protection for machines NS2PTOC (46I2)..................................................................................380 Introduction......................................................................................381 Principle of operation.......................................................................381 Pickup sensitivity........................................................................384 Alarm function.............................................................................384 Logic diagram.............................................................................384 Function block.................................................................................385 Input and output signals..................................................................385 Setting parameters..........................................................................386 Technical data.................................................................................387 Accidental energizing protection for synchronous generator AEGGAPC (50AE)................................................................................388 Introduction .....................................................................................388 Principle of operation.......................................................................388 Function block.................................................................................389 Input and output signals..................................................................389 Setting parameters..........................................................................390 Technical data.................................................................................390
Section 8
Voltage protection.............................................................393
Two step undervoltage protection UV2PTUV (27)................................393 Introduction......................................................................................393 Principle of operation.......................................................................393 Measurement principle...............................................................394 Time delay..................................................................................394 Blocking......................................................................................400 Design........................................................................................401 Function block.................................................................................403 Input and output signals..................................................................403 Setting parameters..........................................................................404 Technical data.................................................................................406 Two step overvoltage protection OV2PTOV (59).................................407 Introduction......................................................................................407 Principle of operation.......................................................................407 Measurement principle...............................................................408 Time delay..................................................................................409 Blocking......................................................................................414 Design........................................................................................414
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Function block.................................................................................416 Input and output signals..................................................................416 Setting parameters..........................................................................417 Technical data.................................................................................419 Two step residual overvoltage protection ROV2PTOV (59N)...............420 Introduction......................................................................................420 Principle of operation.......................................................................420 Measurement principle...............................................................421 Time delay..................................................................................421 Blocking......................................................................................426 Design........................................................................................426 Function block.................................................................................427 Input and output signals..................................................................428 Setting parameters..........................................................................428 Technical data.................................................................................430 Overexcitation protection OEXPVPH (24)............................................431 Introduction......................................................................................431 Principle of operation.......................................................................431 Measured voltage.......................................................................434 Operate time of the overexcitation protection.............................435 Cooling.......................................................................................439 Overexcitation protection function measurands.........................439 Overexcitation alarm...................................................................440 Logic diagram.............................................................................441 Function block.................................................................................441 Input and output signals..................................................................442 Setting parameters..........................................................................442 Technical data.................................................................................443 Voltage differential protection VDCPTOV (60).....................................444 Introduction......................................................................................444 Principle of operation.......................................................................444 Function block.................................................................................446 Input and output signals..................................................................446 Setting parameters..........................................................................447 Technical data.................................................................................447 100% Stator ground fault protection, 3rd harmonic based STEFPHIZ (59THD)..............................................................................448 Introduction......................................................................................448 Principle of operation.......................................................................449 Function block.................................................................................455
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Section 9
Frequency protection.........................................................459
Underfrequency protection SAPTUF (81).............................................459 Introduction......................................................................................459 Principle of operation.......................................................................459 Measurement principle...............................................................460 Time delay..................................................................................460 Voltage dependent time delay....................................................461 Blocking......................................................................................462 Design........................................................................................462 Function block.................................................................................463 Input and output signals..................................................................463 Setting parameters..........................................................................464 Technical data.................................................................................465 Overfrequency protection SAPTOF (81)...............................................465 Introduction......................................................................................466 Principle of operation.......................................................................466 Measurement principle...............................................................466 Time delay..................................................................................466 Blocking......................................................................................467 Design........................................................................................467 Function block.................................................................................468 Input and output signals..................................................................468 Setting parameters..........................................................................469 Technical data.................................................................................469 Rate-of-change frequency protection SAPFRC (81)............................469 Introduction......................................................................................470 Principle of operation.......................................................................470 Measurement principle...............................................................470 Time delay..................................................................................471 Blocking......................................................................................471 Design........................................................................................471 Function block.................................................................................473 Input and output signals..................................................................473 Setting parameters..........................................................................473 Technical data.................................................................................474
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General current and voltage protection CVGAPC................................475 Introduction......................................................................................475 Inadvertent generator energization.............................................476 Principle of operation.......................................................................476 Measured quantities within CVGAPC.........................................476 Base quantities for CVGAPC function........................................479 Built-in overcurrent protection steps...........................................479 Built-in undercurrent protection steps.........................................485 Built-in overvoltage protection steps...........................................486 Built-in undervoltage protection steps........................................486 Inadvertent generator energizing................................................486 Logic diagram.............................................................................488 Function block.................................................................................493 Input and output signals..................................................................494 Setting parameters..........................................................................495 Technical data.................................................................................503 Rotor ground fault protection (64R)......................................................505 Introduction......................................................................................505 Principle of operation.......................................................................506 Rotor ground fault.......................................................................506 Technical data.................................................................................510
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Technical data.................................................................................527
Section 12 Control...............................................................................529
Synchronism check, energizing check, and synchronizing SESRSYN (25).....................................................................................529 Introduction......................................................................................529 Principle of operation.......................................................................530 Basic functionality.......................................................................530 Logic diagrams...........................................................................530 Function block.................................................................................540 Input and output signals..................................................................541 Setting parameters..........................................................................543 Technical data.................................................................................546 Apparatus control APC.........................................................................547 Introduction......................................................................................547 Principle of operation.......................................................................547 Error handling..................................................................................548 Bay control QCBAY.........................................................................550 Introduction.................................................................................550 Principle of operation..................................................................550 Function block............................................................................552 Input and output signals.............................................................552 Setting parameters.....................................................................553 Local/Remote switch LOCREM, LOCREMCTRL............................553 Introduction.................................................................................553 Principle of operation..................................................................553 Function block............................................................................555 Input and output signals.............................................................555 Setting parameters.....................................................................556 Switch controller SCSWI..................................................................557 Introduction.................................................................................557 Principle of operation..................................................................557 Function block............................................................................562 Input and output signals.............................................................562 Setting parameters.....................................................................564 Circuit breaker SXCBR....................................................................564 Introduction.................................................................................564 Principle of operation..................................................................564 Function block............................................................................569 Input and output signals.............................................................569
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Setting parameters.....................................................................570 Circuit switch SXSWI.......................................................................570 Introduction.................................................................................570 Principle of operation..................................................................571 Function block............................................................................575 Input and output signals.............................................................575 Setting parameters.....................................................................576 Bay reserve QCRSV........................................................................576 Introduction.................................................................................576 Principle of operation..................................................................577 Function block............................................................................579 Input and output signals.............................................................580 Setting parameters.....................................................................581 Reservation input RESIN.................................................................581 Introduction.................................................................................581 Principle of operation..................................................................581 Function block............................................................................583 Input and output signals.............................................................584 Setting parameters.....................................................................585 Interlocking (3)......................................................................................585 Introduction......................................................................................585 Principle of operation.......................................................................586 Logical node for interlocking SCILO (3)...........................................589 Introduction.................................................................................589 Logic diagram.............................................................................590 Function block............................................................................590 Input and output signals.............................................................590 Interlocking for busbar grounding switch BB_ES (3).......................591 Introduction.................................................................................591 Function block............................................................................591 Logic diagram.............................................................................592 Input and output signals.............................................................592 Interlocking for bus-section breaker A1A2_BS (3)...........................592 Introduction.................................................................................592 Function block............................................................................593 Logic diagram.............................................................................594 Input and output signals.............................................................595 Interlocking for bus-section disconnector A1A2_DC (3)..................597 Introduction.................................................................................597 Function block............................................................................597
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Logic diagram.............................................................................598 Input and output signals.............................................................599 Interlocking for bus-coupler bay ABC_BC (3)..................................599 Introduction.................................................................................600 Function block............................................................................601 Logic diagram.............................................................................602 Input and output signals.............................................................604 Interlocking for breaker-and-a-half diameter BH (3)........................607 Introduction.................................................................................607 Function blocks...........................................................................609 Logic diagrams...........................................................................611 Input and output signals.............................................................616 Interlocking for double CB bay DB (3).............................................620 Introduction.................................................................................621 Function block............................................................................622 Logic diagrams...........................................................................624 Input and output signals ............................................................627 Interlocking for line bay ABC_LINE (3)............................................631 Introduction.................................................................................631 Function block............................................................................633 Logic diagram.............................................................................634 Input and output signals.............................................................639 Interlocking for transformer bay AB_TRAFO (3)..............................642 Introduction.................................................................................642 Function block............................................................................643 Logic diagram.............................................................................644 Input and output signals.............................................................646 Position evaluation POS_EVAL.......................................................648 Introduction.................................................................................648 Logic diagram.............................................................................648 Function block............................................................................648 Input and output signals.............................................................648 Logic rotating switch for function selection and LHMI presentation SLGGIO................................................................................................649 Introduction......................................................................................649 Principle of operation.......................................................................649 Functionality and behaviour .......................................................651 Graphical display........................................................................651 Function block.................................................................................653 Input and output signals..................................................................653
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Setting parameters..........................................................................655 Selector mini switch VSGGIO...............................................................655 Introduction......................................................................................655 Principle of operation.......................................................................655 Function block.................................................................................656 Input and output signals..................................................................657 Setting parameters..........................................................................657 IEC61850 generic communication I/O functions DPGGIO...................657 Introduction......................................................................................658 Principle of operation.......................................................................658 Function block.................................................................................658 Input and output signals..................................................................658 Settings............................................................................................659 Single point generic control 8 signals SPC8GGIO...............................659 Introduction......................................................................................659 Principle of operation.......................................................................659 Function block.................................................................................660 Input and output signals..................................................................660 Setting parameters..........................................................................661 AutomationBits, command function for DNP3.0 AUTOBITS................661 Introduction......................................................................................662 Principle of operation.......................................................................662 Function block.................................................................................663 Input and output signals..................................................................663 Setting parameters..........................................................................664 Single command, 16 signals SINGLECMD..........................................680 Introduction......................................................................................680 Principle of operation.......................................................................680 Function block.................................................................................681 Input and output signals..................................................................681 Setting parameters..........................................................................682
Section 13 Logic..................................................................................683
Tripping logic SMPPTRC (94)..............................................................683 Introduction......................................................................................683 Principle of operation.......................................................................683 Logic diagram.............................................................................685 Function block.................................................................................688 Input and output signals..................................................................689 Setting parameters..........................................................................690
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Technical data.................................................................................690 Trip matrix logic TMAGGIO..................................................................690 Introduction......................................................................................691 Principle of operation.......................................................................691 Function block.................................................................................693 Input and output signals..................................................................693 Setting parameters..........................................................................694 Configurable logic blocks......................................................................695 Introduction......................................................................................695 Inverter function block INV..............................................................696 OR function block OR......................................................................696 AND function block AND.................................................................697 Timer function block TIMER............................................................697 Pulse timer function block PULSETIMER........................................698 Exclusive OR function block XOR...................................................699 Loop delay function block LOOPDELAY.........................................699 Set-reset with memory function block SRMEMORY.......................700 Reset-set with memory function block RSMEMORY.......................701 Controllable gate function block GATE............................................702 Settable timer function block TIMERSET........................................703 Technical data.................................................................................703 Fixed signal function block FXDSIGN...................................................704 Principle of operation.......................................................................704 Function block.................................................................................705 Input and output signals..................................................................705 Setting parameters..........................................................................705 Boolean 16 to Integer conversion B16I.................................................706 Introduction......................................................................................706 Principle of operation.......................................................................706 Function block.................................................................................706 Input and output signals..................................................................707 Setting parameters..........................................................................707 Boolean 16 to Integer conversion with logic node representation B16IFCVI..............................................................................................707 Introduction......................................................................................708 Principle of operation.......................................................................708 Function block.................................................................................708 Input and output signals..................................................................708 Setting parameters..........................................................................709 Integer to Boolean 16 conversion IB16.................................................709
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Introduction......................................................................................709 Principle of operation.......................................................................710 Function block.................................................................................710 Input and output signals..................................................................710 Setting parameters..........................................................................711 Integer to Boolean 16 conversion with logic node representation IB16FCVB.............................................................................................711 Introduction......................................................................................711 Principle of operation.......................................................................711 Function block.................................................................................712 Input and output signals..................................................................712 Setting parameters..........................................................................713
Section 14 Monitoring..........................................................................715
Measurements......................................................................................715 Introduction......................................................................................716 Principle of operation.......................................................................717 Measurement supervision..........................................................717 Measurements CVMMXN...........................................................721 Phase current measurement CMMXU........................................726 Phase-phase and phase-neutral voltage measurements VMMXU, VNMMXU....................................................................727 Voltage and current sequence measurements VMSQI, CMSQI........................................................................................727 Function block.................................................................................727 Input and output signals..................................................................729 Setting parameters..........................................................................733 Technical data.................................................................................746 Event counter CNTGGIO......................................................................748 Identification....................................................................................748 Introduction......................................................................................748 Principle of operation.......................................................................749 Reporting....................................................................................749 Design........................................................................................749 Function block.................................................................................750 Input signals....................................................................................750 Setting parameters..........................................................................751 Technical data.................................................................................751 Event function EVENT..........................................................................751 Introduction......................................................................................751 Principle of operation.......................................................................751
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Function block.................................................................................753 Input and output signals..................................................................753 Setting parameters..........................................................................754 Logical signal status report BINSTATREP...........................................756 Introduction......................................................................................756 Principle of operation.......................................................................757 Function block.................................................................................757 Input and output signals..................................................................758 Setting parameters..........................................................................759 Measured value expander block RANGE_XP......................................759 Introduction......................................................................................759 Principle of operation.......................................................................759 Function block.................................................................................760 Input and output signals..................................................................760 Disturbance report DRPRDRE.............................................................760 Introduction......................................................................................761 Principle of operation.......................................................................762 Function block.................................................................................770 Input and output signals..................................................................771 Setting parameters..........................................................................773 Technical data.................................................................................783 Sequential of events.............................................................................783 Introduction......................................................................................783 Principle of operation.......................................................................783 Function block.................................................................................784 Input signals....................................................................................784 Technical data.................................................................................784 Indications.............................................................................................785 Introduction......................................................................................785 Principle of operation.......................................................................785 Function block.................................................................................786 Input signals....................................................................................786 Technical data.................................................................................786 Event recorder .....................................................................................786 Introduction......................................................................................786 Principle of operation.......................................................................787 Function block.................................................................................787 Input signals....................................................................................787 Technical data.................................................................................788 Trip value recorder................................................................................788
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Introduction......................................................................................788 Principle of operation.......................................................................788 Function block.................................................................................789 Input signals....................................................................................789 Technical data.................................................................................789 Disturbance recorder............................................................................789 Introduction......................................................................................789 Principle of operation.......................................................................790 Memory and storage...................................................................791 IEC 60870-5-103........................................................................792 Function block.................................................................................793 Input and output signals..................................................................793 Setting parameters..........................................................................793 Technical data.................................................................................793
Section 15 Metering............................................................................795
Pulse-counter logic PCGGIO................................................................795 Introduction......................................................................................795 Principle of operation.......................................................................795 Function block.................................................................................798 Input and output signals..................................................................798 Setting parameters..........................................................................799 Technical data.................................................................................799 Function for energy calculation and demand handling ETPMMTR......799 Introduction......................................................................................800 Principle of operation.......................................................................800 Function block.................................................................................801 Input and output signals..................................................................801 Setting parameters..........................................................................802
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Setting parameters.....................................................................808 IEC 61850 generic communication I/O functions MVGGIO.............808 Principle of operation..................................................................808 Function block............................................................................808 Input and output signals.............................................................808 Setting parameters.....................................................................809 IEC 61850-8-1 redundant station bus communication....................809 Introduction.................................................................................809 Principle of operation..................................................................810 Function block............................................................................812 Output signals.............................................................................812 Setting parameters.....................................................................812 LON communication protocol...............................................................812 Introduction......................................................................................812 Principle of operation.......................................................................813 Setting parameters..........................................................................832 Technical data.................................................................................832 SPA communication protocol................................................................832 Introduction......................................................................................832 Principle of operation.......................................................................833 Communication ports..................................................................841 Design..............................................................................................841 Setting parameters..........................................................................842 Technical data.................................................................................842 IEC 60870-5-103 communication protocol...........................................842 Introduction......................................................................................842 Principle of operation.......................................................................843 General.......................................................................................843 Communication ports..................................................................853 Function block.................................................................................853 Input and output signals..................................................................856 Setting parameters..........................................................................861 Technical data.................................................................................864 Horizontal communication via GOOSE for interlocking GOOSEINTLKRCV...............................................................................865 Function block.................................................................................865 Input and output signals..................................................................866 Setting parameters..........................................................................867 Goose binary receive GOOSEBINRCV................................................868 Function block.................................................................................868
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Input and output signals..................................................................868 Setting parameters..........................................................................869 Multiple command and transmit MULTICMDRCV, MULTICMDSND...................................................................................870 Introduction......................................................................................870 Principle of operation.......................................................................870 Design..............................................................................................871 General.......................................................................................871 Function block.................................................................................871 Input and output signals..................................................................872 Setting parameters..........................................................................874
Table of contents
Design........................................................................................896 Technical data............................................................................896 Local human-machine interface (Local HMI)...................................896 Transformer input module (TRM)....................................................897 Introduction.................................................................................897 Design........................................................................................897 Technical data............................................................................898 Analog digital conversion module, with time synchronization (ADM) .............................................................................................899 Introduction.................................................................................899 Design........................................................................................899 Binary input module (BIM)...............................................................901 Introduction.................................................................................901 Design........................................................................................901 Technical data............................................................................905 Binary output modules (BOM).........................................................905 Introduction.................................................................................905 Design........................................................................................906 Technical data............................................................................907 Binary input/output module (IOM)....................................................908 Introduction.................................................................................908 Design........................................................................................908 Technical data............................................................................911 mA input module (MIM)...................................................................913 Introduction.................................................................................913 Design........................................................................................913 Technical data............................................................................914 Serial and LON communication module (SLM) ..............................915 Introduction.................................................................................915 Design........................................................................................915 Technical data............................................................................916 Optical ethernet module (OEM).......................................................917 Introduction.................................................................................917 Functionality...............................................................................917 Design........................................................................................917 Technical data............................................................................918 Line data communication module (LDCM)......................................918 Introduction.................................................................................918 Design........................................................................................919 Technical data............................................................................920
24 Technical reference manual
Table of contents
GPS antenna...................................................................................921 Introduction.................................................................................921 Design........................................................................................921 Technical data............................................................................922 IRIG-B time synchronization module IRIG-B...................................922 Introduction.................................................................................922 Design........................................................................................923 Technical data............................................................................924 Dimensions...........................................................................................925 Case without rear cover...................................................................925 Case with rear cover........................................................................927 Flush mounting dimensions.............................................................929 Side-by-side flush mounting dimensions.........................................930 Wall mounting dimensions...............................................................932 External resistor unit for high impedance differential protection......932 External current transformer unit.....................................................934 Mounting alternatives............................................................................934 Flush mounting................................................................................934 Overview.....................................................................................934 Mounting procedure for flush mounting......................................935 19 panel rack mounting..................................................................936 Overview.....................................................................................936 Mounting procedure for 19 panel rack mounting.......................937 Wall mounting..................................................................................938 Overview.....................................................................................938 Mounting procedure for wall mounting.......................................938 How to reach the rear side of the IED........................................939 Side-by-side 19 rack mounting.......................................................940 Overview.....................................................................................940 Mounting procedure for side-by-side rack mounting..................940 IED in the 670 series mounted with a RHGS6 case...................941 Side-by-side flush mounting............................................................941 Overview.....................................................................................941 Mounting procedure for side-by-side flush mounting..................942 Technical data......................................................................................943 Enclosure.........................................................................................943 Connection system..........................................................................943 Influencing factors...........................................................................944 Type tests according to standard....................................................945
Table of contents
Section 20 Labels................................................................................963
Labels on IED.......................................................................................963 Labels on injection equipment..............................................................966
Section 23 Glossary..........................................................................1051
Section 1 Introduction
Section 1
Introduction
1.1
1.1.1
Commissioning
Engineering
Engineeringmanual Installation and Commissioning manual Operators manual Application manual Technical reference manual
The Application Manual (AM) contains application descriptions, setting guidelines and setting parameters sorted per function. The application manual should be used to find out when and for what purpose a typical protection function could be used. The manual should also be used when calculating settings.
27 Technical reference manual
Operation
Installing
Maintenance
Section 1 Introduction
The Technical Reference Manual (TRM) contains application and functionality descriptions and it lists function blocks, logic diagrams, input and output signals, setting parameters and technical data sorted per function. The technical reference manual should be used as a technical reference during the engineering phase, installation and commissioning phase, and during normal service. The Installation and Commissioning Manual (ICM) contains instructions on how to install and commission the protection IED. The manual can also be used as a reference during periodic testing. The manual covers procedures for mechanical and electrical installation, energizing and checking of external circuitry, setting and configuration as well as verifying settings and performing directional tests. The chapters are organized in the chronological order (indicated by chapter/section numbers) in which the protection IED should be installed and commissioned. The Operators Manual (OM) contains instructions on how to operate the protection IED during normal service once it has been commissioned. The operators manual can be used to find out how to handle disturbances or how to view calculated and measured network data in order to determine the cause of a fault. The Engineering Manual (EM) contains instructions on how to engineer the IEDs using the different tools in PCM600. The manual provides instructions on how to set up a PCM600 project and insert IEDs to the project structure. The manual also recommends a sequence for engineering of protection and control functions, LHMI functions as well as communication engineering for IEC 61850 and DNP3.
1.1.2
28
Section 1 Introduction
Logic describes trip logic and related functions. Monitoring describes measurement related functions that are used to provide data regarding relevant quantities, events and faults, for example. Station communication describes Ethernet based communication in general, including the use of IEC 61850 and horizontal communication via GOOSE. Remote communication describes binary and analog signal transfer, and the associated hardware. Hardware describes the IED and its components. Connection diagrams provides terminal wiring diagrams and information regarding connections to and from the IED. Inverse time characteristics describes and explains inverse time delay, inverse time curves and their effects. Glossary is a list of terms, acronyms and abbreviations used in ABB technical documentation.
1.1.3
This manual
The description of each IED related function follows the same structure (where applicable). The different sections are outlined below.
1.1.3.1
Introduction
Outlines the implementation of a particular protection function.
1.1.3.2
Principle of operation
Describes how the function works, presents a general background to algorithms and measurement techniques. Logic diagrams are used to illustrate functionality.
Logic diagrams
Logic diagrams describe the signal logic inside the function block and are bordered by dashed lines. Signal names Input and output logic signals consist of two groups of letters separated by two dashes. The first group consists of up to four letters and presents the abbreviated name for the corresponding function. The second group presents the functionality of the particular signal. According to this explanation, the meaning of the signal BLKTR in figure 4 is as follows: BLKTR informs the user that the signal will BLOCK the TRIP command from the under-voltage function, when its value is a logical one (1).
Section 1 Introduction
Input signals are always on the left hand side, and output signals on the right hand side. Settings are not displayed. Input and output signals In a logic diagram, input and output signal paths are shown as a lines that touch the outer border of the diagram. Input and output signals can be configured using the ACT tool. They can be connected to the inputs and outputs of other functions and to binary inputs and outputs. Examples of input signals are BLKTR, BLOCK and VTSU. Examples output signals are TRIP, START, STL1, STL2, STL3. Setting parameters Signals in frames with a shaded area on their right hand side represent setting parameter signals. These parameters can only be set via the PST or LHMI. Their values are high (1) only when the corresponding setting parameter is set to the symbolic value specified within the frame. Example is the signal Block TUV=Yes. Their logical values correspond automatically to the selected setting value. Internal signals Internal signals are illustrated graphically and end approximately 2 mm from the frame edge. If an internal signal path cannot be drawn with a continuous line, the suffix -int is added to the signal name to indicate where the signal starts and continues, see figure 1.
Section 1 Introduction
BLKTR TEST TEST Block TUV=Yes BLOCK VTSU BLOCK-int. PU_V_A BLOCK-int. PU_V_B BLOCK-int. PU_V_C AND AND OR AND AND 0-t 0 TRIP PICKUP PU_A PU_B PU_C AND OR BLOCK-int.
xx04000375_ansi.vsd
ANSI04000375 V1 EN
Figure 1:
External signals Signal paths that extend beyond the logic diagram and continue in another diagram have the suffix -cont., see figure 2 and figure 3.
Section 1 Introduction
OR
STZMPP-cont.
AB BC CA AG BG CG
Figure 2:
15 ms
0
15 ms
0
or or
15 ms
0
15 ms
BLK-cont.
Xx04000377_ansi.vsd
ANSI04000377 V1 EN
Figure 3:
Section 1 Introduction
Input and output signals
Input and output signals are presented in two separate tables. Each table consists of two columns. The first column contains the name of the signal and the second column contains the description of the signal.
1.1.3.3
1.1.3.4
Function block
Each function block is illustrated graphically. Input signals are always on the left hand side and output signals on the right hand side. Settings are not displayed. Special kinds of settings are sometimes available. These are supposed to be connected to constants in the configuration scheme and are therefore depicted as inputs. Such signals will be found in the signal list but described in the settings table. The ^ character in front of an input or output signal name in the function block symbol given for a function, indicates that the user can set a signal name of their own in PCM600. The * character after an input or output signal name in the function block symbol given for a function, indicates that the signal must be connected to another function block in the application configuration to achieve a valid application configuration.
IEC 61850 - 8 -1 Logical Node
Inputs
BLOCK READ_VAL BI_PULSE* RS_CNT INVALID RESTART BLOCKED NEW_VAL ^SCAL_VAL en05000511-1-en.vsd
Diagram Number
IEC05000511 V2 EN
Figure 4:
Section 1 Introduction
1.1.3.5 Setting parameters
These are presented in tables and include all parameters associated with the function in question.
1.1.3.6
Technical data
The technical data section provides specific technical information about the function or hardware described.
1.1.4
Intended audience
General
This manual addresses system engineers, installation and commissioning personnel, who use technical data during engineering, installation and commissioning, and in normal service.
Requirements
The system engineer must have a thorough knowledge of protection systems, protection equipment, protection functions and the configured functional logics in the protective devices. The installation and commissioning personnel must have a basic knowledge in the handling electronic equipment.
1.1.5
Documents related to REG670 Operators manual
Related documents
Identity number 1MRK 502 028-UUS 1MRK 502 029-UUS 1MRK 502 027-UUS 1MRK 502 030-UUS 1MRK 502 031-BUS
Installation and commissioning manual Technical reference manual Application manual Product guide customized
Connection and Installation components Test system, COMBITEST Accessories for 670 series IEDs 670 series SPA and signal list IEC 61850 Data objects list for 670 series Engineering manual 670 series Buyers guide REG 216 Communication set-up for Relion 670 series
1MRK 513 003-BEN 1MRK 512 001-BEN 1MRK 514 012-BEN 1MRK 500 092-WUS 1MRK 500 091-WUS 1MRK 511 240-UUS 1MRB520004-BEN 1MRK 505 260-UEN
Section 1 Introduction
1.1.6
Revision notes
Revision A Description First issue for 670 series version 1.2 Maintenance updates, PR corrections
36
Section 2
Analog inputs
2.1
Introduction
Analog input channels must be configured and set properly to get correct measurement results and correct protection operations. For power measuring and all directional and differential functions the directions of the input currents must be defined properly. Measuring and protection algorithms in the IED use primary system quantities. Setting values are in primary quantities as well and it is important to set the data about the connected current and voltage transformers properly. A reference PhaseAngleRef can be defined to facilitate service values reading. This analog channels phase angle will always be fixed to zero degrees and all other angle information will be shown in relation to this analog input. During testing and commissioning of the IED the reference channel can be changed to facilitate testing and service values reading. The availability of VT inputs depends on the ordered transformer input module (TRM) type.
2.2
Operation principle
The direction of a current depends on the connection of the CT. The main CTs are typically star (WYE) connected and can be connected with the Star (WYE) point to the object or from the object. This information must be set in the IED. The convention of the directionality is defined as follows: Positive value of current or power means that the quantity has the direction into the object. Negative value of current or power means that the quantity has the direction out from the object.
For directional functions the directional conventions are defined as follows (see figure 5)
Forward means direction into the object. Reverse means direction out from the object.
Definition of direction for directional functions Reverse Forward Definition of direction for directional functions Forward Reverse
en05000456_ansi.vsd
ANSI05000456 V1 EN
Figure 5:
If the settings of the primary CT is right, that is CTStarPoint set as FromObject or ToObject according to the plant condition, then a positive quantity always flows towards the protected object, and a Forward direction always looks towards the protected object. The settings of the IED is performed in primary values. The ratios of the main CTs and VTs are therefore basic data for the IED. The user has to set the rated secondary and primary currents and voltages of the CTs and VTs to provide the IED with their rated ratios. The CT and VT ratio and the name on respective channel is done under Main menu/ Hardware/Analog modules in the Parameter Settings tool.
2.3
Function block
The function blocks are not represented in the configuration tool. The signals appear only in the SMT tool when a TRM is included in the configuration with the function selector tool. In the SMT tool they can be mapped to the desired virtual input (SMAI) of the IED and used internally in the configuration.
2.4
Setting parameters
Dependent on ordered IED type.
Table 1:
Name PhaseAngleRef
Table 2:
Name CT_WyePoint1 CTsec1 CTprim1 CT_WyePoint2 CTsec2 CTprim2 CT_WyePoint3 CTsec3 CTprim3 CT_WyePoint4 CTsec4 CTprim4 CT_WyePoint5 CTsec5 CTprim5 CT_WyePoint6 CTsec6 CTprim6 CT_WyePoint7 CTsec7 CTprim7 CT_WyePoint8 CTsec8 CTprim8 CT_WyePoint9 CTsec9 CTprim9 CT_WyePoint10 CTsec10
Table 3:
Name CT_WyePoint1 CTsec1 CTprim1 CT_WyePoint2 CTsec2 CTprim2 CT_WyePoint3 CTsec3 CTprim3 CT_WyePoint4 CTsec4 CTprim4 CT_WyePoint5 CTsec5 CTprim5 CT_WyePoint6 CTsec6 CTprim6 VTsec7 VTprim7 VTsec8
Rated VT primary voltage Rated VT secondary voltage Rated VT primary voltage Rated VT secondary voltage Rated VT primary voltage Rated VT secondary voltage Rated VT primary voltage Rated VT secondary voltage Rated VT primary voltage
Table 4:
Name CT_WyePoint1 CTsec1 CTprim1 CT_WyePoint2 CTsec2 CTprim2 CT_WyePoint3 CTsec3 CTprim3 CT_WyePoint4 CTsec4 CTprim4 CT_WyePoint5 CTsec5 CTprim5 CT_WyePoint6 CTsec6 CTprim6
Table 5:
Name CT_WyePoint1 CTsec1 CTprim1 CT_WyePoint2 CTsec2 CTprim2 CT_WyePoint3 CTsec3 CTprim3 CT_WyePoint4 CTsec4 CTprim4 CT_WyePoint5 CTsec5 CTprim5 CT_WyePoint6 CTsec6 CTprim6 CT_WyePoint7 CTsec7 CTprim7 VTsec8 VTprim8 VTsec9 VTprim9 VTsec10 VTprim10 VTsec11 VTprim11 VTsec12 VTprim12
Table 6:
Name CT_WyePoint1 CTsec1 CTprim1 CT_WyePoint2 CTsec2 CTprim2 CT_WyePoint3 CTsec3 CTprim3 CT_WyePoint4 CTsec4 CTprim4 CT_WyePoint5 CTsec5 CTprim5 CT_WyePoint6 CTsec6 CTprim6 CT_WyePoint7 CTsec7 CTprim7 CT_WyePoint8 CTsec8 CTprim8 CT_WyePoint9 CTsec9 CTprim9 VTsec10 VTprim10 VTsec11
46
Section 3
Local HMI
3.1
ANSI07000083 V1 EN
Figure 6:
3.2
3.2.1
This is a fully graphical monochrome LCD which measures 4.7 x 3.5 inches. It has 28 lines with up to 40 characters per line. To display the single line diagram, this LCD is required.
3.2.2
IEC07000077-CALLOUT V1 EN
Figure 7:
1 Status indication LEDs 2 LCD 3 Indication LEDs 4 Label 5 Local/Remote LEDs 6 RJ45 port 7 Communication indication LED 8 Keypad
3.3
Keypad
The keypad is used to monitor and operate the IED. The keypad has the same look and feel in all IEDs. LCD screens and other details may differ but the way the keys function is identical.
IEC06000531 V1 EN
Figure 8:
Table 7 describes the HMI keys that are used to operate the IED.
Table 7:
Key
IEC06000532 V1 EN
Press to open two sub menus: Key operation and IED information.
IEC05000103 V1 EN
Press to open the main menu and to move to the default screen.
IEC05000105 V1 EN
Press to start the editing mode and confirm setting changes, when in editing mode.
IEC05000108 V1 EN
Press to navigate forward between screens and move right in editing mode.
IEC05000109 V1 EN
Press to navigate backwards between screens and move left in editing mode.
IEC05000110 V1 EN
Press to move up in the single line diagram and in the menu tree.
IEC05000111 V1 EN
Press to move down in the single line diagram and in the menu tree.
IEC05000112 V1 EN
3.4
3.4.1
LED
Introduction
The LED module is a unidirectional means of communicating. This means that events may occur that activate a LED in order to draw the operators attention to something that has occurred and needs some sort of action.
3.4.2
3.4.3
Indication LEDs
The LED indication module comprising 15 LEDs is standard in 670 series. Its main purpose is to present an immediate visual information for protection indications or alarm signals. Alarm indication LEDs and hardware associated LEDs are located on the right hand side of the front panel. Alarm LEDs are located on the right of the LCD screen and show steady or flashing light. Steady light indicates normal operation. Flashing light indicates alarm.
Alarm LEDs can be configured in PCM600 and depend on the binary logic. Therefore they can not be configured on the local HMI. Typical examples of alarm LEDs Bay controller failure CB close blocked Interlocking bypassed Differential protection trip SF6 Gas refill Position error CB spring charge alarm Oil temperature alarm Thermal overload trip Pressure relief/Bucholtz
The RJ45 port has a yellow LED indicating that communication has been established between the IED and a computer. The Local/Remote key on the front panel has two LEDs indicating whether local or remote control of the IED is active.
3.5
3.5.1
3.5.2
Table 8:
Name Language DisplayTimeout AutoRepeat ContrastLevel DefaultScreen EvListSrtOrder SymbolFont
3.5.3
3.5.3.1
Status LEDs
Design
The function block LocalHMI controls and supplies information about the status of the status indication LEDs. The input and output signals of local HMI are configured with PCM600. The function block can be used if any of the signals are required in a configuration logic. See section "Status indication LEDs" for information about the LEDs.
3.5.3.2
Figure 9:
3.5.3.3
Table 10:
Name HMI-ON RED-S YELLOW-S YELLOW-F RSTPULSE LEDSRST
3.5.4
3.5.4.1
Indication LEDs
Introduction
The function block LEDGEN controls and supplies information about the status of the indication LEDs. The input and output signals of LEDGEN are configured with PCM600. The input signal for each LED is selected individually with the Signal Matrix Tool in PCM600. LEDs (number 16) for trip indications are red. LEDs (number 715) for pickup indications are yellow.
Each indication LED on the local HMI can be set individually to operate in six different sequences Two sequences operate as follow type. Four sequences operate as latch type. Two of the latching sequence types are intended to be used as a protection indication system, either in collecting or restarting mode, with reset functionality. Two of the latching sequence types are intended to be used as signaling system in collecting (coll) mode with an acknowledgment functionality.
The light from the LEDs can be steady (-S) or flashing (-F). See the technical reference manual for more information.
3.5.4.2
Design
The information on the LEDs is stored at loss of the auxiliary power to the IED in some of the modes of LEDGEN. The latest LED picture appears immediately after the IED is successfully restarted.
Operating modes
Collecting mode LEDs which are used in collecting mode of operation are accumulated continuously until the unit is acknowledged manually. This mode is suitable when the LEDs are used as a simplified alarm system.
Re-starting mode In the re-starting mode of operation each new pickup resets all previous active LEDs and activates only those which appear during one disturbance. Only LEDs defined for re-starting mode with the latched sequence type 6 (LatchedReset-S) will initiate a reset and a restart at a new disturbance. A disturbance is defined to end a settable time after the reset of the activated input signals or when the maximum time limit has elapsed.
Acknowledgment/reset
From local HMI Active indications can be acknowledged or reset manually. Manual acknowledgment and manual reset have the same meaning and is a common signal for all the operating sequences and LEDs. The function is positive edge triggered, not level triggered. The acknowledged or reset is performed
via the reset button and menus on the local HMI. See the operator's manual for more information. From function input Active indications can also be acknowledged or reset from an input, RESET, to the function. This input can, for example, be configured to a binary input operated from an external push button. The function is positive edge triggered, not level triggered. This means that even if the button is continuously pressed, the acknowledgment or reset only affects indications active at the moment when the button is first pressed.
Automatic reset Automatic reset can only be performed for indications defined for re-starting mode with the latched sequence type 6 (LatchedReset-S). When automatic reset of the LEDs has been performed, still persisting indications will be indicated with a steady light.
Operating sequences
The operating sequences can be of type Follow or Latched. For the Follow type the LED follows the input signal completely. For the Latched type each LED latches to the corresponding input signal until it is reset.
Figure 10 show the function of available sequences that are selectable for each LED separately. The acknowledgment or reset function is not applicable for sequence 1 and 2 (Follow type). Sequence 3 and 4 (Latched type with acknowledgement) are only working in collecting mode. Sequence 5 is working according to Latched type and collecting mode. Sequence 6 is working according to Latched type and re-starting mode.
The letters S and F in the sequence names have the meaning S = Steady and F = Flashing. At the activation of the input signal, the indication operates according to the selected sequence diagrams. In the sequence diagrams the LEDs have the characteristics as shown in figure 10.
= No indication
= Steady light
= Flash
en05000506.vsd
IEC05000506 V1 EN
Figure 10:
Sequence 1 (Follow-S) This sequence follows all the time, with a steady light, the corresponding input signals. It does not react on acknowledgment or reset. Every LED is independent of the other LEDs in its operation.
Activating signal
LED
IEC01000228_2_en.vsd
IEC01000228 V2 EN
Figure 11:
Sequence 2 (Follow-F) This sequence is the same as sequence 1, Follow-S, but the LEDs are flashing instead of showing steady light. Sequence 3 (LatchedAck-F-S) This sequence has a latched function and works in collecting mode. Every LED is independent of the other LEDs in its operation. At the activation of the input signal, the indication starts flashing. After acknowledgment the indication disappears if the signal is not present any more. If the signal is still present after acknowledgment it gets a steady light.
Activating signal
LED
Acknow.
en01000231.vsd
IEC01000231 V1 EN
Figure 12:
58
LED
Reset
IEC01000235_2_en.vsd
IEC01000235 V2 EN
Figure 13:
Sequence 6 (LatchedReset-S) In this mode all activated LEDs, which are set to sequence 6 (LatchedReset-S), are automatically reset at a new disturbance when activating any input signal for other LEDs set to sequence 6 (LatchedReset-S). Also in this case indications that are still activated will not be affected by manual reset, that is, immediately after the positive edge of that the manual reset has been executed a new reading and storing of active signals is performed. LEDs set for sequence 6 are completely independent in its operation of LEDs set for other sequences. Definition of a disturbance A disturbance is defined to last from the first LED set as LatchedReset-S is activated until a settable time, tRestart, has elapsed after that all activating signals for the LEDs set as LatchedReset-S have reset. However if all activating signals have reset and some signal again becomes active before tRestart has elapsed, the tRestart timer does not restart the timing sequence. A new disturbance start will be issued first when all signals have reset after tRestart has elapsed. A diagram of this functionality is shown in figure 14.
OR
OR
tRestart 0 0-100s
New disturbance
AND
OR
AND OR
AND
en01000237_ansi.vsd
ANSI01000237 V1 EN
Figure 14:
In order not to have a lock-up of the indications in the case of a persisting signal each LED is provided with a timer, tMax, after which time the influence on the definition of a disturbance of that specific LED is inhibited. This functionality is shown i diagram in figure 15.
Activating signal To LED
AND 0-tMax 0
ANSI05000507 V1 EN
en05000507_ansi.vsd
Figure 15:
Timing diagram for sequence 6 Figure 16 shows the timing diagram for two indications within one disturbance.
Disturbance
tRestart
LED 1
IEC01000239_2-en.vsd
Figure 16:
Figure 17 shows the timing diagram for a new indication after tRestart time has elapsed.
Disturbance tRestart
LED 1
Figure 17:
Figure 18 shows the timing diagram when a new indication appears after the first one has reset but before tRestart has elapsed.
LED 1
Figure 18:
Operating sequence 6 (LatchedReset-S), two indications within same disturbance but with reset of activating signal between
LED 1
Figure 19:
3.5.4.3
Function block
LEDGEN BLOCK RESET LEDTEST NEWIND ACK
IEC05000508_2_en.vsd
IEC05000508 V2 EN
Figure 20:
3.5.4.4
Table 12:
Name NEWIND ACK
3.5.4.5
Table 13:
Name Operation tRestart tMax SeqTypeLED1
Setting parameters
LEDGEN Non group settings (basic)
Values (Range) Disabled Enabled 0.0 - 100.0 0.0 - 100.0 Follow-S Follow-F LatchedAck-F-S LatchedAck-S-F LatchedColl-S LatchedReset-S Follow-S Follow-F LatchedAck-F-S LatchedAck-S-F LatchedColl-S LatchedReset-S Follow-S Follow-F LatchedAck-F-S LatchedAck-S-F LatchedColl-S LatchedReset-S Follow-S Follow-F LatchedAck-F-S LatchedAck-S-F LatchedColl-S LatchedReset-S Follow-S Follow-F LatchedAck-F-S LatchedAck-S-F LatchedColl-S LatchedReset-S Unit s s Step 0.1 0.1 Default Disabled 0.0 0.0 Follow-S Description Operation mode for the LED function Defines the disturbance length Maximum time for the definition of a disturbance Sequence type for LED 1
SeqTypeLED2
Follow-S
SeqTypeLED3
Follow-S
SeqTypeLED4
Follow-S
SeqTypeLED5
Follow-S
SeqTypeLED7
Follow-S
SeqTypeLED8
Follow-S
SeqTypeLED9
Follow-S
SeqTypeLED10
Follow-S
SeqTypeLED11
Follow-S
SeqTypeLED12
Follow-S
Name SeqTypeLED13
SeqTypeLED14
Follow-S
SeqTypeLED15
Follow-S
68
Section 4
4.1
Authorization
To safeguard the interests of our customers, both the IED and the tools that are accessing the IED are protected, by means of authorization handling. The authorization handling of the IED and the PCM600 is implemented at both access points to the IED: local, through the local HMI remote, through the communication ports
4.1.1
Principle of operation
There are different levels (or types) of users that can access or operate different areas of the IED and tools functionality. The pre-defined user types are given in Table 14. Be sure that the user logged on to the IED has the access required when writing particular data to the IED from PCM600. The meaning of the legends used in the table: R= Read W= Write - = No access rights
Table 14:
Access rights
Basic setting possibilities (change setting group, control settings, limit supervision) Advanced setting possibilities (for example protection settings) Basic control possibilities (process control, no bypass) Advanced control possibilities (process control including interlock trigg) Basic command handling (for example clear LEDs, manual trigg) Advanced command handling (for example clear disturbance record) Basic configuration possibilities (I/Oconfiguration in SMT) Advanced configuration possibilities (application configuration including SMT, GDE and CMT) File loading (database loading from XML-file) File dumping (database dumping to XML-file) File transfer (FTP file transfer) File transfer (limited) (FTP file transfer) File Transfer (SPA File Transfer) Database access for normal user User administration (user management FTP File Transfer) User administration (user management SPA File Transfer)
R R R R R R R
R R/W R/W R R R R
R R R -
R R R -
The IED users can be created, deleted and edited only with the IED User Management within PCM600. The user can only LogOn or LogOff on the local HMI on the IED, there are no users, groups or functions that can be defined on local HMI. Only characters A - Z, a - z and 0 - 9 should be used in user names and passwords. The maximum of characters in a password is 18.
At least one user must be included in the UserAdministrator group to be able to write users, created in PCM600, to IED.
4.1.1.1
4.2
4.2.1
4.2.2
Principle of operation
The self-supervision operates continuously and includes: Normal micro-processor watchdog function. Checking of digitized measuring signals. Other alarms, for example hardware and time synchronization.
The self-supervision function status can be monitored from the local HMI, from the Event Viewer in PCM600 or from a SMS/SCS system. Under the Diagnostics menu in the local HMI the present information from the selfsupervision function can be reviewed. The information can be found under Main menu/Diagnostics/Internal events or Main menu/Diagnostics/IED status/General. The information from the self-supervision function is also available in the Event Viewer in PCM600. A self-supervision summary can be obtained by means of the potential free alarm contact (INTERNAL FAIL) located on the power supply module. The function of this output relay is an OR-function between the INT-FAIL signal see figure 22 and a couple of more severe faults that can occur in the IED, see figure 21
Fault
Fault
AND INTERNAL FAIL
CEM
Fault
Figure 21:
OR
OR OR OR
LON ERROR FTF fatal error Watchdog RTE fatal error RTE Appl-fail RTE OK IEC61850 not ready RTCERROR RTC OK TIMESYNCHERROR Time reset SYNCH OK Settings changed Set Reset OR Set Reset 1 second pulse Set Reset OR
Internal FAIL
TIMESYNCHERROR SETCHGD
en04000519-1.vsd
IEC04000519 V2 EN
Figure 22:
Some signals are available from the INTERRSIG function block. The signals from this function block are sent as events to the station level of the control system. The signals from the INTERRSIG function block can also be connected to binary outputs for signalization via output relays or they can be used as conditions for other functions if required/desired. Individual error signals from I/O modules can be obtained from respective module in the Signal Matrix tool. Error signals from time synchronization can be obtained from the time synchronization block TIMEINTERRSIG.
4.2.2.1
Internal signals
Self supervision provides several status signals, that tells about the condition of the IED. As they provide information about the internal status of the IED, they are also called internal signals. The internal signals can be divided into two groups. Standard signals are always presented in the IED, see Table 15. Hardware dependent internal signals are collected depending on the hardware configuration, see Table 16.
Table 16:
Card PSM ADOne BIM BOM IOM MIM LDCM
Table 17:
Name of signal FAIL
WARNING
NUMFAIL
IEC61850ERROR
WATCHDOG
LMDERROR APPERROR
This signal will generate an Internal Event to the Internal Event list if any settings are changed. This signal will generate an Internal Event to the Internal Event list if any setting groups are changed. This signal will be active if both the working file and the backup file are corrupted and can not be recovered.
4.2.2.2
Run-time model
The analog signals to the A/D converter is internally distributed into two different converters, one with low amplification and one with high amplification, see Figure 23.
ADx ADx_Low
x1 u1 x2
ADx_High
x1 u1 x2
ADx Controller
IEC05000296-3-en.vsd
IEC05000296 V3 EN
Figure 23:
The technique to split the analog input signal into two A/D converter(s) with different amplification makes it possible to supervise the A/D converters under normal conditions where the signals from the two A/D converters should be identical. An alarm is given if the signals are out of the boundaries. Another benefit is that it improves the dynamic performance of the A/D conversion. The self-supervision of the A/D conversion is controlled by the ADx_Controller function. One of the tasks for the controller is to perform a validation of the input signals. This is done in a validation filter which has mainly two objects: First is the validation part that checks that the A/D conversion seems to work as expected. Secondly, the filter chooses which of the two signals that shall be sent to the CPU, that is the signal that has the most suitable signal level, the ADx_LO or the 16 times higher ADx_HI.
When the signal is within measurable limits on both channels, a direct comparison of the two A/D converter channels can be performed. If the validation fails, the CPU will be informed and an alarm will be given for A/D converter failure. The ADx_Controller also supervise other parts of the A/D converter.
4.2.3
Function block
IEC09000787 V1 EN
Figure 24:
4.2.4
Output signals
Table 18:
Name FAIL WARNING CPUFAIL CPUWARN
4.2.5
Setting parameters
The function does not have any parameters available in the local HMI or PCM600.
4.2.6
Technical data
Table 19:
Data Recording manner List size
4.3
4.3.1
Time synchronization
Introduction
The time synchronization source selector is used to select a common source of absolute time for the IED when it is a part of a protection system. This makes it possible to compare event and disturbance data between all IEDs in a station automation system. Micro SCADA OPC server should not be used as a time synchronization source.
4.3.2
4.3.2.1
Principle of operation
General concepts Time definitions
The error of a clock is the difference between the actual time of the clock, and the time the clock is intended to have. Clock accuracy indicates the increase in error, that is, the time gained or lost by the clock. A disciplined clock knows its own faults and tries to compensate for them.
The time system is based on a software clock, which can be adjusted from external time sources and a hardware clock. The protection and control modules will be timed from a hardware clock, which runs independently from the software clock. See figure 25
External Synchronization sources Off LON SPA Min. pulse GPS SNTP DNP IRIG-B PPS TimeRegulator (Setting, see technical reference manual)
Communication
Events
A/D converter
Diff.communication
IEC08000287 V2 EN
Figure 25:
All time tagging is performed by the software clock. When for example a status signal is changed in the protection system with the function based on free running hardware clock, the event is time tagged by the software clock when it reaches the event recorder. Thus the hardware clock can run independently. The echo mode for the differential protection is based on the hardware clock. Thus, there is no need to synchronize the hardware clock and the software clock. The synchronization of the hardware clock and the software clock is necessary only when GPS or IRIG B 00X with optical fibre, IEEE 1344 is used for differential protection. The two clock systems are synchronized by a special clock synchronization unit with two modes, fast and slow. A special feature, an automatic fast clock time regulator is used. The automatic fast mode makes the synchronization time as short as possible during start up or at interruptions/disturbances in the GPS timing. The setting fast or slow is also available on the local HMI. If a GPS clock is used for 670 series IEDs other than line differential RED670, the hardware and software clocks are not synchronized
79 Technical reference manual
At startup and after interruptions in the GPS or IRIG B time signal, the clock deviation between the GPS time and the internal differential time system can be substantial. A new startup is also required after for example maintenance of the auxiliary voltage system. When the time difference is >16s, the differential function is blocked and the time regulator for the hardware clock automatically uses a fast mode to synchronize the clock systems. The time adjustment is made with an exponential function, that is, big time adjustment steps in the beginning, then smaller steps until a time deviation between the GPS time and the differential time system of >16s has been reached. Then the differential function is enabled and the synchronization remains in fast mode or switches to slow mode, depending on the setting.
Synchronization principle
From a general point of view synchronization can be seen as a hierarchical structure. A function is synchronized from a higher level and provides synchronization to lower levels.
Function
IEC09000342-1-en.vsd
IEC09000342 V1 EN
Figure 26:
Synchronization principle
A function is said to be synchronized when it periodically receives synchronization messages from a higher level. As the level decreases, the accuracy of the synchronization decreases as well. A function can have several potential sources of synchronization, with different maximum errors. This gives the function the possibility
to choose the source with the best quality, and to adjust its internal clock after this source. The maximum error of a clock can be defined as: The maximum error of the last used synchronization message The time since the last used synchronization message The rate accuracy of the internal clock in the function.
4.3.2.2
During power off, the system time in the IED is kept by a capacitor-backed real-time clock that will provide 35 ppm accuracy for 5 days. This means that if the power is off, the time in the IED may drift with 3 seconds per day, during 5 days, and after this time the time will be lost completely.
Synchronization messages configured as coarse are only used for initial setting of the time. After this has been done, the messages are checked against the internal time and only an offset of more than 10 seconds resets the time.
In the IED, the rate accuracy at cold start is 100 ppm but if the IED is synchronized for a while, the rate accuracy is approximately 1 ppm if the surrounding temperature is constant. Normally, it takes 20 minutes to reach full accuracy.
All synchronization interfaces has a time-out and a configured interface must receive time-messages regularly in order not to give an error signal (TSYNCERR). Normally, the time-out is set so that one message can be lost without getting a TSYNCERR, but if more than one message is lost, a TSYNCERR is given.
4.3.2.3
Synchronization alternatives
Three main alternatives of external time synchronization are available. The synchronization message is applied: via any of the communication ports of the IED as a telegram message including date and time as a minute pulse connected to a binary input via GPS
The minute pulse is used to fine tune already existing time in the IEDs.
SNTP provides a ping-pong method of synchronization. A message is sent from an IED to an SNTP server, and the SNTP server returns the message after filling in a reception time and a transmission time. SNTP operates via the normal Ethernet network that connects IEDs together in an IEC 61850 network. For SNTP to operate properly, there must be an SNTP server present, preferably in the same station. The SNTP synchronization provides an accuracy that gives +/- 1 ms accuracy for binary inputs. The IED itself can be set as an SNTP-time server. SNTP server requirements The SNTP server to be used is connected to the local network, that is not more than 4-5 switches or routers away from the IED. The SNTP server is dedicated for its task, or at least equipped with a real-time operating system, that is not a PC with SNTP server software. The SNTP server should be stable, that is, either synchronized from a stable source like GPS, or local without synchronization. Using a local SNTP server without synchronization as primary or secondary server in a redundant configuration is not recommended.
On the serial buses (both LON and SPA) two types of synchronization messages are sent.
Coarse message is sent every minute and comprises complete date and time, that is, year, month, day, hours, minutes, seconds and milliseconds. Fine message is sent every second and comprises only seconds and milliseconds.
The IED accepts minute pulses to a binary input. These minute pulses can be generated from, for example station master clock. If the station master clock is not synchronized from a world wide source, time will be a relative time valid for the substation. Both positive and negative edge on the signal can be accepted. This signal is also considered as a fine time synchronization signal. The minute pulse is connected to any channel on any Binary Input Module in the IED. The electrical characteristic is thereby the same as for any other binary input. If the objective of synchronization is to achieve a relative time within the substation and if no station master clock with minute pulse output is available, a simple minute pulse generator can be designed and used for synchronization of the IEDs. The minute pulse generator can be created using the logical elements and timers available in the IED. The definition of a minute pulse is that it occurs one minute after the last pulse. As only the flanks are detected, the flank of the minute pulse shall occur one minute after the last flank. Binary minute pulses are checked with reference to frequency. Pulse data: Period time (a) should be 60 seconds. Pulse length (b): Minimum pulse length should be >50 ms. Maximum pulse length is optional.
a b
c
en05000251.vsd
IEC05000251 V1 EN
Figure 27:
The default time-out-time for a minute pulse is two minutes, and if no valid minute pulse is received within two minutes a SYNCERR will be given. If contact bounce occurs, only the first pulse will be detected as a minute pulse. The next minute pulse will be registered first 60 s - 50 ms after the last contact bounce. If the minute pulses are perfect, for example, it is exactly 60 seconds between the pulses, contact bounces might occur 49 ms after the actual minute pulse without effecting the system. If contact bounce occurs more than 50 ms, for example, it is less than 59950 ms between the two most adjacent positive (or negative) flanks, the minute pulse will not be accepted. Binary synchronization example An IED is configured to use only binary input, and a valid binary input is applied to a binary input card. The HMI is used to tell the IED the approximate time and the minute pulse is used to synchronize the IED thereafter. The definition of a minute pulse is that it occurs one minute after the previous minute pulse, so the first minute pulse is not used at all. The second minute pulse will probably be rejected due to the spike filter. The third pulse will give the IED a good time and will reset the time so that the fourth minute pulse will occur on a minute border. After the first three minutes, the time in the IED will be good if the coarse time is set properly via the HMI or the RTC backup still keeps the time since last up-time. If the minute pulse is removed for instance for an hour, the internal time will drift by maximum the error rate in the internal clock. If the minute pulse is returned, the first pulse automatically is rejected. The second pulse will possibly be rejected due to the spike filter. The third pulse will either synchronize the time, if the time offset is more than 100 ms, or adjust the time, if the time offset is small enough. If the time is set, the application will be brought to a safe state before the time is set. If the time is adjusted, the time will reach its destination within 1.7 minutes.
4.3.3
Function block
TIMEERR TSYNCERR RTCERR IEC05000425-2-en.vsd
IEC05000425 V2 EN
Figure 28:
4.3.4
Output signals
Table 20:
Name TSYNCERR RTCERR
FineSyncSource
Disabled
Activate IED as synchronization master Adjust rate for time synchronization Hardware time synchronization source
AppSynch SyncAccLevel
NoSynch Unspecified
Table 22:
Name ModulePosition BinaryInput BinDetection
Table 23:
Name ServerIP-Add RedServIP-Add
Table 24:
Name MonthInYear
DayInWeek
Sunday
WeekInMonth
Last
UTCTimeOfDay
3600
Table 25:
Name MonthInYear
DayInWeek
Sunday
WeekInMonth
Last
UTCTimeOfDay
3600
Table 26:
Name NoHalfHourUTC
Table 27:
Name SynchType TimeDomain Encoding
TimeZoneAs1344
PlusTZ
4.3.6
4.4
4.4.1
4.4.2
Principle of operation
Parameter setting groups ActiveGroup function has six functional inputs, each corresponding to one of the setting groups stored in the IED. Activation of any of these inputs changes the active setting group. Seven functional output signals are available for configuration purposes, so that up to date information on the active setting group is always available. A setting group is selected by using the local HMI, from a front connected personal computer, remotely from the station control or station monitoring system or by activating the corresponding input to the ActiveGroup function block. Each input of the function block can be configured to connect to any of the binary inputs in the IED. To do this PCM600 must be used. The external control signals are used for activating a suitable setting group when adaptive functionality is necessary. Input signals that should activate setting groups must be either permanent or a pulse exceeding 400 ms. More than one input may be activated at the same time. In such cases the lower order setting group has priority. This means that if for example both group four and group two are set to activate, group two will be the one activated. Every time the active group is changed, the output signal GRP_CHGD is sending a pulse.
89
The parameter MAXSETGR defines the maximum number of setting groups in use to switch between.
ACTIVATE GROUP 6 ACTIVATE GROUP 5 ACTIVATE GROUP 4 ACTIVATE GROUP 3 ACTIVATE GROUP 2 +RL2 ACTIVATE GROUP 1 IOx-Bly1 IOx-Bly2 IOx-Bly3 IOx-Bly4 IOx-Bly5 IOx-Bly6 ActiveGroup ACTGRP1 GRP1 ACTGRP2 ACTGRP3 ACTGRP4 ACTGRP5 ACTGRP6 GRP2 GRP3 GRP4 GRP5 GRP6 GRP_CHGD
ANSI05000119-2-en.vsd
ANSI05000119 V2 EN
Figure 29:
The above example also includes seven output signals, for confirmation of which group that is active. SETGRPS function block has an input where the number of setting groups used is defined. Switching can only be done within that number of groups. The number of setting groups selected to be used will be filtered so only the setting groups used will be shown on the Parameter Setting Tool.
4.4.3
Function block
ActiveGroup ACTGRP1 GRP1 ACTGRP2 GRP2 ACTGRP3 GRP3 ACTGRP4 GRP4 ACTGRP5 GRP5 ACTGRP6 GRP6 GRP_CHGD ANSI05000433-2-en.vsd
ANSI05000433 V2 EN
Figure 30:
Figure 31:
4.4.4
Table 30:
Name GRP1 GRP2 GRP3 GRP4 GRP5 GRP6 GRP_CHGD
4.4.5
Table 31:
Name t
Setting parameters
ActiveGroup Non group settings (basic)
Values (Range) 0.0 - 10.0 Unit s Step 0.1 Default 1.0 Description Pulse length of pulse when setting changed
Table 32:
Name ActiveSetGrp
MAXSETGR
No
4.5
4.5.1
4.5.2
Principle of operation
The Change lock function (CHNGLCK) is configured using ACT. The function, when activated, will still allow the following changes of the IED state that does not involve reconfiguring of the IED: Monitoring Reading events Resetting events Reading disturbance data Clear disturbances Reset LEDs Reset counters and other runtime component states Control operations Set system time Enter and exit from test mode Change of active setting group
The binary input signal LOCK controlling the function is defined in ACT or SMT:
4.5.3
Function block
CHNGLCK LOCK IEC09000946-1-en.vsd
IEC09000946 V1 EN
Figure 32:
4.5.4
4.5.5
Table 34:
Name Operation
Setting parameters
CHNGLCK Non group settings (basic)
Values (Range) LockHMI and Com LockHMI, EnableCom EnableHMI, LockCom Unit Step Default LockHMI and Com Description Operation mode of change lock
4.6
4.6.1
restored, the IED will remain in TESTMODE with the same protection functions blocked or unblocked as before the power was removed. All testing will be done with actually set and configured values within the IED. No settings will be changed, thus mistakes are avoided.
4.6.2
Principle of operation
Put the IED into test mode to test functions in the IED. Set the IED in test mode by configuration, activating the input SIGNAL on the function block TESTMODE. setting TestMode to Enabled in the local HMI, under Main menu/TEST/IED test mode.
While the IED is in test mode, the ACTIVE of the function block TESTMODE is activated. The other outputs of the function block TESTMODE shows the cause of the "Test mode: Enabled" state input from configuration (OUTPUT output is activated) or setting from local HMI (SETTING output is activated). While the IED is in test mode, the yellow PICKUP LED will flash and all functions are blocked. Any function can be unblocked individually regarding functionality and event signalling. Most of the functions in the IED can individually be blocked by means of settings from the local HMI. To enable these blockings the IED must be set in test mode (output ACTIVE is activated), see example in figure 33. When leaving the test mode, that is entering normal mode, these blockings are disabled and everything is set to normal operation. All testing will be done with actually set and configured values within the IED. No settings will be changed, thus no mistakes are possible. The blocked functions will still be blocked next time entering the test mode, if the blockings were not reset. The blocking of a function concerns all output signals from the actual function, so no outputs will be activated. When a binary input is used to set the IED in test mode and a parameter, that requires restart of the application, is changed, the IED will re-enter test mode and all functions will be blocked, also functions that were unblocked before the change. During the re-entering to test mode, all functions will be temporarily unblocked for a short time, which might lead to unwanted operations. This is only valid if the IED is put in TEST mode by a binary input, not by local HMI. The TESTMODE function block might be used to automatically block functions when a test handle is inserted in a test switch. A contact in the test switch (RTXP24 contact
94 Technical reference manual
29-30) or an FT switch finger can supply a binary input which in turn is configured to the TESTMODE function block. Each of the functions includes the blocking from the TESTMODE function block. A typical example from the undervoltage function is shown in figure 33. The functions can also be blocked from sending events over IEC 61850 station bus to prevent filling station and SCADA databases with test events, for example during a maintenance test.
Disconnection
tBlkUV1 < t1,t1Min IntBlkStVal1 IntBlkStVal2 Time Block step 1 Block step 2
en05000466_ansi.vsd
ANSI05000466 V1 EN
Figure 33:
IEC09000219-1.vsd
IEC09000219 V1 EN
Figure 34:
4.6.4
Table 36:
Name ACTIVE OUTPUT SETTING NOEVENT
4.6.5
Table 37:
Name TestMode EventDisable CmdTestBit
Setting parameters
TESTMODE Non group settings (basic)
Values (Range) Disabled Enabled Disabled Enabled Disabled Enabled Unit Step Default Disabled Disabled Disabled Description Test mode in operation (Enabled) or not (Disabled) Event disable during testmode Command bit for test required or not during testmode
4.7
4.7.1
IED identifiers
Introduction
IED identifiers (TERMINALID) function allows the user to identify the individual IED in the system, not only in the substation, but in a whole region or a country. Use only characters A-Z, a-z and 0-9 in station, object and unit names.
4.7.2
Table 38:
Name StationName StationNumber ObjectName ObjectNumber UnitName UnitNumber
Setting parameters
TERMINALID Non group settings (basic)
Values (Range) 0 - 18 0 - 99999 0 - 18 0 - 99999 0 - 18 0 - 99999 Unit Step 1 1 1 1 1 1 Default Station name 0 Object name 0 Unit name 0 Description Station name Station number Object name Object number Unit name Unit number
4.8
4.8.1
Product information
Introduction
The Product identifiers function identifies the IED. The function has seven pre-set, settings that are unchangeable but nevertheless very important: IEDProdType ProductDef FirmwareVer SerialNo OrderingNo ProductionDate
The settings are visible on the local HMI , under Main menu/Diagnostics/IED status/ Product identifiers
They are very helpful in case of support process (such as repair or maintenance).
4.8.2
Setting parameters
The function does not have any parameters available in the local HMI or PCM600.
4.8.3
IEDMainFunType
4.9
4.9.1
the application manual to get information about how binary inputs are brought in for one IED configuration.
4.9.2
Principle of operation
The Signal matrix for binary inputs (SMBI) function , see figure 35, receives its inputs from the real (hardware) binary inputs via the Signal Matrix Tool (SMT), and makes them available to the rest of the configuration via its outputs, BI1 to BI10. The inputs and outputs, as well as the whole block, can be given a user defined name. These names will be represented in SMT as information which signals shall be connected between physical IO and SMBI function. The input/output user defined name will also appear on the respective output/input signal.
4.9.3
Function block
SMBI ^VIN1 ^VIN2 ^VIN3 ^VIN4 ^VIN5 ^VIN6 ^VIN7 ^VIN8 ^VIN9 ^VIN10 ^BI1 ^BI2 ^BI3 ^BI4 ^BI5 ^BI6 ^BI7 ^BI8 ^BI9 ^BI10 IEC05000434-2-en.vsd
IEC05000434 V2 EN
Figure 35:
4.9.4
Table 40:
Name BI1 BI2 BI3 BI4 BI5 BI6 BI7 BI8 BI9 BI10
4.10
4.10.1
4.10.2
Principle of operation
The Signal matrix for binary outputs (SMBO) function , see figure 36, receives logical signal from the IED configuration, which is transferring to the real (hardware) outputs, via the Signal Matrix Tool (SMT). The inputs in SMBO are BO1 to BO10 and they, as well as the whole function block, can be tag-named. The name tags will appear in SMT as information which signals shall be connected between physical IO and the SMBO. It is important that SMBO inputs are connected when SMBOs are connected to physical outputs through the Signal Matrix Tool. If SMBOs are connected (in SMT) but their inputs not, all the physical outputs will be set by default. This might cause malfunction of primary equipment and/or injury to personnel.
4.10.3
Figure 36:
4.10.4
4.11
4.11.1
The Signal matrix for mA inputs (SMMI) function, see figure 37, receives its inputs from the real (hardware) mA inputs via the Signal Matrix Tool (SMT), and makes them available to the rest of the configuration via its analog outputs, named AI1 to AI6. The inputs, as well as the whole block, can be tag-named. These tags will be represented in SMT. The outputs on SMMI are normally connected to the IEC61850 generic communication I/O functions (MVGGIO) function for further use of the mA signals.
4.11.3
Function block
SMMI ^VIN1 ^VIN2 ^VIN3 ^VIN4 ^VIN5 ^VIN6 AI1 AI2 AI3 AI4 AI5 AI6 IEC05000440-2-en.vsd
IEC05000440 V2 EN
Figure 37:
4.11.4
Table 43:
Name AI1 AI2 AI3
4.12
4.12.1
4.12.2
Principle of operation
Every Signal matrix for analog inputs function (SMAI) can receive four analog signals (three phases and one neutral value), either voltage or current, see figure 39 and figure 40. SMAI outputs give information about every aspect of the 3ph analog signals acquired (phase angle, RMS value, frequency and frequency derivates etc. 244 values in total). The BLOCK input will reset all outputs to 0. The output signal AI1 to AI4 are direct output of the, in SMT, connected input to GRPx_A, GRPxB, GRPxC and GRPx_N, x=1-12. AIN is always the neutral current, calculated residual sum or the signal connected to GRPx_N. Note that function block will always calculate the residual sum of current/voltage if the input is not connected in SMT. Applications with a few exceptions shall always be connected to AI3P.
4.12.3
Frequency values
The frequency functions includes a functionality based on level of positive sequence voltage, IntBlockLevel, to validate if the frequency measurement is valid or not. If positive sequence voltage is lower than IntBlockLevel the function is blocked. IntBlockLevel, is set in % of VBase/3
If SMAI setting ConnectionType is Ph-Ph at least two of the inputs GRPx_A, GRPx_B and GRPx_C must be connected in order to calculate positive sequence voltage. If SMAI setting ConnectionType is Ph-N, all three inputs GRPx_A, GRPx_B and GRPx_C must be connected in order to calculate positive sequence voltage. If only one phase-phase voltage is available and SMAI setting ConnectionType is PhPh the user is advised to connect two (not three) of the inputs GRPx_A, GRPx_B and GRPx_C to the same voltage input as shown in figure 38 to make SMAI calculating a positive sequence voltage (that is input voltage/3).
IEC10000060-1-en.vsd
IEC10000060 V1 EN
Figure 38:
Connection example
The above described scenario does not work if SMAI setting ConnectionType is Ph-N. If only one phase-ground voltage is available, the same type of connection can be used but the SMAI ConnectionType setting must still be Ph-Ph and this has to be accounted for when setting IntBlockLevel. If SMAI setting ConnectionType is Ph-N and the same voltage is connected to all three SMAI inputs, the positive sequence voltage will be zero and the frequency functions will not work properly.
The outputs from the above configured SMAI block shall only be used for Overfrequency protection (SAPTOF, 81), Underfrequency protection (SAPTUF, 81) and Rate-of-change frequency protection (SAPFRC, 81) due to that all other information except frequency and positive sequence voltage might be wrongly calculated. The same phase-phase voltage connection principle shall be used for frequency tracking master SMAI block in pump-storage power plant applications when swapping of positive and negative sequence voltages happens during generator/motor mode of operation.
4.12.4
Figure 39:
SMAI2 BLOCK ^GRP2_A ^GRP2_B ^GRP2_C ^GRP2_N TYPE
ANSI07000130 V1 EN
Figure 40:
4.12.5
Table 45:
Name SPFCOUT AI3P AI1 AI2 AI3 AI4 AIN
Table 46:
Name BLOCK GRP2_A GRP2_B GRP2_C GRP2_N
Table 47:
Name AI3P AI1 AI2 AI3 AI4 AIN
4.12.6
Setting parameters
Settings DFTRefExtOut and DFTReference shall be set to default value InternalDFTRef if no VT inputs are available. Internal nominal frequency DFT reference is then the reference.
Table 48:
Name DFTRefExtOut
DFTReference
InternalDFTRef
DFT reference
ConnectionType TYPE
Ch
Ph-N 1
Table 49:
Name Negation
MinValFreqMeas VBase
% kV
1 0.05
10 400.00
Table 50:
Name DFTReference
ConnectionType TYPE
Ch
Ph-N 1
Table 51:
Name Negation
MinValFreqMeas VBase
% kV
1 0.05
10 400.00
4.13
4.13.1
4.13.2
Principle of operation
Summation block 3 phase 3PHSUM receives the three-phase signals from Signal matrix for analog inputs function (SMAI). In the same way, the BLOCK input will reset all the outputs of the function to 0.
4.13.3
Figure 41:
4.13.4
Table 53:
Name AI3P AI1 AI2 AI3 AI4
4.13.5
Setting parameters
Settings DFTRefExtOut and DFTReference shall be set to default value InternalDFTRef if no VT inputs are available.
Table 54:
Name SummationType
DFTReference
InternalDFTRef
DFT reference
Table 55:
Name FreqMeasMinVal VBase
4.14
4.14.1
4.14.2
Principle of operation
Authority status (ATHSTAT) function informs about two events related to the IED and the user authorization: the fact that at least one user has tried to log on wrongly into the IED and it was blocked (the output USRBLKED) the fact that at least one user is logged on (the output LOGGEDON)
Whenever one of the two events occurs, the corresponding output (USRBLKED or LOGGEDON) is activated. The output can for example, be connected on Event (EVENT) function block for LON/SPA.The signals are also available on IEC 61850 station bus.
4.14.3
Figure 42:
4.14.4
Output signals
Table 56:
Name USRBLKED LOGGEDON
4.14.5
Setting parameters
The function does not have any parameters available in the local HMI or PCM600.
4.15
4.15.1
4.15.2
Principle of operation
The Denial of service functions (DOSFRNT, DOSOEMAB and DOSOEMCD) measures the IED load from communication and, if necessary, limit it for not jeopardizing the IEDs control and protection functionality due to high CPU load. The function has the following outputs:
LINKUP indicates the Ethernet link status WARNING indicates that communication (frame rate) is higher than normal ALARM indicates that the IED limits communication
4.15.3
Function blocks
DOSFRNT LINKUP WARNING ALARM IEC09000749-1-en.vsd
IEC09000749 V1 EN
Figure 43:
Figure 44:
Figure 45:
4.15.4
Signals
Table 57:
Name LINKUP WARNING ALARM
Table 58:
Name LINKUP WARNING ALARM
Table 59:
Name LINKUP WARNING ALARM
4.15.5
Settings
The function does not have any parameters available in the local HMI or PCM600.
114
Section 5
Differential protection
5.1
Id>
SYMBOL-NN V1 EN
5.1.1
Introduction
Short circuit between the phases of the stator windings causes normally very large fault currents. The short circuit gives risk of damages on insulation, windings and stator iron core. The large short circuit currents cause large forces, which can cause damage even to other components in the power plant, such as turbine and generator-turbine shaft. To limit the damage due to stator winding short circuits, the fault clearance must be as fast as possible (instantaneous). If the generator block is connected to the power system close to other generating blocks, the fast fault clearance is essential to maintain the transient stability of the non-faulted generators. Normally, the short circuit fault current is very large, that is, significantly larger than the generator rated current. There is a risk that a short circuit can occur between phases close to the neutral point of the generator, thus causing a relatively small fault current. The fault current can also be limited due to low excitation of the generator. Therefore, it is desired that the detection of generator phase-to-phase short circuits shall be relatively sensitive, detecting small fault currents. It is also of great importance that the generator differential protection does not trip for external faults, with large fault currents flowing from the generator.
To combine fast fault clearance, as well as sensitivity and selectivity, the generator differential protection is normally the best choice for phase-to-phase generator short circuits. Generator differential protection GENPDIF (87G) is also well suited to generate fast, sensitive and selective fault clearance, if used to protect shunt reactors or small busduct.
5.1.2
Principle of operation
The task of Generator differential protection GENPDIF (87G) is to determine whether a fault is within the protected zone, or outside the protected zone. The protected zone is delimited by the position of current transformers, as shown in figure 46.
IEC06000430-2-en.vsd
IEC06000430 V2 EN
Figure 46:
If the fault is internal, the faulty generator must be quickly tripped, that is, disconnected from the network, the field breaker tripped and the power to the prime mover interrupted. GENPDIF (87G) function always uses reference (default) directions of CTs towards the protected generator as shown in figure 46. Thus, it always measures the currents on the two sides of the generator with the same reference direction towards the generator windings. With the orientation of CTs as in figure 46, the difference of currents flowing in, and out, of a separate stator winding phase is simply obtained by summation of the two currents fed to the differential protection function. Numerical IEDs have brought a large number of advantages and new functionality to the protective relaying. One of the benefits is the simplicity and accuracy of calculating symmetrical components from individual phase quantities. Within the firmware of a numerical IED, it is no more difficult to calculate negative-sequence components than it is to calculate zero-sequence components. Diversity of operation principles integrated in the same protection function enhances the overall performance without a significant increase in cost. A novelty in GENPDIF (87G), namely the negative-sequence-current-based internalexternal fault discriminator, is used with advantage in order to determine whether a fault is internal or external. Indeed, the internal-external fault discriminator not only positively discriminates between internal and external faults, but can independently detect minor faults which may not be felt (until they develop into more serious faults) by the "usual" differential protection based on operate-restrain characteristic.
116 Technical reference manual
GENPDIF (87G) is using fundamental frequency phase current phasors and negative sequence current phasors. These quantities are derived outside the differential protection function block, in the general pre-processing blocks. GENPDIF (87G) is also using with advantage the DC component of the instantaneous differential current and the 2nd and 5th harmonic components of the instantaneous differential currents. The instantaneous differential currents are calculated from the input samples of the instantaneous values of the currents measured at both ends of the stator winding. The DC and the 2nd and 5th harmonic components of each separate instantaneous differential current are extracted inside the differential protection.
5.1.2.1
5.1.2.2
(Equation 1)
One common fundamental frequency bias current is used. The bias current is the magnitude of the highest measured current in the protected circuit. The bias current is not allowed to drop instantaneously, instead, it decays exponentially with a predefined time constant. These principles make the differential IED more secure, with less risk to operate for external faults. The maximum principle brings as well more meaning to the breakpoint settings of the operate-restrain characteristic.
(Equation 2)
IAt
Idiff
IAn
ANSI0700018_3_en.vsd
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Figure 47:
Internal fault
IAn
IAt
IAt Idiff = 0
ANSI07000019 V2 EN
IAn
en07000019-2_ansi.vsd
Figure 48:
External fault
Generator differential protection GENPDIF (87G) function uses two mutually independent characteristics to which magnitudes of the three fundamental frequency RMS differential currents are compared at each execution of the differential protection function. These two characteristics divide, each of them independently, the operate current restrain current plane into two regions: the operate (trip) region and the restrain (block) region, as shown in figure 50. Two kinds of protection are obtained:
118 Technical reference manual
the non-stabilized (instantaneous unrestrained) differential protection the stabilized differential protection
The non-stabilized (instantaneous) differential protection is used for very high differential currents, where it must be beyond any doubt, that the fault is internal. This limit, (defined by the setting UnrestrainedLimit), is a constant, not proportional dependent on the bias (restrain) current. No harmonic or any other restrain is applied to this limit, which is, therefore, called the unrestrained limit. The reset ratio of the unrestrained characteristic is equal to 0.95. The stabilized differential protection applies a differential (operate) current, and the common bias (restrain) current, on the operate-restrain characteristic, as shown in figure 50. Here, the actual limit, where the protection can operate, is dependent on the bias (restrain) current. The operate value, is stabilized by the bias current. This operate restrain characteristic is represented by a double-slope, double-breakpoint characteristic. The restrained characteristic is determined by the following 5 settings: IdMin (Sensitivity in section 1, set as multiple of generator rated current) EndSection1 (End of section 1, set as multiple of generator rated current) EndSection2 (End of section 2, set as multiple of generator rated current) SlopeSection2 (Slope in section 2 of the characteristic, set in percent) SlopeSection3 (Slope in section 3 of the characteristic, set in percent)
(Equation 3)
Note that both slopes are calculated from the characteristics break points.
The operate-restrain characteristic is tailor-made, in other words, it can be constructed by the user. A default operate-restrain characteristic is suggested which gives acceptably good results in a majority of applications. The operate-restrain characteristic has in principle three sections with a section-wise proportionality dependence of the operate value to the common restrain (bias) current. The reset ratio is in all parts of the characteristic equal to 0.95. Section 1 is the most sensitive part on the characteristic. In section 1, normal currents flow through the protected circuit and its current transformers, and risk for higher false differential currents is low. With generators the only cause of small false differential currents in this section can be tolerances of the current transformers used on both sides of the protected generator. Slope in section 1 is always zero percent. Normally, with
the protected machine at rated load, the restrain, bias current will be around 1 p.u., that is, equal to the machine rated current. In section 2, a certain minor slope is introduced which is supposed to cope with false differential currents proportional to higher than normal currents through the current transformers. The more pronounced slope in section 3 is designed to result in a higher tolerance to substantial current transformer saturation at high through-fault currents, which can be expected in this section. Temporarily decreased sensitivity of differential protection is activated if the binary input DESENSIT is (temporarily) set to 1 (TRUE). In this case, a new, separate limit is superposed to the otherwise unchanged operate-bias characteristic. This limit is called TempIdMin and is a setting. The value of the setting TempIdMin must be given as a multiple of the setting IdMin. In this case no trip command can be issued if all fundamental frequency differential currents are below the value of the setting TempIdMin. AddTripDelay: If the input DESENSIT is activated also the operation time of the protection function can be increased by using the setting AddTripDelay.
Operate conditionally
TempIdMin IdMin
Restrain 4 5
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Figure 50:
Operate-restrain characteristic
GENPDIF (87G) can also be temporarily desensitized if the Boolean setting OperDCBiasing is set to 1 (TRUE). In this case, the DC component is extracted online from the instantaneous differential currents. The highest DC component is taken as a kind of bias in the sense that the highest sensitivity of the differential protection is inversely proportional to the ratio of this DC component to the maximum fundamental frequency differential current. Similar to the desensitization described above, a separate (temporary) additional limit is activated. The value of this limit is limited to either the generator rated current, or 3 times IdMin, whichever is smaller. This temporary extra limit decays exponentially from its maximum value with a time constant equal to T = 1 second. This feature must be used when unmatched CTs are used on the generator or shunt reactor, especially where a long DC time constant can be expected. The new limit is superposed on the otherwise unchanged operate-bias characteristic, and temporarily determines the highest sensitivity of the differential protection. This temporary sensitivity must be lower than the sensitivity in section 1 of the operate-bias characteristic.
This DC desensitization is not active, if a disturbance has been detected and characterized as internal fault.
5.1.2.3
Supplementary criteria
To relieve the burden of constructing an exact optimal operate-restrain characteristic, two special features supplement the basic stabilized differential protection function, making Generator differential protection GENPDIF (87G) a very reliable one. The supplementary criteria are: Internal/external fault discriminator (enhances, or blocks, the trip command) Harmonic restrain (blocks only)
The internal/external fault discriminator is a very reliable supplementary criterion. It discriminates with a high speed between internal and external faults. The discriminator is the main part of what is here called the negative-sequence-current-based differential protections. It is recommended that this feature is always used (that is, enabled, OpNegSeqDiff = On). If a fault is classified as internal, then any eventual block signals by the harmonic criterion are ignored, and the differential protection can operate very quickly without any further delay. If a fault (disturbance) is classified as external, then generally, but not unconditionally, a trip command is prevented. If a fault is classified as external, harmonic analysis of the fault conditions is initiated. If all the differential currents which caused their respective pickup signals to be set, are free of harmonic pollution, that is, if no harmonic block signal has been set, then a (minor) internal fault, simultaneous with a predominant external fault, can be suspected. This conclusion can be drawn because at external faults, major false differential currents can only exist when one or more current transformers saturate transiently. In this case, the false instantaneous differential currents are highly polluted by higher harmonic components, the 2nd, and the 5th. The existence of relatively high negative-sequence currents is in itself an indication of a disturbance, as the negative-sequence currents are superimposed, pure-fault quantities. The negative-sequence currents are measurable indications of abnormal conditions. The negative sequence currents are particularly suitable for directional tests. The negative sequence internal or external fault discriminator works satisfactorily even in case of three-phase faults. Because of the fundamental frequency components (50/60 Hz) of the decaying DC offset of the fault currents, the system is not fully symmetrical immediately after the fault. Due to the transient existence of the negative
122 Technical reference manual
sequence system, faults can be distinguished as internal or external, even for threephase faults. The internal or external fault discriminator responds to the relative phase angles of the negative sequence fault currents at both ends of the stator winding. Observe that the source of the negative sequence currents at unsymmetrical faults is at the fault point. If the two negative sequence currents, as seen by the differential relay, flow in the same direction (that is with the CTs oriented as in figure 46), the fault is internal. If the two negative sequence currents flow in opposite directions, the fault is external. Under external fault condition, the relative angle is theoretically equal to 180. Under internal fault condition, the angle is ideally 0, but due to possible different negative-sequence impedance angles on both sides of the internal fault, it may differ somewhat from 0.
The setting NegSeqROA, as shown in figure 51, represents the so called Relay Operate Angle, which determines the boundary between the internal and external fault regions. It can be selected in the range 30 to 90, with a step of 1. The default value is 60. The default setting, 60, favors somewhat security in comparison to dependability. Magnitudes of both negative-sequence currents which are to be compared as to their phase positions in the complex plane must be high enough so that one can be sure that they are due to a fault. The limit value IMinNegSeq is settable in the range [0.02 0.20] of the protected generator rated current. Adaptability is introduced if the bias current is higher than 150 % rated current. Adaptability is introduced 10 ms after this limit of 150 % rated current has been crossed so that the internal/external discriminator is given the time to detect correctly a fault before an eventual CT saturation sets in. The threshold IMinNegSeq is dynamically increased by 4 % of the bias current, in case of internal faults, and by 8 % of the bias current in case of external faults. Only if magnitudes of both currents are above the limit IMinNegSeq, the angle between the two currents is calculated. If any of the two currents is too small, no decision is taken regarding the relative position of the fault, and this feature then remains inactive rather than to produce a wrong decision. The relative angle is then assigned the value of 120 (2.094 radians). If this value persists, then this is an indication that no directional comparison has been made. Neither internal, nor external fault (disturbance) is declared in this case.
180 deg
IminNegSeq
0 deg
The characteristic is defined by the settings: IMinNegSeq and NegSeqROA 270 deg
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Figure 51:
NegSeqROA determines the boundary between the internal and external fault regions
If one or more pickup signals have been set by the restrained differential protection algorithm, because one or more of the fundamental frequency differential currents entered the operate region of the restrained differential protection, then the internal/ external fault discriminator can enhance the final, common, trip command by the differential protection. If a fault is classified as internal, then any eventual block signals by the harmonic criterion are ignored, and the differential protection operates immediately without any further delay. This makes the overall generator differential protection very fast. Operation of this protection is signaled on the output of GENPDIF (87G) as TRNSUNRE.
The difference from the unrestrained negative sequence differential protection, described above, is that the sensitive one does not require any pickup signal to be set. It is enough that both of the negative sequence currents, contributions to the total negative sequence differential current, which should be compared, are above the setting IMinNegSeq. Thus, this protection can be made very sensitive. Further, an intentional delay of one cycle is added in order not to inadvertently operate for some eventual transients. Further, the sensitive negative sequence differential protection is automatically disabled when the bias current exceeds 1.5 times the rated current of the
124 Technical reference manual
protected generator. Operation of this protection is signaled on the output of the function as TRNSENS.
5.1.2.4
Harmonic restrain
Harmonic restrain is the classical restrain method traditionally used with power transformer differential protections. The goal there was to prevent an unwanted trip command due to magnetizing inrush currents at switching operations, due to magnetizing currents at over-voltages, or external faults. Harmonic restrain is just as useful with Generator differential protection GENPDIF (87G). The harmonic analysis is only executed in those phases, where pickup signals have been set. There is no magnetizing inrush to a generator, but there may be some in case of shunt reactors. The false initial differential currents of a shunt reactor have an appreciable amount of higher harmonic currents. At external faults dangerous false differential currents can arise for different reasons, mainly due to saturation of one or more current transformers. The false differential currents display in this case a considerable amount of higher harmonics, which can, therefore, be used to prevent an unwanted trip of a healthy generator or shunt reactor. If a fault is recognized as external by the internal/external fault discriminator, but nevertheless one or more pickup signals have been set, the harmonic analysis is initiated in the phases with pickup signal, as previously described. If all of the instantaneous differential currents, where trip signals have been set, are free of higher harmonics (that is the cross-block principle is imposed temporarily), a (minor) internal fault is assumed to have happened simultaneously with a predominant external one. A trip command is then allowed.
5.1.2.5
The principle design of the Generator differential protection GENPDIF (87G) is shown in figure 52.
TRIP Signals
Diff.prot. characteristic
PICKUP Signals
BLOCK Signals Samples IAN, IBN,ICN Calculation instantaneous Idiff Samples Idiff Hamonic analysis: DC, 2nd and 5th Harm. Block Pickup and trip logic
The sensitive protection is deactivated above bias current > 150 % rated current. Phasor IAN (neg.seq.) Internal/ External Fault Discriminator and Sensitive differential protection Intern/ extern Fault Analog Outputs
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Figure 52:
Simplified logic diagrams of the function are shown in figures 53, 54, 55 and 56.
b>a
AND
TRIPUNRE_A
AND
PU_A
AND OR
ID_A
2nd and 5th Harmonic
TRIPRES_A
NOT
BLKH
AND AND
Cross Block To B or C
ANSI07000020-3-en.vsd
ANSI07000020 V3 EN
Figure 53:
EXTFAULT
INTFAULT
TRNSSENS
OpNegSeqDiff=On
IBIAS
a b
AND
b>a
Constant
BLKNSSEN BLKNSUNR BLOCK PU_A PU_B PU_C
AND OR
TRNSUNR
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ANSI07000021 V2 EN
Figure 54:
OR
PICKUP
OR
BLKH
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ANSI07000022 V1 EN
Figure 55:
OR
TRIPRES
OR
TRIPUNRE
TRNSSENS TRNSUNR
OR
TRIP
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ANSI07000023 V1 EN
Figure 56:
5.1.3
Figure 57:
5.1.4
Table 61:
Name TRIP TRIPRES TRIPUNRE TRNSUNR TRNSSENS PICKUP PU_A BFI_B BFI_C BLKH OPENCT OPENCTAL ID_A ID_B ID_C IDMAG_NS IBIAS
5.1.5
Table 62:
Name Operation IdMin IdUnre OpNegSeqDiff IMinNegSeq
Setting parameters
GENPDIF (87G) Group settings (basic)
Values (Range) Disabled Enabled 0.05 - 1.00 1.00 - 50.00 No Yes 0.02 - 0.20 Unit IB IB IB Step 0.01 0.01 0.01 Default Disabled 0.25 10.00 Yes 0.04 Description Operation Disable / Enable Section 1 sensitivity, multiple of generator rated current Unrestr. prot. limit, multiple of generator rated current Negative Sequence Differential Enable Off/On Neg. sequence curr. limit, as multiple of gen. rated curr.
Table 63:
Name EndSection1 EndSection2 SlopeSection2 SlopeSection3 OpCrossBlock NegSeqROA HarmDistLimit TempIdMin AddTripDelay OperDCBiasing OpenCTEnable tOCTAlarmDelay tOCTResetDelay tOCTUnrstDelay
Table 64:
Name IBase InvertCT2Curr
IBase
(0.020.2)p.u. of IBase 25 ms typically at 0 to 2 x set level 20 ms typically at 2 to 0 x set level 12 ms typically at 0 to 5 x set level 25 ms typically at 5 to 0 x set level 15 ms typically at 0 to 5 x set level 2 ms typically at 0 to 5 x set level
5.2
3Id/I
SYMBOL-BB V1 EN
T3WPDIF
87T
3Id/I
SYMBOL-BB V1 EN
5.2.1
152
352
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152
352
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252
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twowinding power transformer with two circuit breakers on one side Table continues on next page
152
352
252
452
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twowinding power transformer with two circuit breakers and two CT-sets on both sides Three-winding applications
452
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452
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threewinding power transformer with two circuit breakers and two CT-sets on one side
152 252
552
352
452
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Autotransformer with two circuit breakers and two CT-sets on two out of three sides
Figure 58:
The setting facilities cover the application of the differential protection to all types of power transformers and auto-transformers with or without load tap changer as well as shunt reactors and local feeders within the station. An adaptive stabilizing feature is included for heavy through-faults.By introducing the load tap changer position, the differential protection pick-up can be set to optimum sensitivity thus covering internal faults with low fault level. Harmonic restraint is included for inrush and overexcitation currents respectively. Adaptive stabilization is also included for system recovery inrush and CT saturation during external faults. A high set unrestrained differential current protection element is included for a very high speed tripping at a high internal fault currents. Included is an innovative sensitive differential protection element based on the theory of symmetrical components. This element offers the best possible coverage of power transformer windings turn to turn faults.
5.2.2
Principle of operation
The task of the power transformer differential protection is to determine whether a fault is within the protected zone, or outside of the protected zone. The protected zone is limited by the position of current transformers (see figure 59), and in principle can include more objects than just a transformer. If the fault is found to be internal, the faulty power transformer must be quickly disconnected from the system.
The main CTs are normally supposed to be Wye connected. The main CTs can be grounded in anyway (that is, either "ToObject" or "FromObject"). However internally the differential function will always use reference directions towards the protected transformer as shown in figure 59. Thus the IED will always internally measure the currents on all sides of the power transformer with the same reference direction towards the power transformer windings as shown in figure 59.For more information see the Application manual
IW1 Z1S1 IW1 IW2 Z1S2 IW2
E1S1
E1S2
IED
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ANSI05000186 V1 EN
Figure 59:
Even in a healthy power transformer, the currents are generally not equal when they flow through it. This is due to the ratio of the number of turns of the windings and the connection group of the protected transformer. Therefore the differential protection must first correlate all currents to each other before any calculation can be performed. In numerical differential protections this correlation and comparison is performed mathematically. First, compensation for the protected transformer transformation ratio and connection group is made, and only then are the currents compared phase-wise. This makes external auxiliary (interposing) current transformers unnecessary. Conversion of all currents to the common reference side of the power transformer is performed by pre-programmed coefficient matrices, which depends on the protected power transformer transformation ratio and connection group. Once the power transformer phase shift, rated currents and voltages have been entered by the user, the differential protection is capable to calculate off-line matrix coefficients required in order to perform the on-line current comparison by means of a fixed equation. Numerical IEDs have brought a large number of well-known advantages and new functionality to protective relaying. One of the benefits is the simplicity and accuracy of calculating symmetrical components from individual phase quantities. Within the firmware of a numerical IED, it is no more difficult to calculate negative-sequence components than it is to calculate zero-sequence components. Diversity of operation principles integrated in the same protection function enhances the overall performance without a significant increase in cost.
A novelty in power transformer differential protection, namely the negative-sequencecurrent-based internal-external fault discriminator, is used with advantage in order to determine whether a fault is internal or external. Indeed, the internal-external fault discriminator not only positively discriminates between internal and external faults, but can also independently detect minor faults which may not be sensed by the "usual" differential protection based on operate-restrain characteristic. For all differential functions it is the common trip that shall be used to initiate a trip of a breaker. The separate trip signals from the different parts lacks the safety against maloperation. This will in some cases result in a 6 ms time difference between, for example restrained trip is issued and common trip is issued. The separate trip signals shall only be used for information purpose of which part that has caused the trip.
5.2.2.1
The fundamental frequency differential current is a vectorial sum (sum of fundamental frequency phasors) of the individual phase currents from the different sides of the protected power transformer. Before any differential current can be calculated, the power transformer phase shift, and its transformation ratio, must be accounted for. Conversion of all currents to a common reference is performed in two steps: all current phasors are phase-shifted to (referred to) the phase-reference side, (whenever possible the first winding with wye connection) all currents magnitudes are always referred to the first winding of the power transformer (typically transformer high-voltage side)
The two steps of conversion are made simultaneously on-line by the pre-programmed coefficient matrices, as shown in equation 5 for a two-winding power transformer, and in equation 6 for a three-winding power transformer.
These are the internal compensation within the differential function. The protected power transformer data is always entered per its nameplate. The Differential function will correlateadapt nameplate data and select proper reference windings.
(Equation 5)
where: 1. 2. 3. is the resulting Differential Currents is the current contribution from the W1 side is the current contribution from the W2 side
(Equation 6)
where: 1. 2. 3. 4. is the resulting Differential Currents is the current contribution from the W1 side is the current contribution from the W2 side is the current contribution from the W3 side
and where, for equation 5 and equation 6: ID_A ID_B ID_C is the fundamental frequency differential current in phaseA (in W1 side primary amperes) is the fundamental frequency differential current in phase B (in W1 side primary amperes) is the fundamental frequency differential current in phaseC (in W1 side primary amperes)
I_A_W1 I_B_W1 I_C_W1 I_A_W2 I_B_W2 I_C_W2 I_A_W3 I_B_W3 I_C_W3 Vn_W1 Vn_W2 Vn_W3 A, B and C
is the fundamental frequency phase current in phaseA on the W1 side is the fundamental frequency phase current in phaseB on the W1 side is the fundamental frequency phase current in phaseC on the W1 side is the fundamental frequency phase current in phaseA on the W2 side is the fundamental frequency phase current in phase B on the W2 side is the fundamental frequency phase current in phase C on the W2 side is the fundamental frequency phase current in phase A on the W3 side is the fundamental frequency phase current in phaseB on the W3 side is the fundamental frequency phase current in phaseC on the W3 side is transformer rated phase-to-phase voltage on the W1 side (setting parameter) is transformer rated phase-to-phase voltage on the W2 side (setting parameter) is transformer rated phase-to-phase voltage on the W3 side (setting parameter) are three by three matrices with numerical coefficients
Values of the matrix A, B and C coefficients depend on: 1. The Power transformer winding connection type, such as wye (Y/y) or delta (D/d) Note! The capitalized letter Y or D is used to represent the high voltage (HV) side of the transformer and the smaller letter y or d to represent lower voltage(LV) level. When neutral bushing of a wye winding is brought out, the same may be represented as YN or yn depending on whether the winding is HV or LV.
2.
3.
The Transformer phase shift such as Yd1, Dy11, YNautod5, Yy0d5 and so on, which introduce phase displacement between individual windings currents in multiples of 30. Since the HV and LV winding voltages are in phase for wye/wye or Delta/Delta transformers, the same is represented in IEC as represented as Dd0, Yy0. Polarity reversal in one of the windings would give 180 degree phase displacement which can be represented by clock position 6. Such transformers can thus be represented as Dd6 or Yy6. It is also possible to rename the phases ABC to CAB or BCA, giving 120 or 240 degree displacements, represented by clock positions 4 & 8 . Polarity reversals in one of the windings would provide clock positions 10 & 2. These can all be represented for example: Yy0, Yy2, Yy4, Dd0, Dd6. ANSI wye/Delta or Delta/wye transformers have the HV winding leading the LV winding by 30degrees. This can be represented by Yd1 or Dy1. Again considering polarity reversals and renaming of phases gives rise to other clock positions 4,7,5,11 The Settings for elimination of zero sequence currents for the individual windings.
When the end user enters all these parameters, transformer differential function automatically calculates the matrix coefficients. During this calculations the following rules are used:
139 Technical reference manual
For the phase reference, the first winding with set wye (Y) connection is always used. For example, if the power transformer is a Yd1 power transformer, the HV winding (Y) is taken as the phase reference winding. If the power transformer is a Dy1, then the LV winding (y) is taken for the phase reference. If there is no wye connected winding, such as in Dd0 type of power transformers, then the HV delta winding (D) is automatically chosen as the phase reference winding. The fundamental frequency differential currents are in general composed of currents of all sequences, that is, the positive-, the negative-, and the zero-sequence currents. If the zero-sequence currents are eliminated (see section "Optional Elimination of zero sequence currents"), then the differential currents can consist only of the positive-, and the negative-sequence currents. When the zero-sequence current is subtracted on one side of the power transformer , then it is subtracted from each individual phase current. As it can be seen from equation 5 and equation 6 the first entered winding (W1) is always taken for ampere level reference (current magnitudes from all other sides are always transferred to W1 side). In other words, within the differential protection function, all differential currents and bias current are always expressed in HV side primary Amperes. It can be shown that the values of the matrix A, B & C coefficients (see equation 5 and equation 6) can be pre-calculated in advance depending on the relative phase shift between the reference winding and other power transformer windings. Table 66 summarizes the values of the matrices for all standard phase shifts between windings.
Table 66: Matrices for differential current calculation
Matrix with Zero Sequence Reduction set to On Matrix for Reference Winding Matrix with Zero Sequence Reduction set to Off
2 -1 -1 1 -1 2 -1 3 -1 -1 2
EQUATION1227 V1 EN
1 0 0 0 1 0 0 0 1
(Equation 7)
EQUATION1228 V1 EN
(Equation 8)
1 -1 0 0 1 -1 3 -1 0 1
(Equation 9)
EQUATION1229 V1 EN
1 1 1 3 -2
-2 1 1
-2 1
(Equation 10)
0 -1 0 0 0 -1 -1 0 0
EQUATION1231 V1 EN
EQUATION1230 V1 EN
(Equation 11)
0 -1 1 1 0 -1 3 -1 1 0
(Equation 12)
EQUATION1232 V1 EN
-1 -1 2 1 2 -1 -1 3 -1 2 -1
EQUATION1233 V1 EN
0 0 1 1 0 0 0 1 0
EQUATION1234 V1 EN
(Equation 13)
(Equation 14)
-1 0 1 1 1 -1 0 3 0 1 -1
EQUATION1235 V1 EN
(Equation 15)
-2 1 1 3 1
-2 1 1 -2
(Equation 16)
-1 0 0 0 -1 0 0 0 -1
EQUATION1237 V1 EN
EQUATION1236 V1 EN
(Equation 17)
-1 1 0 0 -1 1 3 1 0 -1
(Equation 18)
EQUATION1238 V1 EN
-1 2 -1 1 -1 -1 2 3 2 -1 -1
EQUATION1239 V1 EN
0 1 0 0 0 1 1 0 0
EQUATION1240 V1 EN
(Equation 19)
(Equation 20)
Matrix with Zero Sequence Reduction set to Off Not applicable. Matrix on the left used.
0 1 -1 -1 0 1 3 1 -1 0
(Equation 21)
EQUATION1241 V1 EN
1 1 -2 3 1
1 1 -2
-2 1 1
(Equation 22)
0 0 -1 -1 0 0 0 -1 0
EQUATION1243 V1 EN
EQUATION1242 V1 EN
(Equation 23)
1 0 -1 1 -1 1 0 3 0 -1 1
EQUATION1244 V1 EN
(Equation 24)
By using this table complete equation for calculation of fundamental frequency differential currents for two winding power transformer with YNd5 phase shift and enabled zero sequence current reduction on HV side will be derived. From the given power transformer phase shift the following is possible to be concluded: 1. 2. The HV wye (Y) connected winding will be used as the reference winding and zero sequence currents shall be subtracted on that side The LV winding is lagging for 150
With the help of table 66, the following matrix equation can be written for this power transformer:
ID _ A 2 -1 -1 I _ A _ W 1 -1 0 1 I _ A _ W 2 ID _ B = 1 -1 2 -1 I _ B _ W 1 + Vr _ W 2 1 1 -1 0 I _ B _ W 2 3 Vr _ W 1 3 ID _ C -1 -1 2 I _ C _ W 1 0 1 -1 I _ C _ W 2
EQUATION1810-ANSI V1 EN
(Equation 25)
where: ID_A ID_B ID_C I_A_W1 I_B_W1 is the fundamental frequency differential current in phase A (in W1 side primary amperes) is the fundamental frequency differential current in phase B (in W1 side primary amperes) is the fundamental frequency differential current in phase C (in W1 side primary amperes) is the fundamental frequency phase current in phase A on the W1 side is the fundamental frequency phase current in phase B on the W1 side
is the fundamental frequency phase current in phaseC on the W1 side is the fundamental frequency phase current in phase A on the W2 side is the fundamental frequency phase current in phase B on the W2 side is the fundamental frequency phase current in phaseC on the W2 side is transformer rated phase-to-phase voltage on the W1 side (setting parameter) is transformer rated phase-to-phase voltage on the W2 side (setting parameter)
As marked in equation 5 and equation 6, the first term on the right hand side of the equation, represents the total contribution from the individual phase currents from the W1 side to the fundamental frequency differential currents, compensated for eventual power transformer phase shift. The second term on the right hand side of the equation, represents the total contribution from the individual phase currents from the W2 side to the fundamental frequency differential currents, compensated for eventual power transformer phase shift and transferred to the power transformer W1 side. The third term on the right hand side of the equation, represents the total contribution from the individual phase currents from the W3 side to the fundamental frequency differential currents, compensated for eventual power transformer phase shift and transferred to the power transformer W1 side. These current contributions are important, because they are used for calculation of common bias current. The fundamental frequency differential currents are the "usual" differential currents, the magnitudes which are applied in a phase-wise manner to the operate - restrain characteristic of the differential protection. The magnitudes of the differential currents can be read as service values from the function and they are available as outputs IDMAG_A, IDMAG_B, IDMAG_C from the differential protection function block. Thus they can be connected to the disturbance recorder and automatically recorded during any external or internal fault condition.
A load tap changer is a mechanical device, which is used to step-wise change number of turns within one power transformer winding. Consequently the power transformer overall turns ratio is changed. Typically the load tap changer is located within the HV winding (that is, winding 1, W1) of the power transformer. By operating load tap changer, it is possible to step-wise regulate voltage on the LV side of the power transformer. However at the same time the differential protection for power transformer becomes unbalanced. Differential function in the IED has built-in feature to continuously monitor the load tap changer position and dynamically compensate online for changes in power transformer turns ratio. Differential currents are calculated as shown in equation 5and equation 6. By setting parameters, the winding location of the OLTC is defined. Also, the voltage change of each step. Thus, if for example the load tap changer is located within winding 1 the noload voltage Un_W1 will be treated as a function of the actual load tap changer
143 Technical reference manual
position in equation 5and equation 6. Thus for every load tap changer position a corresponding value for Vn_W1 will be calculated and used in the above mentioned equations. By doing this, complete on-line compensation for load tap changer movement is achieved. Differential protection will be ideally balanced for every load tap changer position and no false differential current will appear irrespective of actual load tap changer position. Typically the minimum differential protection pickup for power transformer with load tap changer is set between 30% to 40%. However with this load tap changer compensation feature it is possible to set the differential protection in the IED more sensitive with a pickup value of 15% to 20%. Load tap changer position is measured within the IED by Tap changer control and supervision, (TCLYLTC ,84). Within this function block, the load tap changer position value is continuously monitored to insure its integrity. When any error in the load tap changer position is detected an alarm is given. This signal shall be connected to the OLTCxAL input of the differential function block. While OLTCxAL input has a logical value of one the differential protection minimum pickup, originally defined by setting parameter IdMin, will be increased by the set range of the load tap changer. Alternatively the differential current alarm feature can be used to alarm for any problems in the whole load tap changer compensation chain. It shall be noted that: two-winding differential protection in the IED can on-line compensate for one load tap changer within the protected power transformer three-winding differential protection in the IED can on-line compensate for up to two load tap changers within the protected power transformer
Fundamental frequency differential current level is monitored all the time within the differential function. As soon as all three fundamental frequency differential currents are above the set threshold defined by setting parameter IDiffAlarm a delay on pickup timer is started. When the pre-set time, defined by setting parameter tAlarmDelay, has expired the differential current alarm is generated and output signal IDALARM is set to logical value one. This feature can be effectively used to provide alarm when load tap changer position compensation is used and something in the whole compensation chain goes wrong. This alarm can be as well used with some additional IED configuration logic to desensitize the differential function.
Bias current
The bias current is calculated as the highest current amongst all individual winding current contributions to the total fundamental frequency differential currents, as shown in equation 5 and equation 6. All individual winding current contributions are already
referred to the power transformer winding one side (power transformer HV winding) and therefore they can be compared regarding their magnitudes. There are six (or nine in the case of a three-winding transformer) contributions to the total fundamental differential currents, which are the candidates for the common bias current. The highest individual current contribution is taken as a common bias (restrain) current for all three phases. This "maximum principle" makes the differential protection more secure, with less risk to operate for external faults and in the same time brings more meaning to the breakpoint settings of the operate - restrain characteristic. It shall be noted that if the zero-sequence currents are subtracted from the separate contributions to the total differential current, then the zero-sequence component is automatically eliminated from the bias current as well. This ensures that for secondary injection from just one power transformer side the bias current is always equal to the highest differential current regardless of the fault type. During normal through-load operation of the power transformer, the bias current is equal to the maximum load current from two (three) -power transformer windings. The magnitudes of the common bias (restrain) current expressed in HV side amperes can be read as service value from the function. At the same time it is available as an output IBIAS from the differential protection function block. It can be connected to the disturbance recorder and automatically recorded during any external or internal fault condition. For application with so called "T" configuration, that is, two restraint CT inputs from one side of the protected power transformer, such as in the case of breaker-and-a-half schemes the primary CT ratings can be much higher than the rating of the protected power transformer. In order to determine the bias current for such T configuration, the two separate currents flowing in the T-side are scaled down to the protected power transform level by means of additional settings. This is done in order to prevent unwanted de-sensitizing of the overall differential protection. In addition to that, the resultant currents (the sum of two currents) into the protected power transformer winding, which is not directly measured is calculated, and included in the common bias calculation. The rest of the bias calculation procedure is the same as in protection schemes without breaker-and-a-half arrangements.
To avoid unwanted trips for external ground-faults, the zero sequence currents should be subtracted on the side of the protected power transformer, where the zero sequence currents can flow at external ground-faults. The zero sequence currents can be explicitly eliminated from the differential currents and common bias current calculation by special, dedicated parameter settings, which are available for every individual winding. Elimination of the zero sequence component of current is necessary whenever:
the protected power transformer cannot transform the zero sequence currents to the other side. the zero sequence currents can only flow on one side of the protected power transformer.
In most cases, power transformers do not properly transform the zero sequence current to the other side. A typical example is a power transformer of the wye-delta type, for example YNd1. Transformers of this type do not transform the zero sequence quantities, but zero sequence currents can flow in the grounded wye connected winding. In such cases, an external ground-fault on the wye-side causes zero sequence current to flow on the wye-side of the power transformer, but not on the other side. This results in false differential currents - consisting exclusively of the zero sequence currents. If high enough, these false differential currents can cause an unwanted disconnection of the healthy power transformer. They must therefore be subtracted from the fundamental frequency differential currents if an unwanted trip is to be avoided. For delta windings this feature shall be enabled only if a grounding transformer exist within the differential zone on the delta side of the protected power transformer. Removing the zero sequence current from the differential currents decreases to some extent the sensitivity of the differential protection for internal ground-faults. In order to counteract this effect to some degree, the zero sequence current is subtracted not only from the three fundamental frequency differential currents, but from the bias current as well.
The power transformer differential protection function uses two limits, to which actual magnitudes of the three fundamental frequency differential currents are compared at each execution of the function. The unrestrained (that is, non-stabilized, "instantaneous") part of the differential protection is used for very high differential currents, where it should be beyond any doubt, that the fault is internal. This settable limit is constant and not proportional to the bias current. Neither harmonic, nor any other restrain is applied to this limit, which is therefore allowed to trip the power transformer instantaneously. The restrained (stabilized) part of the differential protection compares the calculated fundamental differential (operating) currents and the bias (restrain) current, by applying them to the operate - restrain characteristic. Practically, the magnitudes of the individual fundamental frequency differential currents are compared with an adaptive limit. This limit is adaptive because it is dependent on the bias (that is, restrain) current magnitude. This limit is called the operate - restrain characteristic. It is represented by a double-slope, double-breakpoint characteristic, as shown in figure 60. The restrained characteristic is determined by the following 5 settings:
1. 2. 3. 4. 5.
IdMin (Sensitivity in section 1, multiple of trans. HV side rated current set under the parameter RatedCurrentW1) EndSection1 (End of section 1, as multiple of transformer HV side rated current set under the parameter RatedCurrentW1) EndSection2 (End of section 2, as multiple of transformer HV side rated current set under the parameter RatedCurrentW1) SlopeSection2 (Slope in section 2, as multiple of transformer HV side rated current set under the parameter RatedCurrentW1) SlopeSection3 (Slope in section 2, as multiple of transformer HV side rated current set under the parameter RatedCurrentW1)
The restrained characteristic in figure 60 is defined by the settings: 1. 2. 3. 4. 5. IdMin EndSection1 EndSection2 SlopeSection2 SlopeSection3
Operate conditionally
Restrain 4 5
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Figure 60:
where:
The operate - restrain characteristic is tailor-made and can be designed freely by the user after his needs. The default characteristic is recommended to be used. It gives good results in a majority of applications. The operate - restrain characteristic has in principle three sections with a section-wise proportionality of the operate value to the bias (restrain) current. The reset ratio is in all parts of the characteristic equal to 0.95. Section 1: This is the most sensitive part on the characteristic. In section 1, normal currents flow through the protected circuit and its current transformers, and risk for higher false differential currents is relatively low. An un-compensated on-load tap-
changer is a typical reason for existence of the false differential currents in this section. The slope in section 1 is always zero percent. Section 2: In section 2, a certain minor slope is introduced which is supposed to cope with false differential currents proportional to higher than normal currents through the current transformers. Section 3: The more pronounced slope in section 3 is designed to result in a higher tolerance to substantial current transformer saturation at high through-fault currents, which may be expected in this section. The operate - restrain characteristic should be designed so that it can be expected that: for internal faults, the operate (differential) currents are always with a good margin above the operate - restrain characteristic for external faults, the false (spurious) operate currents are with a good margin below the operate - restrain characteristic
Existence of relatively high negative sequence currents is in itself a proof of a disturbance on the power system, possibly a fault in the protected power transformer. The negative-sequence currents are a measurable indication of an abnormal condition, similar to the zero sequence current. One of the several advantages of the negative sequence currents compared to the zero sequence currents is that they provide coverage for phase-to-phase and power transformer turn-to-turn faults. Theoretically, the negative sequence currents do not exist during symmetrical three-phase faults, however they do appear during initial stage of such faults for a long enough time (in most cases) for the IED to make the proper decision. Further, the negative sequence currents are not stopped at a power transformer by the Yd, or Dy connection type. The negative sequence currents are always properly transformed to the other side of any power transformer for any external disturbance. Finally, the negative sequence currents are not affected by symmetrical through-load currents. For power transformer differential protection applications, the negative sequence based differential currents are calculated by using exactly the same matrix equations, which are used to calculate the traditional phase-wise fundamental frequency differential currents. The same equation shall be fed by the negative sequence currents from the two power transformer sides instead of individual phase currents, as shown in matrix equation 27 for a case of two-winding, YNd5 power transformer.
3
(Equation 27)
where: 1. 2. 3. is the Negative Sequence Differential Currents is Negative Sequence current contribution from the W1 side is the Negative Sequence current contribution from the W2 side
and where: IDNS_A IDNS_B IDNS_C INS_W1 INS_W2 Vn_W1 Vn_W2 is the negative sequence differential current in phase A (in W1 side primary amperes) is the negative sequence differential current in phase B (in W1 side primary amperes) is the negative sequence differential current in phase C (in W1 side primary amperes) is the negative sequence current on the W1 side in primary amperes (phase A reference) is the negative sequence current on the W1 side in primary amperes (phase A reference) is the transformer rated phase-to-phase voltage on the W1 side (setting parameter) is transformer rated phase-to-phase voltage on W2 side (setting parameter) is the complex operator for sequence quantities, for example,
a=e
j 120
=-
1 2
+ j
3 2
(Equation 28)
EQUATION1248 V1 EN
Because the negative sequence currents always form the symmetrical three phase current system on each transformer side (that is, negative sequence currents in every phase will always have the same magnitude and be phase displaced for 120 electrical degrees from each other), it is only necessary to calculate the first negative sequence differential current that is, IDNS_A.
As marked in equation 27, the first term on the right hand side of the equation, represents the total contribution of the negative sequence current from the W1 side compensated for eventual power transformer phase shift. The second term on the right hand side of the equation, represents the total contribution of the negative sequence current from the W2 side compensated for eventual power transformer phase shift and transferred to the power transformer W1 side. These negative sequence current contributions are phasors, which are further used in directional comparisons, to characterize a fault as internal or external. See section "Internal/external fault discriminator" for more information. The magnitudes of the negative sequence differential current expressed in the HV side A can be read as service values from the function. In the same time it is available as outputs IDMAG_NS from the differential protection function block. Thus, it can be connected to the disturbance recorder and automatically recorded during any external or internal fault condition. The internal/external fault discriminator is a very powerful and reliable supplementary criterion to the traditional differential protection. It is recommended that this feature shall be always used (that is, enabled) when protecting three-phase power transformers. The internal/external fault discriminator detects even minor faults, with a high sensitivity and at high speed, and at the same time discriminates with a high degree of dependability between internal and external faults. The algorithm of the internal/external fault discriminator is based on the theory of symmetrical components. Already in 1933, Wagner and Evans in their famous book "Symmetrical Components" have stated that:
1. Source of the negative-sequence currents is at the point of fault,
E NS = - I NS Z NS
EQUATION1254 V1 EN
(Equation 29)
2. 3.
Negative-sequence currents distribute through the negative-sequence network Negative-sequence currents obey the first Kirchhoff"s law
The internal/external fault discriminator responds to the magnitudes and the relative phase angles of the negative-sequence fault currents at the different windings of the protected power transformer. The negative sequence fault currents must first be referred to the same phase reference side, and put to the same magnitude reference. This is done by the matrix expression (see equation 27). Operation of the internal/external fault discriminator is based on the relative position of the two phasors representing the winding one (W1) and winding two (W2) negative
sequence current contributions, respectively, defined by expression shown in equation 27. It performs a directional comparison between these two phasors. First, the LV side phasor is referred to the HV side (W1 side): both the magnitude, and the phase position are referred to the HV (W1 side). Then the relative phase displacement between the two negative sequence current phasors is calculated. In case of threewinding power transformers, a little more complex algorithm is applied, with two directional tests. The overall directional characteristic of the internal/external fault discriminator is shown in figure 61, where the directional characteristic is defined by two setting parameters: 1. 2. IMinNegSeq NegSeqROA
90 deg 120 deg If one or the other of currents is too low, then no measurement is done, and 120 degrees is mapped Internal/external fault boundary
180 deg
0 deg
IMinNegSeq
270 deg
IEC05000188 V3 EN
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Figure 61:
In order to perform directional comparison of the two phasors their magnitudes must be high enough so that one can be sure that they are due to a fault. On the other hand, in order to guarantee a good sensitivity of the internal/external fault discriminator, the value of this minimum limit must not be too high. Therefore this limit value, called IminNegSeq, is settable in the range of 0.02 to 0.20 times the IBase of the power transformer winding one. The default value is 0.04. Note that, in order to enhance stability at higher fault currents, the relatively very low threshold value IminNegSeq is
dynamically increased at currents higher than normal currents: if the bias current is higher than 110% of IBase ,then 10% of the bias current is added to the IminNegSeq. Only if the magnitudes of both negative sequence current contributions are above the actual limit, the relative position between these two phasors is checked. If either of the negative sequence current contributions, which should be compared, is too small (less than the set value for IminNegSeq), no directional comparison is made in order to avoid the possibility to produce a wrong decision. This magnitude check guarantees stability of the algorithm, when the power transformer is energized. The setting NegSeqROA represents the Relay Operate Angle, which determines the boundary between the internal and external fault regions. It can be selected in a range from 30 degrees to 90 degrees, with a step of 0.1 degree. The default value is 60 degrees. The default setting 60 degree favours somewhat security in comparison to dependability somewhat. If the above condition concerning magnitudes is fulfilled, the internal/external fault discriminator compares the relative phase angle between the negative sequence current contributions from W1 and W2 sides of the power transformer using the following two rules: If the negative sequence current contributions from the W1 and the W2 sides are in phase, the fault is internal (that is, both phasors are within protected zone) If the negative sequence currents contributions from W1 and W2 sides are 180 degrees out of phase, the fault is external (that is, W1 phasors is outside protected zone)
For example, for any unsymmetrical external fault, ideally the respective negative sequence current contributions from the W1 and W2 power transformer sides will be exactly 180 degrees apart and equal in magnitude, regardless the power transformer turns ratio and phase displacement. An example is shown in figure 62, which shows trajectories of the two separate phasors representing the negative sequence current contributions from the HV and LV sides of an Yd5 power transformer (after compensation of the transformer turns ratio and phase displacement) by using equation 27) for an unsymmetrical external fault. Observe that the relative phase angle between these two phasors is 180 electrical degrees at any point in time. No current transformer saturation was assumed for this case.
90 60
150 10 ms
30
0.4 kA
330
240 270
Contribution to neg. seq. differential current from HV side Contribution to neg. seq. differential current from LV side
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Figure 62:
Trajectories of Negative Sequence Current Contributions from HV and LV sides of Yd5 power transformer during external fault
Under external fault conditions, the relative angle is theoretically equal to 180 degrees. During internal faults, the angle shall ideally be 0 degrees, but due to possible different negative sequence source impedance angles on the W1 and W2 sides of the protected power transformer, it may differ somewhat from the ideal zero value. However, during heavy faults, CT saturation might cause the measured phase angle to differ from 180 degrees for an external, and from 0 degrees for an internal fault. See figure 63 for an example of a heavy internal fault with transient CT saturation.
Dire ctiona l Compa ris on Crite rion: Inte rna l fa ult a s s e e n from the HV s ide 90 120
35 ms
60
e xcurs ion from 0 de gre e s due to CT s a tura tion 30 de finite ly a n inte rna l fa ult
150
trip c o mmand in 12 ms Inte rna l fa ult de cla re d 7 ms a fte r inte rna l fa ult occure d
0.5 kA
210
1.0 kA
330
240 270
1.5 kA
300
HV s ide contribution to the tota l ne ga tive s e que nce diffe re ntia l curre nt in kA Dire ctiona l limit (within the re gion de limite d by 60 de gre e s is inte rna l fa ult)
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Figure 63:
Operation of the internal/external fault discriminator for internal fault with CT saturation
It shall be noted that additional security measures are implemented in the internal/ external fault discriminator algorithm in order to guarantee proper operation with heavily saturated current transformers. The trustworthy information on whether a fault is internal or external is typically obtained in about 10ms after the fault inception, depending on the setting IminNegSeq, and the magnitudes of the fault currents. During heavy faults, approximately 5ms time to full saturation of the main CT is sufficient in order to produce a correct discrimination between internal and external faults.
Two sub functions, which are based on the internal/external fault discriminator with the ability to trip a faulty power transformer, are parts to the traditional power transformer differential protection. The unrestrained negative sequence differential protection The unrestrained negative sequence protection is activated if one or more pickup signals have been set by the traditional differential protection algorithm. This happens because one or more of the fundamental frequency differential currents entered the operate region on the operate - restrain characteristic. So, this protection is not
155 Technical reference manual
independent of the traditional restrained differential protection - it is activated after the first start signal has been placed. If the same fault has been positively recognized as internal, then the unrestrained negative sequence differential protection places its own trip request. Any block signals by the harmonic and/or waveform criteria, which can block the traditional differential protection are overridden, and the differential protection operates quickly without any further delay. This logic guarantees a fast disconnection of a faulty power transformer for any internal fault. If the same fault has been classified as external, then generally, but not unconditionally, a trip command is prevented. If a fault is classified as external, the further analysis of the fault conditions is initiated. If all the instantaneous differential currents in phases where pickup signals have been issued are free of harmonic pollution, then a (minor) internal fault, simultaneous with a predominant external fault can be suspected. This conclusion can be drawn because at external faults, major false differential currents can only exist when one or more current transformers saturate. In this case, the false instantaneous differential currents are polluted by higher harmonic components, the 2nd, the 5th etc. Sensitive negative sequence based turn-to-turn fault protection The sensitive, negative sequence current based turn-to-turn fault protection detects the low level faults, which are not detected by the traditional differential protection until they develop into more severe faults, including power transformer iron core. The sensitive protection is independent from the traditional differential protection and is a very good complement to it. The essential part of this sensitive protection is the internal/ external fault discriminator. In order to be activated, the sensitive protection requires no pickup signal from the traditional power transformer biased differential protection. If magnitudes of HV and LV negative sequence current contributions are above the set limit for IminNegSeq, then their relative positions are determined. If the disturbance is characterized as an internal fault, then a separate trip request will be placed. Any decision on the way to the final trip request must be confirmed several times in succession in order to cope with eventual CT transients. This causes a short additional operating time delay due to this security count. For very low level turn-to-turn faults the overall response time of this protection is about 30ms. The instantaneous differential currents are calculated from the instantaneous values of the input currents in order to perform the harmonic analysis and waveform analysis upon each one of them (see section "Harmonic and waveform block criteria" for more information).
The instantaneous differential currents are calculated using the same matrix expression as shown in equation 5 and equation 6. The same matrices A, B and C are used for these calculations. The only difference is that the matrix algorithm is fed by instantaneous values of currents, that is, samples.
The two block criteria are the harmonic restrain and the waveform restrain. These two criteria have the power to block (that is, to prevent) a trip command by the traditional differential protection, which produces pickup signals by applying the differential currents, and the bias current, to the operate - restrain characteristic. Harmonic restrain The harmonic restrain is the classical restrain method traditionally used with power transformer differential protections. The goal is to prevent an unwanted trip command due to magnetizing inrush currents at switching operations, or due to magnetizing currents at over-voltages. The magnetizing currents of a power transformer flow only on one side of the power transformer (one or the other) and are therefore always the cause of false differential currents. The harmonic analysis (the 2nd and the 5th harmonic) is applied to instantaneous differential currents. Typical instantaneous differential currents during power transformer energizing are shown in figure 64. The harmonic analysis is only applied in those phases, where pickup signals have been set. For example, if the content of the 2nd harmonic in the instantaneous differential current of phase A is above the setting I2/I1Ratio, then a block signal is set for that phase, which can be read as BLK2H_A output of the differential protection. Waveform restrain The waveform restrain criterion is a good complement to the harmonic analysis. The waveform restrain is a pattern recognition algorithm, which looks for intervals within each fundamental power system cycle with low instantaneous differential current. This interval is often called current gap in protection literature. However, within differential function this criterion actually searches for long-lasting intervals with low rate-ofchange in instantaneous differential current, which are typical for the power transformer inrush currents. Block signals BLKWAV_A(B,C) are set in those phases where such behavior is detected. The algorithm does not require any end user settings. The waveform algorithm is automatically adapted dependent only on the power transformer rated data.
400kV Currents
Current [%]
Time [cycles]
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Figure 64:
Inrush currents to a transformer as seen by a protective IED. Typical is a high amount of the 2nd harmonic, and intervals of low current, and low rate-of-change of current within each period.
Cross-blocking between phases The basic definition of the cross-blocking is that one of the three phases can block operation (that is, tripping) of the other two phases due to the harmonic pollution of the differential current in that phase (that is, waveform, 2nd or 5th harmonic content). In differential algorithm the user can control the cross-blocking between the phases via the setting parameter CrossBlockEn=Enabled. When parameter CrossBlockEn=Enabled cross blocking between phases is introduced. There is no time settings involved, but the phase with the operating point above the set bias characteristic (in the operate region) will be able to cross-block the other two phases if it is itself blocked by any of the previously explained restrained criteria. As soon as the operating point for this phase is below the set bias characteristic (that is, in the restrain region) cross blocking from that phase will be inhibited. In this way crossblocking of the temporary nature is achieved. It should be noted that this is the default (recommended) setting value for this parameter. When parameter CrossBlockEn=Disabled, any cross blocking between phases will be disabled. It is recommended to use the value Disabled with caution in order to avoid the unwanted tripping during initial energizing of the power transformer. Transformer differential function in the IED has a built-in, advanced switch onto fault feature. This feature can be enabled or disabled by a setting parameter SOTFMode. When enabled this feature ensures quick differential protection tripping in cases where
a transformer is energized with an internal fault (for example, forgotten grounding on transformer LV side). Operation of this feature is based on the fact that a current gap (term current gap is explained under waveblock feature above) will exist within the first power system cycle when healthy power transformer is energized. If this is not the case the waveblock criterion will reset quickly. This quick reset of the waveblock criterion will temporarily disable the second harmonic blocking feature of the differential protection function. This consequently ensures fast operation of the transformer differential function for a switch onto a fault condition. It shall be noted that this feature is only active during initial power transformer energizing, more exactly, under the first 50 ms. When the switch onto fault feature is disabled by the setting parameter SOTFMode, the waveblock and second harmonic blocking features work in parallel and are completely independent from each other.
differential protection has a built-in, advanced open CT detection feature. The open CT circuit condition creates unexpected operations for differential protection under the normal load conditions. It is also possible to damage secondary equipment due to high voltage produced from open CT circuit outputs. Therefore, it is always a requirement from security and reliability points of view to have open CT detection function to block differential protection function in case of open CT conditions and at the same time, produce the alarm signal to the operational personal to make quick remedy actions to correct the open CT condition. The built-in open CT feature can be enabled or disabled by a setting parameter OpenCTEnable (Disabled/Enabled). When enabled, this feature prevents maloperation when a loaded main CT connected to differential protection is by mistake open circuited on the secondary side. Note that this feature can only detect interruption of one CT phase current at the time. If two or even all three-phase currents of one set of CT are accidentally interrupted at the same time this feature cannot operate and differential protection generates trip signal, if the false differential current is sufficiently high. To ensure blocking of the differential protection for open CT condition this algorithm must operate within 10 ms in order to be able to prevent unwanted operation of differential protection under all loading conditions. The principle applied to detect an open CT is a simple pattern recognition method, similar to the waveform check which has been with advantage used by the Power Transformer Differential Protection in order to detect the magnetizing inrush condition. The open CT detection principle is based on the fact, that for an open CT, the current in the phase with the open CT suddenly drops (at least theoretically) to zero (that is, as seen by the protection), while the currents of the other two phases continue as before. The open CT function is supposed to detect an open CT under normal conditions, that is, with the protected multi-terminal circuit under normal load. If the load currents are very low or zero, the open CT condition cannot be detected. The open CT algorithm only detects an open CT if the load on the power transformer is from 10% to 110% of
159 Technical reference manual
the rated load. Outside this range an open CT condition is not even looked for. The search for an open CT starts after 60 seconds (50 seconds in 60 Hz systems) since the bias current enters the 10110% range. The Open CT detection feature can also be explicitly deactivated by setting: OpenCTEnable = 0 (Disabled). If an open CT is detected and the output OPENCT set to 1, then all the differential functions are blocked, except of the unrestrained (instantaneous) differential. An alarm signal is also produced after a settable delay (tOCTAlarmDelay) to report to operational personal for quick remedy actions once the open CT is detected. When the open CT condition is removed (that is, the previously open CT reconnected), the functions remain blocked for a specified interval of time, which is also a setting (tOCTResetDelay). The task of this measure is to prevent an eventual mal-operation after the reconnection of the previously open CT secondary circuit. The open CT feature works only during normal loading condition. Thus, the open CT feature must be automatically disabled for all external faults, big overloads and inrush conditions. The open CT algorithm provides detailed information about the location of the defective CT secondary circuit. The algorithm clearly indicates IED side, CT input and phase in which open CT condition has been detected. These indications are provided via the following outputs from Line differential protection function: 1. 2. 3. 4. Output OPENCT provides instant information to indicate that open CT circuit has been detected Output OPENCTAL provides time delayed alarm that the open CT circuit has been detected. Time delay is defined by setting parameter tOCTAlarmDelay. Integer output OPENCTIN provides information on the local HMI regarding which open CT circuit has been detected (1=CT input No 1; 2=CT input No 2) Integer output OPENCTPH provides information on the local HMI regarding in which phase open CT circuit has been detected (1=Phase A; 2= Phase B; 3= Phase C)
Once the open CT condition is declared, the algorithm stops to search for further open CT circuits. It waits until the first open CT circuit has been corrected. Note that once the open CT condition has been detected, it can be automatically reset within the differential function. It is not possible to externally reset open CT condition. To reset the open CT circuit alarm automatically, the following conditions must be fulfilled: Bias current is for at least one minute smaller than 110% Open CT condition in defective CT circuit has been rectified (for example, current asymmetry disappears) Above two conditions are fulfilled for longer time than defined by the setting parameter tOCTResetDelay
After the reset, the open CT detection algorithm starts again to search for any other open CT circuit within the protected zone.
5.2.2.2
Logic diagram
The simplified internal logics, for transformer differential protection are shown in the following figures.
IED
ADM Trafo Data
Phasor calculation of individual phase current
ID_A
Differential function
52
Instantaneous (sample based) Differential current, phase B Instantaneous (sample based) Differential current, phase C
ID_B
ID_C
Negative sequence diff current & NS current contribution from individual windings
IDMAG_NS
152
Fundamental frequency (phasor based) Diff current, phase A & phase current contributions from individual windings Fundamental frequency (phasor based) Diff current, phase B & phase current contributions from individual windings Fundamental frequency (phasor based) Diff current, phase C & phase current contributions from individual windings
IDMAG_A
IDMAG_B
IDMAG_C
MAX
IBIAS
Figure 65:
Figure 65 shows how internal treatment of measured currents is done in case of twowinding transformer.
The following currents are inputs to the power transformer differential protection function. They must all be expressed in true power system (primary) A, that is, as measured. 1. 2. 3. Instantaneous values of currents (samples) from HV, and LV sides for twowinding power transformers, and from the HV, the first LV, and the second LV sides for three-winding power transformers. Currents from all power transformer sides expressed as fundamental frequency phasors, with their real, and imaginary parts. These currents are calculated within the protection function by the fundamental frequency Fourier filters. Negative sequence currents from all power transformer sides expressed as phasors. These currents are calculated within the protection function by the symmetrical components module.
The power transformer differential protection: 1. Calculates three fundamental frequency differential currents, and one common bias current. The zero-sequence component can optionally be eliminated from each of the three fundamental frequency differential currents, and at the same time from the common bias current. Calculates three instantaneous differential currents. They are used for harmonic, and waveform analysis. Instantaneous differential currents are useful for post-fault analysis using disturbance recording Calculates negative-sequence differential current. Contributions to it from both (all three) power transformer sides are used by the internal/external fault discriminator to detect and classify a fault as internal or external.
2. 3.
b>a
AND
TRIPUNRE_A
AND
AND OR
IDA 2nd Harmonic 5th Harmonic Wave block Cross Block from B or C phases CrossBlockEn=Enabled
TRIPRES_A
NOT
BLK2H_A BLK5H_A BLKWAV_A
AND
OR
AND
ANSI05000168_2_en.vsd
ANSI05000168 V2 EN
Figure 66:
EXTFAULT INTFAULT
OpNegSeqDiff=On
IBIAS
a b
AND
t 0
TRNSSENS
b>a
Constant
BLKNSSEN BLKNSUNR BLOCK PU_A PU_B PU_C
AND OR
TRNSUNR
en05000167_ansi.vsd
ANSI05000167 V1 EN
Figure 67:
Transformer differential protection simplified logic diagram for external/ internal fault discriminator
OR
TRIPRES
OR
TRIPUNRE
TRNSSENS TRNSUNR
OR
TRIP
en05000278_ansi.vsd
ANSI05000278 V1 EN
Figure 68:
PU_A PU_B PU_C BLK2H_A BLK2H_B BLK2H_C BLK5H_A BLK5H_B BLK5H_C BLKWAV_A BLKWAV_B BLKWAV_C
OR
PICKUP
OR
BLK2H
OR
BLK5H
OR
BLKWAV
en05000279_ansi.vsd
ANSI05000279 V1 EN
Figure 69:
Logic in figures 66, 67, 68 and 69 can be summarized as follows: 1. The three fundamental frequency differential currents are applied in a phase-wise manner to two limits. The first limit is the operate-restrain characteristic, while the other is the high-set unrestrained limit. If the first limit is exceeded, a pickup signal PICKUP is set. If the unrestrained limit is exceeded, an immediate unrestrained trip TRIPUNRE and common trip TRIP are issued. If a pickup signal is issued in a phase, then the harmonic-, and the waveform block signals are checked. Only a pickup signal, which is free of all of its respective block signals, can result in a trip command. If the cross-block logic scheme is applied, then only if all phases with set pickup signal are free of their respective block signals, a restrained trip TRIPRES and common trip TRIP are issued If a pickup signal is issued in a phase, and the fault has been classified as internal, then any eventual block signals are overridden and a unrestrained negativesequence trip TRNSUNR and common trip TRIP are issued without any further delay. This feature is called the unrestrained negative-sequence protection 110% bias. The sensitive negative sequence differential protection is independent of any pickup signals. It is meant to detect smaller internal faults, such as turn-to-turn faults, which are often not detected by the traditional differential protection. The sensitive negative sequence differential protection pickup whenever both contributions to the total negative sequence differential current (that must be compared by the internal/external fault discriminator) are higher than the value of the setting IMinNegSeq. If a fault is positively recognized as internal, and the condition is stable with no interruption for at least one fundamental frequency cycle the sensitive negative sequence differential protection TRNSSENS and
165 Technical reference manual
2.
3.
4.
5.
6.
common trip TRIP are issued. This feature is called the sensitive negative sequence differential protection. If a pickup signal is issued in a phase (see signal PU_A), even if the fault has been classified as an external fault, then the instantaneous differential current of that phase (see signal ID_A) is analyzed for the 2nd and the 5th harmonic contents (see the blocks with the text inside: 2nd Harmonic; Wave block and 5th Harmonic). If there is less harmonic pollution, than allowed by the settings I2/I1Ratio, and I5/ I1Ratio, (then the outputs from the blocks 2nd harmonic and 5th harmonic is 0) then it is assumed that a minor simultaneous internal fault must have occurred. Only under these conditions a trip command is allowed (the signal TRIPRES_A is = 1). The cross-block logic scheme is automatically applied under such circumstances. (This means that the cross block signals from the other two phases B and C is not activated to obtain a trip on the TRIPRES_A output signal in figure 66) All pickup and blocking conditions are available as phase segregated as well as common (that is three-phase) signals.
a a>b b
a a>b b &
0-tAlarmDelay 0
IDALARM
a a>b b
ANSI06000546-2-en.vsd
ANSI06000546 V2 EN
Figure 70:
5.2.3
Figure 71:
T3WPDIF (87T) I3PW1CT1* TRIP I3PW1CT2* TRIPRES I3PW2CT1* TRIPUNRE I3PW2CT2* TRNSUNR I3PW3CT1* TRNSSENS I3PW3CT2* PICKUP TAPOLTC1 PU_A TAPOLTC2 PU_B OLTC1AL PU_C OLTC2AL BLK2H BLOCK BLK2H_A BLKRES BLK2H_B BLKUNRES BLK2H_C BLKNSUNR BLK5H BLKNSSEN BLK5H_A BLK5H_B BLK5H_C BLKWAV BLKWAV_A BLKWAV_B BLKWAV_C IDALARM OPENCT OPENCTAL ID_A ID_B ID_C IDMAG_A IDMAG_B IDMAG_C IBIAS IDMAG_NS ANSI06000250-2-en.vsd
ANSI06000250 V2 EN
Figure 72:
5.2.4
Table 68:
Name TRIP TRIPRES TRIPUNRE TRNSUNR TRNSSENS PICKUP PU_A PU_B PU_C BLK2H BLK2H_A BLK2H_B BLK2H_C BLK5H BLK5H_A BLK5H_B BLK5H_C BLKWAV BLKWAV_A BLKWAV_B BLKWAV_C IDALARM OPENCT OPENCTAL ID_A ID_B ID_C
Magnitude of fundamental frequency differential current, phase A Magnitude of fundamental frequency differential current, phase B Magnitude of fundamental frequency differential current, phase C Magnitude of the bias current, which is common to all phases Magnitude of the negative sequence differential current
Table 69:
Name I3PW1CT1 I3PW1CT2 I3PW2CT1 I3PW2CT2 I3PW3CT1 I3PW3CT2 TAPOLTC1 TAPOLTC2 OLTC1AL OLTC2AL BLOCK BLKRES BLKUNRES BLKNSUNR BLKNSSEN
Table 70:
Name TRIP TRIPRES TRIPUNRE TRNSUNR TRNSSENS PICKUP PU_A PU_B PU_C BLK2H BLK2H_A BLK2H_B BLK2H_C BLK5H BLK5H_A BLK5H_B BLK5H_C BLKWAV BLKWAV_A BLKWAV_B BLKWAV_C IDALARM OPENCT OPENCTAL ID_A ID_B ID_C IDMAG_A IDMAG_B
Magnitude of fundamental frequency differential current, phase C Magnitude of the bias current, which is common to all phases Magnitude of the negative sequence differential current
5.2.5
Table 71:
Name Operation SOTFMode tAlarmDelay IDiffAlarm IdMin IdUnre CrossBlockEn NegSeqDiffEn IMinNegSeq NegSeqROA
Setting parameters
T2WPDIF (87T) Group settings (basic)
Values (Range) Disabled Enabled Disabled Enabled 0.000 - 60.000 0.05 - 1.00 0.05 - 0.60 1.00 - 50.00 Disabled Enabled Disabled Enabled 0.02 - 0.20 30.0 - 120.0 Unit s IB IB IB IB Deg Step 0.001 0.01 0.01 0.01 0.01 0.1 Default Disabled Enabled 10.000 0.20 0.30 10.00 Enabled Enabled 0.04 60.0 Description Operation Disable / Enable Operation mode for switch onto fault Time delay for diff currents alarm level Dif. cur. alarm, multiple of base curr, usually W1 curr. Section1 sensitivity, multi. of base curr, usually W1 curr. Unrestrained protection limit, multiple of Winding 1 rated current Operation Off/On for cross-block logic between phases Operation Off/On for neg. seq. differential protections Negative sequence current must be higher than this level to be used Operate Angle for internal / external negative sequence fault discriminator
Table 72:
Name EndSection1 EndSection2 SlopeSection2 SlopeSection3 I2/I1Ratio
Table 73:
Name RatedVoltageW1 RatedVoltageW2 RatedCurrentW1 RatedCurrentW2 ConnectTypeW1 ConnectTypeW2 ClockNumberW2
A A
1 1
Enable zer. seq. current subtraction for W1 side, On / Off Enable zer. seq. current subtraction for W2 side, On / Off Two CT inputs (T-config.) for winding 1, YES / NO CT primary rating in A, T-branch 1, on transf. W1 side CT primary in A, T-branch 2, on transf. W1 side
Two CT inputs (T-config.) for winding 2, YES / NO CT primary rating in A, T-branch 1, on transf. W2 side CT primary rating in A, T-branch 2, on transf. W2 side Transformer winding where OLTC1 is located
1 1 1 1 0.01
1 6 11 1 1.00
OLTC1 lowest tap position designation (e.g. 1) OLTC1 rated tap/mid-tap position designation (e.g. 6) OLTC1 highest tap position designation (e.g. 11) OLTC1 end-tap position with winding highest no-load voltage Voltage change per OLTC1 step in percent of rated voltage
Table 74:
Name Operation SOTFMode tAlarmDelay IDiffAlarm IdMin IdUnre CrossBlockEn NegSeqDiffEn IMinNegSeq NegSeqROA
Table 75:
Name EndSection1 EndSection2 SlopeSection2 SlopeSection3 I2/I1Ratio I5/I1Ratio OpenCTEnable tOCTAlarmDelay tOCTResetDelay tOCTUnrstDelay
Table 76:
Name RatedVoltageW1 RatedVoltageW2 RatedVoltageW3 RatedCurrentW1 RatedCurrentW2 RatedCurrentW3 ConnectTypeW1 ConnectTypeW2 ConnectTypeW3
ClockNumberW3
ZSCurrSubtrW1 ZSCurrSubtrW2 ZSCurrSubtrW3 TconfigForW1 CT1RatingW1 CT2RatingW1 TconfigForW2 CT1RatingW2 CT2RatingW2 TconfigForW3 CT1RatingW3 CT2RatingW3
A A A A A A
1 1 1 1 1 1
Enable zer. seq. current subtraction for W1 side, On / Off Enable zer. seq. current subtraction for W2 side, On / Off Enable zer. seq. current subtraction for W3 side, On / Off Two CT inputs (T-config.) for winding 1, YES / NO CT primary rating in A, T-branch 1, on transf. W1 side CT primary in A, T-branch 2, on transf. W1 side Two CT inputs (T-config.) for winding 2, YES / NO CT primary rating in A, T-branch 1, on transf. W2 side CT primary rating in A, T-branch 2, on transf. W2 side Two CT inputs (T-config.) for winding 3, YES / NO CT primary rating in A, T-branch 1, on transf. W3 side CT primary rating in A, T-branch 2, on transf. W3 side
Name LocationOLTC1
% -
1 1 1 1 0.01 -
OLTC1 lowest tap position designation (e.g. 1) OLTC1 rated tap/mid-tap position designation (e.g. 6) OLTC1 highest tap position designation (e.g. 11) OLTC1 end-tap position with winding highest no-load voltage Voltage change per OLTC1 step in percent of rated voltage Transformer winding where OLTC2 is located
1 1 1 1 0.01
1 6 11 1 1.00
OLTC2 lowest tap position designation (e.g. 1) OLTC2 rated tap/mid-tap position designation (e.g. 6) OLTC2 highest tap position designation (e.g. 11) OLTC2 end-tap position with winding highest no-load voltage Voltage change per OLTC2 step in percent of rated voltage
5.2.6
Technical data
Table 77:
Function Operating characteristic Reset ratio Unrestrained differential current limit Base sensitivity function Second harmonic blocking
Connection type for each of the windings Table continues on next page
25 ms typically at 0 to 2 x set level 20 ms typically at 2 to 0 x set level 12 ms typically at 0 to 5 x set level 25 ms typically at 5 to 0 x set level 2 ms typically at 0 to 5 x Ib
5.3
IdN/I
SYMBOL-AA V1 EN
5.3.1
Introduction
Restricted fault protection, low-impedance function (REFPDIF, 87N) can be used on all solidly or low-impedance grounded windings. The REFPDIF (87N) function provides high sensitivity and high speed tripping as it protects each winding separately and thus does not need inrush stabilization. The low-impedance function is a percentage biased function with an additional zero sequence current directional comparison criterion. This gives excellent sensitivity and stability during through faults. REFPDIF can also protect autotransformers. In this case, the negative sequence current directional comparison must be used. The most typical and the most complicated configuration of an autotransformer is shown in figure 73. Five currents are measured in the case illustrated in figure 73.
CT
CT CB CB
YNdx
CT CB
d
CB Autotransformer
IED
CT
CT
CB
CB
CT
IEC05000058-2 V1 EN
Figure 73:
5.3.2
5.3.2.1
Operation principle
Fundamental principles of the restricted groundfault protection
Restricted earth-fault protection, low impedance function (REFPDIF, 87N) must detect ground faults on grounded power transformer windings. REFPDIF (87N) is a unit protection of differential type. Since REFPDIF (87N) is based on the zero sequence currents, which theoretically only exist in case of a ground-fault, the REFPDIF (87N) can be made very sensitive; regardless of normal load currents. It is the fastest protection a power transformer winding can have. It must be borne in mind, however, that the high sensitivity, and the high speed, tend to make such a protection instable, and special measures must be taken to make it insensitive to conditions, for which it should not operate, for example heavy through faults of phase-to-phase type, or heavy external ground faults. REFPDIF (87N) is of low impedance type. All three phase power transformer terminal currents, and the power transformer neutral point current, must be fed separately to REFPDIF (87N). These input currents are then conditioned within REFPDIF (87N) by mathematical tools. Fundamental frequency components of all currents are extracted from all input currents, while other eventual zero sequence components (for example, the 3rd harmonic currents) are fully suppressed. Then the residual current phasor is constructed from the three line current phasors. This zero sequence current phasor is then vectorially added to the neutral current, in order to obtain differential current.
The following facts may be observed from the figure 74 and the figure 75 (where the three-phase line CTs are lumped into a single 3Io current, for the sake of simplicity).
ROA (Relay Operate Angle) ROA = 60 deg IN REFPDIF never operates for any faults external to the protected zone. Currents 3Io and IN are theoretically 180o out of phase for any external ground-fault.
ANSI05000724 V3 EN
Figure 74:
Uzs
Uzs
IN
ANSI05000725 V3 EN
Figure 75:
180
1.
2.
3. 4.
For an external ground fault, (figure 74) the residual current 3Io and the neutral conductor current IN have equal magnitude, but they are 180 degree out-of-phase due to internal CT reference directions used in the IED. This is easy to understand, as both CTs ideally measure exactly the same component of the ground fault current. For an internal fault, the total ground-fault current is composed generally of two zero sequence components. One zero sequence component (that is, 3IZS1) flows towards the power transformer neutral point and into the ground, while the other zero sequence component (that is, 3IZS2) flows out into the connected power system. These two primary currents can be expected to be of approximately opposite directions (about the same zero sequence impedance angle is assumed on both sides of the ground-fault). However, on the secondary CT sides they will be approximately in phase due to internal CT reference directions used in the IED. The magnitudes of the two components may be different, dependent on the magnitudes of zero sequence impedances of both sides. No current can flow towards the power system, if the only point where the system is grounded, is at the protected power transformer. Likewise, no current can flow into the power system, if the winding is not connected to the power system (circuit breaker open and power transformer energized from the other side). For both internal and external ground faults, the current in the neutral connection IN has always the same direction, that is, towards the ground. The two measured zero sequence current are 3Io and IN. The vectorial sum between them is the REFPDIF (87N) differential current, which is equal to Idiff = IN +3Io.
Since REFPDIF (87N) is a differential protection where the line zero sequence (residual) current is constructed from 3 line (terminal) currents, a bias quantity must give stability against false operations due to high through fault currents. An operate bias characteristic (only one) has been devised to the purpose. It is not only external ground faults that REFPDIF (87N) should be stable against, but also heavy phase-to-phase faults, not including ground. These faults may also give rise to false zero sequence currents due to saturated line CTs. Such faults, however, produce no neutral current, and can thus be eliminated as a source of danger, at least during the fault. As an additional measure against unwanted operation, a directional check is made in agreement with the above points 1, and 2. An operation is only allowed if currents 3Io and IN (as shown in figure 74 and the figure 75) are both within the operating region. By taking a smaller ROA, REFPDIF (87N) can be made more stable under heavy external fault conditions, as well as under the complex conditions, when external faults are cleared by other protections.
The differential protection, REFPDIF (87N) calculates a differential current and a bias current. In case of internal ground-faults, the differential current is theoretically equal to the total ground-fault current. The bias current is supposed to give stability to REFPDIF(87N). The bias current is a measure of how high the currents are, or better, a measure of how difficult the conditions are under which the CTs operate. The higher the bias, the more difficult conditions can be suspected, and the more likely that the calculated differential current has a component of a false current, primarily due to CT saturation. This law is formulated by the operate-bias characteristic. This characteristic divides the Idiff - Ibias plane into two parts. The part above the operate bias characteristic is the so called operate area, while that below is the block area, see the figure 76.
operate current in pu
4
Base Sensitivity Idmin
operate
*************************************
Range : 5 % to 50 % rated current Step : 1 % transformer rated current
zone 1
zone 2
second slope
1
minimum base sensitivity 50 % default base sensitivity 30 % maximum base sensitivity 5 % first slope 0 1 2 1.25 pu 3 4 block 5 6
IEC98000017 V3 EN
Figure 76:
Operate - bias characteristic of the Restricted ground-fault protection, low impedance REFPDIF (87N)
5.3.2.3
Idiff = IN + 3 Io
EQUATION1533 V1 EN
(Equation 30)
where: IN 3Io current in the power transformer neutral as a fundamental frequency phasor, residual current of the power transformer line (terminal) currents as a phasor.
If there are two three-phase CT inputs on the HV winding side for REFPDIF (87N) (such as in breaker-and-a-half configurations), then their respective residual currents are added within REFPDIF (87N) function so that: I3PW1 = I3PW1CT1 + I3PW1CT2
183 Technical reference manual
where the signals are defined in the input and output signal tables for REFPDIF (87N). The bias current is a measure (expressed as a current in Amperes) of how difficult the conditions are under which the instrument current transformers operate. Dependent on the magnitude of the bias current, the corresponding zone (section) of the operate - bias characteristic is applied, when deciding whether to trip, or not to trip. In general, the higher the bias current, the higher the differential current required to produce a trip. The bias current is the highest current of all separate input currents to REFPDIF (87N), that is, of current in phase A, phase B, phase C, and the current in the neutral point (designated as IN in the figure 74 and in the figure 75). If there are 2 feeders included in the zone of protection of REFPDIF (87N), then the respective bias current is found as the relatively highest of the following currents:
current[1] = max (I3PW1CT1)
EQUATION1526 V1 EN
1 CTFactorPri1
(Equation 31)
1 CTFactorPri2
(Equation 32)
1 CTFactorSec1
(Equation 33)
1 CTFactorSec2
(Equation 34)
current[5] = IN
EQUATION1530 V1 EN
(Equation 35)
The bias current is thus generally equal to none of the input currents. If all primary ratings of the CTs were equal to IBase, then the bias current would be equal to the highest current in Amperes. IBase shall be set equal to the rated current of the protected winding where REFPDIF (87N) function is applied.
5.3.2.4
overcurrent, or ground fault protection, and so on. The conditions during a heavy external fault, and particularly immediately after the clearing of such a fault may be complex. The circuit breakers poles may not open exactly at the same moment, some of the CTs may still be highly saturated, and so on. The detection of external ground faults is based on the fact that for such a fault a high neutral current appears first, while a false differential current only appears if one or more current transformers saturate. An external ground fault is thus assumed to have occurred when a high neutral current suddenly appears, while at the same time the differential current Idiff remains low, at least for a while. This condition must be detected before a trip request is placed within REFPDIF (87N). Any search for external fault is aborted if a trip request has been placed. A condition for a successful detection is that it takes not less than 4ms for the first CT to saturate. For an internal ground fault, a true differential current develops immediately, while for an external fault it only develops if a CT saturates. If a trip request comes first, before an external fault could be positively established, then it must be an internal fault. If an external ground fault has been detected, then the REFPDIF (87N) is temporarily desensitized.
Directional criterion
The directional criterion is applied in order to positively distinguish between internaland external ground faults. This check is an additional criterion, which should prevent malfunctions at heavy external ground faults, and during the disconnection of such faults by other protections. Ground faults on lines connecting the power transformer occur much more often than ground faults on a power transformer winding. It is important therefore that the Restricted ground faults protection, low impedance (REFPDIF,87N) must remain stable during an external fault, and immediately after the fault has been cleared by some other protection. For an external ground faults with no CT saturation, the residual current in the lines (3Io) and the neutral current (IN in the figure 74) are theoretically equal in magnitude and are 180 degree out-of-phase. The current in the neutral (IN) serves as a directional reference because it has the same direction for both internal and external ground faults. The directional criterion in REFPDIF (87N) protection makes it a current-polarized protection. If one or more CTs saturate, then the measured currents 3Io and IN may no more be equal, nor will their positions in the complex plane be exactly 180 degree apart. There is a risk that the resulting false differential current Idiff enters the operate area when clearing the external fault. If this happens, a directional test may prevent a malfunction. A directional check is only executed if:
185 Technical reference manual
1. 2.
a trip request signal has been issued, REFPDIF (87N) function PICKUP signal set to 1) if the residual current in lines (3Io) is at least 3% of the IBase current.
If a directional check is either unreliable or not possible to do, due to too small currents, then the direction is cancelled as a condition for an eventual trip. If a directional check is executed, the REFPDIF (87N) protection operation is only allowed if currents 3Io and IN (as seen in figure 74 and figure 75) are both within the operating region.
RCA = 0 degrees = constant; where RCA stands for Relay Characteristic Angle ROA = 60 to 90 degrees; where ROA stands for Relay Operate Angle.
RCA determines a direction MTA (Maximum Torque Angle) where the line residual current 3Io must lie for an internal ground fault, while ROA sets a tolerance margin.
At energizing of a transformer, a false differential current may appear in restricted earthfault protection, low impedance function (REFPDIF 87N). The phase CTs may saturate due to a high dc-component with long duration but the current through the neutral CT does not have either the same dc-component or the same magnitude and the risk for saturation in this CT is not as high. The differential current due to the saturation may be so high that it reaches the operate characteristic. A calculation of the content of 2nd harmonic in the neutral current is made when neutral current, residual current and bias current are within some windows and some timing criteria are fulfilled. If the ratio between second and fundamental harmonic exceeds 60%, REFPDIF (87N) is blocked.
5.3.2.5
6. 7.
8.
9.
current. If an external ground fault has been detected, a flag is set which remains set until the external fault has been cleared. The external fault flag is reset to 0 when Ineutral falls below 50% of the base sensitivity Idmin. Any search for external fault is aborted if trip request counter is more than 0. For as long as the external fault persists an additional temporary trip condition is introduced. That means that REFPDIF (87N) is temporarily desensitized. If point P(Ibias, Idiff) is found to be above the operate - bias characteristic), so that trip request counter is becomes more than 0, a directional check can be made. The directional check is made only if Iresidual (3Io) is more than 3% of the IBase current. If the result of the check means external fault, then the internal trip request is reset. If the directional check cannot be executed, then direction is no longer a condition for a trip. When neutral current, residual current and bias current are within some windows and some timing criteria are fulfilled, the ratio of 2nd to fundamental tone is calculated. If it is found to be above 60% the trip request counter is reset and TRIP remains zero. Finally, a check is made if the trip request counter is equal to, or higher than 2. If it is, and that at the same instance of time tREFtrip, the actual bias current at this instance of time tREFtrip is at least 50% of the highest bias current Ibiasmax (Ibiasmax is the highest recording of any of the three phase currents measured during the disturbance) then REFPDIF (87N) sets output TRIP to 1. If the counter is less than 2, TRIP signal remains 0.
5.3.3
Function block
REFPDIF (87N) I3P* TRIP I3PW1CT1* PICKUP I3PW1CT2* DIR_INT I3PW2CT1* BLK2H I3PW2CT2* IRES BLOCK IN IBIAS IDIFF ANGLE 2NDHARM ANSI06000251-2-en.vsd
ANSI06000251 V2 EN
Figure 77:
Table 80:
Name TRIP START DIROK BLK2H IRES IN IBIAS IDIFF ANGLE I2RATIO
5.3.5
Table 81:
Name Operation IBase IdMin CTFactorPri1
Setting parameters
REFPDIF (87N) Group settings (basic)
Values (Range) Disabled Enabled 1 - 99999 4.0 - 100.0 1.0 - 10.0 Unit A %IB Step 1 0.1 0.1 Default Disabled 3000 10.0 1.0 Description Disable/Enable Operation Base current Maximum sensitivity in % of IBase CT factor for HV side CT1 (CT1rated/ HVrated current)
Table 82:
Name ROA
5.3.6
Technical data
Table 83:
Function Operate characteristic
Operate time, trip function Reset time, trip function Second harmonic blocking
5.4
HZPDIF
Id
SYMBOL-CC V2 EN
87
5.4.2
Introduction
The 1Ph High impedance differential protection (HZPDIF, 87) function can be used when the involved CTs have the same turns ratio and similar magnetizing characteristics. It utilizes an external CT current summation by wiring, a series resistor, and a voltage dependent resistor which are mounted externally connected to the IED. HZPDIF (87) can be used to protect generator stator windings, tee-feeders or busbars. Six single phase function blocks are available to allow application for two three-phase zones busbar protection.
5.4.3
Principle of operation
The 1Ph High impedance differential protection (HZPDIF, 87) function is based on one current input with external stabilizing resistor and voltage dependent resistor. Three functions can be used to provide a three phase differential protection function. The stabilizing resistor value is calculated from the IED function operating value V TripPickup calculated to achieve through fault stability. The supplied stabilizing resistor has a link to allow setting of the correct resistance value . See the application manual for operating voltage and sensitivity calculation.
5.4.3.1
Logic diagram
The logic diagram shows the operation principles for the 1Ph High impedance differential protection function HZPDIF (87), see figure 78. It is a simple one step IED function with an additional lower alarm level. By activating inputs, the HZPDIF (87) function can either be blocked completely, or only the trip output.
AlarmPickup 0-tAlarm 0
AlarmPickup 0.03s 0
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ANSI05000301 V1 EN
Figure 78:
Logic diagram for 1Ph High impedance differential protection HZPDIF (87)
5.4.4
Function block
HZPDIF (87) ISI* BLOCK BLKTR TRIP ALARM MEASVOLT ANSI05000363-2-en.vsd
ANSI05000363 V2 EN
Figure 79:
5.4.5
Table 85:
Name TRIP ALARM MEASVOLT
5.4.6
Table 86:
Name Operation AlarmPickup tAlarm TripPickup R series
Setting parameters
HZPDIF (87) Group settings (basic)
Values (Range) Disabled Enabled 2 - 500 0.000 - 60.000 5 - 900 10 - 20000 Unit V s V ohm Step 1 0.001 1 1 Default Disabled 10 5.000 100 250 Description Disable/Enable Operation Alarm voltage level on CT secondary Time delay to activate alarm Pickup voltage level in volts on CT secondary side Value of series resistor in Ohms
5.4.7
Technical data
Table 87:
Function Operate voltage Reset ratio Maximum continuous power Operate time Reset time Critical impulse time
Section 6
Impedance protection
6.1
S00346 V1 EN
6.1.1
Introduction
The numerical mho line distance protection is a, up to four zone full scheme protection for back-up detection of short circuit and ground faults. The four zones have fully independent measuring and settings, which gives high flexibility for all types of lines.
The function can be used as under impedance back-up protection for transformers and generators.
Principle of operation
Full scheme measurement
The execution of the different fault loops within the IED are of full scheme type, which means that each fault loop for phase-to-ground faults and phase-to-phase faults are executed in parallel. The use of full scheme technique gives faster operation time compared to switched schemes which mostly uses a phase selector element to select correct voltages and current depending on fault type. So each distance protection zone performs like one independent distance protection function with six measuring elements.
6.1.2.2
Impedance characteristic
The distance function consists of four instances. Each instance can be selected to be either forward or reverse with positive sequence polarized mho characteristic alternatively self polarized offset mho characteristics with reverse offset. The operating characteristic is in accordance to figure 80.
jx X Mho, zone4 Mho, zone3 Zs=0 Mho, zone2 Mho, zone1 R
Zs=Z1 Zs=2Z1
IEC11000223-1-en.vsd
IEC11000223 V1 EN
Figure 80:
Mho characteristic and the source impedance influence on the mho characteristic
The mho characteristic has a dynamic expansion due to the source impedance. Instead of crossing the origin as for the mho to the left of figure 80, which is only valid where
194 Technical reference manual
the source impedance is zero, the crossing point is moved to the coordinates of the negative source impedance given an expansion of the circle shown to the right of figure 80. The polarization quantities used for the mho circle are 100% memorized positive sequence voltages. This will give a somewhat less dynamic expansion of the mho circle during faults. However, if the source impedance is high, the dynamic expansion of the mho circle might lower the security of the function too much with high loading and mild power swing conditions. The mho distance element has a load encroachment function which cuts off a section of the characteristic when enabled. The function is enabled by setting the setting parameter LoadEnchMode to Enabled. Enabling of the load encroachment function increases the possibility to detect high resistive faults without interfering with the load impedance. The algorithm for the load encroachment is located in the Faulty phase identification with load encroachment for mho function FMPSPDIS (21), where also the relevant settings can be found. Information about the load encroachment from FMPSPDIS (21) to the zone measurement is given in binary format to the input signal LDCND.
6.1.2.3
The zone reach for phase-to-ground fault and phase-to-phase fault is set individually in polar coordinates. The impedance is set by the parameters ZPG and ZPP and the corresponding angles by the parameters ZAngPG and ZAngPP. Compensation for ground-return path for faults involving ground is done by setting the parameter KNMag and KNAng where KNMag is the magnitude of the ground-return path and KNAng is the difference of angles between KNMag and ZPG.
KNMag =
EQUATION1579 V1 EN
Z0-Z1 3 Z1
(Equation 36)
KNAng = ang
EQUATION1807-ANSI V1 EN
Z 0 - Z1 3 Z1
)
(Equation 37)
where Z0 Z1 is the complex zero sequence impedance of the line in /phase is the complex positive sequence impedance of the line in /phase
The phase-to-ground and phase-to-phase measuring loops can be time delayed individually by setting the parameter tPG and tPP respectively. To release the time delay, the operation mode for the timers, OpModetPG and OpModetPP, has to be set to On. This is also the case for instantaneous operation. The operate timers triggering input can be selected by setting the parameter ZnTimerSel. The parameter ZnTimerSel can be set to: Timers seperated: Phase-to-ground and phase-to-phase timers are triggered by the respective measuring loop start signals. Timers linked: Start of any of the phase-to-ground or phase-to-phase loops will trigger both the phase-to-ground or phase-to-phase timers. Internal start: Phase-to-ground and phase-to-phase timers are triggered by the INTRNST input. Start from PhSel: The phase-to-ground and phase-to-phase timers are triggered by the DIRCND, STCND, LDCND inputs. Each of the three inputs consist binary
status information related to the six measuring loops. Hence if any of the measuring loop status is High, then the timers will be triggered. External start: Phase-to-ground and phase-to-phase timers are triggered by the EXTNST input.
The function can be blocked in the following ways: activating of input BLOCK blocks the whole function activating of the input BLKZ (fuse failure) blocks all output signals activating of the input BLKZMTD blocks the delta based algorithm activating of the input BLKHSIR blocks the high speed part of the algorithm for high SIR values activating of the input BLKTRIP blocks all output signals activating the input BLKPG blocks the phase-to-ground fault loop outputs activating the input BLKPP blocks the phase-to-phase fault loop outputs
The activation of input signal BLKZ can be made by external fuse failure function or from the loss of voltage check in the Mho supervision logic (ZSMGAPC). In both cases the output BLKZ in the Mho supervision logic shall be connected to the input BLKZ in the Mho distance function block (ZMHPDIS, 21) The input signal BLKZMTD is activated during some ms after fault has been detected by ZSMGAPC to avoid unwanted operations due to transients. It shall be connected to the BLKZMTD output signal of ZSMGAPC function. At SIR values >10, the use of electronic CVT might cause overreach due to the built-in resonance circuit in the CVT, which reduce the secondary voltage for a while. The input BLKHSIR shall be connected to the output signal HSIR on ZSMGAPC for increasing of the filtering and high SIR values. This is valid only when permissive underreach scheme is selected by setting ReachMode=Underreach.
6.1.2.4
Theory of operation
The mho algorithm is based on the phase comparison of a operating phasor and a polarizing phasor. When the operating phasor leads the reference polarizing phasor by more than 90 degrees, the function operates and gives a trip output.
Phase-to-phase fault
Mho The plain mho circle has the characteristic as in figure 81. The condition for deriving the angle is according to equation 38.
(Equation 38)
where
V AB
EQUATION1790-ANSI V1 EN
I AB
EQUATION1791-ANSI V1 EN
is the current vector difference between phases A and B is the positive sequence impedance setting for phase-to-phase fault is the polarizing voltage
ZPP Vpol
The polarized voltage consists of 100% memorized positive sequence voltage (VAB for phase A to B fault). The memorized voltage will prevent collapse of the mho circle for close in faults. Operation occurs if 90270
IABX
I AB ZPP
V pol
V AB
IABR
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Figure 81:
Simplified mho characteristic and vector diagram for phase A-to-B fault
Offset Mho The characteristic for offset mho is a circle where two points on the circle are the setting parameters ZPP and ZRevPP. The vector ZPP in the impedance plane has the settable angle AngZPP and the angle for ZRevPP is AngZPP+180. The condition for operation at phase-to-phase fault is that the angle between the two compensated voltages Vcomp1 and Vcomp2 is greater than or equal to 90 (figure 82). The angle will be 90 for fault location on the boundary of the circle. The angle for A-to-B fault can be defined according to equation 39.
b = arg
EQUATION1792-ANSI V1 EN
where
V
EQUATION1801 V1 EN
is the VAB voltage is the positive sequence impedance setting for phase-to-phase fault in reverse direction
ZRevPP
IABjX
I AB ZPP
Vcomp2 = V
=IFZF =VAB
IABR
- I AB
Z Re vPP
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ANSI07000110 V1 EN
Figure 82:
Simplified offset mho characteristic and voltage vectors for phase A-toB fault.
Operation occurs if 90270. Offset mho, forward direction When forward direction has been selected for the offset mho, an extra criteria beside the one for offset mho (90<<270) is introduced, that is the angle between the voltage and the current must lie between the blinders in second quadrant and fourth quadrant. See figure 83. Operation occurs if 90270 and ArgDirArgNegRes.
200 Technical reference manual
where
ArgDir ArgNegRes
is the setting parameter for directional line in fourth quadrant in the directional element, ZDMRDIR (21D). is the setting parameter for directional line in second quadrant in the directional element, ZDMRDIR (21D). is calculated according to equation 39
The directional information is brought to the mho distance measurement from the mho directional element as binary coded information to the input DIRCND. See Directional impedance element for mho characteristic (ZDMRDIR ,21D) for information about the mho directional element.
IABjX
ZPP
VAB
ArgNegRes
IAB
ArgDir
en07000111_ansi
ANSI07000111 V1 EN
Figure 83:
Simplified offset mho characteristic in forward direction for phase A-toB fault
Offset mho, reverse direction The operation area for offset mho in reverse direction is according to figure 84. The operation area in second quadrant is ArgNegRes+180. Operation occurs if 90270 and 180 - ArgDir ArgNegRes + 180
The is derived according to equation 39 for the mho circle and is the angle between the voltage and current.
X ZPP
ArgNegRes
IAB
ArgDir
VAB
ZRevPP
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ANSI06000469 V1 EN
Figure 84:
Phase-to-ground fault
Mho The measuring of ground faults uses ground-return compensation applied in a conventional way. The compensation voltage is derived by considering the influence from the ground-return path. For a ground fault in phase A, the compensation voltage Vcomp can be derived, as shown in figure 85.
Vcomp = V
EQUATION1793-ANSI V1 EN
pol
- I A Z loop
(Equation 40)
where Vpol Zloop is the polarizing voltage (memorized VA for Phase A-to- ground fault) is the loop impedance, which in general terms can be expressed as
Z1+ZN = Z 1 1 + KN
EQUATION1799 V1 EN
)
(Equation 41)
where Z1 KN is the positive sequence impedance of the line (Ohm/phase) is the zero-sequence compensator factor
The angle between the Vcomp and the polarize voltage Vpol for a A-to-ground fault is
b = arg V A - I A + IN KN ZPE - arg(Vpol)
EQUATION1592 V1 EN
(Equation 42)
where VA IA IA IN is the phase voltage in faulty phase A is the phase current in faulty phase A is the phase current in faulty phase A is the zero-sequence current in faulty phase A (3I0)
KN
EQUATION1593 V1 EN
Z0-Z1 3 Z1
EQUATION1594 V1 EN
the setting parameter for the zero sequence compensation consisting of the magnitude KN and the angle KNAng. Vpol Vpol is the 100% of positive sequence memorized voltage VA is the 100% of positive sequence memorized voltage VA
IAX IAZN
V comp
I A Z loop
IAZPE Vpol f IA (Ref)
IAR
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ANSI06000472 V1 EN
Figure 85:
Simplified offset mho characteristic and vector diagram for phase A-toground fault
Operation occurs if 90270. Offset mho The characteristic for offset mho at ground fault is a circle containing the two vectors from the origin ZPE and ZRevPE where ZPE and ZrevPE are the setting reach for the positive sequence impedance in forward respective reverse direction. The vector ZPE in the impedance plane has the settable angle AngZPE and the angle for ZRevPP is AngZPE+180. The condition for operation at phase-to-ground fault is that the angle between the two compensated voltages Vcomp1 and Vcomp2 is greater or equal to 90 see figure 86. The angle will be 90 for fault location on the boundary of the circle. The angle for A-to-ground fault can be defined as
IABjX
IA ZPE
V comp1 = VA - IA ZPE
VA
- IA Z RevPe
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ANSI06000465 V1 EN
Figure 86:
Simplified offset mho characteristic and voltage vector for phase A-toground fault
Operation occurs if 90270. Offset mho, forward direction In the same way as for phase-to-phase fault, selection of forward direction of offset mho will introduce an extra criterion for operation. Beside the basic criteria for offset mho according to equation 45 and 90270, also the criteria that the angle between the voltage and the current must lie between the blinders in second and fourth quadrant. See figure 87. Operation occurs if 90270 and ArgDirArgNegRes.
where
ArgDir ArgNegRes
is the setting parameter for directional line in fourth quadrant in the directional element, ZDMRDIR (21D). is the setting parameter for directional line in second quadrant in the directional element, ZDMRDIR (21D). is calculated according to equation 45
IA jX
VA
ArgNegRes
IA
ArgDir
IAR
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ANSI06000466 V1 EN
Figure 87:
Simplified characteristic for offset mho in forward direction for A-toground fault
Offset mho, reverse direction In the same way as for offset in forward direction, the selection of offset mho in reverse direction will introduce an extra criterion for operation compare to the normal offset mho. The extra is that the angle between the fault voltage and the fault current shall lie between the blinders in second and fourth quadrant. The operation area in second quadrant is limited by the blinder defined as 180 -ArgDir and in fourth quadrant ArgNegRes+180, see figure 88. The conditions for operation of offset mho in reverse direction for A-to-ground fault is 90270 and 180-ArgdirArgNegRes+180. The is derived according to equation 45 for the offset mho circle and is the angle between the voltage and current.
X ZPE
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ANSI06000470 V1 EN
Figure 88:
Simplified characteristic for offset mho in reverse direction for A-toground fault
6.1.2.5
One type of function block, ZMHPDIS (21) are used in the IED for zone 1 - 5.
207 Technical reference manual
The PHSEL input signal represents a connection of six different integer values from Phase selection with load encroachment, quadrilateral characteristic function FMPSPDIS (21) within the IED, which are converted within the zone measuring function into corresponding boolean expressions for each condition separately. Input signal PHSEL is connected to FMPSPDIS (21) function output signal PHSCND. The input signal DIRCND is used to give condition for directionality for the distance measuring zones. The signal contains binary coded information for both forward and reverse direction. The zone measurement function filters out the relevant signals depending on the setting of the parameter DirMode. Input signal DIRCND must be configured to the STDIRCND output signal on ZDMRDIR (21D) function.
OffsetMhoDir= Non-directional DirMode=Offset PHSEL AND
AND
AND T F AND
LoadEnchMode= On/Off LDCND True T F AND DIRCND OffsetMhoDir= Forward/Reverse DirMode= Forward/Reverse
Release
AND
BLKZ BLOCK OR
ANSI11000216-1-en.vsd
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Figure 89:
When load encroachment mode is switched on (LoadEnchMode=On) then start signal PHSEL is also checked against LDCND signal. Results of the directional measurement enter the logic circuits, when the zone operates in directional (forward or reverse) mode, as shown in figure 89. Composition of the phase pickup signals is presented in figure 90.
208 Technical reference manual
Release
OR
PHG_FLT
PU_A
PU_B
PU_C
OR
PICKUP PHPH_FLT
OR
ANSI11000217-1-en.vsd
ANSI11000217 V1 EN
Figure 90:
Tripping conditions for the distance protection zone one are symbolically presented in figure 91.
tPP t OR tPG t
ANSI11000218-1-en.vsd
ANSI11000218 V1 EN
Figure 91:
6.1.3
Function block
ZMHPDIS (21) I3P* TRIP V3P* TR_A CURR_INP* TR_B VOLT_INP* TR_C POL_VOLT* TRPG BLOCK TRPP BLKZ PICKUP BLKZMTD PU_A BLKHSIR PU_B BLKTRIP PU_C BLKPG PHG_FLT BLKPP PHPH_FLT DIRCND PHSEL LDCND ANSI06000423-2-en.vsd
ANSI06000423 V2 EN
Figure 92:
6.1.4
Table 89:
Name TRIP TR_A TR_B TR_C TRPG TRPP PICKUP PU_A PU_B PU_C PHG_FLT PHPH_FLT
Setting parameters
ZMHPDIS (21) Group settings (basic)
Values (Range) Disabled Enabled 1 - 99999 0.05 - 2000.00 Disabled Offset Forward Reverse Disabled Enabled Overreach Underreach Disabled Enabled 0.005 - 3000.000 10 - 90 0.00 - 3.00 -180 - 180 0.005 - 3000.000 0.000 - 60.000 10 - 30 Disabled Enabled 0.005 - 3000.000 10 - 90 0.005 - 3000.000 0.000 - 60.000 10 - 30 Unit A kV Step 1 0.05 Default Enabled 3000 400.00 Forward Description Operation Enable/Disable Base current Base voltage Direction mode
LoadEncMode ReachMode OpModePG ZPG ZAngPG KN KNAng ZRevPG tPG IMinPUPG OpModePP ZPP ZAngPP ZRevPP tPP IMinPUPP
Disabled Overreach Enabled 30.000 80 0.80 -15 30.000 0.000 20 Enabled 30.000 85 30.000 0.000 20
Load encroachment mode Off/On Reach mode Over/Underreach Operation mode Disable/Enable of PhaseGround loops Positive sequence impedance setting for Phase-Ground loop Angle for positive sequence line impedance for Phase-Ground loop Magnitud of ground return compensation factor KN Angle for ground return compensation factor KN Reverse reach of the phase to ground loop(magnitude) Delay time for operation of phase to ground elements Minimum operation phase to ground current Operation mode Disable/Enable of PhasePhase loops Impedance setting reach for phase to phase elements Angle for positive sequence line impedance for Phase-Phase elements Reverse reach of the phase to phase loop(magnitude) Delay time for operation of phase to phase Minimum operation phase to phase current
Table 91:
Name OffsetMhoDir
OpModetPG OpModetPP
Enabled Enabled
Operation mode Disable/ Enable of Zone timer, Ph-G Operation mode Off / On of Zone timer, Ph-ph
6.1.6
Technical data
Table 92:
Function Number of zones with selectable directions Minimum operate current Positive sequence impedance, phase-to-ground loop Positive sequence impedance angle, phase-to-ground loop Reverse reach, phase-to-ground loop (Magnitude) Magnitude of ground return compensation factor KN Angle for ground compensation factor KN Dynamic overreach Timers Operate time Reset ratio Reset time
6.2
S00346 V1 EN
6.2.1
Introduction
The phase-to-ground impedance elements can be optionally supervised by a phase unselective directional function based on symmetrical components.
6.2.2
6.2.2.1
Principle of operation
Directional impedance element for mho characteristic ZDMRDIR (21D)
The evaluation of the directionality takes place in Directional impedance element for mho characteristic (ZDMRDIR ,21D). Equation 46 and equation 47 are used to classify that the fault is in the forward direction for phase-to-ground fault and phase-to-phase fault respectively.
- AngDir < Ang
EQUATION1618 V1 EN
0.85 V 1A + 0.15 V 1 AM IA
< AngNeg Re s
(Equation 46)
< AngNeg Re s
(Equation 47)
Where: AngDir AngNegRes V1A V1AM Setting for the lower boundary of the forward directional characteristic, by default set to 15 (= -15 degrees) Setting for the upper boundary of the forward directional characteristic, by default set to 115 degrees, see figure 93 for mho characteristics. Positive sequence phase voltage in phase A Positive sequence memorized phase voltage in phase A
Phase current in phase A Voltage difference between phase A and B (B lagging A) Memorized voltage difference between phase A and B (B lagging A) Current difference between phase A and B (B lagging A)
The default settings for AngDir and AngNegRes are 15 (= -15) and 115 degrees respectively (see figure 93) and they should not be changed unless system studies show the necessity. If one sets DirEvalType to Comparator (which is recommended when using the mho characteristic) then the directional lines are computed by means of a comparator-type calculation, meaning that the directional lines are based on mho-circles (of infinite radius). The default setting value Impedance otherwise means that the directional lines are implemented based on an impedance calculation equivalent to the one used for the quadrilateral impedance characteristics. When Directional impedance element for mho characteristic (ZDMRDIR) is used together with Fullscheme distance protection, mho characteristic (ZMHPDIS) the following settings for parameter DirEvalType is vital: alternative Comparator is strongly recommended alternative Imp/Comp should generally not be used alternative Impedance should not be used. This altenative is intended for use together with Distance protection zone, quadrilateral characteristic (ZMQPDIS)
AngNegRes
-AngDir
-Zs
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Figure 93:
The reverse directional characteristic is equal to the forward characteristic rotated by 180 degrees. The polarizing voltage is available as long as the positive-sequence voltage exceeds 5% of the set base voltage VBase. So the directional element can use it for all unsymmetrical faults including close-in faults. For close-in three-phase faults, the V1AM memory voltage, based on the same positive sequence voltage, ensures correct directional discrimination. The memory voltage is used for 100ms or until the positive sequence voltage is restored. After 100ms, the following occurs: If the current is still above the set value of the minimum operating current the condition seals in. If the fault has caused tripping, the trip endures. If the fault was detected in the reverse direction, the measuring element in the reverse direction remains in operation.
If the current decreases below the minimum operating value, no directional indications will be given until the positive sequence voltage exceeds 10% of its rated value.
The Directional impedance element for mho characteristic (ZDMRDIR ,21D) function has the following output signals: The STDIRCND output provides an integer signal that depends on the evaluation and is derived from a binary coded signal as follows:
The PUFW output is a logical signal with value 1 or 0. It is made up as an OR-function of all the forward starting conditions, that is, FWD_A, FWD_B, FWD_C, FWD_AB, FWD_BC and RWD_CA. The PUREV output is similar to the PUFW output, the only difference being that it is made up as an OR-function of all the reverse starting conditions, that is, REV_A, REV_B, REV_C. REV_AB, REV_BC and REV_CA. Values for the following parameters are calculated, and may be viewed as service values: resistance phase A reactance phase A resistance phase B reactance phase B resistance phase C reactance phase C direction phase A direction phase B direction phase C
6.2.3
Function block
I3P* V3P* ZDMRDIR (21D) DIR_CURR DIR_VOLT DIR_POL PUFW PUREV STDIRCND ANSI06000422-2-en.vsd
ANSI06000422 V2 EN
Figure 94:
Table 94:
Name DIR_CURR DIR_VOLT DIR_POL PUFW PUREV STDIRCND
6.2.5
Table 95:
Name IBase VBase DirEvalType
Setting parameters
ZDMRDIR (21D) Group settings (basic)
Values (Range) 1 - 99999 0.05 - 2000.00 Impedance Comparator Imp/Comp 90 - 175 5 - 45 5 - 30 5 - 30 Unit Step 1 0.05 Default 3000 400.00 Comparator Description Base setting for current level Base setting for voltage level Directional evaluation mode Impedance / Comparator Angle of blinder in second quadrant for forward direction Angle of blinder in fourth quadrant for forward direction Minimum pickup phase current for Phase-toground loops Minimum pickup delta current (2 x current of lagging phase) for Phase-to-phase loops
1 1 1 1
115 15 5 10
6.3
6.3.1
Introduction
The phenomenon pole slip, also named out of step conditions, occurs when there is phase opposition between different parts of a power system. This is often shown in a simplified way as two equivalent generators connected to each other via an equivalent transmission line and the phase difference between the equivalent generators is 180.
Angle = 90 Angle = -90
Figure 95:
The centre of the pole slip can occur in the generator itself or somewhere in the power system. When a pole slip occurs within the generator it is essential to trip the generator. If the centre of pole slip occurs outside any generator the power system should be split into two different parts that could have the ability to get stable operating conditions. Pole slip protection (PSPPPAM ,78) function in the IED can be used both for generator protection application as well as, line protection applications. The situation with pole slip of a generator can be caused by different reasons. A short circuit may occur in the external power grid, close to the generator. If the fault clearing time is too long, the generator will accelerate so much, that the synchronism cannot be maintained.
Un-damped oscillations occur in the power system, where generator groups at different locations, oscillate against each other. If the connection between the generators is too weak the magnitude of the oscillations will increase until the angular stability is lost. The operation of a generator having pole slip will give risk of damages to the generator, shaft and turbine. At each pole slip there will be significant torque impact on the generator-turbine shaft. In asynchronous operation there will be induction of currents in parts of the generator normally not carrying current, thus resulting in increased heating. The consequence can be damages on insulation and stator/rotor iron.
The Pole slip protection (PSPPPAM ,78) function shall detect pole slip conditions and trip the generator as fast as possible if the locus of the measured impedance is inside the generator-transformer block. If the centre of pole slip is outside in the power grid, the first action should be to split the network into two parts, after line protection action. If this fails there should be operation of the generator PSPPPAM (78) in zone 2, to prevent further damages to the generator, shaft and turbine.
6.3.2
Principle of operation
If the generator is faster than the power system, the rotor movement in the impedance and voltage diagram is from right to left and generating is signalled. If the generator is slower than the power system, the rotor movement is from left to right and motoring is signalled (the power system drives the generator as if it were a motor). The movements in the impedance plain can be seen in figure 96. The transient behaviour is described by the transient EMF's EA and EB, and by X'd, XT and the transient system impedance ZS.
Zone 1 EB Xd IED jX XT
Zone 2 XS EA
A XS
XT
Xd B
IEC06000437_2_en.vsd
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Figure 96:
where: X'd XT ZS
= transient reactance of the generator = short-circuit reactance of the step-up transformer = impedance of the power system A
the minimum current exceeds 0.10 IN (IN is IBase parameter set under general setting). the maximum voltage falls below 0.92 VBase the voltage Ucos (the voltage in phase with the generator current) has an angular velocity of 0.2...8 Hz and the corresponding direction is not blocked.
en07000004.vsd
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Figure 97:
Different generator quantities as function of the angle between the equivalent generators
An alarm is given when movement of the rotor is detected and the rotor angle exceeds the angle set for 'WarnAngle'. Slipping is detected when: a change of rotor angle of min. 50 ms is recognized the slip line is crossed between ZA and ZB.
When the impedance crosses the slip line between ZB and ZC it counts as being in zone 1 and between ZC and ZA in zone 2. The entire distance ZA-ZB becomes zone 1 when signal EXTZONE1 is high (external device detects the direction of the centre of slipping).
After the first slip, the signals ZONE1 or ZONE2 and depending on the direction of slip - either GEN or MOTOR are issued. Every time pole slipping is detected, the impedance of the point where the slip line is crossed and the instantaneous slip frequency are displayed as measurements. Further slips are only detected, if they are in the same direction and if the rate of rotor movement has reduced in relation to the preceding slip or the slip line is crossed in the opposite direction outside ZA-ZB. A further slip in the opposite direction within ZA-ZB resets all the signals and is then signalled itself as a first slip. The TRIP1 tripping command and signal are generated after N1 slips in zone 1, providing the rotor angle is less than TripAngle. The TRIP2 signal is generated after N2 slips in zone 2, providing the rotor angle is less than TripAngle. All signals are reset if: the direction of movement reverses the rotor angle detector resets without a slip being counted or no rotor relative movement was detected during the time ResetTime.
0.2 Slip.Freq. 8 Hz
d startAngle ZONE1
Z cross line ZA - ZC
AND
Z cross line ZC - ZB
AND
ZONE2
Counter N1Limit
a b
ab
AND
TRIP1
OR a b ab
TRIP
AND
TRIP2
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Figure 98:
6.3.3
Figure 99:
6.3.4
Table 97:
Name TRIP TRIP1 TRIP2 PICKUP ZONE1 ZONE2 GEN MOTOR SFREQ
Slip impedance in percent of ZBase UCosPhi voltage VCosPhi voltage in percent of VBase
6.3.5
Table 98:
Name Operation OperationZ1 OperationZ2 ImpedanceZA ImpedanceZB ImpedanceZC AnglePhi StartAngle TripAngle N1Limit N2Limit
Setting parameters
PSPPPAM (78) Group settings (basic)
Values (Range) Disabled Enabled Disabled Enabled Disabled Enabled 0.00 - 1000.00 0.00 - 1000.00 0.00 - 1000.00 72.00 - 90.00 0.0 - 180.0 0.0 - 180.0 1 - 20 1 - 20 Unit % % % Deg Deg Deg Step 0.01 0.01 0.01 0.01 0.1 0.1 1 1 Default Disabled Enabled Enabled 10.00 10.00 10.00 85.00 110.0 90.0 1 3 Description Operation Enable / Disable Operation Enable/Disable zone Z1 Operation Enable/Disable zone Z2 Forward impedance in % of Zbase Reverse impedance in % of Zbase Impedance of zone1 limit in % of Zbase Angle of the slip impedance line Rotor angle for the pickup signal Rotor angle for the trip1 and trip2 signals Count limit for the trip1 signal Count limit for the trip2 signal
Table 99:
Name ResetTime
Table 100:
Name IBase Vbase MeasureMode
InvertCTcurr
No
6.3.6
Technical data
Table 101:
Function Impedance reach Characteristic angle Start and trip angles Zone 1 and Zone 2 trip counters
6.4
<
SYMBOL-MM V1 EN
6.4.1
Introduction
There are limits for the under-excited operation of a synchronous machine. A reduction of the excitation current weakens the coupling between the rotor and the stator. The machine may lose the synchronism and start to operate like an induction machine. Then, the reactive power consumption will increase. Even if the machine does not loose synchronism it may not be acceptable to operate in this state for a long time. Reduction of excitation increases the generation of heat in the end region of the
227
synchronous machine. The local heating may damage the insulation of the stator winding and the iron core. To prevent damages to the generator it should be tripped when excitation is lost.
6.4.2
Principle of operation
The Loss of excitation (LEXPDIS ,40) protection in the IED measures the apparent impedance seen out from the generator.The measurement loop of apparent impedance can be chosen as the positive sequence loop or any one of the three phase-to-phase loops depending on the available current and voltage signals. It is recommended to use positive sequence quantities for function operation.
Measured mode Measured apparent impedance
Zposseq
Vposseq I posseq
(Equation 48)
EQUATION2051-ANSI V1 EN
ZAB
VA - VB IA - IB
(Equation 49)
EQUATION2052-ANSI V1 EN
ZBC
VB - VC IB - IC
(Equation 50)
EQUATION2053-ANSI V1 EN
ZCA
VC - VA IC - IA
(Equation 51)
EQUATION2054-ANSI V1 EN
There are three characteristics in LEXPDIS (40) protection as shown in figure 100. Naimly: Offset mho circle for Z1 Offset mho circle for Z2 Directional blinder
R Directional blinder
Figure 100:
When the apparent impedance reaches the zone Z1 this zone will operate, normally with a short delay. The zone is related to the dynamic stability of the generator. When the apparent impedance reaches the zone Z2 this zone will operate, normally with a longer delay. The zone is related to the static stability of the generator. LEXPDIS (40) protection also has a directional blinder (supervision). See figure 100. In LEXPDIS (40) function the zone measurement is done as shown in figure 101.
Offset
Z1diameter
Z1 = Z - (XoffsetZ1 + Z1diameter/2)
Z1 or Z2
en06000456-2.vsd
IEC06000456 V2 EN
Figure 101:
The impedance Z1 is constructed from the measured apparent impedance Z and the impedance corresponding to the centre point of the impedance characteristic (Z1 or Z2). If the magnitude of this impedance is less than the radius (diameter/2) of the characteristic, this part of the protection will operate. If the directional restrain is set Disabled the impedance zone operation will start the appropriate timer and LEXPDIS (40) will trip after the set delay (tZ1 or tZ2). If the directional restrain is set Enabled the directional release function must also operate to enable operation. A new impedance is constructed from the measured apparent impedance Z and the XoffsetDirLine point on the y-axis. If the phase angle of this impedance is less than the set DirAngle LEXPDIS (40) function will be released, see figure 102.
XoffsetDirLine DirAngle
Z (apparent impedance)
en06000457.vsd
IEC06000457 V1 EN
Figure 102:
Positive sequence current phasor Positive sequence voltage phasor Apparent impedance calculation Z
Z in Z1 char.
AND
pickupZ1
tZ1 0
TripZ1
Z in Z2 char.
AND
pickupZ2
tZ2 0
TripZ2
en060004582_ansi.vsd
ANSI06000458 V2 EN
Figure 103:
6.4.3
Function block
LEXPDIS (40) I3P* V3P* BLOCK BLKTRZ1 BLKTRZ2 TRIP TRZ1 TRZ2 PICKUP PU_Z1 PU_Z2 XOHM XPERCENT ROHM RPERCENT ANSI0700031-1-en.vsd
ANSI0700031 V1 EN
Figure 104:
6.4.4
Table 103:
Name TRIP TRZ1 TRZ2 START STZ1 STZ2 XOHM XPERCENT ROHM RPERCENT
6.4.5
Table 104:
Name Operation OperationZ1 XoffsetZ1 Z1diameter tZ1
Setting parameters
LEXPDIS (40) Group settings (basic)
Values (Range) Disabled Enabled Disabled Enabled -1000.00 - 1000.00 0.01 - 3000.00 0.00 - 6000.00 Unit % % s Step 0.01 0.01 0.01 Default Disabled Enabled -10.00 100.00 0.01 Description Disable/Enable Operation Operation Disable/Enable zone Z1 Offset of Z1 circle top point along X axis in % of Zbase Diameter of impedance circle for Z1 in % of Zbase Trip time delay for Z1
Operation Disable/Enable zone Z2 Offset of Z2 circle top point along X axis in % of Zbase Diameter of impedance circle for Z2 in % of Zbase Trip time delay for Z2
Table 105:
Name DirSuperv XoffsetDirLine DirAngle
Table 106:
Name IBase UBase MeasureMode
Table 107:
Name InvertCTcurr
6.4.6
Technical data
Table 108:
Function X offset of Mho top point Diameter of Mho circle Timers
6.5
6.5.1
Introduction
The sensitive rotor earth fault protection (ROTIPHIZ, 64R) is used to detect ground faults in the rotor windings of generators. ROTIPHIZ (64R) is applicable for all types of synchronous generators. To implement the above concept, a separate injection box is required. The injection box generates a square wave voltage signal at a certain preset frequency which is fed into the rotor winding. The magnitude of the injected voltage signal and the resulting injected current is measured through a resistive shunt located within the injection box. These two measured values are fed to the IED. Based on these two measured quantities, the protection IED determines the rotor winding resistance to ground. The resistance value is then compared with the preset fault resistance alarm and trip levels. The protection function can detect ground faults in the entire rotor winding and associated connections. Requires injection unit REX060 and a coupling capacitor unit REX061 for correct operation.
6.5.2
Principle of operation
The protection principle is based on injection of voltage to the exciter point of the field circuit.
U>
3 1
Vinj
7
Rshunt
R C
5 6
GEN
ROTOR EF
REX061
I
RN
ANSI11000014_1_en.vsd
Figure 105:
1 2 3 4 5 6 7 8
Generator unit consisting of a synchronous generator and a step-up transformer Generator field winding Capacitor coupling unit which is used to provide insulation barrier between rotor circuit and injection equipment Cable used to inject the square-wave signal into the rotor circuit Connection for measurement of injected current. This signal is amplified in REX060 before it is passed on to IED for evaluation. Connection for measurement of injected voltage. This signal is amplified in REX060 before it is passed on to IED for evaluation. Two VT inputs into IED which are used to measure injected current and voltage Protection for excessive over-voltages posed by generator. REX060 can withstand without damage maximum voltage of 120V and when used together with REX062 up to 240V.
The injection signals are generated in a separate unit, REX060. The signals have square wave form and are injected to the generator via the coupling capacitor unit REX061 to the excitation circuit. In the REX060 unit the injection voltage and current signals are amplified to a level adapted to the analogue voltage inputs of IED. In IED the measured signals evaluated to detect rotor ground faults.
6.5.2.1
X61
X81
Injection Stator
Injection Rotor
18
PSM
X62
18
1 5
X82
Power
Stator
Rotor
Injection LED
Injection switch
IEC11000015-1-en.vsd
IEC11000015 V1 EN
Figure 106:
The REX060 unit is a common unit that can be configured for either rotor or stator ground fault protection, or for both. The REX060 have separate modules for rotor and stator protection. The REX060 generate square wave signals, where one is used for injection to the stator neutral point and the other to the field winding circuit (rotor circuit), if configured for both stator and rotor protection. The injected voltage and currents are measured by the unit and amplified, resulting in voltage signals both for the injected voltage and current, and adapted to the analogue inputs of IED. The injection unit REX060 shall be located close to the IED, preferably in the same cubicle. For the Sensitive rotor earth fault protection, there are some settings necessary for REX060: System frequency: 50/60 Hz Injected frequency for rotor circuit injection is settable in 1 Hz steps 75 250 Hz. Gain factor in four steps
REX060 will also continuously check the measured signal for detection of saturation which could cause error in the evaluation in IED. If saturation level is reached a binary signal, connected to IED, is activated. Also other errors in the injection circuit will initiate a binary signal to IED for blocking of the function. Rotor injection output is protected against high voltages by a relay blocking the injection circuit. This blocking remains blocked by stored status in non-volatile memory. The output is also protected by a fuse. If this fuse is blown, it is caused by external voltage source, since the injection unit cannot provide enough energy to blow this fuse.
Refer to the Hardware section in this manual for a detailed description of REX060.
6.5.2.2
ANSI11000065_1_en.vsd
ANSI11000065 V1 EN
Figure 107:
The impedance ZMeasured is equal to the capacitive reactance between the rotor winding and ground (1/Crot) and the ground fault resistance (Rf). The series resistance in the injection circuit is eliminated. Rf is very large in the non-faulted case and the measured impedance, called the rotor reference impedance and can be calculated as :
Z ref = - j
EQUATION2510 V1 EN
1 wCrot
alternative
1 = jwCrot Z ref
EQUATION2511 V1 EN
Where
w = 2p finj
EQUATION2512 V1 EN
The injected frequency finj of the square wave, is a set value, deviating from the fundamental frequency (50 or 60 Hz). The injected frequency can be set within the
range 75 250 Hz with the recommended value 113 Hz in 50 Hz systems and 137 Hz in 60 Hz systems. Rseries is a resistance in the REX061 unit used to protect against overvoltage to the injection unit. Such overvoltages can occur if the unit is fed from static excitation system. The injection unit REX060 is connected to the generator and to IED as shown in figure 105.
6.5.2.3
EQUATION2500-ANSI V1 EN
ZMeasured
Zbare
Z series Iinj +
Rf
Z shunt
Vinj -
ANSI11000003_1_en.vsd
ANSI11000003 V1 EN
Figure 108:
Z Measured = k1 Z bare + k 2
EQUATION2501 V1 EN
For definition of k1 and k2, see figure 109 The factors k1 and k2 [] are derived from measurements during commissioning, where calibration to known fault resistance will be used to convert the measurement to true primary impedance. The factor k1 will compensate for transformer ratio and other factors to achieve impedance values related to the primary system. The factor k2 [] will compensate for the series impedance Zseries The healthy impedance measured at non-faulted conditions is referred to as the reference impedance in further text. In IED the measured impedance is compared to the reference impedance. In case of a ground fault, the fault impedance is estimated and compared to the set values RAlarm and RTrip. The measured values are transferred to the primary impedance values by taking the actual impedance value through the complex transformation given by the equation.
Ztrue = k1 Z measured + k2
GUID-20ADF3F6-6A89-4B5F-B0DA-9740C4FD5482 V1 EN
The factors k1 and k2 [] are derived during the calibration measurements under commissioning. As support for the calibration, the Injection Commissioning tool must be used. This tool is an integrated part of the PCM600 tool. In connection to this calibration, the reference impedance is also derived. In case of a rotor ground fault with fault impedance Zf, the measured admittance is:
1 1 1 = + Z Z ref Z f = 1 1 1 = Zf Z Z ref
EQUATION2405 V1 EN
RAlarm and RTrip are the two resistance levels given in the settings. The values of RAlarm and RTrip are given in .
An alarm signal ALARM is given after a set delay tAlarm if Rf < RAlarm A initiate signal BFI is given if Rf < RTrip See figure 111
6.5.2.4
Vinj
Rshunt
2 6 5 4 3
I Inj
v_i_ref
Rf
Z Measured
Compare & Evaluate
Z bare S
X
K1
I
V Inj
v_v_ref
7
ZRef1 ZRef2
K2
REX060
REG670
ANSI10000327_1_en.vsd
ANSI10000327 V1 EN
Figure 109:
1 2 3 4, 5 6 7
Simplified logic diagram for sensitive rotor earth fault protection, injection based ROTIPHIZ (64R)
The sensitive rotor earth fault protection function receives amplified injected voltage and current via the REX060 unit as two voltages signals. (Voltage inputs in the IED) The phasor of injected voltage VInj and phasor of injected current IInj is calculated by using special filter from raw samples. Observe that phasors are calculated for the injected frequency. The complex bare impedance is calculated from Vinj / Iinj. The complex measured impedance is derived as ZMeasured = Zbare*k1 + k2 []. The fault resistance (Rf) is calculated from the complex measured impedance and a selected complex reference. Selection of one (out of maximum 2) ZRef.
Rf
a b
tAlarm a<b t
OR
ALARM
RAlarm
a b
a<b
TRIP
RTrip
IEC10000326-2-en.vsd
IEC10000326 V1 EN
Figure 110:
If the fault resistance Rf is smaller than RAlarm and longer than alarm delay (using delayon), output ALARM is set. If the fault resistance Rf is smaller than RTrip, using internal trip time characteristic, output signal TRIP is set after the calculated time. For trip time delay, see fig 111 When 1s filter length is used and the fault resistance is equal to the set value RTrip, the trip time is about 10 s. If the fault resistance is estimated to be 0 , the trip delay is 2 s. For values in between, the delay follows the linear interpolation describing the fault resistance time characteristic.
Trip time
10 FilterLength
2 FilterLength
Fault resistance
RTrip
IEC11000002 V1 EN
RAlarm
IEC11000002-1-en.vsd
Figure 111:
A third high level step for the detection of excitation system ground faults on the AC side of the excitation rectifier is available. This step uses the network frequency (50 or 60 Hz) for the evaluation. If a ground fault occurs at the AC side of the excitation system rectifier, there is a fundamental frequency component at the measured voltage and current injection points. The third high level step is not applicable if mixed signals are used, that is when the REX060 is used for both rotor and stator ground fault protection and only two, instead of four, analog inputs on the IED are used.
6.5.2.5
commissioning and calibration, ICT performs various tests to verify that the installation is acceptable and the calibration successful. Besides carrying out the actual tests, ICT also provides the commissioning engineer with tips if needed during the commissioning. When ICT is started, rotor earth fault protection is chosen. There are five different parts of the ICT tool to be performed at commissioning and operation: 1. 2. 3. 4. 5. Installing Calibrating Commissioning Monitoring Auditing
Before proceeding make sure that all necessary connections are in place.
Installing
When the injection is started, check that the injected voltage and current are within the permissible limits. If not, adjust the settings in the injection unit REX060. The ICT tool will check automatically for slight differences between actual injected and set injection frequency (for example, due to accuracy of the REX060 hardware). Set manually the actual frequency value measured by ICT in the IED via PST. The high accuracy of this frequency is essential for proper operation of the protection under different operating conditions.
Calibrating
The calibration is based on three measurement steps: 1. 2. 3. The injection is made to the faultless generator and the measured complex impedance is stored. A known resistance is connected between the generator neutral point and ground. The injection is made to the generator and the measured complex impedance is stored. The generator neutral point is directly short-circuited to the ground. The injection is made to the generator and the measured complex impedance is stored.
The sequence of the commissioning calibration measurements is shown in the figure below.
Step 1
Step 2
Step 3
Crot
DC AC
C rot
DC AC
C rot
DC AC
REX061
I inj
REX061
I inj
REX061
Iinj
RTest
ANSI11000205_1_en.vsd
ANSI11000205 V1 EN
Figure 112:
The sequence of the calibration session follows a scheme shown in the tool. Calibration sequence 1: The injection must be activated and the rotor must be left with no impedance connected. The ICT now makes consecutive measurements until the statistical error reaches an acceptable value. This is graphically shown in a diagram. The user stops the sequence by acceptance of the measurement. The result is stored for later calculations. Calibration sequence 2: A known resistor is connected between the rotor winding and ground. The value of the resistance is the input to ICT. The ICT now makes consecutive measurements until the statistical error reaches an acceptable value. This is graphically shown in a diagram. The user stops the sequence by acceptance of the measurement. The result is stored for later calculations. Calibration sequence 3: The ICT now makes consecutive measurements until the statistical error reaches an acceptable value. This is graphically shown in a diagram. The user stops the sequence by acceptance of the measurement. The result is stored for later calculations.
After the three measurements ICT calculates the complex factors k1 and k2. The reference impedance RefR1 + jRefX1 is also calculated. After this the values are downloaded to the parameter setting in PCM600. From PCM600 the settings are downloaded to IED. During the three measurements described above a check is made that there are sufficient changes in the measured impedance in order to guarantee that there is no primary fault from the beginning or other problems due to the installation or calibration procedure. Now the reference impedance is derived for one operational state. It might be necessary to make measurements to derive reference impedance for other operational cases. For information on this, see Commissioning below.
There is a possibility to have two different reference impedances. The need to change the reference impedance is due to different operating conditions of the machine. In the commissioning part of ICT this can be done. For each operation state of interest a measurement is performed. If the reference impedance differs from the first one, calculated under the calibration session, the new reference impedance is stored by the command; Submit toParameter Setting. If more than one reference impedance are to be used, there must be a logic configured to detect such changes in the operation states that requires a change of reference impedance.
Monitoring
In the monitoring part the calibration can be checked by applying the known fault resistance and compare it with the actual function measurement. It is also possible to identify operational states where change of reference impedance is required.
Auditing
In the auditing part calibration and commissioning reports are made.
6.5.3
USI
BLOCK ZREFSEL
6.5.4
Table 110:
Output signal TRIP TRIPDC TRIPAC BFI PU_DC PU_DC ALARM ERROR ERRSTAT RAVE XAVE FREQV RFAULT ZREF ZREFRE ZREFIM VRMSSTAT
ERRSTAT output signal Convert the integer output signal to binary and see table below for interpretation of individual bits:
Table 111:
Priority 3 Bit 7 Interference detected
Definition of errors
ERRSTAT output integer Priority 2 Bit 5 Bit 4 Bit 3 Undervoltage Overcurrent Overvoltage Priority 3 Bit 2 Frequency difference Priority 1
Bit 6 Undercurrent
Bit 1
Bit 0
No current
No voltage
The ERRSTAT description will be shown in clear text in ICT. The priority of the signals is set that the group priority 1 overrides the group priority 2 and 3, and priority 2 overrides priority 3. Note that the ERRSTAT signal can enable several error cases at the same time.
247 Technical reference manual
Following errors is detected and derived in the Error block: B0 = Injected voltage signal not found B1 = Injected current signal not found B2 = Voltage and current signal frequency differs B3 = Measured total RMS voltage too high B4 = Measured total RMS current too high B5 = Injected voltage signal too low B6 = Injected current signal too low B7 = External interference voltage detected
ERRSTAT = BitToInt[B7,,B1,B0] The priority of the error conditions that will be flagged out: Prio1 = B0, B1 Prio2 = B3, B4, B5, B6 Prio3 = B2, B7
6.5.5
Function block
ROTIPHIZ (64R) USV* TRIP USI* TRIPDC BLOCK TRIPAC ZREFSEL BFI PU_DC PU_DC ALARM ERROR ERRSTAT RAVE XAVE FREQV RFAULT ZREF ZREFRE ZREFIM VRMSSTAT ANSI10000297-1-en.vsd
ANSI10000297 V1 EN
Figure 113:
6.5.6
Table 113:
Name TRIP TRIPDC TRIPAC BFI PU_DC PU_DC ALARM ERROR ERRSTAT RAVE XAVE FREQV RFAULT ZREF ZREFRE ZREFIM VRMSSTAT
Setting parameters
ROTIPHIZ (64R) Group settings (basic)
Values (Range) Disabled Enabled 100 - 100000 100 - 1000000 0.00 - 600.00 0.01 - 2.00 0.000 - 60.000 1 - 1000 Unit ohm ohm s s V Step 1 1 1.00 0.01 1.000 1 Default Disabled 1000 10000 30.00 0.25 10.000 100 Description Operation (Enable/Disable) of Function Trip limit of fault resistance in Ohm Alarm limit of fault resistance in Ohm Alarm time delay Scale factor for rotor earth fault on AC side of exciter Time delay for trip on AC side of exciter RMS voltage level
Table 115:
Name FreqInjected
Table 116:
Name k1Real k1Imag k2Real k2Imag RefR1 RefX1 RefR2 RefX2
Table 117:
Name FilterLength
6.5.8
(100 - 1000000)
6.6
6.6.1
Introduction
The 100% stator earth-fault protection STTIPHIZ (64S) is used to detect ground faults in the stator windings of generators and motors. STTIPHIZ (64S) is applicable for generators connected to the power system through a unit transformer in a block connection. An independent signal with a certain frequency different from the generator rated frequency is injected into the stator circuit. The responce of this injected signal is used to detect stator ground faults. To implement the above concept, a separate injection box is required. The injection box generates a square wave voltage signal which for example can be fed into the secondary winding of the generator neutral point voltage transformer or grounding transformer. This signal propagates through this transformer into the stator circuit.
The magnitude of the injected voltage signal is measured on the secondary side of the neutral point voltage transformer or grounding transformer. In addition, the resulting injected current is measured through a resistive shunt located within the injection box. These two measured values are fed to the IED. Based on these two measured quantities, the IED determines the stator winding resistance to ground. The resistance value is then compared with the preset fault resistance alarm and trip levels. The protection function can not only detect the ground fault at the generator star point, but also along the stator windings and at the generator terminals, including the connected components such as voltage transformers, circuit breakers, excitation transformer and so on. The measuring principle used is not influenced by the generator operating mode and is fully functional even with the generator at standstill. It is still required to have a standard 95% stator earth-fault protection, based on the neutral point fundamental frequency displacement voltage, operating in parallel with the 100% stator earth-fault protection function. Requires injection unit REX060 and optional shunt resistor unit REX062 for correct operation.
6.6.2
Principle of operation
The protection function is based on signal injection into a stator winding. These square wave signals are generated in a separate injection unit REX060. The injection signals are connected to the stator winding via: secondary winding of a voltage transformer (VT) located at the stator neutral point open delta winding of a three-phase VT set located at generator terminals secondary winding of a distribution transformer (DT) located at the stator neutral point; note that REX062 is typically required for such arrangement open delta winding of a three-phase grounding transformer (GT) located at generator terminals; note that REX062 is typically required for such arrangement
In the REX060 unit the injection voltage and current signals are amplified to a level adapted to the analogue voltage inputs of IED. In IED the measured signals are processed and evaluation will give detection of stator faults.
6.6.2.1
Configuration principle
Figure 114 shows a typical installation for stator injection.
10
Step-up Transformer
U>
Vinj
Rshunt
1 5
GEN
6
Generator
100% SEF
I
RN
REX060/SIM module
8 3
95 % SEF
REG670
ANSI11000067 V1 EN
ANSI11000067-1-en.vsd
Figure 114:
1 2 3 4 5 6 7 8 9 10
Generator unit consisting of a synchronous generator and a step-up transformer Grounding resistor for the stator winding Neutral point VT which is used as injection point and also to provide galvanic separation between primary circuit and injection equipment Cable used to inject the square-wave signal into the stator circuit Connection for measurement of injected current. This signal is amplified in REX060 before it is given to REG670 for evaluation. Cable for measurement of injected voltage at the injection point. This signal is amplified in REX060 before it is given to REG670 for evaluation. Two VT inputs into REG670 which are used to measure injected current and voltage Cable for 95% stator earth-fault protection Separate VT input in REG670 used for 95% stator earth-fault protection Protection for excessive over-voltages posed by generator. REX060 can withstand without damage maximum voltage of 120V and when used together with REX062 up to 240V.
1 5
X61
X81
Injection Stator
Injection Rotor
18
PSM
X62
18
1 5
X82
Power
Stator
Rotor
Injection LED
Injection switch
IEC11000015-1-en.vsd
IEC11000015 V1 EN
Figure 115:
The REX060 unit is a common unit that can be equipped for either rotor or stator ground fault protection, or for both. The REX060 has specific injection modules for rotor and stator protection. The REX060 generates square wave signals, where one is used for injection to the stator neutral point and the other to the field winding circuit (rotor circuit), if configured for both stator and rotor protection. The injected voltages and currents are measured by the unit and amplified, giving voltage signals both for the injected voltage and current, and adapted to the analogue inputs of IED. The injection unit REX060 shall be located close to the IED. For the stator ground fault protection, there are some settings necessary for REX060: System frequency: 50/60 Hz Injected frequency for stator neutral point is settable in 1 Hz steps 50 250 Hz. VT/DT maximum fundamental frequency voltage during ground fault in the stator winding
REX060 will also continuously check the measured signal for detection of saturation which could cause error in the evaluation in IED. If saturation level is reached, a binary output contact is activated, which is connected to IED. Also other errors in injection will activate another output contact to IED for blocking the function. Stator injection output is protected against voltages exceeding maximum operating range (10% of rated VT/DT) by a relay blocking the injection circuit. This blocking remains blocked by stored status in non-volatile memory. Note REX060 is designed to cope with such voltages of up to 120V. When optional REX062 resistor unit is used, REX060 can cope with voltages of up to 240V at injection point.
The output is also protected by a fuse. If this fuse is blown, it is caused by external voltage source, since the injection unit cannot provide enough energy to blow this fuse. Refer to the Hardware section in this manual for a detailed description of REX060.
6.6.2.2
Normally the generator system has some kind of high resistance grounding, giving ground fault current within the range 5 20 A, thus preventing serious damages in case of stator ground faults. Direct grounding will give too high ground fault current level. Isolated generator system will give risk of transient overvoltages. Below some alternatives for generator system grounding are shown;
A
IEC11000066 V1 EN
C
IEC110000066-1-en.vsd
Figure 116:
A B C
High-resistance grounding with a neutral point resistor Effective high-resistance grounding via a distribution transformer High-resistance grounding via a delta, grounded-wye transformer
These earthing alternatives are characterized by the following properties: A: High-resistance grounding with a neutral point resistor This grounding method utilizes a high resistance in the primary circuit by inserting resistor RN between the generator neutral and the ground. The actual resistance value of RN is generally in order of k. Such high resistance is required in order to limit the primary ground fault current to a quite small value (i.e. always < 20A and quite often < 10A primary). Actual primary ground fault current can be calculated as follows:
= U
G _ Ph - Ph
EF_Max
3 RN
EQUATION2515 V1 EN
where:
RN UG_Ph-Ph
is the ohmic value of the primary resistor is the protected generator rated phase-to-phase voltage
Typically a VT is connected in parallel with this resistor in order to measure voltage in the stator neutral point. This VT typically has rating around 100VA and rated secondary winding voltage of up to 120V. Note that maximum voltage on the secondary side of this VT for an ground fault at generator terminals can be calculated as follows:
U EF_Max =
EQUATION2516 V1 EN
U G _ Ph - Ph 3
U2 U1
where:
U2/U1 UG_Ph-Ph
is the turn (i.e. rated voltage) ratio of the VT is the protected generator rated phase to phase voltage
B: Effective high-resistance grounding via a distribution transformer This earthing method utilizes a distribution transformer that provides high resistance in the primary circuit by utilizing a small resistor RN connected to the secondary winding of the distribution transformer. The primary winding of the distribution transformer is connected between the generator neutral and ground. The actual resistance value RN is generally extremely small (i.e. typically < 1); however, the imposed ohmic value to the primary circuit becomes quite high (i.e. in the order of k). The equivalent resistance in the primary circuit can be calculated as follows:
U1 REq = RN U2
EQUATION2517 V1 EN
where:
U1/U2 RN
is the turn (i.e. rated voltage) ratio of the distribution transformer is the ohmic value of the resistor connected to the secondary winding
The distribution transformer typically has rating of several kVA (e.g. 33kVA) and rated secondary winding voltage of up to 240V. Note that maximum voltage on the secondary side of the distribution transformer for an ground fault at generator terminals can be calculated as follows:
U EF_Max =
EQUATION2516 V1 EN
U G _ Ph - Ph 3
U2 U1
where:
U2/U1 UG_Ph-Ph
is the turn (i.e. rated voltage) ratio of the distribution transformer is the protected generator rated phase to phase voltage
Note that in case of an ground fault in the stator, the secondary current through the RN resistor will be often in order of couple of hundred amperes. This maximum secondary current can be calculated as follows:
I EF _ Sec =
EQUATION2518 V1 EN
U EF _ Max RN
C: High-resistance grounding via a delta, grounded-wye transformer This grounding method utilizes a specially constructed three-phase, five-limb power transformer that provides high resistance in the primary circuit by utilizing a relatively small resistor RN connected to the secondary open-delta connected windings. The primary windings of this transformer is star (i.e. wye) connected and this neutral point is directly connected to ground. The actual resistance value RN is relatively small (i.e. typically < 5); however, the imposed ohmic value to the primary circuit becomes quite high (i.e. in the order of k). The equivalent resistance in the primary circuit can be calculated as follows:
U1 REq = RN 3 U 2
EQUATION2519 V1 EN
where:
U1/U2
is the turn (i.e. rated voltage) ratio of one phase of the power transformer, e.g.
8 kV 3 500V 3
EQUATION2521 V1 EN
RN
The three-phase power transformer typically has rating of several tens of kVA (e.g. 129kVA) and rated secondary winding voltage of up to 550V. Note that maximum voltage across secondary resistor RN for an ground fault at generator terminals can be calculated as follows:
U EF_Max =
EQUATION2520 V1 EN
3 U G _ Ph - Ph
U2 U1
where:
U2/U1
is the turn (i.e. rated voltage) ratio of one phase of the power transformer, e.g.
500V 3 8 kV 3
EQUATION2522 V1 EN
UG_Ph-Ph
Note that in case of an ground fault in the stator, the secondary current through the RN resistor will be often in order of couple of hundred amperes. This maximum secondary current can be calculated as follows:
I EF _ Sec =
EQUATION2518 V1 EN
U EF _ Max RN
For all the alternatives the 100% stator earth fault protection can be applied.
6.6.2.3
Z Bare Z Measured
Z series Cstat R fault Iinj
a
VN
+ Vinj -
Rf
Cstat
RN
ZmT
b
Iinj + RN Vinj Stator Reference Impedance ZRef
b
ANSI11000008_1_en.vsd
ANSI11000008 V1 EN
Figure 117:
There are some alternatives for connection of the neutral point resistor as shown in figure 118 (low voltage neutral point resistor connected via a DT).
Cstat
Iinj + RN Vinj -
ANSI11000009_1_en.vsd
ANSI11000009 V1 EN
Figure 118:
Another alternative is shown in figure 119 (High-resistance grounding via a delta, grounded-wye transformer). In this case the transformer must withstand the large secondary current caused by primary ground fault. The resistor typically has to be divided as shown in figure 119 to limit the voltage to the injection equipment in case of ground fault at the generator terminal. This voltage is often in the range 400 500 V. As the open delta connection gives three times the zero sequence phase voltage this gives too high voltage at the injection point if the resistance is not divided as shown in the figure 119 . By dividing the resistor in two parts it shall be ensured that maximum voltage imposed back on injection equipment is equal to or less than 240V.
ANSI11000010_1_en.vsd
ANSI11000010 V1 EN
Figure 119:
It is also possible to make the injection via VT open delta connection, as shown in figure 120.
V1 / V2
Y Y
I inj + Rd Vinj C
stat
V1 R d >> V2 RN
RN
ANSI11000011_1_en.vsd
ANSI11000011 V1 EN
Figure 120:
It must be observed that the resistor Rd is normally applied for ferro-resonance damping. The resistance Rd is will have very little contribution to the ground fault current as it has high resistance. This injection principle can be used for applications with various generator system grounding methods. It is therefore recommended to make the injection via the open delta VT on the terminal side in most applications. Accuracy for STTIPHIZ (64S) is installation dependent and it mainly depends on the characteristic of grounding or voltage transformer used to inject signal into the stator. Note that large variation of the ambient temperature and variation of stator capacitance
263 Technical reference manual
and conductance to ground between standstill and fully loaded machine will also limit the possible setting level for the alarm stage. As a consequence 10 k sensitivity can be typically reached without problem. Depending on particular installation alarm sensitivity of up to 50 k may be reached at steady state operating condition of the machine. Note that it is possible to connect two REG670 in parallel to the REX060 injection unit in order to obtain redundant measurement in two separate IEDs. However, at commissioning both REG670 IEDs must be connected during calibration procedure.
6.6.2.4
Z bare =
U Inj I Inj
EQUATION2500 V1 EN
ZMeasured
Rf
Z shunt
Uinj -
IEC11000003-2-en.vsd
IEC11000003 V1 EN
Figure 121:
Z Measured = k1 Z bare + k 2
EQUATION2501 V1 EN
For definition of k1 and k2, see figure 109 The factors k1 and k2 [] are derived from measurements during commissioning, where calibration to known fault resistance will be used to convert the measurement to true primary impedance. The factor k1 will compensate for transformer ratio and other factors to achieve impedance values related to the primary system. The factor k2 [] will compensate for the series impedance Zseries The healthy impedance measured at non-faulted conditions is referred to as the reference impedance in further text. In IED the measured impedance is compared to the reference impedance. In case of an ground fault, the fault impedance is estimated and compared to the set values RAlarm and RTrip. If the measured impedance is larger than the setting openCircuitLimit, the output OPCIRC is set TRUE. If OPCIRC is set, it means there is a strong likelihood that the generator neutral resistor is not anymore connected to ground, since only the capacitive part in the circuit is left. The open circuit is only applied on the stator winding protection. To make the open circuit limit more stable a hysteresis is added. If OPCIRC is TRUE, the measured fault impedance must drop below open circuit limit * (1 - OpenCircLim) to reset. The hysteresis is hidden and set to a default value of 10% of open Circuit limit for the stator.
Open- circuit characteristics
no open - circuit open- circuit
{Z
Measured
} re
openCircuitLimit
IEC11000073-1-en.vsd
IEC11000073 V1 EN
Figure 122:
Blocking: The output OPCIRC is blocked during an error occurring and during initialization of function.
265 Technical reference manual
Detailed Set: If the total measured real part of the impedance is greater than the setting OpenCircLim the output OPCIRC is TRUE, see figure 108.
6.6.2.5
1 Z ref
1 RN
+ jw C stat +
1 Z mT
EQUATION2502 V1 EN
Where
w = 2p finj
EQUATION2503 V1 EN
The injected frequency finj of the square wave, is a set value, deviating from the fundamental frequency (50 or 60 Hz). The injected frequency can be set within the range 50 250 Hz with recommend value 87 Hz in 50 Hz systems and 103 Hz in 60 Hz systems. The reference impedance can vary depending on the operational state. The reason for this can be the following: The influence from the impedance ZmT will be different when the generator is standstill and when it is in operation The capacitance to ground will vary if the generator breaker is open or closed The capacitance will vary if the generator is energized or not depending on stator end winding corona protection Non-linearity of used injection transformer, different properties at low and high total voltage and temperature changes Impedance to ground is affected by auxiliary loads connected between generator and unit transformer. If these loads vary, the estimated ground fault resistance will be affected.
The difference from the first reference impedance is identified by monitoring impedance (RAVE + jXRAVE) during different operation modes. This impedance is available as a service value from the stator function both on built-in HMI and in ICT
tool. If the difference is significant more than one reference impedance is required. In the ICT up to five different sets of reference impedances can be derived during commissioning for different states of operation and downloaded to the protection function as different values of the reference impedance; RefRn and RefXn where n = 1, 2, and up to 5. Switching of reference impedance can be made automatically. During commissioning ICT also makes cross-calculations between acquired references, giving basically the calculated fault resistance between each existing reference combination. This would be the fault resistance measured by the function when the reference change occurs from one reference to another if the real generator impedance stays the same, in other words a worst case scenario. RMS voltage (rmsVolt) value at the injection point can be used for detecting when a reference needs to be changed and logical outputs can be set to reflect whether the RMS voltage is higher or lower than a prescribed value. There is one such output for the voltage signal and one for the current signal. It is advantageous to use RMS to determine a change of machine condition because the RMS makes a distinction between the measured values and the total amplitude of the signal. The standstill condition only contains the injected frequency, while the full load condition and full speed condition contains other frequencies, which amplitudes may change under varying machine conditions. In case of a stator ground fault with fault impedance Zf the measured admittance will be:
1 Z
1 Z ref
1 Zf
EQUATION2513 V1 EN
1 Zf
1 Z
1 Z ref
EQUATION2514 V1 EN
In the settings there are given two resistance levels: RAlarm given in . If
R f < RAlarm
EQUATION2524 V1 EN
an alarm signal ALARM is given after a set delay tAlarm. RTrip given in . If
R f < RTrip
EQUATION2523 V1 EN
a start signal BFI is given. If the fault resistance is slightly below the set value RTrip the trip time will be about 10 s with default filter length of 1 s. If the fault resistance is estimated to 0 the trip delay will be 2 s with default filter length of 1 s. For values in between the delay will follow linear interpolation describing the fault resistance time relation, as shown in figure 123. Note that actual tripping time is dependent on the set parameter FilterLength which has default value of 1s.
Trip time
10 FilterLength
2 FilterLength
Fault resistance
RTrip
IEC11000002 V1 EN
RAlarm
IEC11000002-1-en.vsd
Figure 123:
During run-up and shut down of the generator, i.e. when the rotational speed of the generator changes, there will occur harmonic voltages with varying frequency at the injection equipment connection point (for example see voltage generator Vn in Figure 117). If such frequencies interfere with the injected frequency this might create an error in the fault resistance estimation. Such situations are identified in the function and the function is automatically stabilized to prevent unwanted operation of the protection. In connection with this calibration the reference impedance is also derived. It is possible to have up to five different reference impedances. The need to change reference impedance is due to different operating conditions for the generator, for instance: 1. 2. 3. Generator stand still Generator running, not synchronized to the power network Generator in normal operation, synchronized to the power network
The following automatic choice for the actual reference impedance can for example be made: Generator voltage < set value and generator circuit breaker open: Reference impedance 1 Generator voltage > set value and generator circuit breaker open: Reference impedance 2 Generator voltage > set value and generator circuit breaker closed: Reference impedance 3
The monitoring, enabled in ICT, will give indication if several reference impedance values are needed. From the measured impedance the stator ground fault resistance can be estimated since the reference impedance is known. An alarm level () is set at a higher value and the ALARM signal is activated after a set alarm delay time. A trip level () is also set at a lower value. When the trip level is reached a TRIP signal is activated as shown in figure 123.
Uinj
Rshunt
2 6 5 4 3
I Inj
Rf
u_i_sef
Z Measured
Compare & Evaluate
Z Bare
S
X K2 ZRef1 ZRef2 ZRef3 ZRef4 ZRef5 K1
I
U Inj
u_u_sef
REX060
SELECT REFERENCE
95% Trip
tON=0.5s t
a a>b b
UN
un
UN> = 5%
REG670
IEC10000325 V1 EN
Figure 124:
1 2 3 4, 5 6 7 8 9
Simplified logic diagram for 100% stator earth fault protection STTIPHIZ
The 100% stator earth fault protection function receives amplified injected voltage and current via the REX060 unit as two voltage signals. (Voltage inputs in the REG670). The phasor of injected voltage UInj and phasor of injected current IInj is calculated by using special filter from raw samples. Observe that phasors are calculated for the injected frequency. The complex bare impedance is calculated from Uinj / Iinj. The complex measured impedance is derived as ZMeasured = Zbare*k1 + k2. The fault resistance (RFault) is calculated from the complex measured impedance and a selected complex reference. Selection of one (out of maximum 5) ZRef. Fourier filter to derive the phasor of zero sequence voltage at fundamental frequency The 95% stator earth fault zero sequence over voltage function must operate in parallel with STTIPHIZ.
Rf
a b
tAlarm a<b t
OR
ALARM
RAlarm
a b
a<b
TRIP
RTrip
IEC10000326-2-en.vsd
IEC10000326 V1 EN
Figure 125:
If the fault impedance Rf is smaller than RAlarm and last longer than set alarm delay (using delay-on), output ALARM is set. If the fault impedance Rf is smaller than RTrip, output signal TRIP is set after the calculated time. For trip time delay, see fig 123
6.6.2.7
When ICT is started, 100% stator earth fault protection is chosen for the commissioning of this function. There are five different parts that needs to be performed using the ICT tool: 1. 2. 3. 4. 5. Installing Calibrating Commissioning Monitoring Auditing
Installing The injection is started and level of injected voltage and current is checked if they are within the permissible range. If not the settings of the injection unit REX060 must be adjusted. Also the injection frequency is checked and stored for use in ICT and in IED. Calibration The calibration is based on three measurement sessions:
Step 1: Step 2: Step 3: Injection is made to the non-faulted generator and the measured complex impedance is stored. A resistor with known resistance is connected between the primary object (stator circuit). Injection is made to the generator and the measured complex impedance is stored. The primary object (stator circuit) is directly short circuited to ground. Injection is made to the generator and the measured complex impedance is stored.
The sequence of the calibration session follows a scheme shown in the tool. After the three measurements ICT calculates the complex factors k1 and k2. The first reference impedance RefR1 + jRefX1 is also calculated. After this the values are downloaded to the parameter setting part of the PCM600 tool. From PCM600 the setting can be downloaded to IED. It is important to save the settings after download to IED, otherwise the ICT cannot perform the correct calculations. ICT compares settings in PCM600 and IED each time a measurement is started, if these are not equal, no measurement should be made. During the three measurements described above a check is made that there are sufficient changes in the measured impedance in order to guarantee that the function is capable of detecting a fault in the actual installation. Now the reference impedance is derived for one operational state. It might be reasonable to make measurements to derive reference impedance for other operational cases. This is done under the point Commissioning described below.
Commissioning There is a possibility to have up to five different reference impedances. The need to change reference impedance is different operating conditions for the generator: Generator stand still Generator running up, not synchronized to the network Generator normal operation
Comment: The capacitance will change when switching in breaker between step-up transformer and generator. It might therefore be necessary to find reference impedances for different operation states. In the commissioning part of ICT this can be done. For each operation state of interest a measurement is performed. If the reference impedance differs from the first one, calculated under the calibration session, the new reference impedance is stored by the command; Submit to Parameter setting. It is possible to derive up to 5 different reference impedances to be used at different operation states of the generator. Neutral point RMS voltage (rmsVolt) can be used for detecting when a reference needs to be changed and logical outputs can be set to reflect whether the RMS voltage is higher or lower than a prescribed value. There is one such output for the voltage signal and one for the current signal If more than one reference impedance is to be used there must be logics configured to detect changes in operation states where the reference impedance shall be changed. Further, the monitoring part should be consulted if the sensitivity to ground faults is to be set at the highest possible value as this depends on the properties of the individual site. Monitoring In the monitoring part the calibration can be checked. It is also possible to identify operational states where change of reference impedances is required. Auditing In the auditing part reports from calibration and commissioning are made.
6.6.3
Table 119:
Input signal USV
USI
BLOCK ZREFSEL
6.6.4
Convert the integer output signal to binary and see table below for interpretation of individual bits:
Table 121:
Priority 3 Bit 7 Interference detected
Definition of errors
ERRSTAT output integer Priority 2 Bit 5 Bit 4 Bit 3 Undervoltage Overcurrent Overvoltage Priority 3 Bit 2 Frequency difference Priority 1
Bit 6 Undercurrent
Bit 1
Bit 0
No current
No voltage
The ERRSTAT description will be shown in clear text in ICT. The priority of the signals is set that the group priority 1 overrides the group priority 2 and 3, and priority 2 overrides priority 3. Note that the ERRSTAT signal can enable several error cases at the same time. Following errors is detected and derived in the Error block: B0 = Injected voltage signal not found B1 = Injected current signal not found B2 = Voltage and current signal frequency differs B3 = Measured total RMS voltage too high B4 = Measured total RMS current too high B5 = Injected voltage signal too low B6 = Injected current signal too low B7 = External interference voltage detected
ERRSTAT = BitToInt[B7,,B1,B0] The priority of the error conditions that will be flagged out: Prio1 = B0, B1 Prio2 = B3, B4, B5, B6 Prio3 = B2, B7
Figure 126:
6.6.6
Table 123:
Name TRIP BFI ALARM OPCIRC ERROR ERRSTAT RAVE XAVE FREQV RFAULT
6.6.7
Table 124:
Name Operation RTrip RAlarm tAlarm OpenCircLim VLimRMS
Setting parameters
STTIPHIZ (64S) Group settings (basic)
Values (Range) Disabled Enabled 100 - 10000 100 - 100000 0.00 - 600.00 100 - 10000000 1 - 1000 Unit ohm ohm s ohm V Step 1 1 1.00 1 1 Default Disabled 1000 5000 30.00 10000000 100 Description Operation (Enable/Disable) of Function Trip limit of fault resistance in Ohm Alarm limit of fault resistance in Ohm Alarm time delay Open circuit limit in Ohm RMS voltage level
Table 125:
Name FreqInjected
Table 126:
Name k1Real k1Imag k2Real k2Imag RefR1 RefX1 RefR2
Reference reactance X2 in ohm Reference resistance R3 in ohm Reference reactance X3 in ohm Reference resistance R4 in ohm Reference reactance X4 in ohm Reference resistance R5 in ohm Reference reactance X5 in ohm
Table 127:
Name FilterLength
6.6.8
Technical data
Table 128:
Function Fault resistance sensitivity
10 k 0.1 Hz 5% of 1 k at Rf 1 k 10% of set value at Rf > 1 k 5% of 1 k at Rf 1 k 10% of 10 k at 1 k < Rf 10 k 50% of set value at Rf > 10 k 0.5% 10 ms
Injection frequency Trip limit of fault resistance Alarm limit of fault resistance
Section 7
Current protection
7.1
3I>>
SYMBOL-Z V1 EN
7.1.1
Introduction
The instantaneous three phase overcurrent function has a low transient overreach and short tripping time to allow use as a high set short-circuit protection function.
7.1.2
Principle of operation
The sampled analog phase currents are pre-processed in a discrete Fourier filter (DFT) block. The RMS value of each phase current is derived from the fundamental frequency components, as well as sampled values of each phase current. These phase current values are fed to the instantaneous phase overcurrent protection 3-phase output function PHPIOC (50). In a comparator the RMS values are compared to the set operation current value of the function Pickup. If a phase current is larger than the set operation current a signal from the comparator for this phase is set to true. This signal will, without delay, activate the output signal TR_x(x=A, B or C) for this phase and the TRIP signal that is common for all three phases.
There is an operation mode (OpModeSel) setting: 1 out of 3 or 2 out of 3. If the parameter is set to 1 out of 3 any phase trip signal will be activated. If the parameter is set to 2 out of 3 at least two phase signals must be activated for trip. There is also a possibility to activate a preset change of the set operation current (MultPU) via a binary input (MULTPU). In some applications the operation value needs to be changed, for example due to transformer inrush currents. PHPIOC (50) can be blocked from the binary input BLOCK.
7.1.3
Function block
PHPIOC (50) I3P* BLOCK MULTPU TRIP TR_A TR_B TR_C ANSI04000391-2-en.vsd
ANSI04000391 V2 EN
Figure 127:
7.1.4
Table 130:
Name TRIP TR_A TR_B TR_C
7.1.5
Table 131:
Name Operation IBase OpModeSel Pickup
Table 132:
Name MultPU
7.1.6
Technical data
Table 133:
Function Operate current Reset ratio Operate time Reset time Critical impulse time Operate time Reset time Critical impulse time Dynamic overreach
7.2
TOC-REVA V1 EN
7.2.1
Introduction
The four step phase overcurrent protection function OC4PTOC (51/67) has independent inverse time delay settings for step 1 and 4. Step 2 and 3 are always definite time delayed. All IEC and ANSI inverse time characteristics are available together with an optional user defined time characteristic. The directional function is voltage polarized with memory. The function can be set to be directional or non-directional independently for each of the steps. A 2nd harmonic blocking can be set individually for each step.
7.2.2
Principle of operation
The Four step phase overcurrent protection OC4PTOC (51/67) is divided into four different sub-functions, one for each step. For each step x , where x is step 1, 2, 3 and 4, an operation mode is set by DirModeSelx: Disable/Non-directional/Forward/ Reverse. The protection design can be decomposed in four parts: The direction element The harmonic Restraint Blocking function The four step over current function The mode selection If VT inputs are not available or not connected, setting parameter DirModeSelx shall be left to default value, Non-directional.
Direction Element
faultState PICKUP
TRIP
I3P
harmRestrBlock
en05000740_ansi.vsd
ANSI05000740 V1 EN
Figure 128:
A common setting for all steps, NumPhSel, is used to specify the number of phase currents to be high to enable operation. The settings can be chosen: 1 out of 3, 2 out of 3 or 3 out of 3. The sampled analog phase currents are processed in a pre-processing function block. Using a parameter setting MeasType within the general settings for the four step phase overcurrent protection 3-phase output function OC4PTOC (51/67), it is possible to select the type of the measurement used for all overcurrent stages. It is possible to select either discrete Fourier filter (DFT) or true RMS filter (RMS). If DFT option is selected then only the RMS value of the fundamental frequency components of each phase current is derived. Influence of DC current component and higher harmonic current components are almost completely suppressed. If RMS option is selected then the true RMS values is used. The true RMS value in addition to the fundamental frequency component includes the contribution from the current DC
component as well as from higher current harmonic. The selected current values are fed to OC4PTOC (51/67). In a comparator, for each phase current, the DFT or RMS values are compared to the set operation current value of the function (Pickup1, Pickup2, Pickup3, Pickup4). If a phase current is larger than the set operation current, outputs PICKUP, PU_STx, PU_A, PU_B and PU_C are, without delay, activated. Output signals PU_A, PU_B and PU_C are common for all steps. This means that the lowest set step will initiate the activation. The PICKUP signal is common for all three phases and all steps. It shall be noted that the selection of measured value (DFT or RMS) do not influence the operation of directional part of OC4PTOC (51/67) . Service value for individually measured phase currents are also available on the local HMI for OC4PTOC (51/67) function, which simplifies testing, commissioning and in service operational checking of the function. A harmonic restrain of the function can be chosen. A set 2nd harmonic current in relation to the fundamental current is used. The 2nd harmonic current is taken from the pre-processing of the phase currents and the relation is compared to a set restrain current level. The function can be directional. The direction of the fault current is given as current angle in relation to the voltage angle. The fault current and fault voltage for the directional function is dependent of the fault type. To enable directional measurement at close in faults, causing low measured voltage, the polarization voltage is a combination of the apparent voltage (85%) and a memory voltage (15%). The following combinations are used.
Phase-phase short circuit:
Vref _ AB = VA - VB
GUID-4F361BC7-6D91-47B5-8119-A27009C0AD6A V1 EN
I dir _ AB = I A - I B
(Equation 52)
Vref _ BC = VB - VC
ANSIEQUATION1450 V1 EN
I dir _ BC = I B - I C
(Equation 53)
Vref _ CA = VC - VA
ANSIEQUATION1451 V1 EN
I dir _ CA = IC - I A
(Equation 54)
Vref _ A = VA
ANSIEQUATION1452 V1 EN
I dir _ A = I A
(Equation 55)
Vref _ B = VB
ANSIEQUATION1453 V1 EN
I dir _ B = I B
(Equation 56)
Vref _ C = VC
ANSIEQUATION1454 V1 EN
I dir _ C = I C
(Equation 57)
The polarizing voltage is available as long as the positive-sequence voltage exceeds 4% of the set base voltage VBase. So the directional element can use it for all unsymmetrical faults including close-in faults. For close-in three-phase faults, the V1AM memory voltage, based on the same positive sequence voltage, ensures correct directional discrimination. The memory voltage is used for 100 ms or until the positive sequence voltage is restored. After 100 ms, the following occurs: If the current is still above the set value of the minimum operating current (between 10 and 30% of the set terminal rated current IBase), the condition seals in. If the fault has caused tripping, the trip endures. If the fault was detected in the reverse direction, the measuring element in the reverse direction remains in operation.
If the current decreases below the minimum operating value, the memory resets until the positive sequence voltage exceeds 10% of its rated value.
The directional setting is given as a characteristic angle AngleRCA for the function and an angle window AngleROA.
Reverse
Vref RCA
ROA
ROA
Forward
Idir
en05000745_ansi.vsd
ANSI05000745 V1 EN
Figure 129:
The default value of AngleRCA is 65. The parameters AngleROA gives the angle sector from AngleRCA for directional borders. A minimum current for directional phase pickup current signal can be set: PUMinOpPhSel. If no blockings are given the pickup signals will start the timers of the step. The time characteristic for each step can be chosen as definite time delay or inverse time characteristic. A wide range of standardized inverse time characteristics is available. It is also possible to create a tailor made time characteristic. The possibilities for inverse time characteristics are described in section "Inverse characteristics". All four steps in OC4PTOC (51/67) can be blocked from the binary input BLOCK. The binary input BLKx (x=1, 2, 3 or 4) blocks the operation of respective step.
|IOP| Pickupx
Characteristx=DefTime
a b AND a>b
AND
OR
0-tx 0
TRx
STx
BLKSTx BLOCK
0-txMin 0
Inverse
AND
STAGEx_DIR_Int
REVERSE_Int
AND
ANSI12000008-1-en.vsd ANSI12000008-1-en.vsd
ANSI12000008 V1 EN
Figure 130:
Different types of reset time can be selected as described in section "Inverse characteristics". There is also a possibility to activate a preset change (MultiPUx, x= 1, 2, 3 or 4) of the set operation current via a binary input (enable multiplier). In some applications the operation value needs to be changed, for example due to changed network switching state. The function can be blocked from the binary input BLOCK. The pickup signals from the function can be blocked from the binary input BLK. The trip signals from the function can be blocked from the binary input BLKTR.
Figure 131:
7.2.4
Table 135:
Name TRIP TRST1 TRST2 TRST3 TRST4 TR_A TR_B TR_C TRST1_A TRST1_B TRST1_C TRST2_A TRST2_B TRST2_C TRST3_A TRST3_B TRST3_C TRST4_A TRST4_B TRST4_C PICKUP PU_ST1 PU_ST2 PU_ST3
Common pickup signal from step4 Pickup signal from phase A Pickup signal from phase B Pickup signal from phase C Pickup signal from step1 phase A Pickup signal from step1 phase B Pickup signal from step1 phase C Pickup signal from step2 phase A Pickup signal from step2 phase B Pickup signal from step2 phase C Pickup signal from step3 phase A Pickup signal from step3 phase B Pickup signal from step3 phase C Pickup signal from step4 phase A Pickup signal from step4 phase B Pickup signal from step4 phase C Block from second harmonic detection Direction for phase A Direction for phase B Direction for phase C
7.2.5
Table 136:
Name Operation IBase Vbase AngleRCA AngleROA NumPhSel
Setting parameters
OC4PTOC (51_67) Group settings (basic)
Values (Range) Disabled Enabled 1 - 99999 0.05 - 2000.00 40 - 65 40 - 89 1 out of 3 2 out of 3 3 out of 3 Disabled Non-directional Forward Reverse Unit A kV Deg Deg Step 1 0.05 1 1 Default Disabled 3000 400.00 55 80 1 out of 3 Description Disable/Enable Operation Base current Base voltage Relay characteristic angle (RCA) Relay operation angle (ROA) Number of phases required for phase selection (1 of 3, 2 of 3, 3 of 3) Directional mode of step 1 (Disabled, Nondir, Forward, Reverse)
DirModeSel1
Non-directional
Name Characterist1
%IB s %IB s -
Phase current operate level for step1 in % of IBase Definitive time delay of step 1 Time multiplier for the inverse time delay for step 1 Minimum operate current for step1in% of IBase Minimum operate time for inverse curves for step 1 Multiplier for current operate level for step 1 Directional mode of step 2 (Disabled, Nondir, Forward, Reverse)
Characterist2
Pickup2
%IB
500
Definitive time delay of step 2 Time multiplier for the inverse time delay for step 2 Minimum operate current for step2 in % of IBase Minimum operate time for inverse curves for step 2 Multiplier for current operate level for step 2 Directional mode of step 3 (Disabled, Nondir, Forward, Reverse)
Characterist3
%IB s %IB s -
Phase current operate level for step3 in % of IBase Definitive time delay of step 3 Time multiplier for the inverse time delay for step 3 Minimum operate current for step3 in % of IBase Minimum operate time for inverse curves for step 3 Multiplier for current operate level for step 3 Directional mode of step 4 (Disabled, Nondir, Forward, Reverse)
Name Characterist4
%IB s %IB s -
Phase current operate level for step4 in % of IBase Definitive time delay of step 4 Time multiplier for the inverse time delay for step 4 Minimum operate current for step4 in % of IBase Minimum operate time for inverse curves for step 4 Multiplier for current operate level for step 4
Table 137:
Name PUMinOpPhSel 2ndHarmStab ResetTypeCrv1
s -
Reset time delay used in IEC Definite Time curve step 1 Parameter P for customer programmable curve for step 1 Parameter A for customer programmable curve for step 1 Parameter B for customer programmable curve for step 1
Parameter C for customer programmable curve for step 1 Parameter PR for customer programmable curve for step 1 Parameter TR for customer programmable curve for step 1 Parameter CR for customer programmable curve for step 1 Enable block of step 1 from harmonic restrain Selection of reset curve type for step 2
tReset2 tPCrv2 tACrv2 tBCrv2 tCCrv2 tPRCrv2 tTRCrv2 tCRCrv2 HarmRestrain2 ResetTypeCrv3
s -
0.020 1.000 13.500 0.00 1.0 0.500 13.500 1.0 Disabled Instantaneous
Reset time delay used in IEC Definite Time curve step 2 Parameter P for customer programmable curve for step 2 Parameter A for customer programmable curve for step 2 Parameter B for customer programmable curve for step 2 Parameter C for customer programmable curve for step 2 Parameter PR for customer programmable curve for step 2 Parameter TR for customer programmable curve for step 2 Parameter CR for customer programmable curve for step 2 Enable block of step 2 from harmonic restrain Selection of reset curve type for step 3
s -
Reset time delay used in IEC Definite Time curve step 3 Parameter P for customer programmable curve for step 3 Parameter A for customer programmable curve for step 3 Parameter B for customer programmable curve for step 3 Parameter C for customer programmable curve for step 3 Parameter PR for customer programmable curve for step 3
s -
Reset time delay used in IEC Definite Time curve step 4 Parameter P for customer programmable curve for step 4 Parameter A for customer programmable curve for step 4 Parameter B for customer programmable curve for step 4 Parameter C for customer programmable curve for step 4 Parameter PR for customer programmable curve for step 4 Parameter TR for customer programmable curve for step 4 Parameter CR for customer programmable curve for step 4 Enable block of step 4 from harmonic restrain
Table 138:
Name MeasType
7.2.6
Technical data
Table 139:
Function Operate current Reset ratio Min. operating current Table continues on next page 295
2.0 degrees 2.0 degrees 2.0 degrees 2.0% of In 0.5% 10 ms 0.5% 10 ms See table 588, table 589 and table 590 -
7.3
IN>>
IEF V1 EN
7.3.1
Introduction
The Instantaneous residual overcurrent protection EFPIOC (50N) has a low transient overreach and short tripping times to allow the use for instantaneous ground-fault protection, with the reach limited to less than the typical eighty percent of the line at minimum source impedance. EFPIOC (50N) can be configured to measure the residual current from the three-phase current inputs or the current from a separate current input. EFPIOC (50N) can be blocked by activating the input BLOCK.
7.3.2
Principle of operation
The sampled analog residual currents are pre-processed in a discrete Fourier filter (DFT) block. From the fundamental frequency components of the residual current, as
well as from the sample values the equivalent RMS value is derived. This current value is fed to the Instantaneous residual overcurrent protection (EFPIOC,50N). In a comparator the RMS value is compared to the set operation current value of the function (Pickup). If the residual current is larger than the set operation current a signal from the comparator is set to true. This signal will, without delay, activate the output signal TRIP. There is also a possibility to activate a preset change of the set operation current via a binary input (enable multiplier MULTPU). In some applications the operation value needs to be changed, for example due to transformer inrush currents. EFPIOC (50N) function can be blocked from the binary input BLOCK. The trip signals from the function can be blocked from the binary input BLKAR, that can be activated during single pole trip and autoreclosing sequences.
7.3.3
Function block
EFPIOC (50N) I3P* BLOCK BLKAR MULTPU TRIP
ANSI06000269-2-en.vsd
ANSI06000269 V2 EN
Figure 132:
7.3.4
Table 141:
Name TRIP
Setting parameters
EFPIOC (50N) Group settings (basic)
Values (Range) Disabled Enabled 1 - 99999 1 - 2500 Unit A %IB Step 1 1 Default Disabled 3000 200 Description Disable/Enable Operation Base current Operate residual current level in % of IBase
Table 143:
Name MultPU
7.3.6
Technical data
Table 144:
Function Operate current Reset ratio Operate time Reset time Critical impulse time Operate time Reset time Critical impulse time Dynamic overreach
7.4
Four step residual overcurrent protection, zero, negative sequence direction EF4PTOC (51N/67N)
IN 4 4 alt
TEF-REVA V1 EN
7.4.1
Introduction
The four step residual overcurrent protection EF4PTOC (51N/67N) has an inverse or definite time delay independent for each step separately. All IEC and ANSI time-delayed characteristics are available together with an optional user defined characteristic. EF4PTOC (51N/67N) can be set directional or non-directional independently for each of the steps. IDir, VPol and IPol can be independently selected to be either zero sequence or negative sequence. Second harmonic blocking can be set individually for each step. EF4PTOC (51N/67N) can be used as main protection for phase-to-ground faults. EF4PTOC (51N/67N) can also be used to provide a system back-up for example, in the case of the primary protection being out of service due to communication or voltage transformer circuit failure. Directional operation can be combined together with corresponding communication logic in permissive or blocking teleprotection scheme. Current reversal and weak-end infeed functionality are available as well. EF4PTOC (51N/67N) can be configured to measure the residual current from the threephase current inputs or the current from a separate current input.
7.4.2
Principle of operation
This function has the following three Analog Inputs on its function block in the configuration tool: 1. 2. 3. I3P, input used for Operating Quantity. V3P, input used for Voltage Polarizing Quantity. I3PPOL, input used for Current Polarizing Quantity.
These inputs are connected from the corresponding pre-processing function blocks in the Configuration Tool within PCM600.
7.4.2.1
2.
calculated from three-phase current input within the IED (when the fourth analog input into the pre-processing block connected to EF4PTOC (51N/67N) function Analog Input I3P is not connected to a dedicated CT input of the IED in PCM600). In such case the pre-processing block will calculate 3I0 from the first three inputs into the pre-processing block by using the following formula (will take I2 from same SMAI AI3P connected to I3PDIR input (same SMAI AI3P connected to I3P input)):
(Equation 58)
where: IA, IB, IC are fundamental frequency phasors of three individual phase currents.
The residual current is pre-processed by a discrete Fourier filter. Thus the phasor of the fundamental frequency component of the residual current is derived. The phasor magnitude is used within the EF4PTOC (51N/67N) protection to compare it with the set operation current value of the four steps (Pickup1, Pickup2, Pickup3 or Pickup4). If the residual current is larger than the set operation current and the step is used in non300 Technical reference manual
directional mode a signal from the comparator for this step is set to true. This signal will, without delay, activate the output signal PUSTx (x=step 1-4) for this step and a common PICKUP signal.
7.4.2.2
Internal polarizing
A polarizing quantity is used within the protection in order to determine the direction to the ground fault (Forward/Reverse). The function can be set to use voltage polarizing, current polarizing or dual polarizing.
Voltage polarizing
When voltage polarizing is selected the protection will use either the residual voltage -3V0 or the negative sequence voltage -3V2 as polarizing quantity V3P. This voltage can be: 1. directly measured (when a dedicated VT input of the IED is connected in PCM600 to the fourth analog input of the pre-processing block connected to EF4PTOC (51N/ 67N) function input V3P). This dedicated IED VT input shall be then connected to open delta winding of a three phase main VT. calculated from three phase voltage input within the IED (when the fourth analog input into the pre-processing block connected to EF4PTOC (51N/67N) analog function input V3P is NOT connected to a dedicated VT input of the IED in PCM600). In such case the pre-processing block will calculate -3V2 from the first three inputs into the pre-processing block by using the following formula:
2.
(Equation 60)
where: VA, VB, VC are fundamental frequency phasors of three individual phase voltages. In order to use this, all three phase-to-ground voltages must be connected to three IED VT inputs.
The residual voltage is pre-processed by a discrete fourier filter. Thus, the phasor of the fundamental frequency component of the residual voltage is derived. This phasor is used together with the phasor of the operating directional current, in order to determine the direction to the ground fault (Forward/Reverse). In order to
enable voltage polarizing the magnitude of polarizing voltage shall be bigger than a minimum level defined by setting parameter VpolMin. It shall be noted that residual voltage (-3V0) or negative sequence voltage (-3V2) is used to determine the location of the ground fault. This insures the required inversion of the polarizing voltage within the ground-fault function.
Current polarizing
When current polarizing is selected the function will use an external residual current (3I0) as polarizing quantity IPol. This current can be: 1. directly measured (when a dedicated CT input of the IED is connected in PCM600 to the fourth analog input of the pre-processing block connected to EF4PTOC (51N/ 67N) function input I3PPOL). This dedicated IED CT input is then typically connected to one single current transformer located between power system WYE point and ground (current transformer located in the WYE point of a WYE connected transformer winding). For some special line protection applications this dedicated IED CT input can be connected to parallel connection of current transformers in all three phases (Holm-Green connection).
2.
calculated from three phase current input within the IED (when the fourth analog input into the pre-processing block connected to EF4PTOC (51N/67N) function analog input I3PPOL is NOT connected to a dedicated CT input of the IED in PCM600). In such case the pre-processing block will calculate 3I0 from the first three inputs into the pre-processing block by using the following formula:
I Pol = 3 Io = IA + IB + IC
EQUATION2019-ANSI V1 EN
(Equation 62)
where: IA, IB and IC are fundamental frequency phasors of three individual phase currents.
The residual current is pre-processed by a discrete fourier filter. Thus the phasor of the fundamental frequency component of the polarizing current is derived. This phasor is then multiplied with pre-set equivalent zero-sequence source Impedance in order to calculate equivalent polarizing voltage VIPol in accordance with the following formula:
VIPol = Zo S I Pol = ( RNPol + j XNPOL ) I Pol
EQUATION2013-ANSI V1 EN
(Equation 63)
which will be then used, together with the phasor of the operating current, in order to determine the direction to the ground fault (Forward/Reverse).
In order to enable current polarizing the magnitude of polarizing current shall be bigger than a minimum level defined by setting parameter IPolMin.
Dual polarizing
When dual polarizing is selected the function will use the vectorial sum of the voltage based and current based polarizing in accordance with the following formula:
VTotPol = VVPol + VIPol = -3V0 + Z 0 s IPol = -3V0 + ( RNPol + jXNPol ) IPol
ANSIEQUATION1878 V1 EN
(Equation 64)
Vpol and Ipol can be either zero sequence component or negative sequence component depending upon the user selection. Then the phasor of the total polarizing voltage VTotPol will be used, together with the phasor of the operating current, to determine the direction of the ground fault (Forward/ Reverse).
7.4.2.3
7.4.2.4
7.4.2.5
1. 2. 3. 4.
Four residual overcurrent steps. Directional supervision element for residual overcurrent steps with integrated directional comparison step for communication based ground-fault protection schemes (permissive or blocking). Second harmonic blocking element with additional feature for sealed-in blocking during switching of parallel transformers. Switch on to fault feature with integrated Under-Time logic for detection of breaker problems during breaker opening or closing sequence.
7.4.2.6
Simplified logic diagram for one residual overcurrent step is shown in figure 133.
BLKTR IMinx
X
|IOP|
T F
Characteristx=DefTime
b a a>b
tx
a b a>b OR
AND
TRSTx
T F
AND
PUSTx
AND
Inverse
tMin
Characteristx=Inverse 2ndHarm_BLOCK_Int
OR
STEPx_DIR_Int
REVERSE_Int
AND
ANSI10000008-1-en.vsd
ANSI10000008 V1 EN
Figure 133:
The protection can be completely blocked from the binary input BLOCK. Output signals for respective step, and PUSTx and TRSTx, can be blocked from the binary input BLKx. The trip signals from the function can be blocked from the binary input BLKTR.
7.4.2.7
The operating and polarizing quantity are then used inside the directional element, as shown in figure 134, in order to determine the direction of the ground fault.
305 Technical reference manual
Operating area
PUREV
0.6 * INDirPU Characteristic for reverse release of measuring steps -RCA -85 deg Characteristic for PUREV
40% of INDirPU
RCA 65
VPol = -3V0
INDirPU
PUFW
I op = 3I0 Operating area Characteristic for PUFW
ANSI11000243 V1 EN
ANSI11000243-1-en.ai
Figure 134:
Operating characteristic for ground-fault directional element using the zero sequence components
Two relevant setting parameters for directional supervision element are: Directional element will be internally enabled to operate as soon as Iop is bigger than 40% of IDirPU and directional condition is fulfilled in set direction. Relay characteristic angle AngleRCA, which defines the position of forward and reverse areas in the operating characteristic.
Directional comparison step, built-in within directional supervision element, will set EF4PTOC (51N/67N) function output binary signals:
1. 2.
PUFW=1 when operating quantity magnitude Iop x cos( - AngleRCA) is bigger than setting parameter IDirPU and directional supervision element detects fault in forward direction. PUREV=1 when operating quantity magnitude Iop x cos( - AngleRCA) is bigger than 60% of setting parameter IDirPU and directional supervision element detects fault in reverse direction.
These signals shall be used for communication based ground-fault teleprotection communication schemes (permissive or blocking). Simplified logic diagram for directional supervision element with integrated directional comparison step is shown in figure 135:
|IopDir|
a a>b b
REVERSE_Int
a
AND
PUREV
0.6
IDirPU
X
a>b b
FORWARD_Int
AND
PUFW
0.4
FWD polMethod=Voltage polMethod=Dual polMethod=Current IPol 0.0 RNPol XNPol BLOCK OR T F X VIPol 0.0 T F STAGE1_DIR_Int STAGE2_DIR_Int STAGE3_DIR_Int STAGE4_DIR_Int AngleRCA
Directional Characteristic
AND
FORWARD_Int
OR VPol
RVS
AND
REVERSE_Int
Complex Number
OR AND
ANSI07000067-4-en.vsd
ANSI07000067 V4 EN
Figure 135:
Simplified logic diagram for directional supervision element with integrated directional comparison step
A harmonic restrain of the Four step residual overcurrent protection function EF4PTOC (51N67N) can be chosen. If the ratio of the 2nd harmonic component in relation to the fundamental frequency component in the residual current exceeds the preset level (defined by parameter setting 2ndHarmStab) any of the four residual overcurrent stages can be selectively blocked by a parameter setting HarmRestrainx. When 2nd harmonic restraint feature is active the EF4PTOC (51N67N) function output signal 2NDHARMD will be set to logical value one. In addition to the basic functionality explained above the 2nd harmonic blocking can be set in such way to seal-in until residual current disappears. This feature might be required to stabilize EF4PTOC (51N67N) during switching of parallel transformers in the station. In case of parallel transformers there is a risk of sympathetic inrush current. If one of the transformers is in operation, and the parallel transformer is switched in, the asymmetric inrush current of the switched in transformer will cause partial saturation of the transformer already in service. This is called transferred saturation. The 2nd harmonic of the inrush currents of the two transformers will be in phase opposition. The summation of the two currents will thus give a small 2nd harmonic current. The residual fundamental current will however be significant. The inrush current of the transformer in service before the parallel transformer energizing, will be a little delayed compared to the first transformer. Therefore we will have high 2nd harmonic current component initially. After a short period this current will however be small and the normal 2nd harmonic blocking will reset. If the BlkParTransf function is activated the 2nd harmonic restrain signal will be latched as long as the residual current measured by the relay is larger than a selected step current level. This feature has been called Block for Parallel Transformers. This 2nd harmonic seal-in feature will be activated when all of the following three conditions are simultaneously fulfilled: 1. 2. 3. Feature is enabled by entering setting parameter BlkParTransf = On. Basic 2nd harmonic restraint feature has been active for at least 70ms. Residual current magnitude is higher than the set pickup value for one of the four residual overcurrent stages. By a parameter setting Use_PUValue it is possible to select which one of the four pickup values that will be used (Pickup1 or Pickup2 or Pickup3 or Pickup4).
Once Block for Parallel Transformers is activated the basic 2nd harmonic blocking signal will be sealed-in until the residual current magnitude falls below a value defined by parameter setting Use_PUValue (see condition 3 above). Simplified logic diagram for 2nd harmonic blocking feature is shown in figure 136.
BLOCK
IOP
2ndHarmStab
a>b
OR
2NDHARMD
q-1
0-70ms 0
OR
AN D
OR
2ndH_BLOCK_Int
BlkParTransf=On
|IOP|
a b a>b
en07000068-2_ansi.vsd
ANSI07000068 V2 EN
Figure 136:
Simplified logic diagram for 2nd harmonic blocking feature and Block for Parallel Transformers feature
7.4.2.9
The Under-Time logic always uses the pickup signal from the step 4. The Under-Time logic will normally be set to operate for a lower current level than the SOTF function. The Under-Time logic can also be blocked by the 2nd harmonic restraint feature. This enables high sensitivity even if power transformer inrush currents can occur at breaker closing. This logic is typically used to detect asymmetry of CB poles immediately after switching of the circuit breaker. The Under-Time logic is activated either from change in circuit breaker position or from circuit breaker close and open command pulses. This selection is done by setting parameter ActUnderTime. In case of a pickup from step 4 this logic will give a trip after a set delay tUnderTime. This delay is normally set to a relatively short time (default 300 ms). Practically the Under-Time logic acts as circuit breaker pole-discrepancy protection, but it is only active immediately after breaker switching. The Under-Time logic can only be used in solidly or low impedance grounded systems.
SOTF
SOTFSel tSOTF
t
OR
Open Close
OR
ActUndrTimeSel
AND
Figure 137:
EF4PTOC (51N/67N) Logic Diagram Simplified logic diagram for the complete EF4PTOC (51N/67N) function is shown in figure 138:
Direction Element
TRIP
3I0
harmRestrBlock
or
pickup step 2 , 3 and 4 Blocking at parallel transformers SwitchOnToFault CB pos or cmd TRIP
Figure 138:
7.4.3
Function block
EF4PTOC (51N67N) I3P* TRIP V3P* TRST1 I3PPOL* TRST2 BLOCK TRST3 BLKTR TRST4 BLK1 TRSOTF BLK2 PICKUP BLK3 PUST1 BLK4 PUST2 MULTPU1 PUST3 MULTPU2 PUST4 MULTPU3 PUSOTF MULTPU4 PUFW 52A PUREV CLOSECMD 2NDHARMD OPENCMD ANSI06000424-2-en.vsd
ANSI06000424 V2 EN
Figure 139:
Table 146:
Name TRIP TRST1 TRST2 TRST3 TRST4 TRSOTF PICKUP PUST1 PUST2 PUST3 PUST4 PUSOTF
7.4.5
Table 147:
Name Operation IBase VBase AngleRCA polMethod
Setting parameters
EF4PTOC (51N67N) Group settings (basic)
Values (Range) Disabled Enabled 1 - 99999 0.05 - 2000.00 -180 - 180 Voltage Current Dual 1 - 100 2 - 100 0.50 - 1000.00 0.50 - 3000.00 1 - 100 5 - 100 Disabled Enabled ST1 ST2 ST3 ST4 Disabled SOTF UnderTime SOTF&UnderTime Open Closed CloseCommand Step 2 Step 3 Unit A kV Deg Step 1 0.05 1 Default Disabled 3000 400 65 Voltage Description Disable/Enable Operation Base value for current settings Base value for voltage settings Relay characteristic angle (RCA) Type of polarization
1 1 0.01 0.01 1 1 -
Minimum voltage level for polarization in % of VBase Minimum current level for polarization in % of IBase Real part of source Z to be used for current polarisation Imaginary part of source Z to be used for current polarisation Residual current level for directional element in % of IBase Second harmonic restrain operation in % of IN magnitude Enable blocking at parallel transformers Current pickup blocking at parallel transf (step1, 2, 3 or 4)
SOTF
Disabled
SOTFSel
Open
StepForSOTF
Step 2
Enable harmonic restrain function in SOTF Time delay for SOTF Switch-onto-fault active time Select signal to activate under time (CB Pos/ CBCommand) Time delay for under time Directional mode of step 1 (Disabled, Nondir, Forward, Reverse)
Characterist1
%IB s %IB s -
Residual current pickup for step 1 in % of IBase Independent (defenite) time delay of step 1 Time multiplier for the dependent time delay for step 1 Minimum current for step 1 Minimum operate time for inverse curves for step 1 Multiplier for scaling the current setting value for step 1 Reset curve type for step 1
s -
0.001 0.001
Reset time delay for step 1 Enable block of step 1 from harmonic restrain Parameter P for customer programmable curve for step 1
Characterist2
%IB s %IB s -
Residual current pickup for step 2 in % of IBase Independent (definitive) time delay of step 2 Time multiplier for the dependent time delay for step 2 Minimum current for step 2 Minimum operate time for inverse curves step 2 Multiplier for scaling the current setting value for step 2 Reset curve type for step 2
tReset2
0.001
0.020
Enable block of step 2 from harmonic restrain Parameter P for customer programmable curve for step 2 Parameter A for customer programmable curve for step 2 Parameter B for customer programmable curve for step 2 Parameter C for customer programmable curve for step 2 Parameter PR for customer programmable curve for step 2 Parameter TR for customer programmable curve for step 2 Parameter CR for customer programmable curve for step 2 Directional mode of step 3 (Disabled, Nondir, Forward, Reverse)
Characterist3
%IB s %IB s -
Residual current pickup for step 3 in % of IBase Independent time delay of step 3 Time multiplier for the dependent time delay for step 3 Minimum current for step 3 Minimum operate time for inverse curves for step 3 Multiplier for scaling the current setting value for step 3
Name ResetTypeCrv3
tReset3 HarmRestrain3 tPCrv3 tACrv3 tBCrv3 tCCrv3 tPRCrv3 tTRCrv3 tCRCrv3 DirModeSel4
s -
0.020 Enabled 1.000 13.500 0.00 1.0 0.500 13.500 1.0 Non-directional
Reset time delay for step 3 Enable block of step 3 from harmonic restrain Parameter P for customer programmable curve for step 3 Parameter A for customer programmable curve for step 3 Parameter B for customer programmable curve for step 3 Parameter C for customer programmable curve step 3 Parameter PR for customer programmable curve step 3 Parameter TR for customer programmable curve step 3 Parameter CR for customer programmable curve for step 3 Directional mode of step 4 (Disabled, Nondir, Forward, Reverse)
Characterist4
%IB s %IB s
Residual current pickup for step 4 in % of IBase Independent (definitive) time delay of step 4 Time multiplier for the dependent time delay for step 4 Minimum current for step 4 Minimum operate time in inverse curves step 4
Multiplier for scaling the current setting value for step 4 Reset curve type for step 4
s -
Reset time delay for step 4 Enable block of step 4 from harmonic restrain Parameter P for customer programmable curve for step 4 Parameter A for customer programmable curve step 4 Parameter B for customer programmable curve for step 4 Parameter C for customer programmable curve step 4 Parameter PR for customer programmable curve step 4 Parameter TR for customer programmable curve step 4 Parameter CR for customer programmable curve step 4
7.4.6
Technical data
Table 148:
Function Operate current Reset ratio Operate current for directional comparison Timers Inverse characteristics, see table 588, table 589 and table 590 Second harmonic restrain operation Relay characteristic angle Minimum polarizing voltage Minimum polarizing current Real part of source Z used for current polarization Table continues on next page
7.5
Four step directional negative phase sequence overcurrent protection NS4PTOC (46I2)
Function description Four step negative sequence overcurrent protection IEC 61850 identification NS4PTOC
4 4 alt
I2
46I2
IEC10000053 V1 EN
7.5.1
Introduction
Four step negative sequence overcurrent protection (NS4PTOC, (4612) ) has an inverse or definite time delay independent for each step separately. All IEC and ANSI time delayed characteristics are available together with an optional user defined characteristic. The directional function is voltage polarized or dual polarized. NS4PTOC (4612) can be set directional or non-directional independently for each of the steps. NS4PTOC (4612) can be used as main protection for unsymmetrical fault; phase-phase short circuits, phase-phase-ground short circuits and single phase ground faults. NS4PTOC (4612) can also be used to provide a system back-up for example, in the case of the primary protection being out of service due to communication or voltage transformer circuit failure. Directional operation can be combined together with corresponding communication logic in permissive or blocking teleprotection scheme. The same logic as for
319
directional zero sequence current can be used. Current reversal and weak-end infeed functionality are available.
7.5.2
Principle of operation
Four step negative sequence overcurrent protection NS4PTOC (4612) function has the following three Analog Inputs on its function block in the configuration tool: 1. 2. 3. I3P, input used for Operating Quantity. V3P, input used for Voltage Polarizing Quantity. I3PPOL, input used for Polarizing Quantity.
These inputs are connected from the corresponding pre-processing function blocks in the Configuration Tool within PCM600.
7.5.2.1
)
(Equation 65)
ANSIEQUATION2266 V1 EN
where: IA, IB, IC a a2 are fundamental frequency phasors of three individual phase currents. is so called operator which gives a phase shift of 120 deg, that is, a = 1120 deg similarly gives a phase shift of 240 deg, that is, a2 = 1240 deg
The negative sequence current is pre-processed by a discrete Fourier filter. Thus, the phasor of the fundamental frequency component of the negative sequence current is derived. The phasor magnitude is used within the NS4PTOC (4612) protection to compare it with the set operation current value of the four steps (Pickup1, Pickup2, Pickup3 or Pickup4). If the negative sequence current is larger than the set operation current and the step is used in non-directional mode a signal from the comparator for this step is set to true. This signal, without delay, activates the output signal PU_STx (x=1 - 4) for this step and a common PICKUP signal.
7.5.2.2
Voltage polarizing
When voltage polarizing is selected, NS4PTOC (4612) uses the negative sequence voltage -V2 as polarizing quantity V3P. This voltage is calculated from three phase voltage input within the IED. The pre-processing block calculates -V2 from the first three inputs into the pre-processing block by using the following formula:
V2 = 1 3 VA + a VB + a VC
2
ANSIEQUATION00024 V1 EN
where: VA, VB, VC are fundamental frequency phasors of three individual phase voltages. To use this all three phase-to-ground voltages must be connected to three IED VT inputs.
The negative sequence voltage is pre-processed by a discrete fourier filter. Thus, the phasor of the fundamental frequency component of the negative sequence voltage is derived. This phasor is used together with the phasor of the operating current, in order to determine the direction to the fault (Forward/Reverse).To enable voltage polarizing the magnitude of polarizing voltage must be bigger than a minimum level defined by setting VpolMin. Note that V2 is used to determine the location of the fault. This ensures the required inversion of the polarizing voltage within the function.
Dual polarizing
When dual polarizing is selected, the function uses the vectorial sum of the voltage based and current based polarizing in accordance with the following formula:
VTotPol = VVPol + VIPol = -V 2 + Z Pol I Pol = -V 2 + ( R Pol + jX Pol ) I Pol
ANSIEQUATION2315 V1 EN
(Equation 66)
Then the phasor of the total polarizing voltage VTotPol is used, together with the phasor of the operating current, to determine the direction to the fault (Forward/Reverse).
7.5.2.3
7.5.2.4
7.5.2.5
7.5.2.6
itself. The direction of the fault is determined in common Directional Supervision Element described in the next paragraph. Negative sequence current pickup value. Type of operating characteristic (Inverse or Definite Time). By this parameter setting it is possible to select Inverse or definite time delay for negative sequence overcurrent function. Most of the standard IEC and ANSI inverse characteristics are available. For the complete list of available inverse curves, refer to Chapter "Inverse time characteristics" Type of reset characteristic (Instantaneous / IEC Reset /ANSI reset).By this parameter setting it is possible to select the reset characteristic of the stage. For the complete list of available reset curves, refer to Chapter "Inverse time characteristics" Time delay related settings. By these parameter settings the properties like definite time delay, minimum operating time for inverse curves, reset time delay and parameters to define user programmable inverse curve are defined. Multiplier for scaling of the set negative sequence current pickup value by external binary signal. By this parameter setting it is possible to increase negative sequence current pickup value when function binary input MULTPUx has logical value 1.
Simplified logic diagram for one negative sequence overcurrent stage is shown in the following figure:
ANSI09000684 V1 EN
Figure 140:
Simplified logic diagram for negative sequence overcurrent stage x , where x=1, 2, 3 or 4
323
NS4PTOC (4612) can be completely blocked from the binary input BLOCK. The pickup signals from NS4PTOC (4612) for each stage can be blocked from the binary input BLKx. The trip signals from NS4PTOC (4612) can be blocked from the binary input BLKTR.
7.5.2.7
The operating and polarizing quantity are then used inside the directional element, as shown in figure 134, to determine the direction of the fault.
Reverse Area
AngleRCA
Vpol=-V2
ANSI10000031-1-en.vsd
ANSI10000031 V1 EN
Figure 141:
Two relevant setting parameters for directional supervision element are: Directional element is internally enable to operate as soon as IOp is bigger than 40% of INDirPU and the directional condition is fulfilled in set direction. Relay characteristic angle AngleRCA which defines the position of forward and reverse areas in the operating characteristic.
Directional comparison step, built-in within directional supervision element, set NS4PTOC (4612) output binary signals: 1. 2. PUFW=1 when tip of I2 phasor (operating quantity magnitude) is in forward area, see fig 134 (Operating quantity magnitude is bigger than setting INDirPU) PUREV=1 when tip of I2 phasor (operating quantity magnitude) is in the reverse area, see fig 134. (Operating quantity magnitude is bigger than 60% of setting INDirPU)
These signals must be used for communication based fault teleprotection communication schemes (permissive or blocking). Simplified logic diagram for directional supervision element with integrated directional comparison step is shown in figure 135:
|IopDir|
a a>b b
REVERSE_Int
a
AND
PUREV
0.6
IDirPU
X
a>b b
FORWARD_Int
AND
PUFW
0.4
FWD polMethod=Voltage polMethod=Dual polMethod=Current IPol 0.0 RNPol XNPol BLOCK OR T F X VIPol 0.0 T F STAGE1_DIR_Int STAGE2_DIR_Int STAGE3_DIR_Int STAGE4_DIR_Int AngleRCA
Directional Characteristic
AND
FORWARD_Int
OR VPol
RVS
AND
REVERSE_Int
Complex Number
OR AND
ANSI07000067-4-en.vsd
ANSI07000067 V4 EN
Figure 142:
Simplified logic diagram for directional supervision element with integrated directional comparison step
7.5.3
Figure 143:
7.5.4
Table 150:
Name TRIP TRST1 TRST2 TRST3 TRST4 PICKUP PU_ST1 PU_ST2 PU_ST3 PU_ST4 PUFW PUREV
7.5.5
Table 151:
Name Operation IBase VBase AngleRCA polMethod VPolMin IPolMin RPol XPol I>Dir DirModeSel1
Setting parameters
NS4PTOC (46I2) Group settings (basic)
Values (Range) Disabled Enabled 1 - 99999 0.05 - 2000.00 -180 - 180 Voltage Dual 1 - 100 2 - 100 0.50 - 1000.00 0.50 - 3000.00 1 - 100 Disabled Non-directional Forward Reverse Unit A kV Deg %VB %IB ohm ohm %IB Step 1 0.05 1 1 1 0.01 0.01 1 Default Disabled 3000 400 65 Voltage 5 5 5.00 40.00 10 Non-directional Description Disable/Enable Operation Base value for current settings Base value for voltage settings Relay characteristic angle (RCA) Type of polarization Minimum voltage level for polarization in % of VBase Minimum current level for polarization in % of IBase Real part of neg. seq. source imp. to be used for current polarisation Imaginary part of neg. seq. source imp. to be used for current polarisation Neg. seq. curr. I2 level for Direction release in % of IBase Directional mode of step 1 (Disabled, Nondir, Forward, Reverse)
Name Characterist1
%IB s %IB s -
Operate neg. seq. curr. I2 level for step 1 in % of IBase Independent (defenite) time delay of step 1 Time multiplier for the dependent time delay for step 1 Minimum current for step 1 Minimum operate time for inverse curves for step 1 Multiplier for scaling the current setting value for step 1 Reset curve type for step 1
s -
Reset time delay for step 1 Parameter P for customer programmable curve for step 1 Parameter A for customer programmable curve for step 1 Parameter B for customer programmable curve for step 1 Parameter C for customer programmable curve for step 1 Parameter PR for customer programmable curve for step 1 Parameter TR for customer programmable curve for step 1 Parameter CR for customer programmable curve for step 1
Characterist2
%IB s %IB s -
Operate neg. seq. curr. I2 level for step 2 in % of IBase Independent (definitive) time delay of step 2 Time multiplier for the dependent time delay for step 2 Minimum current for step 2 Minimum operate time for inverse curves step 2 Multiplier for scaling the current setting value for step 2 Reset curve type for step 2
s -
Reset time delay for step 2 Parameter P for customer programmable curve for step 2 Parameter A for customer programmable curve for step 2 Parameter B for customer programmable curve for step 2 Parameter C for customer programmable curve for step 2 Parameter PR for customer programmable curve for step 2 Parameter TR for customer programmable curve for step 2
Characterist3
%IB s %IB s -
Operate neg. seq. curr. I2 level for step 3 in % of IBase Independent time delay of step 3 Time multiplier for the dependent time delay for step 3 Minimum current for step 3 Minimum operate time for inverse curves for step 3 Multiplier for scaling the current setting value for step 3 Reset curve type for step 3
s -
Reset time delay for step 3 Parameter P for customer programmable curve for step 3 Parameter A for customer programmable curve for step 3 Parameter B for customer programmable curve for step 3 Parameter C for customer programmable curve step 3 Parameter PR for customer programmable curve step 3
Parameter TR for customer programmable curve step 3 Parameter CR for customer programmable curve for step 3 Directional mode of step 4 (Disabled, Nondir, Forward, Reverse)
Characterist4
%IB s %IB s -
Operate neg. seq. curr. I2 level for step 4 in % of IBase Independent (definitive) time delay of step 4 Time multiplier for the dependent time delay for step 4 Minimum current for step 4 Minimum operate time in inverse curves step 4 Multiplier for scaling the current setting value for step 4 Reset curve type for step 4
s -
Reset time delay for step 4 Parameter P for customer programmable curve for step 4 Parameter A for customer programmable curve step 4 Parameter B for customer programmable curve for step 4 Parameter C for customer programmable curve step 4
7.5.6
Technical data
Table 152:
Function Operate value, negative sequence current, step 1-4 Reset ratio Timers Inverse characteristics, see table 588, table 589 and table 590 Minimum operate current for step 1 - 4 Operate value, negative current for directional release Relay characteristic angle Minimum polarizing voltage Minimum polarizing current Real part of negative sequence source impedance used for current polarization Imaginary part of negative sequence source impedance used for current polarization Operate time, pickup function Reset time, pickup function Critical impulse time, pickup function Impulse margin time, pickup function Transient overreach
(0.503000.00) W/phase
25 ms typically at 0.5 to 2 x Iset 25 ms typically at 2 to 0.5 x Iset 10 ms typically at 0 to 2 x Iset 15 ms typically <10% at = 100 ms
7.6
7.6.1
Introduction
In networks with high impedance grounding, the phase-to-ground fault current is significantly smaller than the short circuit currents. Another difficulty for ground-fault protection is that the magnitude of the phase-to-ground fault current is almost independent of the fault location in the network. Directional residual current can be used to detect and give selective trip of phase-toground faults in high impedance grounded networks. The protection uses the residual current component 3I0 cos , where is the angle between the residual current and the residual voltage (-3V0), compensated with a characteristic angle. Alternatively, the function can be set to strict 3I0 level with a check of angle 3I0 and cos . Directional residual power can also be used to detect and give selective trip of phase-toground faults in high impedance grounded networks. The protection uses the residual power component 3I0 3V0 cos , where is the angle between the residual current and the reference residual voltage, compensated with a characteristic angle. A normal non-directional residual current function can also be used with definite or inverse time delay. A back-up neutral point voltage function is also available for non-directional sensitive back-up protection. In an isolated network, that is, the network is only coupled to ground via the capacitances between the phase conductors and ground, the residual current always has -90 phase shift compared to the reference residual voltage. The characteristic angle is chosen to -90 in such a network. In resistance grounded networks or in Petersen coil grounded, with a parallel resistor, the active residual current component (in phase with the residual voltage) should be used for the ground-fault detection. In such networks the characteristic angle is chosen to 0.
As the magnitude of the residual current is independent of the fault location the selectivity of the ground-fault protection is achieved by time selectivity. When should the sensitive directional residual overcurrent protection be used and when should the sensitive directional residual power protection be used? Consider the following facts: Sensitive directional residual overcurrent protection gives possibility for better sensitivity. The setting possibilities of this function are down to 0.25 % of IBase, 1 A or 5 A. This sensitivity is in most cases sufficient in high impedance network applications, if the measuring CT ratio is not too high. Sensitive directional residual power protection gives possibility to use inverse time characteristics. This is applicable in large high impedance grounded networks, with large capacitive ground-fault current In some power systems a medium size neutral point resistor is used, for example, in low impedance grounded system. Such a resistor will give a resistive groundfault current component of about 200 - 400 A at a zero resistive phase-to-ground fault. In such a system the directional residual power protection gives better possibilities for selectivity enabled by inverse time power characteristics.
7.6.2
7.6.2.1
Principle of operation
Function inputs
The function is using phasors of the residual current and voltage. Group signals I3P and V3P containing phasors of residual current and voltage is taken from pre-processor blocks. The sensitive directional ground fault protection has the following sub-functions included:
Vref
RCA = 0, ROA = 90
3I0
en06000648_ansi.vsd
ANSI06000648 V1 EN
Figure 144:
RCADir set to 0
Vref RCA = -90, ROA = 90
en06000649_ansi.vsd
ANSI06000649 V1 EN
Figure 145:
For trip, both the residual current 3I0cos and the release voltage 3V0, must be larger than the set levels: INCosPhiPU and VNRelPU.
Trip from this function can be blocked from the binary input BLKTRDIR. When the function is activated binary output signals PICKUP and PUDIRIN are activated. If the output signals are active after the set delay tDef the binary output signals TRIP and TRDIRIN are activated. The trip from this sub-function has definite time delay. There is a possibility to increase the operate level for currents where the angle is larger than a set value as shown in figure 146. This is equivalent to blocking of the function if > ROADir. This option is used to handle angle error for the instrument transformers.
3I0
Operate area
RCA = 0
ANSI06000650-2vsd en06000650_ansi.vsd
ANSI06000650 V2 EN
Figure 146:
The function indicates forward/reverse direction to the fault. Reverse direction is defined as 3I0cos ( + 180) the set value.
It is also possible to tilt the characteristic to compensate for current transformer angle error with a setting RCAComp as shown in the figure 147:
Operate area
-3V0=Vref
RCA = 0
3I0 (prim)
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ANSI06000651 V1 EN
Figure 147:
Explanation of RCAComp
The function shall indicate forward/reverse direction to the fault. Reverse direction is defined as 3I0 3V0cos ( + 180) the set value. This variant has the possibility of choice between definite time delay and inverse time delay. The inverse time delay is defined as:
tinv = TDSN (3I 0 3V0 cos (reference)) 3I 0 3V0 cos (measured )
(Equation 67)
EQUATION2032-ANSI V2 EN
ANSI06000652-2-en.vsd
ANSI06000652 V2 EN
Figure 148:
Example of characteristic
For trip, both the residual current 3I0 and the release voltage 3V0, shall be larger than the set levels INDirPU and VNRelPU and the angle shall be in the set sector ROADir and RCADir. Trip from this function can be blocked from the binary input BLKTRDIR.
When the function is activated binary output signals PICKUP and PUDIRIN are activated. If the output signals are active after the set delay tDef the binary output signals TRIP and TRDIRIN are activated. The function indicate forward/reverse direction to the fault. Reverse direction is defined as is within the angle sector: RCADir + 180 ROADir This variant has definite time delay.
Directional functions
For all the directional functions there are directional pickup signals PUFW: fault in the forward direction, and PUREV: Pickup in the reverse direction. Even if the directional function is set to operate for faults in the forward direction a fault in the reverse direction will give the pickup signal PUREV. Also if the directional function is set to operate for faults in the reverse direction a fault in the forward direction will give the pickup signal PUFW.
This function will measure the residual current without checking the phase angle. The function will be used to detect cross-country faults. This function can serve as alternative or back-up to distance protection with phase preference logic. To assure selectivity the distance protection can block the non-directional ground fault current function via the input BLKNDN. The non-directional function is using the calculated residual current, derived as sum of the phase currents. This will give a better ability to detect cross-country faults with high residual current, also when dedicated core balance CT for the sensitive ground fault protection will saturate. This variant has the possibility of choice between definite time delay and inverse time delay. The inverse time delay shall be according to IEC 60255-3. For trip, the residual current 3I0 shall be larger than the set level (INNonDirPU). Trip from this function can be blocked from the binary input BLKNDN. When the function is activated binary output signal PUNDIN is activated. If the output signal is active after the set delay tINNonDir or after the inverse time delay the binary output signals TRIP and TRNDIN are activated.
The directional function shall be released when the residual voltage gets higher than a set level. There shall also be a separate trip, with its own definite time delay, from this level set voltage level.
340 Technical reference manual
For trip, the residual voltage 3V0 shall be larger than the set level (UN_PU). Trip from this function can be blocked from the binary input BLKVN. When the function is activated binary output signal PUVN is activated. If the output signals are active after the set delay tVNNonDir TRIP and TRUN are activated. A simplified logical diagram of the total function is shown in figure 149.
INNonDirPU UN_PU
OpMODE=INcosPhi
Pickup_N INCosPhiPU
OpMODE=INVNCosPhi
AND
OR
AND
t
PUDIRIN
SN TimeChar = InvTime
AND
TRDIRIN
AND
TimeChar = DefTime
AND
AND
OR PUFW
AND
PUREV
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ANSI06000653 V1 EN
Figure 149:
Figure 150:
7.6.4
Table 154:
Name TRIP TRDIRIN TRNDIN TRVN PICKUP PUDIRIN PUNDIN PUVN
7.6.5
Table 155:
Name Operation OpModeSel
Setting parameters
SDEPSDE (67N) Group settings (basic)
Values (Range) Disabled Enabled 3I0Cosfi 3I03V0Cosfi 3I0 and fi Forward Reverse -179 - 180 -10.0 - 10.0 0 - 90 0.25 - 200.00 0.25 - 200.00 0.25 - 200.00 0.000 - 60.000 0.03 - 200.00 0.00 - 2.00 Disabled Enabled 1.00 - 400.00 0.000 - 60.000 Unit Step Default Disabled 3I0Cosfi Description Operation Disable / Enable Selection of operation mode for protection
DirMode RCADir RCAComp ROADir INCosPhiPU SN_PU INDirPU tDef SRef TDSN OpINNonDir INNonDirPU tINNonDir
Forward -90 0.0 90 1.00 10.00 5.00 0.100 10.00 0.10 Disabled 10.00 1.000
Direction of operation forward or reverse Relay characteristic angle RCA, in deg Relay characteristic angle compensation Relay open angle ROA used as release in phase mode, in deg Set level for 3I0cosFi, directional res over current, in %Ib Set level for 3I03V0cosFi, pickup inv time count, in %Sb Set level for directional residual over current prot, in %Ib Definite time delay directional residual overcurrent, in sec Reference value of res power for inverse time count, in %Sb Time multiplier setting for directional residual power mode Operation of non-directional residual overcurrent protection Set level for non directional residual over current, in %Ib Time delay for non-directional residual over current, in sec
Minimum operate time for IEC IDMT curves, in sec IDMT time mult for non-dir res over current protection Operation of non-directional residual overvoltage protection Set level for non-directional residual over voltage, in %Vb Time delay for non-directional residual over voltage, in sec Residual release current for all directional modes, in %Ib Residual release voltage for all direction modes, in %Vb
Table 156:
Name tReset tPCrv tACrv tBCrv tCCrv ResetTypeCrv
Setting PR for customer programmable curve Setting TR for customer programmable curve Setting CR for customer programmable curve
Table 157:
Name IBase VBase SBase
Table 158:
Name RotResV
7.6.6
Technical data
Table 159:
Function Operate level for 3I0cosj directional residual overcurrent
(0.25-200.00)% of SBase
1.0% of Sn at S Sn 1.0% of S at S > Sn At low setting: (0.25-5.00)% of SBase 10% of set value
(0.25-200.00)% of lBase
1.0% of In at In 1.0% of I at I > In At low setting: (0.25-1.00)% of In: 0.05% of In (1.00-5.00)% of In: 0.1% of In
(1.00-400.00)% of lBase
Operate level for nondirectional residual overvoltage Table continues on next page
(1.00-200.00)% of VBase
1.0% of In at I In 1.0% of I at I > In At low setting: (0.25-1.00)% of In: 0.05% of In (1.00-5.00)% of In: 0.1% of In
Residual release voltage for all directional modes Reset ratio Timers Inverse characteristics, see table 588, table 589 and table 590 Relay characteristic angle RCA Relay open angle ROA Operate time, non-directional residual over current Reset time, non-directional residual over current Operate time, pickup function Reset time, pickup function
0.5% of Vn at VVn 0.5% of V at V > Vn 0.5% 10 ms See table 588, table 589 and table 590 2.0 degrees 2.0 degrees -
(-179 to 180) degrees (0-90) degrees 60 ms typically at 0 to 2 x Iset 60 ms typically at 2 to 0 x Iset 150 ms typically at 0 to 2 x Iset 50 ms typically at 2 to 0 x Iset
7.7
SYMBOL-A V1 EN
7.7.1
Introduction
If a power transformer or generator reaches very high temperatures the equipment might be damaged. The insulation within the transformer/generator will have forced ageing. As a consequence of this the risk of internal phase-to-phase or phase-to-ground
faults will increase. High temperature will degrade the quality of the transformer/ generator insulation. The thermal overload protection estimates the internal heat content of the transformer/ generator (temperature) continuously. This estimation is made by using a thermal model of the transformer/generator with two time constants, which is based on current measurement. Two warning pickup levels are available. This enables actions in the power system to be done before dangerous temperatures are reached. If the temperature continues to increase to the trip value, the protection initiates a trip of the protected transformer/ generator.
7.7.2
Principle of operation
The sampled analog phase currents are pre-processed and for each phase current the true RMS value of each phase current is derived. These phase current values are fed to the Thermal overload protection, two time constants (TRPTTR, 49). From the largest of the three phase currents a relative final temperature (heat content) is calculated according to the expression:
Q final
I = I ref
EQUATION1171 V1 EN
(Equation 68)
If this calculated relative temperature is larger than the relative temperature level corresponding to the set operate (trip) current a pickup output signal PICKUP is activated. The actual temperature at the actual execution cycle is calculated as:
If
Q final > Q n
EQUATION1172 V1 EN
(Equation 69)
Dt Qn = Qn -1 + ( Q final - Q n-1 ) 1 - e t
EQUATION1173 V1 EN
(Equation 70)
If
Q final < Qn
EQUATION1174 V1 EN
(Equation 71)
Dt
Qn = Q final - ( Q final - Q n -1 ) e
EQUATION1175 V1 EN
(Equation 72)
where: Qn Qn-1 Qfinal Dt t is the calculated present temperature is the calculated temperature at the previous time step is the calculated final (steady state) temperature with the actual current is the time step between calculation of the actual and final temperature is the set thermal time constant Tau1 or Tau2 for the protected transformer
The calculated transformer relative temperature can be monitored as it is exported from the function as a real figure HEATCONT. When the transformer temperature reaches any of the set alarm levels Alarm1 or Alarm2 the corresponding output signals ALARM1 or ALARM2 are activated. When the temperature of the object reaches the set trip level which corresponds to continuous current equal to ITrip the output signal TRIP is activated. There is also a calculation of the present time to operation with the present current. This calculation is only performed if the final temperature is calculated to be above the operation temperature:
(Equation 73)
The calculated time to trip can be monitored as it is exported from the function as a real figure TTRIP.
348 Technical reference manual
After a trip, caused by the thermal overload protection, there can be a lockout to reconnect the tripped circuit. The output lockout signal LOCKOUT is activated when the temperature of the object is above the set lockout release temperature setting ResLo. The time to lockout release is calculated, That is, a calculation of the cooling time to a set value.
(Equation 74)
In the above equation, the final temperature is calculated according to equation 68. Since the transformer normally is disconnected, the current I is zero and thereby the final is also zero. The calculated component temperature can be monitored as it is exported from the function as a real figure, TRESLO. When the current is so high that it has given a pickup signal PICKUP, the estimated time to trip is continuously calculated and given as analog output TTRIP. If this calculated time get less than the setting time Warning, set in minutes, the output WARNING is activated. In case of trip a pulse with a set duration tPulse is activated.
PICKUP
ALARM1 ALARM2
Current base used TRIP Actual Temp > TripTemp Binary input: Forced cooling On/Off S R Actual Temp < Recl Temp LOCKOUT
Tau used
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ANSI05000833 V1 EN
Figure 151:
7.7.3
Figure 152:
7.7.4
Table 161:
Name TRIP PICKUP ALARM1 ALARM2 LOCKOUT WARNING
Setting parameters
TRPTTR (49) Group settings (basic)
Values (Range) Disabled Enabled 1 - 99999 10.0 - 1000.0 0.01 - 10.00 30.0 - 250.0 30.0 - 250.0 1.0 - 500.0 1.0 - 500.0 30.0 - 250.0 5 - 2000 30.0 - 250.0 5 - 2000 30.0 - 250.0 5 - 2000 30.0 - 250.0 5 - 2000 50.0 - 250.0 50.0 - 99.0 50.0 - 99.0 10.0 - 95.0 Unit A %IB %IB %IB Min Min %IB1 %tC1 %IB1 %tC1 %IB2 %tC2 %IB2 %tC2 %IBx %Itr %Itr %Itr Step 1 1.0 0.01 1.0 1.0 1.0 1.0 1.0 1 1.0 1 1.0 1 1.0 1 1.0 1.0 1.0 1.0 Default Disabled 3000 100.0 1.00 100.0 100.0 60.0 60.0 100.0 100 100.0 100 100.0 100 100.0 100 110.0 80.0 90.0 60.0 Description Disable/Enable Operation Base current in A Reference current in % of IBASE Multiplication Factor for reference current Base current,IBase1 without Cooling inpout in % of IBASE Base Current,IBase2, with Cooling input ON in % of IBASE Time constant without cooling input in min, with IBase1 Time constant with cooling input in min, with IBase2 Current Sett, in % of IBase1 for rescaling TC1 by TC1-IHIGH Multiplier in % to TC1 when current is > IHIGHTC1 Current Set, in % of IBase1 for rescaling TC1 by TC1-ILOW Multiplier in % to TC1 when current is < ILOWTC1 Current Set, in % of IBase2 for rescaling TC2 by TC2-IHIGH Multiplier in % to TC2 when current is >IHIGHTC2 Current Set, in % of IBase2 for rescaling TC2 by TC2-ILOW Multiplier in % to TC2 when current is < ILOWTC2 Steady state operate current level in % of IBasex First alarm level in % of heat content trip value Second alarm level in % of heat content trip value Lockout reset level in % of heat content trip value
7.7.6
Technical data
Table 163:
Function Base current 1 and 2 Operate time:
I 2 - I p2 t = t ln 2 I - Ib 2
EQUATION1356 V1 EN
(Equation 75)
I = Imeasured Alarm pickup 1 and 2 Operate current Reset level temperature (5099)% of heat content trip value (50250)% of IBase (1095)% of heat content trip 2.0% of heat content trip 1.0% of In 2.0% of heat content trip
7.8
3I>BF
SYMBOL-U V1 EN
7.8.1
Introduction
Breaker failure protection (CCRBRF) ensures fast back-up tripping of surrounding breakers in case the own breaker fails to open. CCRBRF (50BF) can be current based, contact based, or an adaptive combination of these two conditions.
Current check with extremely short reset time is used as check criterion to achieve high security against unnecessary operation. Contact check criteria can be used where the fault current through the breaker is small. CCRBRF (50BF) can be single- or three-phase initiated to allow use with single pole tripping applications. For the three-phase version of CCRBRF (50BF) the current criteria can be set to operate only if two out of four for example, two phases or one phase plus the residual current pickups. This gives a higher security to the back-up trip command. CCRBRF (50BF) function can be programmed to give a single- or three-phase re-trip of the own breaker to avoid unnecessary tripping of surrounding breakers at an incorrect initiation due to mistakes during testing.
7.8.2
Principle of operation
Breaker failure protection CCRBRF (50BF) is initiated from protection trip command, either from protection functions within the IED or from external protection devices. The initiate signal can be phase selective or general (for all three phases). Phase selective initiate signals enable single pole re-trip function. This means that a second attempt to open the breaker is done. The re-trip attempt can be made after a set time delay. For transmission lines single pole trip and autoreclosing is often used. The retrip function can be phase selective if it is initiated from phase selective line protection. The re-trip function can be done with or without current check. With the current check the re-trip is only performed if the current through the circuit breaker is larger than the operate current level. The initiate signal can be an internal or external protection trip signal. This signal will initiate the back-up trip timer. If the opening of the breaker is successful this is detected by the function, by detection of either low current through RMS evaluation and a special adapted current algorithm or by open contact indication. The special algorithm enables a very fast detection of successful breaker opening, that is, fast resetting of the current measurement. If the current and/or contact detection has not detected breaker opening before the back-up timer has run its time a back-up trip is initiated. Further the following possibilities are available: The minimum length of the re-trip pulse, the back-up trip pulse and the back-up trip pulse 2 are settable. The re-trip pulse, the back-up trip pulse and the back-up trip pulse 2 will however sustain as long as there is an indication of closed breaker. In the current detection it is possible to use three different options: 1 out of 3 where it is sufficient to detect failure to open (high current) in one pole, 1 out of 4 where it is sufficient to detect failure to open (high current) in one pole or high
residual current and 2 out of 4 where at least two current (phase current and/or residual current) shall be high for breaker failure detection. The current detection level for the residual current can be set different from the setting of phase current detection. It is possible to have different back-up time delays for single-phase faults and for multi-phase faults. The back-up trip can be made without current check. It is possible to have this option activated for small load currents only. It is possible to have instantaneous back-up trip function if a signal is high if the circuit breaker is insufficient to clear faults, for example at low gas pressure.
BFI_3P BFI_A
30 ms
OR
BFP Started A
150 ms
AND S R OR
BLOCK Reset A
SR
AND
Time out A
ANSI09000976-1-en.vsd
ANSI09000976 V1 EN
Figure 153:
Pickup_PH
a b
a>b
OR AND
FunctionMode
Current Contact
OR
Reset A
Time out A
Current and Contact
OR AND
Current High A
CB Closed A
OR
I_A
AND
BFP Started A
a
Pickup_BlkCont 52a_A
a>b
AND
OR
AND
AND
AND
Contact Closed A
ANSI09000977-1-en.vsd
ANSI09000977 V1 EN
Figure 154:
BFP Started A
0-t1 0
TRRET_C TRRET_B
OR
TRRET TRRET_A
RetripMode
200 ms
OR OR
No CBPos Check
OR
AND
52FAIL
AND
ANSI09000978-2-en.vsd
ANSI09000978 V2 EN
Figure 155:
IN Pickup_N BUTripMode
1
a b
a>b
AND
Contact Closed A
OR OR
Current High A
AND
AND
t2
BFP Started A
t2MPh
AND
t
OR
AND
Backup Trip A
OR
AND
OR
200 ms
OR OR
TRBU
200 ms t3
S AND R
SR
OR
TRBU2
ANSI09000979-2-en.vsd
ANSI09000979 V2 EN
Figure 156:
Internal logical signals PU_A, PU_B, PU_C have logical value 1 when current in respective phase has magnitude larger than setting parameter Pickup_PH.
7.8.3
ANSI06000188-2-en.vsd
ANSI06000188 V2 EN
Figure 157:
7.8.4
Table 165:
Name TRBU TRBU2 TRRET TRRET_A TRRET_B TRRET_C CBALARM
Setting parameters
CCRBRF (50BF) Group settings (basic)
Values (Range) Disabled Enabled 1 - 99999 Current Contact Current&Contact 2 out of 4 1 out of 3 1 out of 4 Retrip Off CB Pos Check No CBPos Check 5 - 200 2 - 200 0.000 - 60.000 0.000 - 60.000 0.000 - 60.000 0.000 - 60.000 Unit A Step 1 Default Disabled 3000 Current Description Disable/Enable Operation Base current Detection principle for back-up trip
BuTripMode
1 out of 3
RetripMode
Retrip Off
%IB %IB s s s s
Phase current pickup in % of IBase Operate residual current level in % of IBase Time delay of re-trip Time delay of back-up trip Time delay of back-up trip at multi-phase pickup Trip pulse duration
Table 167:
Name Pickup_BlkCont t3 tCBAlarm
7.8.6
Technical data
Table 168:
Function Operate phase current Reset ratio, phase current Operate residual current Table continues on next page
7.9
PD
SYMBOL-S V1 EN
7.9.1
Introduction
An open phase can cause negative and zero sequence currents which cause thermal stress on rotating machines and can cause unwanted operation of zero sequence or negative sequence current functions. Normally the own breaker is tripped to correct such a situation. If the situation warrants the surrounding breakers should be tripped to clear the unsymmetrical load situation. The Polediscrepancy protection function CCRPLD (52PD) operates based on information from auxiliary contacts of the circuit breaker for the three phases with additional criteria from unsymmetrical phase currents when required.
7.9.2
Principle of operation
The detection of pole discrepancy can be made in two different ways. If the contact based function is used an external logic can be made by connecting the auxiliary contacts of the circuit breaker so that a pole discrepancy is indicated, see figure 158.
359
C.B.
Figure 158:
This binary signal is connected to a binary input of the IED. The appearance of this signal will start a timer that will give a trip signal after the set time delay. There is also a possibility to connect all phase selective auxiliary contacts (phase contact open and phase contact closed) to binary inputs of the IED, see figure 159.
C.B.
poleOneClosed from C.B. poleTwoClosed from C.B. poleThreeClosed from C.B. poleOneOpened from C.B. poleTwoOpened from C.B. poleThreeOpened from C.B.
en05000288_ansi.vsd
ANSI05000288 V1 EN
Figure 159:
In this case the logic is realized within the function. If the inputs are indicating pole discrepancy the trip timer is started. This timer will give a trip signal after the set delay. Pole discrepancy can also be detected by means of phase selective current measurement. The sampled analog phase currents are pre-processed in a discrete Fourier filter (DFT) block. From the fundamental frequency components of each phase
360 Technical reference manual
current the RMS value of each phase current is derived. The smallest and the largest phase current are derived. If the smallest phase current is lower than the setting CurrUnsymPU times the largest phase current the settable trip timer (tTrip) is started. The tTrip timer gives a trip signal after the set delay. The TRIP signal is a pulse 150 ms long. The current based pole discrepancy function can be set to be active either continuously or only directly in connection to breaker open or close command. The function also has a binary input that can be configured from the autoreclosing function, so that the pole discrepancy function can be blocked during sequences with a single pole open if single pole autoreclosing is used.
BLOCK BLKDBYAR OR
PolPosAuxCont 52b_A 52a_A 52b_B 52a_B 52b_C 52a_C AND Pole Disc repancy detection 150 ms AND OR PD signal from CB EXTPDIND CLOSECMD OPENCMD OR AND Unsymmetry current detection en 05000747 _ansi.vsd
ANSI05000747 V1 EN
0- t 0
TRIP
AND
t+ 200 ms
Figure 160:
Simplified block diagram of pole discrepancy function CCRPLD (52PD) - contact and current based
CCRPLD (52PD) is disabled if: The IED is in TEST mode and CCRPLD (52PD) has been blocked from the local HMI The input signal BLOCK is high The input signal BLKDBYAR is high
The BLOCK signal is a general purpose blocking signal of the pole discrepancy protection. It can be connected to a binary input in the IED in order to receive a block command from external devices or can be software connected to other internal functions in the IED itself in order to receive a block command from internal functions. Through OR gate it can be connected to both binary inputs and internal function outputs.
The BLKDBYAR signal blocks the pole discrepancy operation when a single phase autoreclosing cycle is in progress. It can be connected to the output signal 1PT1 on SMBRREC (79) function block. If the autoreclosing function is an external device, then BLKDBYAR has to be connected to a binary input in the IED and this binary input is connected to a signalization 1phase autoreclosing in progress from the external autoreclosing device. If the pole discrepancy protection is enabled, then two different criteria can generate a trip signal TRIP: Pole discrepancy signaling from the circuit breaker. Unsymmetrical current detection.
7.9.2.1
7.9.2.2
If these conditions are true, an unsymmetrical condition is detected and the internal signal INPS is turned high. This detection is enabled to generate a trip after a set time delay tTrip if the detection occurs in the next 200 ms after the circuit breaker has received a command to open trip or close and if the unbalance persists. The 200 ms limitation is for avoiding unwanted operation during unsymmetrical load conditions. The pole discrepancy protection is informed that a trip or close command has been given to the circuit breaker through the inputs CLOSECMD (for closing command information) and OPENCMD (for opening command information). These inputs can be connected to terminal binary inputs if the information are generated from the field (that is from auxiliary contacts of the close and open push buttons) or may be software connected to the outputs of other integrated functions (that is close command from a control function or a general trip from integrated protections).
7.9.3
Figure 161:
7.9.4
Table 170:
Name TRIP PICKUP
Setting parameters
CCRPLD (52PD) Group settings (basic)
Values (Range) Disabled Enabled 1 - 99999 0.000 - 60.000 Disabled PD signal from CB Pole pos aux cont. Disabled CB oper monitor Continuous monitor 0 - 100 0 - 100 Unit s Step 1 0.001 Default Disabled 3000 0.300 Disabled Description Disable/Enable Operation Base current Time delay between trip condition and trip signal Contact function selection
CurrentSel
Disabled
CurrUnsymPU CurrRelPU
% %IB
1 1
80 10
Unsym magn of lowest phase current compared to the highest. Current magnitude for release of the function in % of IBase
7.9.6
Technical data
Table 172:
Function Operate current Time delay
7.10
P<
SYMBOL-LL V1 EN
7.10.1
IEC06000315-2-en.vsd
IEC06000315 V2 EN
Figure 162:
A simplified scheme showing the principle of the power protection function is shown in figure 163. The function has two stages with individual settings.
P Derivation of S( composant) in Char angle S( angle) S( angle) < Power1 t 0 TRIP1 PICKUP1
t 0
TRIP2 PICKUP2
P = POWRE Q = POWIM
ANSI06000438-2-en.vsd
ANSI06000438 V2 EN
Figure 163:
The function will use voltage and current phasors calculated in the pre-processing blocks. The apparent complex power is calculated according to chosen formula as shown in table 173.
Table 173:
Set value: Mode A, B, C
S = V A I A* + VB I B* + VC I C *
EQUATION2055-ANSI V1 EN
(Equation 76)
Arone
S = V AB I A* - VBC IC *
EQUATION2056-ANSI V1 EN
(Equation 77)
PosSeq
S = 3 VPosSeq I PosSeq*
EQUATION2057-ANSI V1 EN
(Equation 78)
AB
S = VAB ( I A* - I B* )
EQUATION2058-ANSI V1 EN
(Equation 79)
S = VBC ( I B* - IC * )
EQUATION2059-ANSI V1 EN
(Equation 80)
CA
S = VCA ( I C * - I A* )
EQUATION2060-ANSI V1 EN
(Equation 81)
S = 3 VA I A*
EQUATION2061-ANSI V1 EN
(Equation 82)
S = 3 VB I B*
EQUATION2062-ANSI V1 EN
(Equation 83)
S = 3 VC I C *
EQUATION2063-ANSI V1 EN
(Equation 84)
The active and reactive power is available from the function and can be used for monitoring and fault recording. The component of the complex power S = P + jQ in the direction Angle1(2) is calculated. If this angle is 0 the active power component P is calculated. If this angle is 90 the reactive power component Q is calculated. The calculated power component is compared to the power pick up setting Power1(2). For directional underpower protection, a pickup signal PICKUP1(2) is activated if the calculated power component is smaller than the pick up value. For directional overpower protection, a pickup signal PICKUP1(2) is activated if the calculated power component is larger than the pick up value. After a set time delay TripDelay1(2) a trip TRIP1(2) signal is activated if the pickup signal is still active. At activation of any of the two stages a common signal PICKUP will be activated. At trip from any of the two stages also a common signal TRIP will be activated. To avoid instability there is a settable hysteresis in the power function. The absolute hysteresis of the stage1(2) is Hysteresis1(2) = abs (Power1(2) + drop-power1(2)). For generator low forward power protection the power setting is very low, normally down to 0.02 p.u. of rated generator power. The hysteresis should therefore be set to a smaller value. The drop-power value of stage1 can be calculated with the Power1(2), Hysteresis1(2): drop-power1(2) = Power1(2) + Hysteresis1(2) For small power1 values the hysteresis1 may not be too big, because the droppower1(2) would be too small. In such cases, the hysteresis1 greater than (0.5 Power1(2)) is corrected to the minimal value.
If the measured power drops under the drop-power1(2) value, the function will reset after a set time DropDelay1(2). The reset means that the pickup signal will drop out and that the timer of the stage will reset.
7.10.2.1
S = TD SOld + (1 TD ) SCalculated
EQUATION1959-ANSI V1 EN
(Equation 85)
Where S Sold is a new measured value to be used for the protection function is the measured value given from the function in previous execution cycle
SCalculated is the new calculated value in the present execution cycle TD is settable parameter by the end user which influence the filter properties
Default value for parameter TD is 0.00. With this value the new calculated value is immediately given out without any filtering (that is without any additional delay). When TD is set to value bigger than 0, the filtering is enabled. A typical value for TD=0.92 in case of slow operating functions.
7.10.2.2
Magnitude compensation
Angle compensation
ANSI05000652_3_en.vsd
ANSI05000652 V3 EN
Figure 164:
Calibration curves
The first current and voltage phase in the group signals will be used as reference and the amplitude and angle compensation will be used for related input signals. Analog outputs (Monitored data) from the function can be used for service values or in the disturbance report. The active power is provided as MW value: P, or in percent of base power: PPERCENT. The reactive power is provided as Mvar value: Q, or in percent of base power: QPERCENT.
Figure 165:
7.10.4
Table 175:
Name TRIP TRIP1 TRIP2 PICKUP PICKUP1 PICKUP2 P PPERCENT Q QPERCENT
7.10.5
Table 176:
Name Operation OpMode1 Power1 Angle1 TripDelay1 DropDelay1 OpMode2 Power2 Angle2 TripDelay2 DropDelay2
Table 177:
Name TD Hysteresis1 Hysteresis2 IMagComp5 IMagComp30 IMagComp100 VMagComp5 VMagComp30 VMagComp100 IAngComp5 IAngComp30 IAngComp100
Table 178:
Name IBase VBase Mode
7.10.6
Technical data
Table 179:
Function Power level
*) To achieve this accuracy for reverse power protection it is also recommended to apply setting AngleN=-179.3 degrees instead of standard 180 degrees. This setting will help to minimize the overall measurement error ensuring the above stated accuracy for this application.
7.11
P>
DOCUMENT172362-IMG158942 V1 EN
7.11.1
IEC06000315-2-en.vsd
IEC06000315 V2 EN
Figure 166:
A simplified scheme showing the principle of the power protection function is shown in figure 167. The function has two stages with individual settings.
P Derivation of S(composant) in Char angle S(angle) S(angle) > Power1 t TRIP1 PICKUP1
TRIP2 PICKUP2
P = POWRE Q = POWIM
ANSI06000567-2-en.vsd
ANSI06000567 V2 EN
Figure 167:
The function will use voltage and current phasors calculated in the pre-processing blocks. The apparent complex power is calculated according to chosen formula as shown in table 180.
Table 180:
Set value: Mode A,B,C
S = V A I A + V B I B + V C IC
EQUATION2038 V1 EN
(Equation 86)
* *
Arone
S = V AB I A - V BC I C
EQUATION2039 V1 EN
(Equation 87)
*
PosSeq
S = 3 V PosSeq I PosSeq
EQUATION2040 V1 EN
(Equation 88)
*
A,B
S = V AB (I A - I B )
EQUATION2041 V1 EN
(Equation 89)
S = V BC (I B - I C )
EQUATION2042 V1 EN
(Equation 90)
*
C,A
S = V CA (I C - I A )
EQUATION2043 V1 EN
(Equation 91)
*
S = 3 V A IA
EQUATION2044 V1 EN
(Equation 92)
*
S = 3 V B IB
EQUATION2045 V1 EN
(Equation 93)
*
S = 3 V C IC
EQUATION2046 V1 EN
(Equation 94)
The active and reactive power is available from the function and can be used for monitoring and fault recording. The component of the complex power S = P + jQ in the direction Angle1(2) is calculated. If this angle is 0 the active power component P is calculated. If this angle is 90 the reactive power component Q is calculated. The calculated power component is compared to the power pick up setting Power1(2). A pickup signal PICKUP1(2) is activated if the calculated power component is larger than the pick up value. After a set time delay TripDelay1(2) a trip TRIP1(2) signal is activated if the pickup signal is still active. At activation of any of the two stages a common signal PICKUP will be activated. At trip from any of the two stages also a common signal TRIP will be activated. To avoid instability there is a settable hysteresis in the power function. The absolute hysteresis of the stage1(2) is Hysteresis1(2) = abs (Power1(2) drop-power1(2)). For generator reverse power protection the power setting is very low, normally down to 0.02 p.u. of rated generator power. The hysteresis should therefore be set to a smaller value. The drop-power value of stage1 can be calculated with the Power1(2), Hysteresis1(2): drop-power1(2) = Power1(2) Hysteresis1(2) For small power1 values the hysteresis1 may not be too big, because the droppower1(2) would be too small. In such cases, the hysteresis1 greater than (0.5 Power1(2)) is corrected to the minimal value.
If the measured power drops under the drop-power1(2) value the function will reset after a set time DropDelay1(2). The reset means that the pickup signal will drop out ant that the timer of the stage will reset.
7.11.2.1
(Equation 95)
Where S Sold is a new measured value to be used for the protection function is the measured value given from the function in previous execution cycle
SCalculated is the new calculated value in the present execution cycle k is settable parameter by the end user which influence the filter properties
Default value for parameter k is 0.00. With this value the new calculated value is immediately given out without any filtering (that is, without any additional delay). When k is set to value bigger than 0, the filtering is enabled. A typical value for k = 0.92 in case of slow operating functions.
7.11.2.2
Magnitude compensation
Angle compensation
ANSI05000652_3_en.vsd
ANSI05000652 V3 EN
Figure 168:
Calibration curves
The first current and voltage phase in the group signals will be used as reference and the amplitude and angle compensation will be used for related input signals. Analog outputs from the function can be used for service values or in the disturbance report. The active power is provided as MW value: P, or in percent of base power: PPERCENT. The reactive power is provided as Mvar value: Q, or in percent of base power: QPERCENT.
Figure 169:
7.11.4
Table 182:
Name TRIP TRIP1 TRIP2 PICKUP PICKUP1 PICKUP2 P PPERCENT Q QPERCENT
7.11.5
Table 183:
Name Operation OpMode1 Power1 Angle1 TripDelay1 DropDelay1 OpMode2 Power2 Angle2 TripDelay2 DropDelay2
Table 184:
Name k Hysteresis1 Hysteresis2 IMagComp5 IMagComp30 IMagComp100 VMagComp5 VMagComp30 VMagComp100 IAngComp5 IAngComp30 IAngComp100
Table 185:
Name IBase VBase Mode
7.11.6
Technical data
Table 186:
Function Power level
*) To achieve this accuracy for reverse power protection it is also recommended to apply setting AngleN=-179.3 degrees instead of standard 180 degrees. This setting will help to minimize the overall measurement error ensuring the above stated accuracy for this application.
7.12
7.12.1
NS2PTOC (46I2) can also be used as a backup protection, that is, to protect the generator in case line protections or circuit breakers fail to clear unbalanced system faults. To provide an effective protection for the generator for external unbalanced conditions, NS2PTOC (46I2) is able to directly measure the negative sequence current. NS2PTOC (46I2) also has a time delay characteristic which matches the heating characteristic of
2 the generator I 2 t = K as defined in standard IEEE C50.13.
where: I2 t K is negative sequence current expressed in per unit of the rated generator current is operating time in seconds is a constant which depends of the generators size and design
NS2PTOC (46I2) has a wide range of K settings and the sensitivity and capability of detecting and tripping for negative sequence currents down to the continuous capability of a generator. A separate output is available as an alarm feature to warn the operator of a potentially dangerous situation.
7.12.2
Principle of operation
The negative sequence time overcurrent protection for machines (NS2PTOC, 46I2) function directly measures the amplitude of the negative phase sequence component of the measured current. NS2PTOC (46I2) sets the PICKUP, PU_ST1 or PU_ST2 outputs active and starts to count trip time only when the measured negative sequence current value rises above the set value of parameters I2-1> or I2-2> respectively.
To avoid oscillation in the output signals, a certain hysteresis has been included. For both steps, the reset ratio is 0.97. Step 1 of NS2PTOC (46I2) can operate in the Definite Time (DT) or Inverse Time (IDMT) mode depending on the selected value for the CurveType1 parameter. If CurveType1= Definite, NS2PTOC (46I2) operates with a Definite Time Delay characteristic and if CurveType1 = Inverse, NS2PTOC (46I2) operates with an Inverse Time Delay characteristic. Step 2 can only operate in the Definite Time (DT) mode. The characteristic defines the time period between the moment when measured negative sequence current exceeds the set pickup levels in parameter I2-1> or I2-2> until the trip signal is initiated. Definite time delay is not dependent on the magnitude of measured negative sequence current. Once the measured negative sequence current exceeds the set level, the settable definite timer t1 or t2 respectively, starts to count and the corresponding trip signal gets activated after the pre-set definite time delay has elapsed. Reset time in definite time mode is determined by the setting parameters tResetDef1 or tResetDef2 respectively. If NS2PTOC (46I2) has already picked up but not tripped and measured negative sequence current goes below the pickup value, the pickup outputs remains active for the time defined by the resetting parameters. A BLOCK input signal resets NS2PTOC (46I2) momentarily. When the parameter CurveType1 is set to Inverse, an inverse curve is selected according to selected value for parameter K1. The minimum trip time setting of parameter t1Min and reset time parameter ResetMultip1 also influence step operation. However, to match the heating characteristics of the generator, the reset time is depending on the setting of parameter K1, which must be set according to the generators negative sequence current capacity.
K = I 2 2t
EQUATION2112 V1 EN
Where: I2 t K is negative sequence current expressed in per unit of the rated generator current is operating time in seconds is a constant [s], which depends on generator size and design
Operate time
t1Min (Default= 5 s)
K1
Current I2-1>
IEC09000691-2-en.vsd
IEC09000691 V2 EN
Figure 170:
For a detailed description of inverse time characteristic, see chapter "Inverse characteristics". The reset time is exponential and is given by the following expression:
(Equation 96)
Where INS IPickup is the measured negative sequence current is the desired pickup level in pu of rated generator current is multiplier of the generator capability constant K equal to setting K1 and thus defines reset time of inverse time characteristic
ResetMultip
The trip pickup levels Current I2-1> and I2-2> of NS2PTOC (46I2) are freely settable over a range of 3 to 500 % of rated generator current IBase. The wide range of pickup setting is required in order to be able to protect generators of different types and sizes. After pickup, a certain hysteresis is used before resetting pickup levels. For both steps the reset ratio is 0.97.
7.12.2.2
Alarm function
The alarm function is operated by PICKUP signal and used to warn the operator for an abnormal situation, for example, when generator continuous negative sequence current capability is exceeded, thereby allowing corrective action to be taken before removing the generator from service. A settable time delay tAlarm is provided for the alarm function to avoid false alarms during short-time unbalanced conditions.
7.12.2.3
Logic diagram
DT time selected Negative sequence current I2-1>
a b a>b
0-t1 0
OR
TRST1
AND
Inverse
PU_ST1
ANSI08000466-3-en.vsd
ANSI08000466 V3 EN
Figure 171:
Simplified logic diagram for step 1 of Negative sequence time overcurrent protection for machines (NS2PTOC, 46I2)
Step 2 for Negative sequence time overcurrent protection for machines (NS2PTOC, 46I2) is similar to step 1 above except that it lacks the inverse characteristic.
PU_ST1 PU_ST2
OR 0-tAlarm 0 OR
PICKUP
ALARM TRIP
TRST1 TRST2
ANSI09000690-3-en.vsd
ANSI09000690 V3 EN
Figure 172:
Simplified logic diagram for the PICKUP, ALARM and TRIP signals for NS2PTOC (46I2)
7.12.3
Function block
NS2PTOC (46I2) I3P* BLOCK BLK1 BLK2 TRIP TRST1 TRST2 PICKUP PU_ST1 PU_ST2 ALARM NSCURR ANSI08000359-2-en.vsd
ANSI08000359 V2 EN
Figure 173:
7.12.4
Table 188:
Name TRIP TRST1 TRST2 PICKUP PU_ST1 PU_ST2 ALARM NSCURR
7.12.5
Table 189:
Name Operation IBase tAlarm OpStep1 I2-1> CurveType1 t1 tResetDef1 K1 t1Min t1Max ResetMultip1 OpStep2 I2-2>
Setting parameters
NS2PTOC (46I2) Group settings (basic)
Values (Range) Disabled Enabled 1 - 99999 0.00 - 6000.00 Disabled Enabled 3 - 500 Definite Inverse 0.00 - 6000.00 0.000 - 60.000 1.0 - 99.0 0.000 - 60.000 0.00 - 6000.00 0.01 - 20.00 Disabled Enabled 3 - 500 Unit A s %IB s s s s s %IB Step 1 0.01 1 0.01 0.001 0.1 0.001 0.01 0.01 1 Default Disabled 3000 3.00 Enabled 10 Definite 10.00 0.000 10.0 5.000 1000.00 1.00 Enabled 10 Description Disable/Enable Operation Rated generator current in primary amps Time delay for alarm ( operated by pick up signal) in seconds Enable execution of step 1 Step 1 Neg. Seq. Current pickup level, in % of IBase Selection of definite or inverse timecharacteri. for step 1 Definite time delay for trip of step 1, in sec Time delay for reset of definite timer of step 1, in sec Neg. seq. capability value of generator for step 1, in sec Minimum trip time for inverse delay of step 1, in sec Maximum trip delay for step 1, in sec Reset multiplier for K1, defines reset time of inverse curve Enable execution of step 2 Step 2 Neg. Seq. Current pickup level, in % of IBase
7.12.6
Technical data
Table 190:
Function Operate value, step 1 and 2, negative sequence overcurrent Reset ratio, step 1 and 2 Operate time, pickup Reset time, pickup Time characteristics Inverse time characteristic step 1, I 22t = K Reset time, inverse characteristic step 1, I 22t = K Maximum trip delay, step 1 IDMT Minimum trip delay, step 1 IDMT Timers
>95% 20 ms typically at 0 to 2 x Iset 15 ms typically at 0 to 10 x Iset 30 ms typically at 2 to 0 x Iset Definite or Inverse K=1.0-99.0
K=0.01-20.00
10% + 40 ms
7.13
7.13.1
Introduction
Inadvertent or accidental energizing of off-line generators has occurred often enough due to operating errors, breaker head flashovers, control circuit malfunctions, or a combination of these causes. Inadvertently energized generator operates as induction motor drawing a large current from the system. The voltage supervised overcurrent protection is used to protect the inadvertently energized generator. Accidental energizing protection for synchronous generator (AEGGAPC, 50AE) takes the maximum phase current input from the generator terminal side or from generator neutral side and maximum phase to phase voltage inputs from the terminal side. AEGGAPC (50AE) is enabled when the terminal voltage drops below the specified voltage level for the preset time.
7.13.2
Principle of operation
Accidental energizing protection for synchronous generator AEGGAPC (50AE) function is connected to three phase current input either from the generator terminal side or from generator neutral point side and three phase voltage from the generator terminals. The maximum of the three phase-to-phase voltages and maximum of the three phase currents are measured. When the maximum phase-to-phase voltage is less than the 27_pick_up for the period tArm, it is ensured that the generator is off-line. The Enabled signal will initiate the overcurrent function. If the calculated maximum current of the three phases is larger than IPickup for the period tOC then the TRIP signal becomes activated. Also PICKUP signal becomes activated when overcurrent is detected. When the maximum phase-to-phase voltage is larger than 59_Drop_out for the period tDisarm, it is ensured generator is on line. During this state, undervoltage operation is disarmed, blocking the overcurrent operation and thus the function becomes inoperative. BLOCK input can be used to block AEGGAPC (50AE). In addition, the BLKTR input that blocks the TRIP signal is also present. The input BLKTR can be used if AEGGAPC (50AE) is to be used only for monitoring purposes.
RI
Enabled
AND
S R
OUT NOUT
a a>b 59_Drop_out b
0-tDisarm 0 ON - Delay
OR
ANSI09000784-2-en.vsd
ANSI09000784 V2 EN
Figure 174:
7.13.3
Function block
AEGGAPC (50AE) I3P* TRIP V3P* RI BLOCK ARMED BLKTR ANSI09000783-1-en.vsd
ANSI09000783 V1 EN
Figure 175:
7.13.4
Table 192:
Name TRIP RI ARMED
7.13.5
Table 193:
Name Operation IBase VBase IPickup tOC 27_pick_up tArm 59_Drop_out tDisarm
Setting parameters
AEGGAPC (50AE) Group settings (basic)
Values (Range) Disabled Enabled 1 - 99999 0.05 - 2000.00 2 - 900 0.000 - 60.000 2 - 200 0.000 - 60.000 2 - 200 0.000 - 60.000 Unit A kV %IB s %VB s %VB s Step 1 0.05 1 0.001 1 0.001 1 0.001 Default Disabled 3000 20.00 120 0.030 50 5.000 80 0.500 Description Disable/Enable Operation Base current (primary phase current in A) Base voltage (primary phase-to-phase voltage in kV) Phase current pickup in % of IBase Trip time daly for overcurrent level Undervoltage level to arm protection in % of Vbase Time delay to arm protection with undervoltage pickup Over voltage level to disarm protection in % of Vbase Time delay to disarm protection when voltage greater than drop out level
7.13.6
Technical data
Table 194:
Function Operate value, overcurrent Reset ratio, overcurrent Transient overreach, overcurrent function Critical impulse time, overcurrent Impulse margin time, overcurrent Table continues on next page
392
Section 8
Voltage protection
8.1
3U<
SYMBOL-R-2U-GREATER-THAN V2 EN
8.1.1
Introduction
Undervoltages can occur in the power system during faults or abnormal conditions. Two step undervoltage protection (UV2PTUV, 27) function can be used to open circuit breakers to prepare for system restoration at power outages or as long-time delayed backup to primary protection. UV2PTUV (27) has two voltage steps, each with inverse or definite time delay.
8.1.2
Principle of operation
Two-step undervoltage protection (UV2PTUV ,27) is used to detect low power system voltage. UV2PTUV (27) has two voltage measuring steps with separate time delays. If one, two or three phase voltages decrease below the set value, a corresponding PICKUP signal is generated. UV2PTUV (27) can be set to PICKUP/TRIP based on 1 out of 3, 2 out of 3 or 3 out of 3 of the measured voltages, being below the set point. If the voltage remains below the set value for a time period corresponding to the chosen time delay, the corresponding trip signal is issued. To avoid an unwanted trip due to disconnection of the related high voltage equipment, a voltage controlled blocking of the function is available, that is, if the voltage is lower than the set blocking level the
393
function is blocked and no PICKUP or TRIP signal is generated.The time delay characteristic is individually chosen for each step and can be either definite time delay or inverse time delay. UV2PTUV (27) can be set to measure phase-to-ground fundamental value, phase-tophase fundamental value, phase-to-ground true RMS value or phase-to-phase true RMS value. The choice of the measuring is done by the parameter ConnType. The voltage related settings are made in percent of base voltage which is set in kV phase-tophase voltage. This means operation for phase-to-ground voltage under:
Vpickup < (%) VBase(kV ) 3
EQUATION1606 V1 EN
(Equation 97)
(Equation 98)
When phase-to-ground voltage measurement is selected the function automatically introduces division of the base value by the square root of three.
8.1.2.1
Measurement principle
Depending on the set ConnType value, UV2PTUV (27) measures phase-to-ground or phase-to-phase voltages and compare against set values, Pickup1 and Pickup2. The parameters OpMode1 and OpMode2 influence the requirements to activate the PICKUP outputs. Either 1 out of 3, 2 out of 3, or 3 out of 3 measured voltages have to be lower than the corresponding set point to issue the corresponding PICKUP signal. To avoid oscillations of the output PICKUP signal, a hysteresis has been included.
8.1.2.2
Time delay
The time delay for the two steps can be either definite time delay (DT) or inverse time undervoltage (TUV). For the inverse time delay three different modes are available: inverse curve A inverse curve B customer programmable inverse curve
(Equation 99)
where: Vpickup < V Set value for step 1 and step 2 Measured voltage
2.0
EQUATION1608 V1 EN
(Equation 100)
(Equation 101)
When the denominator in the expression is equal to zero the time delay will be infinity. There will be an undesired discontinuity. Therefore a tuning parameter CrvSatn is set to compensate for this phenomenon. In the voltage interval Vpickup< down to Vpickup< (1.0 CrvSatn/100) the used voltage will be: Vpickup< (1.0 CrvSatn/ 100). If the programmable curve is used this parameter must be calculated so that:
EQUATION1435 V1 EN
The lowest voltage is always used for the inverse time delay integration. The details of the different inverse time characteristics are shown in section 22.3 "Inverse characteristics".
Figure 176: Voltage used for the inverse time characteristic integration
Voltage
IDMT Voltage
Time
ANSI12000186-1-en.vsd
Trip signal issuing requires that the undervoltage condition continues for at least the user set time delay. This time delay is set by the parameter t1 and t2 for definite time mode (DT) and by some special voltage level dependent time curves for the inverse time mode (TUV). If the pickup condition, with respect to the measured voltage ceases during the delay time, and is not fulfilled again within a user defined reset time (tReset1 and tReset2 for the definite time and tIReset1 and tIReset2pickup for the inverse time) the corresponding pickup output is reset. Here it should be noted that after leaving the hysteresis area, the pickup condition must be fulfilled again and it is not sufficient for the signal to only return back to the hysteresis area. Note that for the undervoltage function the TUV reset time is constant and does not depend on the voltage fluctuations during the drop-off period. However, there are three ways to reset the timer, either the timer is reset instantaneously, or the timer value is frozen during the reset time, or the timer value is linearly decreased during the reset time. See figure 177 and figure 178.
TRIP
PICKUP1
Time Integrator t
Frozen Timer
Instantaneous
Linearly decreased
Time
ANSI05000010-3-en.vsd
ANSI05000010 V3 EN
Figure 177:
Voltage profile not causing a reset of the pickup signal for step 1, and inverse time delay at different reset types
Voltage PICKUP
PICKUP 1
Time PICKUP t
TRIP
Time Integrator t
Frozen Timer
Time Instantaneous
ANSI05000011 V2 EN
Linearly decreased
ANSI05000011-2-en.vsd
Figure 178:
Voltage profile causing a reset of the pickup signal for step 1, and inverse time delay at different reset types
When definite time delay is selected the function will operate as shown in figure 179. Detailed information about individual stage reset/operation behavior is shown in figure 180 and figure 181 respectively. Note that by setting tResetn = 0.0s, instantaneous reset of the definite time delayed stage is ensured.
PU_ST1
V Vpickup<
a a<b b
ANSI09000785-2-en.vsd
ANSI09000785 V2 EN
Figure 179:
Pickup1
PICKUP
TRIP tReset1
t1
ANSI10000039-2-en.vsd
ANSI10000039 V2 EN
Figure 180:
Pickup1
PICKUP
TRIP
tReset1
t1
ANSI10000040-2-en.vsd
ANSI10000040 V2 EN
Figure 181:
8.1.2.3
Blocking
It is possible to block Two step undervoltage protection UV2PTUV (27) partially or completely, by binary input signals or by parameter settings, where:
BLOCK: BLKTR1: BLK1: BLKTR2: BLK2: blocks all outputs blocks all trip outputs of step 1 blocks all pickup and trip outputs related to step 1 blocks all trip outputs of step 2 blocks all pickup and trip outputs related to step 2
If the measured voltage level decreases below the setting of IntBlkStVal1, either the trip output of step 1, or both the trip and the PICKUP outputs of step 1, are blocked. The characteristic of the blocking is set by the IntBlkSel1 parameter. This internal blocking can also be set to Disabled resulting in no voltage based blocking. Corresponding settings and functionality are valid also for step 2. In case of disconnection of the high voltage component the measured voltage will get very low. The event will PICKUP both the under voltage function and the blocking function, as seen in figure 182. The delay of the blocking function must be set less than the time delay of under voltage function.
Disconnection
tBlkUV1 < t1,t1Min IntBlkStVal1 IntBlkStVal2 Time Block step 1 Block step 2
en05000466_ansi.vsd
ANSI05000466 V1 EN
Figure 182:
Blocking function
8.1.2.4
Design
The voltage measuring elements continuously measure the three phase-to-neutral voltages or the three phase-to-phase voltages. Recursive fourier filters or true RMS filters of input voltage signals are used. The voltages are individually compared to the set value, and the lowest voltage is used for the inverse time characteristic integration. A special logic is included to achieve the 1 out of 3, 2 out of 3 and 3 out of 3 criteria to fulfill the PICKUP condition. The design of Two step undervoltage protection UV2PTUV (27) is schematically shown in Figure 183.
VL1
Comparator
VL1 < V1<
VL2
Comparator
VL2 < V1<
ST1L1
Phase 1
ST1L2
Phase 2 Phase 3
VL3
Comparator
VL3 < V1<
OR
TRIP
OR Comparator
VL1 < V2<
Comparator
VL2 < V2<
ST2L1
Phase 1
ST2L2
Phase 2
Comparator
VL3 < V2<
OR
MinVoltSelector
TRIP
OR
OR
TRIP
ANSI05000012-2-en.vsd
ANSI05000012 V2 EN
Figure 183:
8.1.3
Figure 184:
8.1.4
Table 196:
Name TRIP TRST1 TRST1_A TRST1_B TRST1_C TRST2 TRST2_A
Common pickup signal from step1 Pickup signal from step1 phase A Pickup signal from step1 phase B Pickup signal from step1 phase C Common pickup signal from step2 Pickup signal from step2 phase A Pickup signal from step2 phase B Pickup signal from step2 phase C
8.1.5
Table 197:
Name Operation VBase OperationStep1 Characterist1
Setting parameters
UV2PTUV (27) Group settings (basic)
Values (Range) Disabled Enabled 0.05 - 2000.00 Disabled Enabled Definite time Inverse curve A Inverse curve B Prog. inv. curve 1 out of 3 2 out of 3 3 out of 3 1 - 100 0.00 - 6000.00 0.000 - 60.000 0.05 - 1.10 Disabled Block of trip Block all 1 - 100 Unit kV Step 0.05 Default Disabled 400.00 Enabled Definite time Description Disable/Enable Operation Base voltage Enable execution of step 1 Selection of time delay curve type for step 1
OpMode1
1 out of 3
Number of phases required for op (1 of 3, 2 of 3, 3 of 3) from step 1 Voltage pickup value (Definite-Time & InverseTime curve) in % of VBase, step 1 Definitive time delay of step 1 Minimum operate time for inverse curves for step 1 Time multiplier for the inverse time delay for step 1 Internal (low level) blocking mode, step 1
%VB s s -
IntBlkStVal1
%VB
20
OpMode2
1 out of 3
Number of phases required for op (1 of 3, 2 of 3, 3 of 3) from step 2 Voltage pickup value (Definite-Time & InverseTime curve) in % of VBase, step 2 Definitive time delay of step 2 Minimum operate time for inverse curves for step 2 Time multiplier for the inverse time delay for step 2 Internal (low level) blocking mode, step 2
%VB s s -
%VB s %VB
1 0.001 0.1
20 0.000 0.5
Voltage setting for internal blocking in % of VBase, step 2 Time delay of internal (low level) blocking for step 2 Absolute hysteresis in % of VBase, step 2
Table 198:
Name tReset1 ResetTypeCrv1
s -
Parameter P for customer programmable curve for step 1 Tuning param for prog. under voltage InverseTime curve, step 1 Reset time delay used in IEC Definite Time curve step 2 Selection of Time Delay reset curve for step 2
s %
Time delay in Inverse-Time reset (s), step 2 Parameter A for customer programmable curve for step 2 Parameter B for customer programmable curve for step 2 Parameter C for customer programmable curve for step 2 Parameter D for customer programmable curve for step 2 Parameter P for customer programmable curve for step 2 Tuning param for prog. under voltage InverseTime curve, step 2
Table 199:
Name ConnType
8.1.6
Technical data
Table 200:
Function Operate voltage, low and high step Absolute hysteresis Internal blocking level, step 1 and step 2 Inverse time characteristics for step 1 and step 2, see table 592 Table continues on next page
8.2
3U>
SYMBOL-C-2U-SMALLER-THAN V2 EN
8.2.1
Introduction
Overvoltages may occur in the power system during abnormal conditions such as sudden power loss, tap changer regulating failures, open line ends on long lines etc. Two step overvoltage protection (OV2PTOV, 59) function can be used to detect open line ends, normally then combined with a directional reactive over-power function to supervise the system voltage. When triggered, the function will cause an alarm, switch in reactors, or switch out capacitor banks. OV2PTOV (59) has two voltage steps, each of them with inverse or definite time delayed. OV2PTOV (59) has an extremely high reset ratio to allow settings close to system service voltage.
8.2.2
Principle of operation
Two step overvoltage protection OV2PTOV (59) is used to detect high power system voltage. OV2PTOV (59) has two steps with separate time delays. If one-, two- or three407
phase voltages increase above the set value, a corresponding PICKUP signal is issued. OV2PTOV (59) can be set to PICKUP/TRIP, based on 1 out of 3, 2 out of 3 or 3 out of 3 of the measured voltages, being above the set point. If the voltage remains above the set value for a time period corresponding to the chosen time delay, the corresponding trip signal is issued. The time delay characteristic is individually chosen for the two steps and can be either, definite time delay or inverse time delay. The voltage related settings are made in percent of the global set base voltage VBase, which is set in kV, phase-to-phase. OV2PTOV (59) can be set to measure phase-to-ground fundamental value, phase-tophase fundamental value, phase-to-ground RMS value or phase-to-phase RMS value. The choice of measuring is done by the parameter ConnType. The setting of the analog inputs are given as primary phase-to-ground or phase-tophase voltage. OV2PTOV (59) will operate if the voltage gets higher than the set percentage of the set base voltage VBase. This means operation for phase-to-ground voltage over:
Vpickup > (%) VBase(kV ) / 3
EQUATION1610 V2 EN
(Equation 103)
(Equation 104)
When phase-to-ground voltage measurement is selected the function automatically introduces division of the base value by the square root of three.
8.2.2.1
Measurement principle
All the three voltages are measured continuously, and compared with the set values, Pickup1 and Pickup2. The parameters OpMode1 and OpMode2 influence the requirements to activate the PICKUP outputs. Either 1 out of 3, 2 out of 3 or 3 out of 3 measured voltages have to be higher than the corresponding set point to issue the corresponding PICKUP signal. To avoid oscillations of the output PICKUP signal, a hysteresis has been included.
8.2.2.2
EQUATION1625 V2 EN
ANSIEQUATION2287 V2 EN
ANSIEQUATION2288 V2 EN
V - Vpickup -C B Vpickup
EQUATION1616 V1 EN
(Equation 108)
When the denominator in the expression is equal to zero the time delay will be infinity. There will be an undesired discontinuity. Therefore, a tuning parameter CrvSatn is set to compensate for this phenomenon. In the voltage interval Vpickup down to Vpickup (1.0 CrvSatn/100) the used voltage will be: Vpickup (1.0 CrvSatn/100). If the programmable curve is used this parameter must be calculated so that:
EQUATION1435 V1 EN
The highest phase (or phase-to-phase) voltage is always used for the inverse time delay integration, see figure 185. The details of the different inverse time characteristics are shown in section "Inverse characteristics"
VA VB VC
Time
ANSI05000016-2-en.vsd
ANSI05000016 V2 EN
Figure 185:
Trip signal issuing requires that the overvoltage condition continues for at least the user set time delay. This time delay is set by the parameter t1 and t2 for definite time mode (DT) and by selected voltage level dependent time curves for the inverse time mode (TOV). If the PICKUP condition, with respect to the measured voltage ceases during the delay time, and is not fulfilled again within a user defined reset time (tReset1 and tReset2 for the definite time and tIReset1 and tIReset2 for the inverse time) the corresponding PICKUP output is reset, after that the defined reset time has elapsed. Here it should be noted that after leaving the hysteresis area, the PICKUP condition must be fulfilled again and it is not sufficient for the signal to only return back to the hysteresis area. The hysteresis value for each step is settable (HystAbs2) to allow an high and accurate reset of the function. It should be noted that for Two step overvoltage protection OV2PTOV (59) the TOV reset time is constant and does not depend on the voltage fluctuations during the drop-off period. However, there are three
ways to reset the timer, either the timer is reset instantaneously, or the timer value is frozen during the reset time, or the timer value is linearly decreased during the reset time..
tIReset1 Voltage PICKUP tIReset1 TRIP
PU_Overvolt1
HystAbs1
Measured Voltage
Time PICKUP t
TRIP
Linearly decreased
Instantaneous
Time
ANSI05000019-3-en.vsd
ANSI05000019 V3 EN
Figure 186:
Voltage profile not causing a reset of the PICKUP signal for step 1, and inverse time delay
Voltage PICKUP
tIReset1
Time PICKUP t
TRIP
Time Integrator
Frozen Timer
ANSI05000020 V2 EN
Figure 187:
Voltage profile causing a reset of the PICKUP signal for step 1, and inverse time delay
Definite time delay When definite time delay is selected the function will operate as shown in figure 188. Detailed information about individual stage reset/operation behavior is shown in figure 180 and figure 181 receptively. Note that by setting tResetn = 0.0s instantaneous reset of the definite time delayed stage is ensured
PU_ST1
V Vpickup>
a a>b b
ANSI10000100-2-en.vsd
ANSI10000100 V2 EN
Figure 188:
Pickup1
PICKUP
TRIP tReset1
t1
ANSI10000037-2-en.vsd
ANSI10000037 V2 EN
Figure 189:
Pickup1
PICKUP
TRIP
tReset1
t1
ANSI10000038-2-en.vsd
ANSI10000038 V2 EN
Figure 190:
8.2.2.3
Blocking
It is possible to block Two step overvoltage protection OV2PTOV, (59) partially or completely, by binary input signals where:
BLOCK: BLKTR1: BLK1: BLKTR2: BLK2: blocks all outputs blocks all trip outputs of step 1 blocks all pickup and trip outputs related to step 1 blocks all trip outputs of step 2 blocks all pickup and trip outputs related to step 2
8.2.2.4
Design
The voltage measuring elements continuously measure the three phase-to-ground voltages or the three phase-to-phase voltages. Recursive Fourier filters filter the input voltage signals. The phase voltages are individually compared to the set value, and the highest voltage is used for the inverse time characteristic integration. A special logic is included to achieve the 1 out of 3, 2 out of 3 or 3 out of 3 criteria to fulfill the PICKUP condition. The design of Two step overvoltage protection (OV2PTOV, 59) is schematically described in figure 191.
VA
VB
VC
PU_ST1_A PU_ST1_B Pickup t1 t1Reset & Trip Output Logic Step1 PU_ ST1_C PU_ST1 TRST1-A TRST1_B TRST1_C TRST1
OR
PICKUP
MaxVoltSelect
TRIP
OR
MaxVoltSelect
TRIP
OR
OR
TRIP
ANSI05000013-2-en.vsd _ .
ANSI05000013 V2 EN
Figure 191:
Figure 192:
8.2.4
Table 202:
Name TRIP TRST1 TRST1_A TRST1_B TRST1_C TRST2 TRST2_A
8.2.5
Table 203:
Name Operation VBase OperationStep1 Characterist1
Setting parameters
OV2PTOV (59) Group settings (basic)
Values (Range) Disabled Enabled 0.05 - 2000.00 Disabled Enabled Definite time Inverse curve A Inverse curve B Inverse curve C Prog. inv. curve 1 out of 3 2 out of 3 3 out of 3 1 - 200 0.00 - 6000.00 0.000 - 60.000 0.05 - 1.10 0.0 - 100.0 Disabled Enabled Unit kV Step 0.05 Default Disabled 400.00 Enabled Definite time Description Disable/Enable Operation Base voltage Enable execution of step 1 Selection of time delay curve type for step 1
OpMode1
1 out of 3
Number of phases required for op (1 of 3, 2 of 3, 3 of 3) from step 1 Voltage pickup value (Definite-Time & InverseTime curve) in % of VBase, step 1 Definitive time delay of step 1 Minimum operate time for inverse curves for step 1 Time multiplier for the inverse time delay for step 1 Absolute hysteresis in % of VBase, step 1 Enable execution of step 2
%VB s s %VB -
OpMode2
1 out of 3
Number of phases required for op (1 of 3, 2 of 3, 3 of 3) from step 2 Voltage pickup value (Definite-Time & InverseTime curve) in % of VBase, step 2 Definitive time delay of step 2 Minimum operate time for inverse curves for step 2 Time multiplier for the inverse time delay for step 2 Absolute hysteresis in % of VBase, step 2
%VB s s %VB
Table 204:
Name tReset1 ResetTypeCrv1
s % s -
tIReset2
0.001
0.025
Table 205:
Name ConnType
8.2.6
Technical data
Table 206:
Function Operate voltage, step 1 and 2 Absolute hysteresis Inverse time characteristics for steps 1 and 2, see table 591 Definite time delay, step 1 Definite time delays Minimum operate time, Inverse characteristics Operate time, pickup function Reset time, pickup function Critical impulse time Impulse margin time
(0.00 - 6000.00) s (0.000-60.000) s (0.000-60.000) s 25 ms typically at 0 to 2 x Vset 25 ms typically at 2 to 0 x Vset 10 ms typically at 0 to 2 x Vset 15 ms typically
8.3
3U0
TRV V1 EN
8.3.1
Introduction
Residual voltages may occur in the power system during ground faults. Two step residual overvoltage protection ROV2PTOV (59N) function calculates the residual voltage from the three-phase voltage input transformers or measures it from a single voltage input transformer fed from a broken delta or neutral point voltage transformer. ROV2PTOV (59N) has two voltage steps, each with inverse or definite time delay. Reset delay ensures operation for intermittent ground faults.
8.3.2
Principle of operation
Two step residual overvoltage protection ROV2PTOV (59N) is used to detect high singlephase voltage, such as high residual voltage, also called 3V0. The residual voltage can be measured directly from a voltage transformer in the neutral of a power transformer or from a three-phase voltage transformer, where the secondary windings are connected in an open delta. Another possibility is to measure the three-phase voltages and internally in the IED calculate the corresponding residual voltage and connect this calculated residual voltage to ROV2PTOV (59N). ROV2PTOV (59N) has two steps with separate time delays. If the single-phase (residual) voltage remains above the set value for a time period corresponding to the chosen time delay, the corresponding TRIP signal is issued. The time delay characteristic is individually chosen for the two steps and can be either, definite time delay or inverse time delay. The voltage related settings are made in percent of the base voltage, which is set in kV, phase-phase.
8.3.2.1
8.3.2.2
Time delay
The time delay for the two steps can be either definite time delay (DT) or inverse time delay (TOV). For the inverse time delay four different modes are available: inverse curve A inverse curve B inverse curve C customer programmable inverse curve
ANSIEQUATION2422 V1 EN
where: Un> U Set value for step 1 and step 2 Measured voltage
- 0.035
ANSIEQUATION2423 V1 EN
(Equation 111)
+ 0.035
ANSIEQUATION2421 V1 EN
(Equation 112)
t=
TD A
V - Vpickup -C B Vpickup
+D
EQUATION1616 V1 EN
(Equation 113)
When the denominator in the expression is equal to zero the time delay will be infinity. There will be an undesired discontinuity. Therefore a tuning parameter CrvSatn is set to compensate for this phenomenon. In the voltage interval Vpickup up to Vpickup (1.0 + CrvSatn/100) the used voltage will be: Vpickup (1.0 + CrvSatn/100). If the programmable curve is used this parameter must be calculated so that:
EQUATION1440 V1 EN
The details of the different inverse time characteristics are shown in section "Inverse characteristics". TRIP signal issuing requires that the residual overvoltage condition continues for at least the user set time delay. This time delay is set by the parameter t1 and t2 for definite time mode (DT) and by some special voltage level dependent time curves for the inverse time mode (TOV). If the PICKUP condition, with respect to the measured voltage ceases during the delay time, and is not fulfilled again within a user defined reset time (tReset1 and tReset2 for the definite time and tIReset1 and tIReset2 for the inverse time) the corresponding PICKUP output is reset, after that the defined reset time has elapsed. Here it should be noted that after leaving the hysteresis area, the PICKUP condition must be fulfilled again and it is not sufficient for the signal to only return back to the hysteresis area. Also notice that for the overvoltage function TOV reset time is constant and does not depend on the voltage fluctuations during the drop-off period. However, there are three ways to reset the timer, either the timer is reset instantaneously, or the timer value is frozen during the reset time, or the timer value is linearly decreased during the reset time. See figure 186 and figure 187.
PU_Overvolt1
HystAbs1
Measured Voltage
Time PICKUP t
TRIP
Linearly decreased
Instantaneous
Time
ANSI05000019-3-en.vsd
ANSI05000019 V3 EN
Figure 193:
Voltage profile not causing a reset of the PICKUP signal for step 1, and inverse time delay
Voltage PICKUP
tIReset1
Time PICKUP t
TRIP
Time Integrator
Frozen Timer
ANSI05000020 V2 EN
Figure 194:
Voltage profile causing a reset of the PICKUP signal for step 1, and inverse time delay
Definite timer delay When definite time delay is selected, the function will operate as shown in figure 195. Detailed information about individual stage reset/operation behavior is shown in figure 180 and figure 181 respectively. Note that by setting tResetn = 0.0s, instantaneous reset of the definite time delayed stage is ensured.
PU_ST1
V Vpickup>
a a>b b
ANSI10000100-2-en.vsd
ANSI10000100 V2 EN
Figure 195:
Pickup1
PICKUP
TRIP tReset1
t1
ANSI10000037-2-en.vsd
ANSI10000037 V2 EN
Figure 196:
Pickup1
PICKUP
TRIP
tReset1
t1
ANSI10000038-2-en.vsd
ANSI10000038 V2 EN
Figure 197:
8.3.2.3
Blocking
It is possible to block Two step residual overvoltage protection ROV2PTOV (59N) partially or completely, by binary input signals where:
BLOCK: BLKTR1: BLK1: BLKTR2: BLK2: blocks all outputs blocks all trip outputs of step 1 blocks all pickup and trip outputs related to step 1 blocks all trip outputs of step 2 blocks all PICKUP and trip inputs related to step 2
8.3.2.4
Design
The voltage measuring elements continuously measure the residual voltage. Recursive Fourier filters filter the input voltage signal. The single input voltage is compared to the set value, and is also used for the inverse time characteristic integration. The design of Two step residual overvoltage protection (ROV2PTOV, 59N) is schematically described in figure 198.
VN
TRIP
PU_ST2 TRST2
OR
PICKUP
TRIP
TRIP
ANSI05000748-2-en.vsd
ANSI05000748 V2 EN
Figure 198:
8.3.3
Function block
ROV2PTOV (59N) V3P* TRIP BLOCK TRST1 BLKTR1 TRST2 BLK1 PICKUP BLKTR2 PU_ST1 BLK2 PU_ST2 ANSI06000278-2-en.vsd
ANSI06000278 V2 EN
Figure 199:
Table 208:
Name TRIP TRST1 TRST2 PICKUP PU_ST1 PU_ST2
8.3.5
Table 209:
Name Operation VBase OperationStep1 Characterist1
Setting parameters
ROV2PTOV (59N) Group settings (basic)
Values (Range) Disabled Enabled 0.05 - 2000.00 Disabled Enabled Definite time Inverse curve A Inverse curve B Inverse curve C Prog. inv. curve 1 - 200 0.00 - 6000.00 0.000 - 60.000 Unit kV Step 0.05 Default Disabled 400.00 Enabled Definite time Description Disable/Enable Operation Base voltage Enable execution of step 1 Selection of time delay curve type for step 1
Pickup1 t1 t1Min
%VB s s
1 0.01 0.001
30 5.00 5.000
Voltage setting/pickup value (DT & TOV), step 1 in % of VBase Definitive time delay of step 1 Minimum operate time for inverse curves for step 1
%VB s s %VB
Voltage setting/pickup value (DT & TOV), step 2 in % of VBase Definitive time delay of step 2 Minimum operate time for inverse curves for step 2 Time multiplier for the inverse time delay for step 2 Absolute hysteresis in % of VBase, step 2
Table 210:
Name tReset1 ResetTypeCrv1
s % s -
Time delay in Inverse-Time reset (s), step 2 Parameter A for customer programmable curve for step 2 Parameter B for customer programmable curve for step 2 Parameter C for customer programmable curve for step 2 Parameter D for customer programmable curve for step 2 Parameter P for customer programmable curve for step 2 Tuning param for programmable over voltage TOV curve, step 2
8.3.6
Technical data
Table 211:
Function Operate voltage, step 1 and step 2 Absolute hysteresis Inverse time characteristics for low and high step, see table 593 Definite time setting, step 1 Definite time setting Minimum operate time Operate time, pickup function Reset time, pickup function Critical impulse time Impulse margin time
(0.006000.00) s (0.00060.000) s (0.000-60.000) s 25 ms typically at 0 to 2 x Vset 25 ms typically at 2 to 0 x Vset 10 ms typically at 0 to 2 x Vset 15 ms typically
8.4
U/f >
SYMBOL-Q V1 EN
8.4.1
Introduction
When the laminated core of a power transformer or generator is subjected to a magnetic flux density beyond its design limits, stray flux will flow into non-laminated components not designed to carry flux and cause eddy currents to flow. The eddy currents can cause excessive heating and severe damage to insulation and adjacent parts in a relatively short time. The function has settable inverse operating curves and independent alarm stages.
8.4.2
Principle of operation
The importance of Overexcitation protection (OEXPVPH, 24) function is growing as the power transformers as well as other power system elements today operate most of the time near their designated limits. Modern design transformers are more sensitive to overexcitation than earlier types. This is a result of the more efficient designs and designs which rely on the improvement in the uniformity of the excitation level of modern systems. Thus, if emergency that causes overexcitation does occur, transformers may be damaged unless corrective action is promptly taken. Transformer manufacturers recommend an overexcitation protection as a part of the transformer protection system. Overexcitation results from excessive applied voltage, possibly in combination with below-normal frequency. Such condition may occur when a transformer unit is on load, but are more likely to arise when it is on open circuit, or at a loss of load occurrence. Transformers directly connected to generators are in particular danger to experience overexcitation condition. It follows from the fundamental transformer equation, see equation 115, that peak flux density Bmax is directly proportional to induced voltage E, and inversely proportional to frequency f, and turns n.
E = 4.44 f n Bmax A
EQUATION898 V2 EN
(Equation 115)
( Vr ) ( fn )
(Equation 116)
ANSIEQUATION2296 V1 EN
Disproportional variations in quantities E and f may give rise to core overfluxing. If the core flux density Bmax increases to a point above saturation level (typically 1.9 Tesla), the flux will no longer be contained within the core, but will extend into other (nonlaminated) parts of the power transformer and give rise to eddy current circulations. Overexcitation will result in: overheating of the non-laminated metal parts a large increase in magnetizing currents an increase in core and winding temperature an increase in transformer vibration and noise
Protection against overexcitation is based on calculation of the relative volt per hertz (V/ Hz) ratio. Protection initiates a reduction of excitation, and if this fails, or if this is not possible, the TRIP signal will disconnect the transformer from the source after a delay ranging from seconds to minutes, typically 5-10 seconds. Overexcitation protection may be of particular concern on directly connected generator unit transformers. Directly connected generator-transformers are subjected to a wide range of frequencies during the acceleration and deceleration of the turbine. In such cases, OEXPVPH (24) may trip the field breaker during a start-up of a machine, by means of the overexcitation ALARM signal. If this is not possible, the power transformer can be disconnected from the source, after a delay, by the TRIP signal. The IEC 60076 - 1 standard requires that transformers operate continuously at not more than 10% above rated voltage at no load, and rated frequency. At no load, the ratio of the actual generator terminal voltage to the actual frequency should not exceed 1.1 times the ratio of transformer rated voltage to the rated frequency on a sustained basis, see equation 117.
E f 1.1 Vn fn
(Equation 117)
EQUATION1630 V1 EN
E f
Pickup1 fn
(Equation 118)
ANSIEQUATION2297 V2 EN
where:
Pickup1 is the maximum continuously allowed voltage at no load, and rated frequency.
Pickup1 is a setting parameter. The setting range is 100% to 180%. If the user does not know exactly what to set, then the default value for Pickup1 = 110 % given by the IEC 60076-1 standard shall be used. In OEXPVPH (24), the relative excitation M is expressed according to equation 119.
M ( p.u.) = E f Vn fn
(Equation 119)
ANSIEQUATION2299 V1 EN
It is clear from the above formula that, for an unloaded power transformer, M = 1 for any E and f, where the ratio E/f is equal to Vn/fn. A power transformer is not overexcited as long as the relative excitation is M Pickup1, Pickup1 expressed in % of Vn/fn. The overexcitation protection algorithm is fed with an input voltage V which is in general not the induced voltage E from the fundamental transformer equation. For no load condition, these two voltages are the same, but for a loaded power transformer the internally induced voltage E may be lower or higher than the voltage V which is measured and fed to OEXPVPH (24), depending on the direction of the power flow through the power transformer, the power transformer side where OEXPVPH (24) is applied, and the power transformer leakage reactance of the winding. It is important to specify in the application configuration on which side of the power transformer OEXPVPH (24) is placed. As an example, at a transformer with a 15% short circuit impedance Xsc, the full load, 0.8 power factor, 105% voltage on the load side, the actual flux level in the transformer core, will not be significantly different from that at the 110% voltage, no load, rated frequency, provided that the short circuit impedance X can be equally divided between the primary and the secondary winding: XLeakage = XLeakage1 = XLeakage2 = Xsc / 2 = 0.075 pu. OEXPVPH (24) calculates the internal induced voltage E if XLeakage (meaning the leakage reactance of the winding where OEXPVPH (24) is connected) is known to the user. The assumption taken for two-winding power transformers that XLeakage = Xsc /
2 is unfortunately most often not true. For a two-winding power transformer the leakage reactances of the two windings depend on how the windings are located on the core with respect to each other. In the case of three-winding power transformers the situation is still more complex. If a user has the knowledge on the leakage reactance, then it should applied. If a user has no idea about it, XLeakage can be set to Xc/2. OEXPVPH (24) protection will then take the given measured voltage V, as the induced voltage E. It is assumed that overexcitation is a symmetrical phenomenon, caused by events such as loss-of-load, etc. It will be observed that a high phase-to-ground voltage does not mean overexcitation. For example, in an ungrounded power system, a single phase-toground fault means high voltages of the healthy two phases-to-ground, but no overexcitation on any winding. The phase-to-phase voltages will remain essentially unchanged. The important voltage is the voltage between the two ends of each winding.
8.4.2.1
Measured voltage
If one phase-to-phase voltage is available from the side where overexcitation protection is applied, then Overexcitation protection OEXPVPH (24) shall be set to measure this voltage, MeasuredV. The particular voltage which is used determines the two currents that must be used. This must be chosen with the setting MeasuredI. It is extremely important that MeasuredV and MeasuredI are set to same value. If, for example, voltage Vab is fed to OEXPVPH(24), then currents Ia, and Ib must be applied. From these two input currents, current Iab = Ia - Ib is calculated internally by the OEXPVPH (24) algorithm. The phase-to-phase voltage must be higher than 70% of the rated value, otherwise the protection algorithm exits without calculating the excitation. ERROR output is set to 1, and the displayed value of relative excitation V/ Hz shows 0.000. If three phase-to-ground voltages are available from the side where overexcitation is connected, then OEXPVPH (24) shall be set to measure positive sequence voltage and current. In this case the positive sequence voltage and the positive sequence current are used by OEXPVPH (24). A check is made if the positive sequence voltage is higher than 70% of rated phase-to-ground voltage, when below this value, OEXPVPH (24) exits immediately, and no excitation is calculated. ERROR output is set to 1, and the displayed value of relative excitation V/Hz shows 0.000. The frequency value is received from the pre-processing block. The function operates for frequencies within the range of 33-60 Hz and of 42-75 Hz for 50 Hz and 60 Hz respectively.
OEXPVPH (24) can be connected to any power transformer side, independent from the power flow. The side with a possible load tap changer must not be used.
8.4.2.2
The so called IEEE law approximates a square law and has been chosen based on analysis of the various transformers overexcitation capability characteristics. They can match the transformer core capability well. The square law is according to equation 120.
top = 0.18 TD
M PUV Hz - 1
0.18 TD overexcitation
2
ANSIEQUATION2298 V2 EN
(Equation 120)
where: M TD the relative excitation is time multiplier for inverse time functions, see figure 201. Parameter TD (time delay multiplier setting) selects one delay curve from the family of curves.
Pickup1 is maximum continuously allowed voltage at no load, and rated frequency, in pu and
Vmeasured fmeasured =
Vmeasured
frated
ANSIEQUATION2404 V1 EN
An analog overexcitation relay would have to evaluate the following integral expression, which means to look for the instant of time t = top according to equation 122.
top
( M ( t ) - Pickup1)
0
dt 0.18 TD
(Equation 122)
ANSIEQUATION2300 V1 EN
A digital, numerical relay will instead look for the lowest j (that is, j = n) where it becomes true that:
Dt
( M( j) - PUV / Hz )
j=k
0.18 TD
(Equation 123)
EQUATION1636 V1 EN
where: Dt is the time interval between two successive executions of OEXPVPH (24) and M(j) - Pickup1 is the relative excitation at (time j) in excess of the normal (rated) excitation which is given as Vn/fn.
As long as M > Pickup1 (that is, overexcitation condition), the above sum can only be larger with time, and if the overexcitation persists, the protected transformer will be tripped at j = n. Inverse delays as per figure 201, can be modified (limited) by two special definite delay settings, namely t_MaxTripDelay and t_MinTripDelay, see figure 200.
under excitation
overexcitation t_MinTripDelay 0 M=Pickup1 Pickup1 Mmax Pickup1 Mmax Emax Overexcitation M-Pickup1 Excitation M E (only if f = fn = const) ANSI99001067-2en.vsd
ANSI99001067 V2 EN
Figure 200:
A definite maximum time, t_MaxTripDelay, can be used to limit the operate time at low degrees of overexcitation. Inverse delays longer than t_MaxTripDelay will not be allowed. In case the inverse delay is longer than t_MaxTripDelay, OEXPVPH (24) trips after t_MaxTripDelay seconds. A definite minimum time, t_MinTripDelay, can be used to limit the operate time at high degrees of overexcitation. In case the inverse delay is shorter than t_MinTripDelay, OEXPVPH (24) function trips after t_MinTripDelay seconds. The inverse delay law is not valid for values exceeding Mmax. The delay will be tMin, irrespective of the overexcitation level, when values exceed Mmax (that is, M>Pickup1).
Time (s)
1000
100 TD = 60
TD = 20
10
TD = 10 TD = 9 TD = 8 TD = 7 TD = 6 TD = 5 TD = 4 TD = 3 TD = 2
TD = 1 1 2 3 4 5 10 20 30 40
OVEREXCITATION IN %
(M-Emaxcont)*100)
en01000373_ansi.vsd
ANSI01000373 V1 EN
Figure 201:
The critical value of excitation M is determined indirectly via OEXPVPH (24) setting Pickup2. Pickup2 can be thought of as a no-load voltage at rated frequency, where the inverse law should be replaced by a short definite delay, t_MinTripDelay. If, for example, Pickup2 = 140 %, then M is according to equation 124.
M=
( Pickup2 f )
Vn/fn
= 1.40
(Equation 124)
ANSIEQUATION2286 V1 EN
The Tailor-Made law allows a user to design an arbitrary delay characteristic. In this case the interval between M = Pickup1, and M = Mmax is automatically divided into
438 Technical reference manual
five equal subintervals, with six delays. (settings t1, t2, t3, t4, t5 and t6) as shown in figure 202. These times should be set so that t1 => t2 => t3 => t4 => t5 => t6.
delay in s
t_MaxTripDelay
underexcitation 0 Emaxcont
ANSI99001068 V1 EN
Figure 202:
Delays between two consecutive points, for example t3 and t4, are obtained by linear interpolation. Should it happen that t_MaxTripDelay be lower than, for example, delays t1, and t2, the actual delay would be t_MaxTripDelay. Above Mmax, the delay can only be t_MinTripDelay.
8.4.2.3
Cooling
Overexcitation protection OEXPVPH (24) is basically a thermal protection; therefore a cooling process has been introduced. Exponential cooling process is applied. Parameter Setting tool is an OEXPVPH (24) setting, with a default time constant t_CoolingK of 20 minutes. This means that if the voltage and frequency return to their previous normal values (no more overexcitation), the normal temperature is assumed to be reached not before approximately 5 times t_CoolingK minutes. If an overexcitation condition would return before that, the time to trip will be shorter than it would be otherwise.
8.4.2.4
The relative excitation M, shown on the local HMI and in PCM600 has a monitored data value VPERHZ, is calculated from the expression:
M ( p.u.) = E f Vn fn
(Equation 125)
ANSIEQUATION2299 V1 EN
If VPERHZ value is less than setting Pickup1 (in %), the power transformer is underexcited. If VPERHZ is equal to Pickup1 (in %), the excitation is exactly equal to the power transformer continuous capability. If VPERHZ is higher than Pickup1, the protected power transformer is overexcited. For example, if VPERHZ = 1.100, while Pickup1 = 110 %, then the power transformer is exactly on its maximum continuous excitation limit. Monitored data value THERMSTA shows the thermal status of the protected power transformer iron core. THERMSTA gives the thermal status in % of the trip value which corresponds to 100%. THERMSTA should reach 100% at the same time, as TMTOTRIP reaches 0 seconds. If the protected power transformer is then for some reason not switched off, THERMSTA shall go over 100%. If the delay as per IEEE law, or Tailor-made Law, is limited by t_MaxTripDelay, and/ or t_MinTripDelay, then the Thermal status will generally not reach 100% at the same time, when tTRIP reaches 0 seconds. For example, if, at low degrees of overexcitation, the very long delay is limited by t_MaxTripDelay, then the OEXPVPH (24) TRIP output signal will be set to 1 before the Thermal status reaches 100%.
8.4.2.5
Overexcitation alarm
A separate step, AlarmPickup, is provided for alarming purpose. It is normally set 2% lower than (Pickup1) and has a definite time delay, tAlarm. This will give the operator an early abnormal voltages warning.
8.4.2.6
&
ALARM
&
TRIP
t_MinTripDelay TD M OR
Ei
IEEE law
Figure 203:
Simplification of the diagram is in the way the IEEE and Tailor-made delays are calculated. The cooling process is not shown. It is not shown that voltage and frequency are separately checked against their respective limit values.
8.4.3
Function block
OEXPVPH (24) I3P* V3P* BLOCK RESET TRIP PICKUP ALARM
ANSI05000329-2-en.vsd
ANSI05000329 V2 EN
Figure 204:
Table 213:
Name TRIP PICKUP ALARM
8.4.5
Table 214:
Name Operation IBase VBase Pickup1 Pickup2 XLeakage t_TripPulse t_MinTripDelay t_MaxTripDelay t_CoolingK CurveType
Setting parameters
OEXPVPH (24) Group settings (basic)
Values (Range) Disabled Enabled 1 - 99999 0.05 - 2000.00 100.0 - 180.0 100.0 - 200.0 0.000 - 200.000 0.000 - 60.000 0.000 - 60.000 0.00 - 9000.00 0.10 - 9000.00 IEEE Tailor made Unit A kV %VB/f %VB/f ohm s s s s Step 1 0.05 0.1 0.1 0.001 0.001 0.001 0.01 0.01 Default Disabled 3000 400.00 110.0 140.0 0.000 0.100 7.000 1800.00 1200.00 IEEE Description Disable/Enable Operation Base current (rated phase current) in A Base voltage (main voltage) in kV Operate level of V/Hz at no load and rated freq in % of (Vbase/frated) High level of V/Hz above which tMin is used, in % of (Vbase/fn) Winding leakage reactance in primary ohms Length of the pulse for trip signal (in sec) Minimum trip delay for V/Hz inverse curve, in sec Maximum trip delay for V/Hz inverse curve, in sec Transformer magnetic core cooling time constant, in sec Inverse time curve selection, IEEE/Tailor made
Table 215:
Name t1_UserCurve t2_UserCurve t3_UserCurve t4_UserCurve t5_UserCurve t6_UserCurve
Table 216:
Name MeasuredV
MeasuredI
AB
8.4.6
Technical data
Table 217:
Function Pickup value, pickup Pickup value, alarm Pickup value, high level Table continues on next page
Accuracy 5% + 40 ms
EQUATION1645 V1 EN
(Equation 126)
where M = (E/f)/(Vn/fn) Minimum time delay for inverse function Maximum time delay for inverse function Alarm time delay (0.00060.000) s (0.009000.00) s (0.009000.00) 0.5% 10 ms 0.5% 10 ms 0.5% 10 ms
8.5
8.5.1
Introduction
A voltage differential monitoring function is available. It compares the voltages from two three phase sets of voltage transformers and has one sensitive alarm step and one trip step.
8.5.2
Principle of operation
The Voltage differential protection function VDCPTOV (60) is based on comparison of the magnitudes of the two voltages connected in each phase. Possible differences between the ratios of the two Voltage/Capacitive voltage transformers can be compensated for with a ratio correction factors RF_X. The voltage difference is evaluated and if it exceeds the alarm level VDAlarm or trip level VDTrip signals for alarm (ALARM output) or trip (TRIP output) is given after definite time delay tAlarm respectively tTrip. The two three phase voltage supplies are also supervised with undervoltage settings V1Low and V2Low. The outputs for loss of voltage V1LOW resp V2LOW will be activated. The V1 voltage is supervised for loss of individual phases whereas the V2 voltage is supervised for loss of all three phases. Loss of all U1or all U2 voltages will block the differential measurement. This blocking can be switched off with setting BlkDiffAtULow = No.
VDCPTOV (60) function can be blocked from an external condition with the binary BLOCK input. It can for example, be activated from Fuse failure supervision function SDDRFUF. To allow easy commissioning the measured differential voltage is available as service value. This allows simple setting of the ratio correction factor to achieve full balance in normal service. The principle logic diagram is shown in figure 205.
VDTrip_A
AND O R
VDTrip_B
AND
0 0-tReset
0-tTrip 0
AND
TRIP
VDTrip_C
AND AND
PICKUP
VDAlarm_A
AND O R
VDAlarm_B
AND
0-tAlarm 0
AND
ALARM
VDAlarm_C
AND
V1Low_A V1Low_B V1Low_C BlkDiffAtULow V2Low_A V2Low_B V2Low_C BLOCK AND 0-t1 0 V2LOW OR AND 0-tAlarm 0 AND V1LOW
AND
AND
en06000382_2_ansi.vsd
ANSI06000382 V3 EN
Figure 205:
Figure 206:
8.5.4
Table 219:
Name TRIP PICKUP ALARM V1LOW V2LOW VDIFF_A VDIFF_B VDIFF_C
8.5.5
Table 220:
Name Operation VBase BlkDiffAtVLow VDTrip tTrip tReset V1Low V2Low tBlock VDAlarm tAlarm
Table 221:
Name RF_A RF_B RF_C
8.5.6
Technical data
Table 222:
Function Voltage difference for alarm and trip Under voltage level Timers
8.6
100% Stator ground fault protection, 3rd harmonic based STEFPHIZ (59THD)
Function description 100% Stator ground fault protection, 3rd harmonic based IEC 61850 identification STEFPHIZ IEC 60617 identification ANSI/IEEE C37.2 device number 59THD
8.6.1
Introduction
Stator ground fault is a fault type having relatively high fault rate. The generator systems normally have high impedance grounding, that is, grounding via a neutral point resistor. This resistor is normally dimensioned to give an ground fault current in the range 3 15 A at a solid ground-fault directly at the generator high voltage terminal. The relatively small ground fault currents give much less thermal and mechanical stress on the generator, compared to the short circuit case, which is between conductors of two phases. Anyhow, the ground faults in the generator have to be detected and the generator has to be tripped, even if longer fault time compared to internal short circuits, can be allowed. In normal non-faulted operation of the generating unit the neutral point voltage is close to zero, and there is no zero sequence current flow in the generator. When a phase-toground fault occurs the neutral point voltage will increase and there will be a current flow through the neutral point resistor. To detect a ground fault on the windings of a generating unit one may use a neutral point overvoltage protection, a neutral point overcurrent protection, a zero sequence overvoltage protection or a residual differential protection. These protections are simple and have served well during many years. However, at best these simple schemes protect only 95% of the stator winding. They leave 5% close to the neutral end unprotected. Under unfavorable conditions the blind zone may extend up to 20% from the neutral. The 95% stator ground fault protection measures the fundamental frequency voltage component in the generator star point and it operates when it exceeds the preset value. By applying this principle approximately 95% of the stator winding can be protected. In order to protect the last 5% of the stator winding close to the neutral end the 3rd harmonic voltage measurement can be performed. In 100% Stator E/F 3rd harmonic protection either the 3rd harmonic voltage differential principle, the neutral point 3rd harmonic undervoltage principle or the terminal side 3rd harmonic overvoltage principle can be applied. However, differential principle is strongly recommended. Combination of these two measuring principles provides coverage for entire stator winding against ground faults.
RN
Rf
Transformer
uN
Samples of the neutral voltage from which the fundamental and 3rd harmonic voltages are filtered out
1- x 1 or 100 %
Neutral point fundamental frequency over-voltage protection 5% - 100%
uT
Samples of the terminal voltage from which the 3rd harmonic voltage is filtered out
ANSI10000202-1-en.vsd
ANSI10000202 V1 EN
Figure 207:
8.6.2
Principle of operation
The protection is a combination of the 95% fundamental frequency ground fault protection and the 3 rd harmonic based stator earth fault protection, (STEFPHIZ, 59THD). The 3rd harmonic based 100% stator ground fault protection is using the 3rd harmonic voltage generated by the generator itself. To assure reliable function of the protection it is necessary that the 3rd harmonic voltage generation is at least 0.8 V RMS on VT secondary side. The 3rd harmonic voltage generated by the generator has the same phase angle in the three phases. It has the characteristic of a zero sequence component. If the generator is connected to the power system via a block transformer that cannot transform zero sequence voltages between the voltage levels, the 3rd harmonic voltage, that is V3N and V3T in fig 208, in the generator system is not influenced by the external power system. At normal operation the generator third harmonic voltage characteristic can be described as in figure 208. Note that angle between V3N and V3T is typically close to 180.
- DV3 +
V3
+ V3T,A -
V3N
+ V3T,B -
+ V3T,C -
V3T
V3N
en06000448_ansi.vsd
ANSI06000448 V1 EN
Figure 208:
The generator is modeled as parts of a winding where a 3rd harmonic voltage is induced along the winding, represented by the end voltages V3N (voltage drop across resistor) and V3T in the figure. Via the winding capacitances to ground and the neutral point resistor there will be a small 3rd harmonic current flow, giving the voltages V3N and V3T. It can easily be seen that the 3rd harmonic voltage in the generator neutral point (V3N) will be close to zero in case of a stator ground-fault close to the neutral. This fact alone can be used as an indication of stator ground-fault. To enable better sensitivity and stability also measurement of the generator's 3rd harmonic voltage V3T is also used. In addition to the decrease of V3N the generator voltage V3T will increase under the stator ground-fault close to the generator neutral point. Therefore the 3rd harmonic voltage V3T , (which is a zero sequence voltage) is used by the protection. In the 3rd harmonic voltage differential protection algorithm equation 127 is used:
(Equation 127)
V3N, and V3T are third harmonic phasors with real and imaginary parts. The factor Beta must be set not to risk operation under non-faulted conditions. The voltage V3N is measured via a voltage transformer between the generator neutral point and ground. The voltage V3T can be measured in different ways. The setting TVoltType defines how the protection function is fed from voltage transformers at the high voltage side of the generator. If V3T is lower than the set level VT3BlkLevel, STEFPHIZ (59THD) function is blocked. The choices of TVoltType are: NoVoltage: There is no voltage measured from the generator terminal side. This can be the case when there are only phase-to-phase voltage transformers available at the generator terminal side. In this case the protection will operate as a simple neutral point 3rd harmonic undervoltage protection, which must be blocked externally during generator start-up and shut-down. ResidualVoltage: The function is fed from a broken delta connection of the phase to ground connected voltage transformers at the generator terminal side, V3T=(1/3)*V_Broken_Delta. AllThreePhases: The function is fed from the three phase to ground connected voltage transformers at the generator terminal side. The 3rd harmonic voltage V3T is calculated in the IED, V3T=(1/3)*(V3A+V3B+V3C). PhaseA, PhaseB, or PhaseC: The function is fed from one phase voltage transformer only. The 3rd harmonic zero sequence voltage is assumed to be equal to any of the phase voltages, as the third harmonic voltage is of zero sequence type, V3T=V3Lx. A simplified block diagram describing the stator ground fault protection function shown in figure 209.
Complex VT3
Pickup
Complex VN3
Pickup
CB Status Block
en06000449_ansi.vsd
ANSI06000449 V2 EN
Figure 209:
STEFPHIZ (59THD) function can be described in a simplified logical diagram as shown in figure 210. Note that the 3rd harmonic numerical filters are not part of the stator ground-fault protection function. These third harmonic voltages are calculated by the preprocessing blocks connected to the function.
Beta V3N V3N+V3T X a b ba AND t 0 OR OR VNFundPU V_N a b ba t 0 PU3H TRIP3H PICKUP TRIP PU_VN TRIPVN
VT3BlkLevel V3T
a b ab
ANSI07000001-2-en.vsd
ANSI07000001 V2 EN
Figure 210:
Simplified Pickup and Trip logical diagram of the 100% Stator earth fault protection, 3rd harmonic based STEFPHIZ (59THD) protection
There are two different cases of generator block configuration; with or without generator circuit breaker. If there is no generator breaker the capacitive coupling to ground is the same under all operating conditions. When there is a generator breaker, the capacitive coupling to ground differs between the operating conditions when the generator is running with the generator breaker open (before synchronization) and with the circuit breaker closed. This can be shown as in figure 211.
- DV3 + + V3T,A Ctr/3 UV3 +
V3N
+ V3T,B -
Ctr/3
+ V3T,C -
Ctr/3
en07000002-2_ansi.vsd
ANSI07000002 V2 EN
Figure 211:
With the circuit breaker open, the total capacitance will be smaller compared to normal operating conditions. This means that the neutral point 3rd harmonic voltage will be reduced compared to the normal operating condition. Therefore, there is a possibility to reduce the sensitivity of the protection when the generator circuit breaker is open. With the setting CBexists change of the sensitivity is enabled. If the binary input signal 52a is activated the set sensitivity is valid. If the generator circuit breaker is opened the binary input 52a is deactivated and the sensitivity is changed. This is done by changing the factor Beta which is multiplied with a set constant FactorCBopen. In addition to the binary outputs also some analog outputs are available from the protection function in order to enable easier commissioning: E3: the magnitude of the 3rd harmonic voltage induced in the stator given in primary volts VN3: the magnitude of the 3rd harmonic voltage measured in the neutral point of the generator VT3: the magnitude of the 3rd harmonic voltage measured in the terminal point of the generator ANGLE: the angle between the phasors VN3 and VT3 given in radians DV3: the magnitude of the 3rd harmonic differential voltage BV3: the magnitude of the 3rd harmonic bias voltage V_N: the fundamental frequency voltage measured in the neutral point of the generator
8.6.3
Figure 212:
8.6.4
Table 224:
Name TRIP TRIP3H TRIP_VN PICKUP PU_3H PU_VN
Mag. of 3rd harm. voltage at generator terminal side, Volts Mag. of 3rd harm. voltage at generator neutral side, Volts Total induced stator 3rd harmonic voltage, primary Volts Angle between 3rd harmonic votage phasors, radians Diff. between 3rd harm. volt. at both sides of gen., Volts Bias voltage, a part of voltN3rdHarmonic, primary Volts Fund. frequency voltage at generator neutral, primary Volts
8.6.5
Table 225:
Name Operation Beta CBexists FactorCBopen VN3rdHPU VT3BlkLevel VNFundPU t3rdH tVNFund
Setting parameters
STEFPHIZ (59THD) Group settings (basic)
Values (Range) Disabled Enabled 0.50 - 10.00 No Yes 1.00 - 10.00 0.5 - 10.0 0.1 - 10.0 1.0 - 50.0 0.020 - 60.000 0.020 - 60.000 Unit % % % s s Step 0.01 0.01 0.1 0.1 0.1 0.001 0.001 Default Disabled 3.00 No 1.00 2.0 1.0 5.0 1.000 0.500 Description Disable/Enable Operation Portion of voltN3rdHarmonic used as bias Defines if generator CB exists (between Gen & Transformer) Beta is multiplied by this factor when CB is open Pickup 3rd Harm V< protection (when activated) % of VB/1,732 If VT3 is below limit 3rdH Diff is blocked, in % of VB/1,732 Pickup fundamental VN> protection (95% SEF), % of VB/1,732 Operation delay of 3rd harm-based protection (100% SEF) in s Operation delay of fundamental VN> protection (95% SEF) in s
Table 226:
Name GenRatedVolt TVoltType
8.6.6
458
Section 9
Frequency protection
9.1
f<
SYMBOL-P V1 EN
9.1.1
Introduction
Underfrequency occurs as a result of a lack of generation in the network. Underfrequency protection SAPTUF (81) is used for load shedding systems, remedial action schemes, gas turbine startup and so on. SAPTUF (81) is also provided with undervoltage blocking. The operation is based on positive sequence voltage measurement and requires two phasephase or three phase-neutral voltages to be connected. For information about how to connect analog inputs, refer to Application manual/IED application/Analog inputs/ Setting guidelines
9.1.2
Principle of operation
Underfrequency protection SAPTUF (81) is used to detect low power system frequency. SAPTUF (81) can either have a definite time delay or a voltage magnitude dependent time delay. If the voltage magnitude dependent time delay is applied, the time delay will be longer if the voltage is higher, and the delay will be shorter if the
459
voltage is lower. If the frequency remains below the set value for a time period corresponding to the chosen time delay, the corresponding trip signal is issued. To avoid an unwanted trip due to uncertain frequency measurement at low voltage magnitude, a voltage controlled blocking of the function is available, that is, if the voltage is lower than the set blocking voltage IntBlockLevel the function is blocked and no PICKUP or TRIP signal is issued.
9.1.2.1
Measurement principle
The fundamental frequency of the measured input voltage is measured continuously, and compared with the set value, PUFrequency. The frequency function is dependent on the voltage magnitude. If the voltage magnitude decreases the setting IntBlockLevel, SAPTUF (81) gets blocked, and the output BLKDMAGN is issued. All voltage settings are made in percent of the setting VBase, which should be set as a phase-phase voltage in kV. To avoid oscillations of the output PICKUP signal, a hysteresis has been included.
9.1.2.2
Time delay
The time delay for underfrequency protection SAPTUF (81) can be either a settable definite time delay or a voltage magnitude dependent time delay, where the time delay depends on the voltage level; a high voltage level gives a longer time delay and a low voltage level causes a short time delay. For the definite time delay, the setting TimeDlyOperate sets the time delay. For the voltage dependent time delay the measured voltage level and the settings VNom, VMin, Exponent, t_MaxTripDelay and t_MinTripDelay set the time delay according to figure 213 and equation 128. The setting TimerOperation is used to decide what type of time delay to apply. Trip signal issuing requires that the underfrequency condition continues for at least the user set time delay TimeDlyOperate. If the PICKUP condition, with respect to the measured frequency ceases during this user set delay time, and is not fulfilled again within a user defined reset time, TimeDlyReset, the PICKUP output is reset, after that the defined reset time has elapsed. Here it should be noted that after leaving the hysteresis area, the PICKUP condition must be fulfilled again and it is not sufficient for the signal to only return back to the hysteresis area. On the output of SAPTUF (81) a 100ms pulse is issued, after a time delay corresponding to the setting of TimeDlyRestore, when the measured frequency returns to the level corresponding to the setting RestoreFreq.
9.1.2.3
Exponent
EQUATION1559 V1 EN
(Equation 128)
where: t V Exponent VMin, VNom is the voltage dependent time delay (at constant voltage), is the measured voltage is a setting, are voltage settings corresponding to
0
TimeDlyOperate [s]
Exponenent 3
0.5
1 2
90
95
100
V [% of VBase]
en05000075_ansi.vsd
ANSI05000075 V1 EN
Figure 213:
Voltage dependent inverse time characteristics for underfrequency protection SAPTUF (81). The time delay to operate is plotted as a function of the measured voltage, for the Exponent = 0, 1, 2, 3, 4 respectively.
9.1.2.4
Blocking
It is possible to block underfrequency protection SAPTUF (81) partially or completely, by binary input signals or by parameter settings, where:
BLOCK: BLKTRIP: BLKREST: blocks all outputs blocks the TRIP output blocks the RESTORE output
If the measured voltage level decreases below the setting of IntBlockLevel, both the PICKUP and the TRIP outputs, are blocked.
9.1.2.5
Design
The frequency measuring element continuously measures the frequency of the positive sequence voltage and compares it to the setting PUFrequency. The frequency signal is filtered to avoid transients due to switchings and faults. The time integrator can operate either due to a definite delay time or to the special voltage dependent delay time. When the frequency has returned back to the setting of RestoreFreq, the RESTORE output is issued after the time delay TimeDlyRestore. The design of underfrequency protection SAPTUF (81) is schematically described in figure 214.
Voltage
Time integrator TimerOperation Mode Selector TimeDlyOperate TimeDlyReset PICKUP TRIP Pickup & Trip Output Logic PICKUP
Frequency
TRIP
en05000726_ansi.vsd
ANSI05000726 V1 EN
Figure 214:
9.1.3
Function block
SAPTUF (81) V3P* BLOCK BLKTRIP BLKREST TRIP PICKUP RESTORE BLKDMAGN FREQ ANSI06000279-2-en.vsd
ANSI06000279 V2 EN
Figure 215:
9.1.4
Table 229:
Name TRIP PICKUP RESTORE BLKDMAGN FREQ
9.1.5
Table 230:
Name Operation Vbase PUFrequency IntBlockLevel TimeDlyOperate TimeDlyReset TimeDlyRestore RestoreFreq TimerOperation VNom VMin Exponent t_MaxTripDelay t_MinTripDelay
Setting parameters
SAPTUF (81) Group settings (basic)
Values (Range) Disabled Enabled 0.05 - 2000.00 35.00 - 75.00 0 - 100 0.000 - 60.000 0.000 - 60.000 0.000 - 60.000 45.00 - 65.00 Definite timer Volt based timer 50 - 150 50 - 150 0.0 - 5.0 0.010 - 60.000 0.010 - 60.000 Unit kV Hz %VB s s s Hz %VB %VB s s Step 0.05 0.01 1 0.001 0.001 0.001 0.01 1 1 0.1 0.001 0.001 Default Disabled 400.00 48.80 50 0.200 0.000 0.000 50.10 Definite timer 100 90 1.0 1.000 1.000 Description Disable/Enable Operation Base voltage Frequency setting pickup value. Internal blocking level in % of VBase. Operate time delay in over/under-frequency mode. Time delay for reset. Restore time delay. Restore frequency if frequency is above frequency value. Setting for choosing timer mode. Nominal voltage in % of VBase for voltage based timer. Lower operation limit in % of VBase for voltage based timer. For calculation of the curve form for voltage based timer. Maximum time operation limit for voltage based timer. Minimum time operation limit for voltage based timer.
9.1.6
Exponent
EQUATION1559 V1 EN
(Equation 129)
V=Vmeasured
9.2
f>
SYMBOL-O V1 EN
Overfrequency protection function SAPTOF (81) is applicable in all situations, where reliable detection of high fundamental power system frequency is needed. Overfrequency occurs because of sudden load drops or shunt faults in the power network. Close to the generating plant, generator governor problems can also cause over frequency. SAPTOF (81) is used mainly for generation shedding and remedial action schemes. It is also used as a frequency stage initiating load restoring. SAPTOF (81) is provided with an undervoltage blocking. The operation is based on positive sequence voltage measurement and requires two phasephase or three phase-neutral voltages to be connected. For information about how to connect analog inputs, refer to Application manual/IED application/Analog inputs/ Setting guidelines
9.2.2
Principle of operation
Overfrequency protection SAPTOF (81) is used to detect high power system frequency. SAPTOF (81) has a settable definite time delay. If the frequency remains above the set value for a time period corresponding to the chosen time delay, the corresponding TRIP signal is issued. To avoid an unwanted TRIP due to uncertain frequency measurement at low voltage magnitude, a voltage controlled blocking of the function is available from the preprocessing function, that is, if the voltage is lower than the set blocking voltage in the preprocessing function, the function is blocked and no PICKUP or TRIP signal is issued.
9.2.2.1
Measurement principle
The fundamental frequency of the positive sequence voltage is measured continuously, and compared with the set value, PUFrequency. Overfrequency protection SAPTOF (81) is dependent on the voltage magnitude. If the voltage magnitude decreases below the setting IntBlockLevel, SAPTOF (81) is blocked, and the output BLKDMAGN is issued. All voltage settings are made in percent of the VBase, which should be set as a phase-phase voltage in kV. To avoid oscillations of the output PICKUP signal, a hysteresis has been included.
9.2.2.2
Time delay
The time delay for Overfrequency protection SAPTOF (81) is a settable definite time delay, specified by the setting TimeDlyOperate.
TRIP signal issuing requires that the overfrequency condition continues for at least the user set time delay, TimeDlyReset. If the PICKUP condition, with respect to the measured frequency ceases during this user set delay time, and is not fulfilled again within a user defined reset time, TimeDlyReset, the PICKUP output is reset, after that the defined reset time has elapsed. It is to be noted that after leaving the hysteresis area, the PICKUP condition must be fulfilled again and it is not sufficient for the signal to only return back to the hysteresis area.
9.2.2.3
Blocking
It is possible to block overfrequency protection SAPTOF (81) partially or completely, by binary input signals or by parameter settings, where:
BLOCK: BLKTRIP: blocks all outputs blocks the TRIP output
If the measured voltage level decreases below the setting of IntBlockLevel, both the PICKUP and the TRIP outputs, are blocked.
9.2.2.4
Design
The frequency measuring element continuously measures the frequency of the positive sequence voltage and compares it to the setting PUFrequency. The frequency signal is filtered to avoid transients due to switchings and faults in the power system. The time integrator operates due to a definite delay time. The design of overfrequency protection SAPTOF (81) is schematically described in figure 216.
Voltage
PICKUP
Frequency
en05000735_ansi.vsd
ANSI05000735 V1 EN
Figure 216:
9.2.3
Function block
SAPTOF (81) V3P* BLOCK BLKTRIP TRIP PICKUP BLKDMAGN FREQ ANSI06000280-2-en.vsd
ANSI06000280 V2 EN
Figure 217:
9.2.4
Table 233:
Name TRIP PICKUP BLKDMAGN FREQ
9.2.5
Table 234:
Name Operation VBase PUFrequency IntBlockLevel TimeDlyOperate TimeDlyReset
Setting parameters
SAPTOF (81) Group settings (basic)
Values (Range) Disabled Enabled 0.05 - 2000.00 35.00 - 75.00 0 - 100 0.000 - 60.000 0.000 - 60.000 Unit kV Hz %VB s s Step 0.05 0.01 1 0.001 0.001 Default Disabled 400.00 51.20 50 0.000 0.000 Description Disable/Enable Operation Base voltage Frequency setting pickup value. Internal blocking level in % of VBase. Operate time delay in over/under-frequency mode. Time delay for reset.
9.2.6
Technical data
Table 235:
Function Operate value, pickup function
Operate time, pickup function Reset time, pickup function Operate time, definite time function Reset time, definite time function
100 ms typically at fset -0.5 Hz to fset +0.5 Hz 100 ms typically (0.000-60.000)s (0.000-60.000)s
9.3
9.3.1
Introduction
Rate-of-change frequency protection function (SAPFRC,81) gives an early indication of a main disturbance in the system. SAPFRC (81) can be used for generation shedding, load shedding and remedial action schemes. SAPFRC (81) can discriminate between positive or negative change of frequency. SAPFRC (81) is provided with an undervoltage blocking. The operation is based on positive sequence voltage measurement and requires two phase-phase or three phaseneutral voltages to be connected. For information about how to connect analog inputs, refer to Application manual/IED application/Analog inputs/Setting guidelines.
9.3.2
Principle of operation
Rate-of-change frequency protection SAPFRC (81) is used to detect fast power system frequency changes, increase as well as, decrease at an early stage. SAPFRC (81) has a settable definite time delay. If the rate-of-change of frequency remains below the set value, for negative rate-of-change, for a time period equal to the chosen time delay, the TRIP signal is issued. If the rate-of-change of frequency remains above the set value, for positive rate-of-change, for a time period equal to the chosen time delay, the TRIP signal is issued. To avoid an unwanted TRIP due to uncertain frequency measurement at low voltage magnitude, a voltage controlled blocking of the function is available, that is if the voltage is lower than the set blocking voltage IntBlockLevel, the function is blocked and no PICKUP or TRIP signal is issued. If the frequency recovers, after a frequency decrease, a restore signal is issued.
9.3.2.1
Measurement principle
The rate-of-change of the fundamental frequency of the selected voltage is measured continuously, and compared with the set value, PUFreqGrad. Rate-of-change frequency protection SAPFRC (81) is also dependent on the voltage magnitude. If the voltage magnitude decreases below the setting IntBlockLevel, SAPFRC (81) is blocked, and the output BLKDMAGN is issued. The sign of the setting PUFreqGrad, controls if SAPFRC (81) reacts on a positive or on a negative change in frequency. If SAPFRC (81) is used for decreasing frequency that is, the setting PUFreqGrad has been given a negative value, and a trip signal has been issued, then a 100 ms pulse is
issued on the RESTORE output, when the frequency recovers to a value higher than the setting RestoreFreq. A positive setting of PUFreqGrad, sets SAPFRC (81) to PICKUP and TRIP for frequency increases. To avoid oscillations of the output PICKUP signal, a hysteresis has been included.
9.3.2.2
Time delay
Rate-of-change frequency protection SAPFRC (81) has a settable definite time delay, tTrip. . Trip signal issuing requires that the rate-of-change of frequency condition continues for at least the user set time delay, tTrip. If the PICKUP condition, with respect to the measured frequency ceases during the delay time, and is not fulfilled again within a user defined reset time, tReset, the PICKUP output is reset, after that the defined reset time has elapsed. Here it should be noted that after leaving the hysteresis area, the PICKUP condition must be fulfilled again and it is not sufficient for the signal to only return back into the hysteresis area. The RESTORE output of SAPFRC (81) is set, after a time delay equal to the setting of tRestore, when the measured frequency has returned to the level corresponding to RestoreFreq, after an issue of the TRIP output signal. If tRestore is set to 0.000 s the restore functionality is disabled, and no output will be given. The restore functionality is only active for lowering frequency conditions and the restore sequence is disabled if a new negative frequency gradient is detected during the restore period, defined by the settings RestoreFreq and tRestore.
9.3.2.3
Blocking
Rate-of-change frequency protection (SAPFRC, 81) can be partially or totally blocked, by binary input signals or by parameter settings, where:
BLOCK: BLKTRIP: BLKREST: blocks all outputs blocks the TRIP output blocks the RESTORE output
If the measured voltage level decreases below the setting of IntBlockLevel, both the PICKUP and the TRIP outputs, are blocked.
9.3.2.4
Design
Rate-of-change frequency protection (SAPFRC, 81) measuring element continuously measures the frequency of the selected voltage and compares it to the setting
471
PUFreqGrad. The frequency signal is filtered to avoid transients due to power system switchings and faults. The time integrator operates with a definite delay time. When the frequency has returned back to the setting of RestoreFreq, the RESTORE output is issued after the time delay tRestore, if the TRIP signal has earlier been issued. The sign of the setting PUFreqGrad is essential, and controls if the function is used for raising or lowering frequency conditions. The design of SAPFRC (81) is schematically described in figure 218.
BLOCK BLKTRIP BLKRESET OR Comparator V < IntBlockLevel Pickup & Trip Output Logic BLOCK
Voltage
BLKDMAGN
Rate-of-Change of Frequency
Comparator If [PickupFreqGrad<0 PICKUP AND df/dt < PickupFreqGrad] OR [PickupFreqGrad>0 AND df/dt > PickupFreqGrad] Then PICKUP
PICKUP
TRIP
en05000835_ansi.vsd
ANSI05000835 V1 EN
Figure 218:
9.3.3
Figure 219:
9.3.4
Table 237:
Name TRIP PICKUP RESTORE BLKDMAGN
9.3.5
Table 238:
Name Operation VBase PUFreqGrad IntBlockLevel tTrip
Setting parameters
SAPFRC (81) Group settings (basic)
Values (Range) Disabled Enabled 0.05 - 2000.00 -10.00 - 10.00 0 - 100 0.000 - 60.000 Unit kV Hz/s %VB s Step 0.05 0.01 1 0.001 Default Disabled 400.00 0.50 50 0.200 Description Disable/Enable Operation Base setting for the phase-phase voltage in kV Frequency gradient start value. Sign defines direction. Internal blocking level in % of VBase. Operate time delay in pos./neg. frequency gradient mode.
Restore frequency if frequency is above frequency value (Hz) Restore time delay. Time delay for reset.
9.3.6
Technical data
Table 239:
Function Operate value, pickup function Operate value, internal blocking level Operate time, pickup function
Section 10
Multipurpose protection
10.1
10.1.1
Introduction
The protection module is recommended as a general backup protection with many possible application areas due to its flexible measuring and setting facilities. The built-in overcurrent protection feature has two settable current pickups. Both of them can be used either with definite time or inverse time characteristic. The overcurrent protection steps can be made directional with selectable voltage polarizing quantity. Additionally they can be voltage and/or current controlled/restrained. 2nd harmonic restraining facility is available as well. At too low polarizing voltage the overcurrent feature can be either blocked, made non directional or ordered to use voltage memory in accordance with a parameter setting. Additionally two overvoltage and two undervoltage steps, either with definite time or inverse time characteristic, are available within each function. The general function suits applications with underimpedance and voltage controlled overcurrent solutions. The general function can also be utilized for generator transformer protection applications where positive, negative or zero sequence components of current and voltage quantities are typically required. Additionally, generator applications such as loss of field, inadvertent energizing, stator or rotor overload, circuit breaker head flash-over and open phase detection are just a few of possible protection arrangements with these functions.
When the generator is taken out of service, and stand-still, there is a risk that the generator circuit breaker flashes over or is closed by mistake. To prevent damages on the generator or turbine, it is essential that high speed tripping is provided in case of inadvertent energization of the generator. This tripping should be almost instantaneous (< 100 ms). There is a risk that the current into the generator at inadvertent energization will be limited so that the normal overcurrent or underimpedance protection will not detect the dangerous situation. The delay of these protection functions might be too long. For big and important machines, fast protection against inadvertent energizing should, therefore, be included in the protective scheme.
10.1.2
10.1.2.1
Principle of operation
Measured quantities within CVGAPC
General current and voltage protection (CVGAPC) function is always connected to threephase current and three-phase voltage input in the configuration tool, but it will always measure only one current and one voltage quantity selected by the end user in the setting tool. The user can select to measure one of the current quantities shown in table 240.
Table 240: Current selection for CVGAPC function
Comment CVGAPC function will measure the phase A current phasor CVGAPC function will measure the phase B current phasor CVGAPC function will measure the phase C current phasor CVGAPC function will measure internally calculated positive sequence current phasor CVGAPC function will measure internally calculated negative sequence current phasor CVGAPC function will measure internally calculated zero sequence current phasor multiplied by factor 3 CVGAPC function will measure current phasor of the phase with maximum magnitude CVGAPC function will measure current phasor of the phase with minimum magnitude
CurrentInput
1 2 3 4 5 6 7 8 PhaseA PhaseB PhaseC PosSeq NegSeq 3ZeroSeq MaxPh MinPh
CurrentInput
9
Comment CVGAPC function will measure magnitude of unbalance current, which is internally calculated as the algebraic magnitude difference between the current phasor of the phase with maximum magnitude and current phasor of the phase with minimum magnitude. Phase angle will be set to 0 all the time CVGAPC function will measure the current phasor internally calculated as the vector difference between the phase A current phasor and phase B current phasor (IA-IB) CVGAPC function will measure the current phasor internally calculated as the vector difference between the phase B current phasor and phase C current phasor (IB-IC) CVGAPC function will measure the current phasor internally calculated as the vector difference between the phase C current phasor and phase L1 current phasor ( IC-IA) CVGAPC function will measure ph-ph current phasor with the maximum magnitude CVGAPC function will measure ph-ph current phasor with the minimum magnitude CVGAPC function will measure magnitude of unbalance current, which is internally calculated as the algebraic magnitude difference between the phph current phasor with maximum magnitude and ph-ph current phasor with minimum magnitude. Phase angle will be set to 0 all the time
UnbalancePh
10
PhaseA-PhaseB
11
PhaseB-PhaseC
12
PhaseC-PhaseA
13 14 15
The user can select to measure one of the voltage quantities shown in table 241:
Table 241: Voltage selection for CVGAPC function
Comment CVGAPC function will measure the phase A voltage phasor CVGAPC function will measure the phase B voltage phasor CVGAPC function will measure the phase C voltage phasor CVGAPC function will measure internally calculated positive sequence voltage phasor CVGAPC function will measure internally calculated negative sequence voltage phasor. This voltage phasor will be intentionally rotated for 180 in order to enable easier settings for the directional feature when used. CVGAPC function will measure internally calculated zero sequence voltage phasor multiplied by factor 3. This voltage phasor will be intentionally rotated for 180 in order to enable easier settings for the directional feature when used. CVGAPC function will measure voltage phasor of the phase with maximum magnitude
VoltageInput
1 2 3 4 5 PhaseA PhaseB PhaseC PosSeq -NegSeq
-3ZeroSeq
MaxPh
VoltageInput
8 9 MinPh
Comment CVGAPC function will measure voltage phasor of the phase with minimum magnitude CVGAPC function will measure magnitude of unbalance voltage, which is internally calculated as the algebraic magnitude difference between the voltage phasor of the phase with maximum magnitude and voltage phasor of the phase with minimum magnitude. Phase angle will be set to 0 all the time CVGAPC function will measure the voltage phasor internally calculated as the vector difference between the phase A voltage phasor and phase B voltage phasor (VA-VB) CVGAPC function will measure the voltage phasor internally calculated as the vector difference between the phase B voltage phasor and phase C voltage phasor (VB-VC) CVGAPC function will measure the voltage phasor internally calculated as the vector difference between the phase C voltage phasor and phase A voltage phasor ( VC-VA) CVGAPC function will measure ph-ph voltage phasor with the maximum magnitude CVGAPC function will measure ph-ph voltage phasor with the minimum magnitude CVGAPC function will measure magnitude of unbalance voltage, which is internally calculated as the algebraic magnitude difference between the phph voltage phasor with maximum magnitude and ph-ph voltage phasor with minimum magnitude. Phase angle will be set to 0 all the time
UnbalancePh
10
PhaseA-PhaseB
11
PhaseB-PhaseC
12
PhaseC-PhaseA
13 14 15
It is important to notice that the voltage selection from table 241 is always applicable regardless the actual external VT connections. The three-phase VT inputs can be connected to IED as either three phase-to-ground voltages VA, VB & VC or three phaseto-phase voltages VAB, VBC & VCA). This information about actual VT connection is entered as a setting parameter for the pre-processing block, which will then take automatic care about it. The user can select one of the current quantities shown in table 242 for built-in current restraint feature:
Table 242:
Set value for the parameter RestrCurr 1 2 3 4 PosSeq NegSeq 3ZeroSeq MaxPh
10.1.2.2
Base voltage shall be entered as: 1. 2. rated phase-to-ground voltage of the protected object in primary kV, when the measured Voltage Quantity is selected from 1 to 9, as shown in table 241. rated phase-to-phase voltage of the protected object in primary kV, when the measured Voltage Quantity is selected from 10 to 15, as shown in table 241.
10.1.2.3
Pickup signal will only come if all of the enabled built-in features in the overcurrent step are fulfilled at the same time. The overcurrent protection step can be restrained by a second harmonic component in the measured current quantity (see table 240). However it shall be noted that this feature is not applicable when one of the following measured currents is selected: PosSeq (positive sequence current) NegSeq (negative sequence current) UnbalancePh (unbalance phase current) UnbalancePh-Ph (unbalance ph-ph current)
This feature will simple prevent overcurrent step pickup if the second-to-first harmonic ratio in the measured current exceeds the set level.
Directional feature
The overcurrent protection step operation can be can be made dependent on the relevant phase angle between measured current phasor (see table 240) and measured voltage phasor (see table 241). In protection terminology it means that the General currrent and voltage protection (CVGAPC) function can be made directional by enabling this built-in feature. In that case overcurrent protection step will only operate if the current flow is in accordance with the set direction (Forward, which means towards the protected object, or Reverse, which means from the protected object). For this feature it is of the outmost importance to understand that the measured voltage phasor (see table 241) and measured current phasor (see table 240) will be used for directional decision. Therefore it is the sole responsibility of the end user to select the appropriate current and voltage signals in order to get a proper directional decision. CVGAPC function will NOT do this automatically. It will just simply use the current and voltage phasors selected by the end user to check for the directional criteria. Table 243 gives an overview of the typical choices (but not the only possible ones) for these two quantities for traditional directional relays.
Table 243:
Set value for the parameter
CurrentInput
PosSeq
VoltageInput
PosSeq
NegSeq
-NegSeq
3ZeroSeq
-3ZeroSeq
Unbalance current or voltage measurement shall not be used when the directional feature is enabled. Two types of directional measurement principles are available, I & V and IcosPhi&V. The first principle, referred to as "I & V" in the parameter setting tool, checks that: the magnitude of the measured current is bigger than the set pick-up level the phasor of the measured current is within the operating region (defined by the relay operate angle, ROADir parameter setting; see figure 220).
V=-3V0
en05000252_anis.vsd
IEC05000252-ANIS V1 EN
Figure 220:
where:
The second principle, referred to as "IcosPhi&V" in the parameter setting tool, checks that: that the product Icos() is bigger than the set pick-up level, where is angle between the current phasor and the mta line that the phasor of the measured current is within the operating region (defined by the Icos() straight line and the relay operate angle, ROADir parameter setting; see figure 220).
V=-3V0
en05000253_ansi.vsd
ANSI05000253 V1 EN
Figure 221:
where:
Note that it is possible to decide by a parameter setting how the directional feature shall behave when the magnitude of the measured voltage phasor falls below the preset value. User can select one of the following three options: Non-directional (operation allowed for low magnitude of the reference voltage) Block (operation prevented for low magnitude of the reference voltage) Memory (memory voltage shall be used to determine direction of the current)
It shall also be noted that the memory duration is limited in the algorithm to 100 ms. After that time the current direction will be locked to the one determined during memory time and it will re-set only if the current fails below set pickup level or voltage goes above set voltage memory limit.
The overcurrent protection step operation can be can be made dependent of a measured voltage quantity (see table 241). Practically then the pickup level of the overcurrent step is not constant but instead decreases with the decrease in the magnitude of the measured voltage quantity. Two different types of dependencies are available: Voltage restraint overcurrent (when setting parameter VDepMode_OC1=Slope)
PickupCurr_OC1
VDepFact_OC1 * PickupCurr_OC1
VLowLimit_OC1
VHighLimit_OC1
ANSI05000324 V1 EN
Figure 222:
Example for OC1 step current pickup level variation as function of measured voltage magnitude in Slope mode of operation
PickupCurr_OC1
VDepFact_OC1 * PickupCurr_OC1
VHighLimit_OC1
ANSI05000323 V1 EN
Figure 223:
Example for OC1 step current pickup level variation as function of measured voltage magnitude in Step mode of operation
This feature will simply change the set overcurrent pickup level in accordance with magnitude variations of the measured voltage. It shall be noted that this feature will as well affect the pickup current value for calculation of operate times for IDMT curves (overcurrent with IDMT curve will operate faster during low voltage conditions).
484 Technical reference manual
The overcurrent protection step operation can be made dependent of a restraining current quantity (see table 242). Practically then the pickup level of the overcurrent step is not constant but instead increases with the increase in the magnitude of the restraining current.
IMeasured
te ra
ea ar
pe O
IsetHigh
ff oe trC s e I>R
tr es *I r
ain
IsetLow
atan(RestrCoeff) Restraint
en05000255.vsd
IEC05000255 V1 EN
Figure 224:
This feature will simply prevent overcurrent step to pickup if the magnitude of the measured current quantity is smaller than the set percentage of the restrain current magnitude. However this feature will not affect the pickup current value for calculation of operate times for IDMT curves. This means that the IDMT curve operate time will not be influenced by the restrain current magnitude. When set, the pickup signal will start definite time delay or inverse (IDMT) time delay in accordance with the end user setting. If the pickup signal has value one for longer time than the set time delay, the overcurrent step will set its trip signal to one. Reset of the pickup and trip signal can be instantaneous or time delay in accordance with the end user setting.
10.1.2.4
time than the set time delay the undercurrent step will set its trip signal to one. Reset of the pickup and trip signal can be instantaneous or time delay in accordance with the setting.
10.1.2.5
10.1.2.6
10.1.2.7
S R
Q Q
ANSI10000028-1-en.vsd
ANSI10000028 V1 EN
Figure 225:
The setting of the general current and voltage function (typical values) is done as shown in table 244.
Table 244: The setting of the general current and voltage function
Measured Quantity UndervoltagePickup Overvoltage Pickup OvercurrentPickup Maximum generator Phase to Phase voltage Maximum generator Phase to Phase voltage Maximum generator Phase current Pickup in % of generator rating < 70% > 85% > 50% Time delay in seconds 10.0 s 1.0 s 0.05 s
In normal operation the overvoltage trip signal is activated and the undervotage trip signal is deactivated. This means that the overcurrent function is blocked.
When the generator is taken out of service the generator voltage gets low. The overvoltage trip signal will be deactivated and the undervoltage trip signal will be activated after the set delay. At this moment the block signal to the overcurrent function will be deactivated. It the generator is energized at stand still conditions, that is, when the voltage is zero, the overcurrent function will operate after the short set delay if the generator current is larger than the set value. When the generator is started the overvoltage trip signal will be activated the set time delay after the moment when the voltage has reached the set value. At this moment the blocking of the overcurrent function is activated. The delay of the undervoltage function will prevent false operation at short circuits in the external power grid.
10.1.2.8
Logic diagram
The simplified internal logics, for CVGAPC function are shown in the following figures.
IED
ADM CVGAPC function
Current and voltage selection settings
52
Selection of which current and voltage shall be given to the built-in protection elements
ANSI05000169_2_en.vsd
ANSI05000169 V2 EN
Figure 226:
Figure 226 shows how internal treatment of measured currents is done for multipurpose protection function The following currents and voltages are inputs to the multipurpose protection function. They must all be expressed in true power system (primary) Amperes and kilovolts. 1. 2. 3. Instantaneous values (samples) of currents & voltages from one three-phase current and one three-phase voltage input. Fundamental frequency phasors from one three-phase current and one three-phase voltage input calculated by the pre-processing modules. Sequence currents & voltages from one three-phase current and one three-phase voltage input calculated by the pre-processing modules.
The multipurpose protection function: 1. 2. 3. Selects one current from the three-phase input system (see table 240) for internally measured current. Selects one voltage from the three-phase input system (see table 241) for internally measured voltage. Selects one current from the three-phase input system (see table 242) for internally measured restraint current.
CURRENT
UC1 2
Selected current
nd
Harmonic restraint
TRUC1
UC2 nd 2 Harmonic restraint OC1 2nd Harmonic restraint Current restraint Directionality Voltage control / restraint OR
PU_UC2 TRUC2
OC2 2nd Harmonic restraint Current restraint Directionality Voltage control / restraint OR
PU_OC2 TROC2
VDIRLOW DIROC2
PU_OV1
OV1
TROV1 PU_OV2
OV2
Selected voltage
TROV2 PU_UV1
UV1
TRUV1 PU_UV2
UV2
TRUV2
VOLTAGE
490
en05000170_ansi.vsd
Figure 227:
Logic in figure 227 can be summarized as follows: 1. 2. 3. The selected currents and voltage are given to built-in protection elements. Each protection element and step makes independent decision about status of its PICKUP and TRIP output signals. More detailed internal logic for every protection element is given in the following four figures Common PICKUP and TRIP signals from all built-in protection elements & steps (internal OR logic) are available from multipurpose function as well.
NOT
0-DEF 0
OR
BLKTROC1
AND
TROC1
Selected current
a b
a>b
OC1=On BLKOC1
PickupCurr_OC1
AND
PU_OC1
Inverse Voltage control or restraint feature Directionality check DIR_OK Inverse time selected
Selected voltage
en05000831_ansi.vsd
ANSI05000831 V1 EN
Figure 228:
Simplified internal logic diagram for built-in first overcurrent step that is, OC1 (step OC2 has the same internal logic)
Selected current
a b
b>a
PickupCurr_UC1
AND
0-DEF 0
AND
TRUC1
PU_UC1
en05000750_ansi.vsd
ANSI05000750 V1 EN
Figure 229:
Simplified internal logic diagram for built-in first undercurrent step that is, UC1 (step UC2 has the same internal logic)
0-DEF 0
BLKTROV1
AND
TROV1
OR
PU_OV1
a>b
PickupVolt_OV1
AND
Inverse
en05000751_ansi.vsd
ANSI05000751 V1 EN
Figure 230:
Simplified internal logic diagram for built-in first overvoltage step OV1 (step OV2 has the same internal logic)
0-DEF 0 OR
BLKTRUV1
AND
TRUV1
b>a
PickupVolt_UV1
AND Inverse
PU_UV1
en05000752_ansi.vsd
ANSI05000752 V1 EN
Figure 231:
Simplified internal logic diagram for built-in first undervoltage step UV1 (step UV2 has the same internal logic)
10.1.3
Function block
CVGAPC I3P* V3P* BLOCK BLKOC1 BLKOC1TR ENMLTOC1 BLKOC2 BLKOC2TR ENMLTOC2 BLKUC1 BLKUC1TR BLKUC2 BLKUC2TR BLKOV1 BLKOV1TR BLKOV2 BLKOV2TR BLKUV1 BLKUV1TR BLKUV2 BLKUV2TR TRIP TROC1 TROC2 TRUC1 TRUC2 TROV1 TROV2 TRUV1 TRUV2 PICKUP PU_OC1 PU_OC2 PU_UC1 PU_UC2 PU_OV1 PU_OV2 PU_UV1 PU_UV2 BLK2ND DIROC1 DIROC2 VDIRLOW CURRENT ICOSFI VOLTAGE VIANGLE
ANSI05000372-2-en.vsd
ANSI05000372 V2 EN
Figure 232:
Table 246:
Name TRIP TROC1 TROC2 TRUC1 TRUC2 TROV1 TROV2
10.1.5
Table 247:
Name Operation CurrentInput
Setting parameters
CVGAPC Group settings (basic)
Values (Range) Disabled Enabled Phase A Phase B Phase C PosSeq NegSeq 3*ZeroSeq MaxPh MinPh UnbalancePh Phase AB Phase BC Phase CA MaxPh-Ph MinPh-Ph UnbalancePh-Ph 1 - 99999 Unit Step Default Disabled MaxPh Description Disable/Enable Operation Select current signal which will be measured inside function
IBase
3000
Base Current
kV % -
0.05 1.0 -
Base Voltage Disable/Enable operation of 2nd harmonic restrain Ratio of second to fundamental current harmonic in % Disable/Enable current restrain function Select current signal which will be used for current restrain
Restraining current coefficient Relay Characteristic Angle Relay Operate Angle Below this level in % of Vbase setting ActLowVolt takes over Disable/Enable Operation of OC1 Pickup current for OC1 in % of Ibase
Name CurveType_OC1
s %IB s -
Independent (definitive) time delay of OC1 Time multiplier for the dependent time delay for OC1 Minimum operate current for step1in% of IBase Minimum operate time for IEC IDMT curves for OC1 Control mode for voltage controlled OC1 function
%VB %VB -
Voltage dependent mode OC1 (step, slope) Multiplying factor for current pickup when OC1 is voltage dependent Voltage low limit setting OC1 in % of Vbase Voltage high limit setting OC1 in % of Vbase Enable block of OC1 by 2nd harmonic restrain Directional mode of OC1 (nondir, forward,reverse) Measuring on IandV or IcosPhiandV for OC1 Low voltage level action for Dir_OC1 (Nodir, Blk, Mem) Disable/Enable Operation od OC2 Pickup current for OC2 in % of Ibase
DirPrinc_OC1 ActLowVolt1_VM
I&V Non-directional
Operation_OC2 PickupCurr_OC2
%IB
1.0
Disabled 120.0
s %IB s -
Independent (definitive) time delay of OC2 Time multiplier for the dependent time delay for OC2 Minimum operate current for step2 in % of IBase Minimum operate time for IEC IDMT curves for OC2 Control mode for voltage controlled OC2 function
%VB %VB -
Voltage dependent mode OC2 (step, slope) Multiplying factor for current pickup when OC2 is voltage dependent Voltage low limit setting OC2 in % of Vbase Voltage high limit setting OC2 in % of Vbase Enable block of OC2 by 2nd harmonic restrain Directional mode of OC2 (nondir, forward,reverse) Measuring on IandV or IcosPhiandV for OC2 Low voltage level action for Dir_OC2 (Nodir, Blk, Mem) Disable/Enable operation of UC1 Enable internal low current level blocking for UC1
DirPrinc_OC2 ActLowVolt2_VM
I&V Non-directional
Operation_UC1 EnBlkLowI_UC1
Disabled Disabled
Name BlkLowCurr_UC1 PickupCurr_UC1 tDef_UC1 tResetDef_UC1 HarmRestr_UC1 Operation_UC2 EnBlkLowI_UC2 BlkLowCurr_UC2 PickupCurr_UC2 tDef_UC2 HarmRestr_UC2 Operation_OV1 PickupVolt_OV1 CurveType_OV1
s s %VB -
Operate time delay in sec for definite time use of OV1 Minimum operate time for Inverse-Time curves for OV1 Time multiplier for the dependent time delay for OV1 Disable/Enable operation of OV2 Pickup voltage for OV2 in % of Vbase Selection of time delay curve type for OV2
tDef_OV2 tMin_OV2
s s
0.01 0.01
1.00 0.05
Operate time delay in sec for definite time use of OV2 Minimum operate time for Inverse-Time curves for OV2
Time multiplier for the dependent time delay for OV2 Disable/Enable operation of UV1 Operate undervoltage level for UV1 in % of Vbase Selection of time delay curve type for UV1
s s %VB %VB -
Operate time delay in sec for definite time use of UV1 Minimum operate time for Inverse-Time curves for UV1 Time multiplier for the dependent time delay for UV1 Enable internal low voltage level blocking for UV1 Internal low voltage blocking level for UV1 in % of Vbase Disable/Enable operation of UV2 Pickup undervoltage for UV2 in % of Vbase Selection of time delay curve type for UV2
s s %VB
Operate time delay in sec for definite time use of UV2 Minimum operate time for Inverse-Time curves for UV2 Time multiplier for the dependent time delay for UV2 Enable internal low voltage level blocking for UV2 Internal low voltage blocking level for UV2 in % of Vbase
Table 248:
Name MultPU_OC1
ResCrvType_OC1
tResetDef_OC1 P_OC1 A_OC1 B_OC1 C_OC1 PR_OC1 TR_OC1 CR_OC1 MultPU_OC2 ResCrvType_OC2
s -
0.00 0.020 0.140 0.000 1.000 0.500 13.500 1.0 2.0 Instantaneous
Reset time delay used in IEC Definite Time curve OC1 Parameter P for customer programmable curve for OC1 Parameter A for customer programmable curve for OC1 Parameter B for customer programmable curve for OC1 Parameter C for customer programmable curve for OC1 Parameter PR for customer programmable curve for OC1 Parameter TR for customer programmable curve for OC1 Parameter CR for customer programmable curve for OC1 Multiplier for scaling the current setting value for OC2 Selection of reset curve type for OC2
s s
Reset time delay used in IEC Definite Time curve OC2 Parameter P for customer programmable curve for OC2 Parameter A for customer programmable curve for OC2 Parameter B for customer programmable curve for OC2 Parameter C for customer programmable curve for OC2 Parameter PR for customer programmable curve for OC2 Parameter TR for customer programmable curve for OC2 Parameter CR for customer programmable curve for OC2 Reset time delay used in IEC Definite Time curve UC2
s s -
Reset time delay in sec for definite time use of OV1 Reset time delay in sec for Inverse-Time curves for OV1 Parameter A for customer programmable curve for OV1 Parameter B for customer programmable curve for OV1 Parameter C for customer programmable curve for OV1 Parameter D for customer programmable curve for OV1 Parameter P for customer programmable curve for OV1 Selection of reset curve type for OV2
s s -
Reset time delay in sec for definite time use of OV2 Reset time delay in sec for Inverse-Time curves for OV2 Parameter A for customer programmable curve for OV2 Parameter B for customer programmable curve for OV2 Parameter C for customer programmable curve for OV2 Parameter D for customer programmable curve for OV2 Parameter P for customer programmable curve for OV2 Selection of reset curve type for UV1
s s -
Reset time delay in sec for definite time use of UV1 Reset time delay in sec for Inverse-Time curves for UV1 Parameter A for customer programmable curve for UV1 Parameter B for customer programmable curve for UV1
s s -
Reset time delay in sec for definite time use of UV2 Reset time delay in sec for Inverse-Time curves for UV2 Parameter A for customer programmable curve for UV2 Parameter B for customer programmable curve for UV2 Parameter C for customer programmable curve for UV2 Parameter D for customer programmable curve for UV2 Parameter P for customer programmable curve for UV2
10.1.6
Technical data
Table 249:
Function Measuring current input
Base voltage Pickup overcurrent, step 1 and 2 Pickup undercurrent, step 1 and 2 Table continues on next page
1.0% of In for I<In 1.0% of I for I>In 1.0% of In for I<In 1.0% of I for I>In
Voltage level where voltage memory takes over Pickup overvoltage, step 1 and 2 Pickup undervoltage, step 1 and 2 Operate time, pickup overvoltage Reset time, pickup overvoltage Operate time pickup undervoltage Reset time pickup undervoltage High and low voltage limit, voltage dependent operation Directional function Relay characteristic angle Relay operate angle Reset ratio, overcurrent Reset ratio, undercurrent Reset ratio, overvoltage Reset ratio, undervoltage Overcurrent: Table continues on next page 504
0.5% of Vn
(2.0 - 200.0)% of VBase (2.0 - 150.0)% of VBase 25 ms typically at 0 to 2 x Vset 25 ms typically at 2 to 0 x Vset 25 ms typically 2 to 0 x Vset 25 ms typically at 0 to 2 x Vset (1.0 - 200.0)% of VBase
0.5% of Vn for V<Vn 0.5% of V for V>Vn 0.5% of Vn for V<Vn 0.5% of V for V>Vn 1.0% of Vn for V<Vn 1.0% of V for V>Vn 2.0 degrees 2.0 degrees -
Settable: NonDir, forward and reverse (-180 to +180) degrees (1 to 90) degrees > 95% < 105% > 95% < 105%
10.2
10.2.1
is required for rotor ground fault protection (RXTTE4) and a protective resistor on plate for correct operation. Rotor ground fault protection can be integrated in the IED among all other protection functions typically required for generator protection. How this is achieved by using COMBIFLEX injection unit RXTTE4 is described in Instruction 1MRG001910.
10.2.2
10.2.2.1
Principle of operation
Rotor ground fault
The protection function uses injection of an ac voltage to the generator field circuit. The COMBIFLEX voltage injection unit RXTTE4, Part No 1MRK 002 108-AB contains a voltage transformer with a primary winding for connection to 120 or 230 V, 50 or 60 Hz supply voltage. From the secondary winding of this internal voltage transformer approximately 40 V AC is injected via series capacitors and resistors into the rotor circuit. The injected voltage and current are fed to one voltage input and one current input on the IED. 1A rated current input into REG670 must be used for this function.
The current caused by the injection is fed to a current input on the IED via injection unit RXTTE4, as shown in figure 233.
421 I 428
230 V AC 120 V AC 0
en07000185_ansi.vsd
ANSI07000185 V1 EN
Figure 233:
By using a two stage directional current measurement in the General current and voltage protection (CVGAPC), as shown in figure 234, the ground fault current on the DC side of the excitation is detected. The protection operates when the resistive component of the measured injected current exceeds the pre-set operate level. Stage one provides an alarm signal and stage two trips the generator after a short time delay for fully developed rotor ground faults.
Operating Region
IINJECTED
VINJECTED
en06000447_ansi.vsd
ANSI06000447 V1 EN
Figure 234:
Two stage directional current measurement in the general application multipurpose function
The sensitivity of the rotor ground fault protection is dependent of the rotor winding capacitance to ground and the set pick-up current level of the General current and voltage protection (CVGAPC). The sensitivity is shown in figure 235.
10
ko hm
0 ,1 0 1 2 uF 3 0 mA 4 0 mA 50 mA 70 mA 10 0 mA 150 mA 2 0 0 mA 3 0 0 mA 3 4 5
en06000445.vsd
IEC06000445 V1 EN
Figure 235:
The undervoltage stage of the General current and voltage protection (CVGAPC) can be used to monitor the injection voltage and give alarm if the injection voltage is absent. It shall be set to 80% of the rated value of the rated value of the injected voltage with a time delay of about 10 s. An additional instance of the General current and voltage protection (CVGAPC) can be used to provide a third non-directional overcurrent stage which can be used to detect ground faults on the AC side of the rectifier in case of a static excitation system. It shall be set to operate when the magnitude of the injected current into the rotor circuit exceeds 125 mA and with a delay of 5 s. As the CT in RXTTE4 has a ratio 10:1 the current measured by the IED will be at least 1.25 A for this fault.
Rotor earth fault protection (64R) based on General current and voltage protection (CVGAPC) and RXTTE4
Range or value Accuracy
Supply voltage 120 or 230 V Operate ground fault resistance value Influence of harmonics in the DC field voltage Permitted leakage capacitance Permitted shaft grounding resistance Protective resistor
50/60 Hz Approx. 120 k Negligible influence of 50 V, 150 Hz or 50 V, 300 Hz (15) F Maximum 200 220 , 100 W, plate 135 x 160 mm
Section 11
11.1
11.1.1
Introduction
Open or short circuited current transformer cores can cause unwanted operation of many protection functions such as differential, ground-fault current and negativesequence current functions. It must be remembered that a blocking of protection functions at an occurrence of open CT circuit will mean that the situation will remain and extremely high voltages will stress the secondary circuit. Current circuit supervision (CCSRDIF, 87) compares the residual current from a three phase set of current transformer cores with the neutral point current on a separate input taken from another set of cores on the current transformer. A detection of a difference indicates a fault in the circuit and is used as alarm or to block protection functions expected to give unwanted tripping.
11.1.2
Principle of operation
Current circuit supervision CCSRDIF (87) compares the absolute value of the vectorial sum of the three phase currents |Iphase| and the numerical value of the residual current |Iref| from another current transformer set, see figure 236. The FAIL output will be set to a logical one when the following criteria are fulfilled:
511
The numerical value of the difference |Iphase| |Iref| is higher than 80% of the numerical value of the sum |Iphase| + |Iref|. The numerical value of the current |Iphase| |Iref| is equal to or higher than the set operate value IMinOp. No phase current has exceeded Pickup_Block during the last 10 ms. CCSRDIF (87) is enabled by setting Operation = Enabled.
The FAIL output remains activated 100 ms after the AND-gate resets when being activated for more than 20 ms. If the FAIL lasts for more than 150 ms an ALARM will be issued. In this case the FAIL and ALARM will remain activated 1 s after the ANDgate resets. This prevents unwanted resetting of the blocking function when phase current supervision element(s) operate, for example, during a fault.
I>Pickup_Block BLOCK
IA IB IC I ref IA IB IC I ref
+ + +
I>IMinOp x 0,8 + -
1,5 x Ir
OR
10 ms
AND
OR
FAIL
20 ms 100 ms
OPERATION BLOCK
150 ms
1s
ALARM
en05000463_ansi.vsd
ANSI05000463 V1 EN
Figure 236:
| I phase | - | I ref |
Slope = 1
Operation area
| I phase | + | I ref |
99000068.vsd
IEC99000068 V1 EN
Figure 237:
Operate characteristics
Due to the formulas for the axis compared, |SIphase | - |I ref | and |S I phase | + | I ref | respectively, the slope can not be above 2.
11.1.3
Function block
CCSRDIF (87) I3P* IREF* BLOCK FAIL ALARM
ANSI05000389-2-en.vsd
ANSI05000389 V2 EN
Figure 238:
11.1.4
Table 252:
Name FAIL ALARM
11.1.5
Table 253:
Name Operation IBase IMinOp
Setting parameters
CCSRDIF (87) Group settings (basic)
Values (Range) Disabled Enabled 1 - 99999 5 - 200 Unit A %IB Step 1 1 Default Disabled 3000 20 Description Disable/Enable Operation IBase value for current pickup detectors Minimum operate current differential pickup in % of IBase
Table 254:
Name Pickup_Block
11.1.6
Technical data
Table 255:
Function Operate current Block current
11.2
11.2.1
11.2.2
11.2.2.1
Principle of operation
Zero and negative sequence detection
The zero and negative sequence function continuously measures the currents and voltages in all three phases and calculates, see figure 239: the zero-sequence voltage 3V0 the zero-sequence current 3I0 the negative sequence current 3I2 the negative sequence voltage 3V2
The measured signals are compared with their respective set values 3V0PU and 3I0PU, 3V2PU and 3I2PU.
The function enable the internal signal FuseFailDetZeroSeq if the measured zerosequence voltage is higher than the set value 3V0PU and the measured zero-sequence current is below the set value 3I0PU. The function enable the internal signal FuseFailDetNegSeq if the measured negative sequence voltage is higher than the set value 3V2PU and the measured negative sequence current is below the set value 3I2PU. A drop out delay of 100 ms for the measured zero-sequence and negative sequence current will prevent a false fuse failure detection at un-equal breaker opening at the two line ends.
Sequence Detection
3I0PU IA Zero sequence filter Negative sequence filter
a b
CurrZeroSeq 3I0
a b
IB
a>b
100 ms 0
IC
a>b
100 ms 0 AND
FuseFailDetNegSeq VoltZeroSeq
a b
a>b VoltNegSeq
3V0
VB
a b
VC 3V2PU
a>b
3V2
ANSI10000036-2-en.vsd
ANSI10000036 V2 EN
Figure 239:
The calculated values 3V0, 3I0, 3I2 and 3V2 are available as service values on local HMI and monitoring tool in PCM600.
The output signals 3PH, BLKV and BLKZ can be blocked in the following conditions:
The input BLOCK is activated The input BLKTRIP is activated at the same time as the internal signal fufailStarted is not present The operation mode selector OpModeSel is set to Disable. The IED is in TEST status (TEST-ACTIVE is high) and the function has been blocked from the HMI (BlockFUSE=Yes)
The input BLOCK signal is a general purpose blocking signal of the fuse failure supervision function. It can be connected to a binary input of the IED in order to receive a block command from external devices or can be software connected to other internal functions of the IED itself in order to receive a block command from internal functions. Through OR gate it can be connected to both binary inputs and internal function outputs. The input BLKSP is intended to be connected to the trip output at any of the protection functions included in the IED. When activated for more than 20 ms, the operation of the fuse failure is blocked during a fixed time of 100 ms. The aim is to increase the security against unwanted operations during the opening of the breaker, which might cause unbalance conditions for which the fuse failure might operate. The output signal BLKZ will also be blocked if the internal dead line detection is activated. The block signal has a 200 ms drop-out time delay. The input signal MCBOP is supposed to be connected via a terminal binary input to the N.C. auxiliary contact of the miniature circuit breaker protecting the VT secondary circuit. The MCBOP signal sets the output signals BLKU and BLKZ in order to block all the voltage related functions when the MCB is open independent of the setting of OpModeSel selector. The additional drop-out timer of 150 ms prolongs the presence of MCBOP signal to prevent the unwanted operation of voltage dependent function due to non simultaneous closing of the main contacts of the miniature circuit breaker. The input signal 89b is supposed to be connected via a terminal binary input to the N.C. auxiliary contact of the line disconnector. The 89b signal sets the output signal BLKU in order to block the voltage related functions when the line disconnector is open. The impedance protection function is not affected by the position of the line disconnector since there will be no line currents that can cause malfunction of the distance protection. If DISCPOS=0 it signifies that the line is connected to the system and when the DISCPOS=1 it signifies that the line is disconnected from the system and the block signal BLKU is generated. The output BLKU can be used for blocking the voltage related measuring functions (undervoltage protection, synchro-check and so on) except for the impedance protection. The function output BLKZ shall be used for blocking the impedance protection function.
AND
3PH
AND FuseFailDetNegSeq AND UNsINs UZsIZs UZsIZs OR UNsINs UZsIZs AND UNsINs OptimZsNs OR
a b
OR OR
OpMode
CurrZeroSeq CurrNegSeq
a>b
AND AND
DeadLineDet1Ph MCBOP
200 ms t
AND 150 ms t
OR
AND
BLKZ
60 s t 5s t
OR AND
OR
AND
BLKU
OR
IEC10000033-2-en.vsd
11.2.2.2
The internal FuseFailDetDUDI signal is activated if the following conditions are fulfilled for a phase: The magnitude of the phase-ground voltage has been above UPh> for more than 1.5 cycle The magnitude of DU is higher than the corresponding setting DU> The magnitude of DI is below the setting DI>
and at least one of the following conditions are fulfilled: The magnitude of the phase current in the same phase is higher than the setting IPh> The circuit breaker is closed (CBCLOSED = True)
The first criterion means that detection of failure in one phase together with high current for the same phase will set the output. The measured phase current is used to reduce the risk of false fuse failure detection. If the current on the protected line is low, a voltage drop in the system (not caused by fuse failure) is not by certain followed by current change and a false fuse failure might occur The second criterion requires that the delta condition shall be fulfilled in any phase at the same time as circuit breaker is closed. Opening circuit breaker at one end and energizing the line from other end onto a fault could lead to wrong start of the fuse failure function at the end with the open breaker. If this is considering to be an important disadvantage, connect the CBCLOSED input to FALSE. In this way only the first criterion can activate the delta function.
DUDI Detection
DUDI detection Phase 1
IL1 One cycle delay |DI| DI< UL1 One cycle delay |DU| DU>
a a b a b
a>b
a>b
AND
a>b
20 ms t
1.5 cycle t
IL3 UL3
UL1
a b
a<b
IL1 IPh>
a b
a>b
AND OR AND
CBCLOSED UL2
a b
AND
OR
a<b
IL2
a b
a>b
AND OR AND
AND UL3
a b
OR
a<b
IL3
a b
a>b
AND
OR
IEC10000034-1-en.vsd
IEC10000034 V1 EN
Figure 241:
11.2.2.3
AllCurrLow
DeadLineDet1Ph a<b a<b a<b AND OR AND AND AND AND DLD3PH AND DLD1PH
ANSI0000035-1-en.vsd
ANSI0000035 V1 EN
Figure 242:
11.2.2.4
Main logic
A simplified diagram for the functionality is found in figure 243. The fuse failure supervision function (SDDRFUF) can be switched on or off by the setting parameter Operation to Enabled or Disabled. For increased flexibility and adaptation to system requirements an operation mode selector, OpModeSel, has been introduced to make it possible to select different operating modes for the negative and zero sequence based algorithms. The different operation modes are: Disabled; The negative and zero sequence function is disabled V2I2; Negative sequence is selected V0I0; Zero sequence is selected
521
V0I0 OR V2I2; Both negative and zero sequence is activated and working in parallel in an OR-condition V0I0 AND V2I2; Both negative and zero sequence is activated and working in series (AND-condition for operation) OptimZsNs; Optimum of negative and zero sequence (the function that has the highest magnitude of measured negative and zero sequence current will be activated)
The delta function can be activated by setting the parameter OpDVDI to Enabled. When selected it operates in parallel with the sequence based algorithms. As soon as any fuse failure situation is detected, signals FuseFailDetZeroSeq, FuseFailDetNegSeq or FuseFailDetDVDI, and the specific functionality is released, the function will activate the output signal BLKV. The output signal BLKZ will be activated as well if not the internal dead phase detection, DeadLineDet1Ph, is not activated at the same time. The output BLKV can be used for blocking voltage related measuring functions (under voltage protection, synchro-check, and so on). For blocking of impedance protection functions output BLKZ shall be used. If the fuse failure situation is present for more than 5 seconds and the setting parameter SealIn is set to Enabled it will be sealed in as long as at least one phase voltages is below the set value VSealInPU. This will keep the BLKV and BLKZ signals activated as long as any phase voltage is below the set value VSealInPU. If all three phase voltages drop below the set value VSealInPU and the setting parameter SealIn is set to Enabled the output signal 3PH will also be activated. The signals 3PH, BLKV and BLKZ signals will now be active as long as any phase voltage is below the set value VSealInPU. If SealIn is set to Enabled the fuse failure condition is stored in the non volatile memory in the IED. At start-up of the IED (due to auxiliary power interruption or restart due to configuration change) it checks the stored value in its non volatile memory and re-establishes the conditions that were present before the shut down. All phase voltages must be greater than VSealInPU before fuse failure is de-activated and removes the block of different protection functions. The output signal BLKV will also be active if all phase voltages have been above the setting VSealInPU for more than 60 seconds, the zero or negative sequence voltage has been above the set value 3V0PU and 3V2PU for more than 5 seconds, all phase currents are below the setting IDLDPU (operate level for dead line detection) and the circuit breaker is closed (input 52a is activated). If a MCB is used then the input signal MCBOP is to be connected via a terminal binary input to the N.C. auxiliary contact of the miniature circuit breaker protecting the VT secondary circuit. The MCBOP signal sets the output signals BLKV and BLKZ in order to block all the voltage related functions when the MCB is open independent of the setting of OpModeSel or OpDVDI. An additional drop-out timer of 150 ms
prolongs the presence of MCBOP signal to prevent the unwanted operation of voltage dependent function due to non simultaneous closing of the main contacts of the miniature circuit breaker. The input signal 89b is supposed to be connected via a terminal binary input to the N.C. auxiliary contact of the line disconnector. The 89b signal sets the output signal BLKV in order to block the voltage related functions when the line disconnector is open. The impedance protection function does not have to be affected since there will be no line currents that can cause malfunction of the distance protection. The output signals 3PH, BLKV and BLKZ as well as the signals DLD1PH and DLD3PH from dead line detections are blocked if any of the following conditions occur: The operation mode selector OpMode is set to Disabled The input BLOCK is activated The input BLKTRIP is activated at the same time as no fuse failure indication is present The IED is in TEST status (TEST-ACTIVE is high) and the function has been blocked from the HMI (BlockFUSE=Yes)
The input BLOCK is a general purpose blocking signal of the fuse failure supervision function. It can be connected to a binary input of the IED in order to receive a block command from external devices or can be software connected to other internal functions of the IED. Through OR gate it can be connected to both binary inputs and internal function outputs. The input BLKTRIP is intended to be connected to the trip output of any of the protection functions included in the IED and/or trip from external equipments via binary inputs. When activated for more than 20 ms without any fuse fail detected, the operation of the fuse failure is blocked during a fixed time of 100 ms. The aim is to increase the security against unwanted operations during the opening of the breaker, which might cause unbalance conditions for which the fuse failure might operate.
AND
AND Any VL < VSealInPU FuseFailDetDUDI OpDVDI = Enabled FuseFailDetZeroSeq AND AND OR 5s t
AND FuseFailDetNegSeq AND UNsINs UZsIZs UZsIZs OR UNsINs UZsIZs AND UNsINs OptimZsNs OR
a b
OR OR
OpModeSel
CurrZeroSeq CurrNegSeq
a>b
AND AND
DeadLineDet1Ph MCBOP
200 ms t
AND 150 ms t
OR
AND
BLKZ
60 s t 5s t
OR AND
OR
AND
BLKV
OR
ANSI10000033-2-en.vsd
ANSI10000033 V2 EN
11.2.3
Function block
SDDRFUF I3P* V3P* BLOCK 52A MCBOP 89B BLKTRIP BLKZ BLKV 3PH DLD1PH DLD3PH
ANSI05000700-2-en.vsd
ANSI05000700 V2 EN
Figure 244:
11.2.4
Table 257:
Name BLKZ BLKV 3PH DLD1PH DLD3PH
Setting parameters
SDDRFUF Group settings (basic)
Values (Range) Disabled Enabled 1 - 99999 0.05 - 2000.00 Disabled V2I2 V0I0 V0I0 OR V2I2 V0I0 AND V2I2 OptimZsNs 1 - 100 1 - 100 1 - 100 1 - 100 Disabled Enabled 1 - 100 1 - 100 1 - 100 1 - 100 Disabled Enabled 1 - 100 1 - 100 1 - 100 Unit A kV Step 1 0.05 Default Enabled 3000 400.00 V0I0 Description Disable/Enable Operation Base current Base voltage Operating mode selection
3V0PU 3I0PU 3V2PU 3I2PU OpDVDI DVPU DIPU VPPU IPPU SealIn VSealInPU IDLDPU VDLDPU
%VB %IB %VB %IB %VB %IB %VB %IB %VB %IB %VB
1 1 1 1 1 1 1 1 1 1 1
30 10 30 10 Disabled 60 15 70 10 Enabled 70 5 60
Pickup of residual overvoltage element in % of VBase Pickup of residual undercurrent element in % of IBase Pickup of negative sequence overvoltage element in % of VBase Pickup of negative sequence undercurrent element in % of IBase Operation of change based function Disable/ Enable Pickup of change in phase voltage in % of VBase Pickup of change in phase current in % of IBase Pickup of phase voltage in % of VBase Pickup of phase current in % of IBase Seal in functionality Disable/Enable Pickup of seal-in phase voltage in % of VBase Pickup for phase current detection in % of IBase for dead line detection Pickup for phase voltage detection in % of VBase for dead line detection
11.2.6
528
Section 12 Control
Section 12
Control
12.1
sc/vc
SYMBOL-M V1 EN
12.1.1
Introduction
The Synchronizing function allows closing of asynchronous networks at the correct moment including the breaker closing time, which improves the network stability. Synchrocheck, energizing check, and synchronizing (SESRSYN, 25) function checks that the voltages on both sides of the circuit breaker are in synchronism, or with at least one side dead to ensure that closing can be done safely. SESRSYN (25) function includes a built-in voltage selection scheme for double bus and breaker-and-a-half or ring busbar arrangements. Manual closing as well as automatic reclosing can be checked by the function and can have different settings. For systems which are running asynchronous a synchronizing function is provided. The main purpose of the synchronizing function is to provide controlled closing of circuit breakers when two asynchronous systems are going to be connected. It is used
Section 12 Control
for slip frequencies that are larger than those for synchronism check and lower than a set maximum level for the synchronizing function. However this function can not be used to automatically synchronize the generator to the network.
12.1.2
12.1.2.1
Principle of operation
Basic functionality
The synchronism check function measures the conditions across the circuit breaker and compares them to set limits. The output is only given when all measured quantities are simultaneously within their set limits. The energizing check function measures the bus and line voltages and compares them to both high and low threshold detectors. The output is given only when the actual measured quantities match the set conditions. The synchronizing function measures the conditions across the circuit breaker, and also determines the angle change occurring during the closing delay of the circuit breaker, from the measured slip frequency. The output is given only when all measured conditions are simultaneously within their set limits. The issue of the output is timed to give closure at the optimal time including the time for the circuit breaker and the closing circuit. For single circuit breaker and breaker-and-a-half circuit breaker arrangements, the SESRSYN (25) function blocks have the capability to make the necessary voltage selection. For single circuit breaker arrangements, selection of the correct voltage is made using auxiliary contacts of the bus disconnectors. For breaker-and-a-half circuit breaker arrangements, correct voltage selection is made using auxiliary contacts of the bus disconnectors as well as the circuit breakers. The internal logic for each function block as well as, the input and outputs, and the setting parameters with default setting and setting ranges is described in this document. For application related information, please refer to the application manual.
12.1.2.2
Section 12 Control
Synchronism check
The voltage difference, frequency difference and phase angle difference values are measured in the IED centrally and are available for the synchronism check function for evaluation. If the bus voltage is connected as phase-phase and the line voltage as phaseneutral (or the opposite), this need to be compensated. This is done with a setting, which scales up the line voltage to a level equal to the bus voltage. When the function is set to OperationSC = Enabled, the measuring will start. The function will compare the bus and line voltage values with the set values for VHighBusSC and VHighLineSC. If both sides are higher than the set values, the measured values are compared with the set values for acceptable frequency, phase angle and voltage difference: FreqDiffA, FreqDiffM, PhaseDiffA, PhaseDiffM and VDiffSC. If a compensation factor is set due to the use of different voltages on the bus and line, the factor is deducted from the line voltage before the comparison of the phase angle values. The frequency on both sides of the circuit breaker is also measured. The frequencies must not deviate from the rated frequency more than +/-5Hz. The frequency difference between the bus frequency and the line frequency is measured and may not exceed the set value. Two sets of settings for frequency difference and phase angle difference are available and used for the manual closing and autoreclose functions respectively, as required. The inputs BLOCK and BLKSC are available for total block of the complete SESRSYN (25) function and block of the Synchronism check function respectively. Input TSTSC will allow testing of the function where the fulfilled conditions are connected to a separate test output. The outputs MANSYOK and AUTOSYOK are activated when the actual measured conditions match the set conditions for the respective output. The output signal can be delayed independently for MANSYOK and AUTOSYOK conditions. A number of outputs are available as information about fulfilled checking conditions. VOKSC shows that the voltages are high, VDIFFSC, FRDIFFA, FRDIFFM, PHDIFFA, PHDIFFM shows when the voltage difference, frequency difference and phase angle difference conditions are out of limits. Output INADVCLS, inadvertent circuit breaker closing, indicate that the circuit breaker has been closed by some other equipment or function than SESRSYN. The output is activated, if the voltage condition is fulfilled at the same time the phase angle difference between bus and line is suddenly changed from being larger than 60 degrees to smaller than 5 degrees.
Section 12 Control
TSTAUTSY
AND
AUTOSYOK
VDiffSC
AND
VHighBusSC VHighLineSC
AND
50 ms 0
1 1
PHDIFFME
100 ms
AND
0 32 ms
AND
INADVCLS
ANSI07000114-3-en.vsd
ANSI07000114 V3 EN
Figure 245:
Synchronizing
When the function is set to OperationSynch = Enabled the measuring will be performed. The function will compare the values for the bus and line voltage with the set values for VHighBusSynch and VHighLineSynch, which is a supervision that the voltages are both live. Also the voltage difference is checked to be smaller than the set value for VDiffSynch, which is a p.u value of set voltage base values. If both sides are higher than the set values and the voltage difference between bus and line is acceptable, the measured values are compared with the set values for acceptable frequency
Section 12 Control
FreqDiffMax and FreqDiffMin, rate of change of frequency FreqRateChange, phase angle, which has to be smaller than the internally preset value of 15 degrees. Measured frequencies between the settings for the maximum and minimum frequency will initiate the measuring and the evaluation of the angle change to allow operation to be sent in the right moment including the set tBreaker time. There is a phase angle release internally to block any incorrect closing pulses. At operation the SYNOK output will be activated with a pulse tClosePulse and the function resets. The function will also reset if the synchronizing conditions are not fulfilled within the set tMaxSynch time. This prevents that the function is, by mistake, maintained in operation for a long time, waiting for conditions to be fulfilled. The inputs BLOCK and BLKSYNCH are available for total block of the complete SESRSYN function and block of the Synchronizing function respectively. TSTSYNCH will allow testing of the function where the fulfilled conditions are connected to a separate output.
SYN1 OPERATION SYNCH OFF ON TEST MODE OFF ON
STARTSYN
AND
BLKSYNCH OR
S R
AND
SYNPROGR
VDiffSynch
50 ms
AND
AND
SYNOK
OR AND OR
TSTSYNOK
AND
tClose Pulse
tMax Synch
SYNFAIL
ANSI06000636-2-en.vsd
ANSI06000636 V2 EN
Figure 246:
Section 12 Control
Energizing check
Voltage values are measured in the IED centrally and are available for evaluation by the Synchronism check function. The function measures voltages on the busbar and the line to verify whether they are live or dead. This is done by comparing with the set values VHighBusEnerg and VLowBusEnerg for bus energizing and VHighLineEnerg and VLowLineEnerg for line energizing. The frequency on both sides of the circuit breaker is also measured. The frequencies must not deviate from the rated frequency more than +/-5Hz. The Energizing direction can be selected individually for the Manual and the Automatic functions respectively. When the conditions are met the outputs AUTOENOK and MANENOK respectively will be activated if the fuse supervision conditions are fulfilled. The output signal can be delayed independently for MANENOK and AUTOENOK conditions. The Energizing direction can also be selected by an integer input AENMODE respective MENMODE, which for example, can be connected to a Binary to Integer function block (B16I). Integers supplied shall be 1=off, 2=DLLB, 3=DBLL and 4= Both. Not connected input with connection of INTZERO output from Fixed Signals (FIXDSIGN) function block will mean that the setting is done from Parameter Setting tool. The active position can be read on outputs MODEAEN resp MODEMEN. The modes are 0=OFF, 1=DLLB, 2=DBLL and 3=Both. The inputs BLOCK and BLKENERG are available for total block of the complete SESRSYN (25) function respective block of the Energizing check function. TSTENERG will allow testing of the function where the fulfilled conditions are connected to a separate test output.
Voltage selection
The voltage selection module including supervision of included voltage transformer fuses for the different arrangements is a basic part of the SESRSYN (25) function and determines the parameters fed to the Synchronizing, Synchrocheck and Energizing check functions. This includes the selection of the appropriate Line and Bus voltages and fuse supervision. The voltage selection type to be used is set with the parameter CBConfig. If No voltage sel. is set the default voltages used will be V-Line1 and V-Bus1. This is also the case when external voltage selection is provided. Fuse failure supervision for the used inputs must also be connected. The voltage selection function, selected voltages, and fuse conditions are the Synchronism check and Energizing check inputs.
Section 12 Control
For the disconnector positions it is advisable to use (NO) a and (NC) b type contacts to supply Disconnector Open and Closed positions but, it is also possible to use an inverter for one of the positions.
This function uses the binary input from the disconnectors auxiliary contacts BUS1_OPBUS1_CL for Bus 1, and BUS2_OP-BUS2_CL for Bus 2 to select between bus 1 and bus 2 voltages. If the disconnector connected to bus 1 is closed and the disconnector connected to bus 2 is opened the bus 1 voltage is used. All other combinations use the bus 2 voltage. The outputs B1SEL and B2SEL respectively indicate the selected Bus voltage. The function checks the fuse-failure signals for bus 1, bus 2 and line voltage transformers. Inputs VB1OK-VB1FF supervise the fuse for Bus 1 and VB2OK-VB2FF supervises the fuse for Bus 2. VL1OK and VL1FF supervises the fuse for the Line voltage transformer. The inputs fail (FF) or healthy (OK) can alternatively be used dependent on the available signal. If a fuse-failure is detected in the selected voltage source an output signal VSELFAIL is set. This output signal is true if the selected bus or line voltages have a fuse failure. This output as well as the function can be blocked with the input signal BLOCK. The function logic diagram is shown in figure 247.
Section 12 Control
B1SEL B2SEL
NOT AND
invalidSelection busVoltage
bus1Voltage bus2Voltage
OR
selectedFuseOK VSELFAIL
OR
OR
BLOCK
en05000779_ansi.vsd
ANSI05000779 V1 EN
Figure 247:
Logic diagram for the voltage selection function of a single circuit breaker with double busbars
Note that with breaker-and-a-half schemes two Synchronism check functions must be used in the IED (three for two IEDs in a complete bay). Below, the scheme for one Bus breaker and the Tie breaker is described. This voltage selection function uses the binary inputs from the disconnectors and circuit breakers auxiliary contacts to select the right voltage for the SESRSYN (Synchronism and Energizing check) function. For the bus circuit breaker one side of the circuit breaker is connected to the busbar and the other side is connected either to line 1, line 2 or the other busbar depending on the arrangement. Inputs LINE1_OP-LINE1_CL, BUS1_OP-BUS1_CL, BUS2_OP-BUS2_CL, LINE2_OP-LINE2_CL are inputs for the position of the Line disconnectors respectively the Bus and Tie breakers. The outputs L1SEL, L2SEL and B2SEL will give indication of the selected Line voltage as a reference to the fixed Bus 1 voltage, which indicates B1SEL.
Section 12 Control
The fuse supervision is connected to VLNOK-VLNFF and with alternative Healthy or Failing fuse signals depending on what is available from each fuse (MCB). The tie circuit breaker is connected either to bus 1 or line 1 on one side and the other side is connected either to bus 2 or line 2. Four different output combinations are possible, bus to bus, bus to line, line to bus and line to line. The line 1 voltage is selected if the line 1 disconnector is closed. The bus 1 voltage is selected if the line 1 disconnector is open and the bus 1 circuit breaker is closed. The line 2 voltage is selected if the line 2 disconnector is closed. The bus 2 voltage is selected if the line 2 disconnector is open and the bus 2 circuit breaker is closed.
The function also checks the fuse-failure signals for bus 1, bus 2, line 1 and line 2. If a fuse-failure is detected in the selected voltage an output signal VSELFAIL is set. This output signal is true if the selected bus or line voltages have a fuse failure. This output as well as the function can be blocked with the input signal BLOCK. The function block diagram for the voltage selection of a bus circuit breaker is shown in figure 248 and for the tie circuit breaker in figure 249.
Section 12 Control
L1SEL
lineVoltage
selectedFuseOK VSELFAIL
OR
AND
AND
OR
AND
en05000780_ansi.vsd
ANSI05000780 V1 EN
Figure 248:
Simplified logic diagram for the voltage selection function for a bus circuit breaker in a breaker-anda-half arrangement
Section 12 Control
LINE1_OP LINE1_CL
AND
BUS1_OP BUS1_CL
AND
AND
busVoltage
BUS2_OP BUS2_CL
AND
invalidSelection
AND
line2Voltage bus2Voltage VB1OK VB1FF VB2OK VB2FF VL1OK VL1FF VL2OK VL2FF BLOCK
lineVoltage
OR
AND OR AND
OR
AND
selectedFuseOK VSELFAIL
OR
AND
AND
OR
AND
en05000781_ansi.vsd
ANSI05000781 V1 EN
Figure 249:
Simplified logic diagram for the voltage selection function for the tie circuit breaker in breaker-and-ahalf arrangement.
External fuse failure signals or signals from a tripped fuse switch/MCB are connected to binary inputs that are configured to the inputs of SESRSYN (25) function in the IED. Alternatively, the internal signals from fuse failure supervision can be used when available. There are two alternative connection possibilities. Inputs labelled OK must be connected if the available contact indicates that the voltage circuit is healthy. Inputs
539 Technical reference manual
Section 12 Control
labelled FF must be connected if the available contact indicates that the voltage circuit is faulty. The VB1OK/VB2OK and VB1FF/VB2FF inputs are related to the busbar voltage and the VLNOK and VLNFF inputs are related to the line voltage. Configure them to the binary input or function outputs that indicate the status of the external fuse failure of the busbar and line voltages. In the event of a fuse failure, the energizing check function is blocked. The synchronism check function requires full voltage on both sides and will be blocked automatically in the event of fuse failures.
12.1.3
Function block
SESRSYN (25) V3PB1* SYNOK V3PB2* AUTOSYOK V3PL1* AUTOENOK V3PL2* MANSYOK BLOCK MANENOK BLKSYNCH TSTSYNOK BLKSC TSTAUTSY BLKENERG TSTMANSY BUS1_OP TSTENOK BUS1_CL VSELFAIL BUS2_OP B1SEL BUS2_CL B2SEL LINE1_OP L1SEL LINE1_CL L2SEL LINE2_OP SYNPROGR LINE2_CL SYNFAIL VB1OK VOKSYN VB1FF VDIFFSYN VB2OK FRDIFSYN VB2FF FRDIFFOK VL1OK FRDERIVA VL1FF VOKSC VL2OK VDIFFSC VL2FF FRDIFFA STARTSYN PHDIFFA TSTSYNCH FRDIFFM TSTSC PHDIFFM TSTENERG INADVCLS AENMODE VDIFFME MENMODE FRDIFFME PHDIFFME Vbus VLine MODEAEN MODEMEN ANSI10000046-1-en.vsd
ANSI10000046 V1 EN
Figure 250:
12.1.4
Section 12 Control
Table 261:
Name SYNOK AUTOSYOK AUTOENOK MANSYOK MANENOK TSTSYNOK TSTAUTSY TSTMANSY TSTENOK VSELFAIL B1SEL B2SEL L1SEL L2SEL SYNPROGR SYNFAIL VOKSYN VDIFFSYN FRDIFSYN FRDIFFOK FRDERIVA VOKSC VDIFFSC FRDIFFA PHDIFFA FRDIFFM PHDIFFM INADVCLS VDIFFME FRDIFFME PHDIFFME Vbus VLine MODEAEN MODEMEN
12.1.5
Table 262:
Name Operation CBConfig
VBaseBus VBaseLine PhaseShift VRatio OperationSynch VHighBusSynch VHighLineSynch VDiffSynch FreqDiffMin FreqDiffMax FreqRateChange tBreaker tClosePulse tMaxSynch tMinSynch OperationSC VHighBusSC VHighLineSC VDiffSC FreqDiffA FreqDiffM
0.001 0.001 5 0.001 1.0 1.0 0.01 0.001 0.001 0.001 0.001 0.001 0.01 0.001 1.0 1.0 0.01 0.001 0.001
400.000 400.000 0 1.000 Disabled 80.0 80.0 0.10 0.010 0.200 0.300 0.080 0.200 600.00 2.000 Enabled 80.0 80.0 0.15 0.010 0.010
Base value for busbar voltage settings Base value for line voltage settings Phase shift Voltage ratio Operation for synchronizing function Off/On Voltage high limit bus for synchronizing in % of UBaseBus Voltage high limit line for synchrocheck in % of VBaseLine Voltage difference limit for synchronizing in p.u Minimum frequency difference limit for synchronizing Maximum frequency difference limit for synchronizing Maximum allowed frequency rate of change Closing time of the breaker Breaker closing pulse duration Resets synch if no close has been made before set time Minimum time to accept synchronizing conditions Operation for synchronism-check function Off/ On Voltage high limit bus for synchrocheck in % of VBaseBus Voltage high limit line for synchrocheck in % of UBaseLine Voltage difference limit in p.u Frequency difference limit between bus and line Auto Frequency difference limit between bus and line Manual
Section 12 Control
Name PhaseDiffA PhaseDiffM tSCA tSCM AutoEnerg Values (Range) 5.0 - 90.0 5.0 - 90.0 0.000 - 60.000 0.000 - 60.000 Disabled DLLB DBLL Both Disabled DLLB DBLL Both Disabled Enabled 50.0 - 120.0 50.0 - 120.0 10.0 - 80.0 10.0 - 80.0 50.0 - 180.0 0.000 - 60.000 0.000 - 60.000 Unit Deg Deg s s Step 1.0 1.0 0.001 0.001 Default 25.0 25.0 0.100 0.100 DBLL Description
Phase angle difference limit between bus and line Auto Phase angle difference limit between bus and line Manual Time delay output for synchrocheck Auto Time delay output for synchrocheck Manual Automatic energizing check mode
ManEnerg
Both
Manual dead bus, dead line energizing Voltage high limit bus for energizing check in % of UBaseBus Voltage high limit line for energizing check in % of VBaseLine Voltage low limit bus for energizing check in % of VBaseBus Voltage low limit line for energizing check in % of VBaseLine Maximum voltage for energizing in % of VBase, Line and/or Bus Time delay for automatic energizing check Time delay for manual energizing check
Section 12 Control
Table 263:
Name SelPhaseBus1
SelPhaseBus2
SelPhaseLine1
SelPhaseLine2
(5.0-90.0) degrees
2.0 degrees
(0.02-0.5) p.u
0.5% of Vn
0.5% 10 ms 2.0 mHz 2.0 mHz 10.0 mHz/s 0.5% 10 ms 0.5% 10 ms 0.5% 10 ms
(0.000-60.000) s (50.0-120.0)% of VBaseBus and VBaseLine > 95% (10.0-80.0)% of VBaseBus and VBaseLine < 105% (50.0-180.0)% of VBaseBus and/ or VBaseLine
Section 12 Control
Function Time delay for energizing check Operate time for synchronism check function Operate time for energizing function Range or value (0.000-60.000) s 160 ms typically 80 ms typically Accuracy 0.5% 10 ms -
12.2
12.2.1
12.2.2
Principle of operation
A bay can handle, for example a power line, a transformer, a reactor, or a capacitor bank. The different primary apparatuses within the bay can be controlled via the apparatus control function directly by the operator or indirectly by automatic sequences. Because a primary apparatus can be allocated to many functions within a Substation Automation system, the object-oriented approach with a function module that handles the interaction and status of each process object ensures consistency in the process information used by higher-level control functions. Primary apparatuses such as breakers and disconnectors are controlled and supervised by one software module (SCSWI) each. Because the number and type of signals connected to a breaker and a disconnector are almost the same, the same software is used to handle these two types of apparatuses. The software module is connected to the physical process in the switchyard via an interface module by means of a number of digital inputs and outputs. One type of interface module is intended for a circuit breaker (SXCBR) and another type is intended for a disconnector or grounding switch (SXSWI). Four types of function blocks are available to cover most of the control and supervision within the bay. These
Section 12 Control
function blocks are interconnected to form a control function reflecting the switchyard configuration. The total number used depends on the switchyard configuration. These four types are: Bay control QCBAY Switch controller SCSWI Circuit breaker SXCBR Circuit switch SXSWI
The three latter functions are logical nodes according to IEC 61850. The functions Local Remote (LOCREM) and Local Remote Control (LOCREMCTRL), to handle the local/remote switch, and the functions Bay reserve (QCRSV) and Reservation input (RESIN), for the reservation function, also belong to the apparatus control function. The principles of operation, function block, input and output signals and setting parameters for all these functions are described below.
12.2.3
Error handling
Depending on the error that occurs during the command sequence the error signal will be set with a value. Table 265 describes vendor specific cause values in addition to these specified in IEC 61850-8-1 standard. The list of values of the cause are in order of priority. The values are available over the IEC 61850. An output L_CAUSE on the function block for Switch controller (SCSWI), Circuit breaker (SXCBR) and Circuit switch (SXSWI) indicates the latest value of the error during the command.
Section 12 Control
Table 265:
Section 12 Control
Attribute value Vendor specific -20 -21 -23 -24 -25 -26 -27 -28 -29 -30 -31 -32 -33 -34 -35 Description Not in use Not in use blocked-for-command blocked-for-opencommand blocked-for-closecommand Not in use Not in use Not in use Not in use long-operation-time switch-not-start-moving persisting-intermediatestate switch-returned-to-initialposition switch-in-bad-state not-expected-final-position
Supported
X X X
X X X X X X
12.2.4
12.2.4.1
12.2.4.2
Principle of operation
The functionality of the Bay control (QCBAY) function is not defined in the IEC 61850 81 standard, which means that the function is a vendor specific logical node. The function sends information about the Permitted Source To Operate (PSTO) and blocking conditions to other functions within the bay for example, switch control functions, voltage control functions and measurement functions.
Section 12 Control
Local panel switch
The local panel switch is a switch that defines the operator place selection. The switch connected to this function can have three positions remote/local/off. The positions are here defined so that remote means that operation is allowed from station/remote level and local from the IED level. The local/remote switch is also on the control/protection IED itself, which means that the position of the switch and its validity information are connected internally, and not via I/O boards. When the switch is mounted separately from the IED the signals are connected to the function via I/O boards. When the local panel switch (or LHMI selection, depending on the set source to select this) is in Off position, all commands from remote and local level will be ignored. If the position for the local/remote switch is not valid the PSTO output will always be set to faulty state (3), which means no possibility to operate. To adapt the signals from the local HMI or from an external local/remote switch, the function blocks LOCREM and LOCREMCTRL are needed and connected to QCBAY. The actual state of the operator place is presented by the value of the Permitted Source To Operate, PSTO signal. The PSTO value is evaluated from the local/remote switch position according to table 266. In addition, there is one configuration parameter that affects the value of the PSTO signal. If the parameter AllPSTOValid is set and LRswitch position is in Local or Remote state, the PSTO value is set to 5 (all), that is, it is permitted to operate from both local and remote level without any priority. When the external panel switch is in Off position the PSTO value shows the actual state of switch that is, 0. In this case it is not possible to control anything.
Table 266:
Local panel switch positions 0 = Off 1 = Local 1 = Local 2 = Remote 2 = Remote 3 = Faulty
0 1 5 2 5 3
Blockings
The blocking states for position indications and commands are intended to provide the possibility for the user to make common blockings for the functions configured within a complete bay.
551 Technical reference manual
Section 12 Control
The blocking facilities provided by the bay control function are the following: Blocking of position indications, BL_UPD. This input will block all inputs related to apparatus positions for all configured functions within the bay. Blocking of commands, BL_CMD. This input will block all commands for all configured functions within the bay. Blocking of function, BLOCK, signal from DO (Data Object) Behavior (IEC 61850 81). If DO Behavior is set to "blocked" it means that the function is active, but no outputs are generated, no reporting, control commands are rejected and functional and configuration data is visible.
The switching of the Local/Remote switch requires at least system operator level. The password will be requested at an attempt to operate if authority levels have been defined in the IED. Otherwise the default authority level, SuperUser, can handle the control without LogOn. The users and passwords are defined in PCM600.
12.2.4.3
Function block
QCBAY LR_OFF LR_LOC LR_REM LR_VALID BL_UPD BL_CMD PSTO UPD_BLKD CMD_BLKD LOC REM
IEC10000048-1-en.vsd
IEC10000048 V1 EN
Figure 251:
12.2.4.4
Section 12 Control
Table 268:
Name PSTO UPD_BLKD CMD_BLKD LOC REM
12.2.4.5
Table 269:
Name AllPSTOValid
Setting parameters
QCBAY Non group settings (basic)
Values (Range) Priority No priority Unit Step Default Priority Description Priority of originators
12.2.5
12.2.5.1
12.2.5.2
Principle of operation
The function block Local remote (LOCREM) handles the signals coming from the local/ remote switch. The connections are seen in figure 252, where the inputs on function block LOCREM are connected to binary inputs if an external switch is used. When the local HMI is used, the inputs are not used and are set to FALSE in the configuration. The outputs from the LOCREM function block control the output PSTO (Permitted Source To Operate) on Bay control (QCBAY).
Section 12 Control
QCBAY LR_ OFF PSTO LR_ LOC UPD_ BLKD LR_ REM CMD_ BLKD LOC LR_ VALID REM BL_ UPD BL_ CMD QCBAY LR_ OFF PSTO LR_ LOC UPD_ BLKD LR_ REM CMD_ BLKD LOC LR_ VALID REM BL_ UPD BL_ CMD
LOCREMCTRL PSTO1 HMICTR1 PSTO2 HMICTR2 PSTO3 HMICTR3 PSTO4 HMICTR4 PSTO5 HMICTR5 PSTO6 HMICTR6 PSTO7 HMICTR7 PSTO8 HMICTR8 PSTO9 HMICTR9 PSTO 10 HMICTR 10 PSTO 11 HMICTR 11 PSTO 12 HMICTR 12 IEC10000052-1-en.vsd
IEC10000052 V1 EN
Figure 252:
Configuration for the local/remote handling for a local HMI with two bays and two screen pages
If the IED contains control functions for several bays, the local/remote position can be different for the included bays. When the local HMI is used the position of the local/ remote switch can be different depending on which single line diagram screen page that is presented on the local HMI. The function block Local remote control (LOCREMCTRL) controls the presentation of the LEDs for the local/remote position to applicable bay and screen page. The switching of the local/remote switch requires at least system operator level. The password will be requested at an attempt to operate if authority levels have been defined in the IED. Otherwise the default authority level, SuperUser, can handle the control without LogOn. The users and passwords are defined in PCM600.
Section 12 Control
Function block
LOCREM CTRLOFF LOCCTRL REMCTRL LHMICTRL OFF LOCAL REMOTE VALID IEC05000360-2-en.vsd
IEC05000360 V2 EN
12.2.5.3
Figure 253:
PSTO1 PSTO2 PSTO3 PSTO4 PSTO5 PSTO6 PSTO7 PSTO8 PSTO9 PSTO10 PSTO11 PSTO12
LOCREMCTRL HMICTR1 HMICTR2 HMICTR3 HMICTR4 HMICTR5 HMICTR6 HMICTR7 HMICTR8 HMICTR9 HMICTR10 HMICTR11 HMICTR12 IEC05000361-2-en.vsd
IEC05000361 V2 EN
Figure 254:
12.2.5.4
Table 271:
Name OFF LOCAL REMOTE VALID
Section 12 Control
Table 272:
Name PSTO1 PSTO2 PSTO3 PSTO4 PSTO5 PSTO6 PSTO7 PSTO8 PSTO9 PSTO10 PSTO11 PSTO12
Table 273:
Name HMICTR1 HMICTR2 HMICTR3 HMICTR4 HMICTR5 HMICTR6 HMICTR7 HMICTR8 HMICTR9 HMICTR10 HMICTR11 HMICTR12
12.2.5.5
Table 274:
Name ControlMode
Setting parameters
LOCREM Non group settings (basic)
Values (Range) Internal LR-switch External LR-switch Unit Step Default Internal LR-switch Description Control mode for internal/external LR-switch
12.2.6
12.2.6.1
12.2.6.2
Principle of operation
The Switch controller (SCSWI) is provided with verification checks for the select execute sequence, that is, checks the conditions prior each step of the operation. The involved functions for these condition verifications are interlocking, reservation, blockings and synchronism-check.
Control handling
Two types of control models can be used. The two control models are "direct with normal security" and "SBO (Select-Before-Operate) with enhanced security". The parameter CtlModel defines which one of the two control models is used. The control model "direct with normal security" does not require a select whereas, the "SBO with enhanced security" command model requires a select before execution. Normal security means that only the command is evaluated and the resulting position is not supervised. Enhanced security means that the command sequence is supervised in three steps, the selection, command evaluation and the supervision of position. Each step ends up with a pulsed signal to indicate that the respective step in the command sequence is finished. If an error occurs in one of the steps in the command sequence, the sequence is terminated and the error is mapped into the enumerated variable "cause" attribute belonging to the pulsed response signal for the IEC 61850 communication. The last cause L_CAUSE can be read from the function block and used for example at commissioning. There is no relation between the command direction and the actual position. For example, if the switch is in close position it is possible to execute a close command. Before an execution command, an evaluation of the position is done. If the parameter PosDependent is true and the position is in intermediate state or in bad state no execution command is sent. If the parameter is false the execution command is sent independent of the position value.
Section 12 Control
Evaluation of position
In the case when there are three one-phase switches connected to the switch control function, the switch control will "merge" the position of the three switches to the resulting three-phase position. In the case when the position differ between the onephase switches, following principles will be applied: The position output from switch (SXCBR or SXSWI) is connected to SCSWI. With the group signal connection the SCSWI obtains the position, time stamps and quality attributes of the position which is used for further evaluation.
All switches in open position: All switches in close position: One switch =open, two switches= close (or inversely): Any switch in intermediate position: Any switch in bad state: switch control position = open switch control position = close switch control position = intermediate switch control position = intermediate switch control position = bad state
The time stamp of the output three-phase position from switch control will have the time stamp of the last changed phase when it goes to end position. When it goes to intermediate position or bad state, it will get the time stamp of the first changed phase. In addition, there is also the possibility that one of the one-phase switches will change position at any time due to a trip. Such situation is here called pole discrepancy and is supervised by this function. In case of a pole discrepancy situation, that is, the position of the one-phase switches are not equal for a time longer than the setting tPoleDiscord, an error signal POLEDISC will be set. In the supervision phase, the switch controller function evaluates the "cause" values from the switch modules Circuit breaker (SXCBR)/ Circuit switch (SXSWI). At error the "cause" value with highest priority is shown.
Blocking principles
The blocking signals are normally coming from the bay control function (QCBAY) and via the IEC 61850 communication from the operator place. The IEC 61850 communication has always priority over binary inputs, e.g. a block command on binary inputs will not prevent commands over IEC 61850. The different blocking possibilities are: Block/deblock of command. It is used to block command for operation of position. Blocking of function, BLOCK, signal from DO (Data Object) Behavior (IEC 61850). If DO Behavior is set to "blocked" it means that the function is active, but
Section 12 Control
no outputs are generated, no reporting, control commands are rejected and functional and configuration data is visible. The different block conditions will only affect the operation of this function, that is, no blocking signals will be "forwarded" to other functions. The above blocking outputs are stored in a non-volatile memory.
The Switch controller (SCSWI) works in conjunction with the synchronism-check and the synchronizing function (SESRSYN, 25). It is assumed that the synchronism-check function is continuously in operation and gives the result to SCSWI. The result from the synchronism-check function is evaluated during the close execution. If the operator performs an override of the synchronism-check, the evaluation of the synchronismcheck state is omitted. When there is a positive confirmation from the synchronismcheck function, SCSWI will send the close signal EXE_CL to the switch function Circuit breaker (SXCBR). When there is no positive confirmation from the synchronism-check function, SCSWI will send a start signal START_SY to the synchronizing function, which will send the closing command to SXCBR when the synchronizing conditions are fulfilled, see figure 255. If no synchronizing function is included, the timer for supervision of the "synchronizing in progress signal" is set to 0, which means no start of the synchronizing function. SCSWI will then set the attribute "blocked-by-synchronismcheck" in the "cause" signal. See also the time diagram in figure 259.
Section 12 Control
SCSWI EXE_CL OR
SXCBR CLOSE
ANSI09000209-1-en.vsd
ANSI09000209 V1 EN
Figure 255:
Example of interaction between SCSWI, SESRSYN (25) (synchronism check and synchronizing function) and SXCBR function
Time diagrams
The Switch controller (SCSWI) function has timers for evaluating different time supervision conditions. These timers are explained here. The timer tSelect is used for supervising the time between the select and the execute command signal, that is, the time the operator has to perform the command execution after the selection of the object to operate.
select execute command tSelect timer t1 t1>tSelect, then longoperation-time in 'cause' is set
en05000092.vsd
IEC05000092 V1 EN
Figure 256:
tSelect
The parameter tResResponse is used to set the maximum allowed time to make the reservation, that is, the time between reservation request and the feedback reservation granted from all bays involved in the reservation function.
560 Technical reference manual
Section 12 Control
select reservation request RES_RQ reservation granted RES_GRT command termination tResResponse timer t1 t1>tResResponse, then 1-of-n-control in 'cause' is set
en05000093.vsd
IEC05000093 V1 EN
Figure 257:
tResResponse
The timer tExecutionFB supervises the time between the execute command and the command termination, see figure 258.
execute command phase A open close phase B open close phase C open close command termination phase A command termination phase B command termination phase C command termination circuit breaker open close tExecutionFB timer t1>tExecutionFB, then long-operation-time in 'cause' is set *
t1
Figure 258:
tExecutionFB
The parameter tSynchrocheck is used to define the maximum allowed time between the execute command and the input SYNC_OK to become true. If SYNC_OK=true at the time the execute command signal is received, the timer "tSynchrocheck" will not start. The start signal for the synchronizing is obtained if the synchronism-check conditions are not fulfilled.
561 Technical reference manual
Section 12 Control
t1
Figure 259:
12.2.6.3
Function block
SCSWI BLOCK PSTO L_SEL L_OPEN L_CLOSE AU_OPEN AU_CLOSE BL_CMD RES_GRT RES_EXT SY_INPRO SYNC_OK EN_OPEN EN_CLOSE XPOS1 XPOS2 XPOS3 EXE_OP EXE_CL SELECTED RES_RQ START_SY POSITION OPENPOS CLOSEPOS POLEDISC CMD_BLK L_CAUSE XOUT POS_INTR
IEC05000337-2-en.vsd
IEC05000337 V2 EN
Figure 260:
12.2.6.4
Section 12 Control
Name AU_OPEN AU_CLOSE BL_CMD RES_GRT RES_EXT SY_INPRO SYNC_OK EN_OPEN EN_CLOSE XPOS1 XPOS2 XPOS3 Type BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN GROUP SIGNAL GROUP SIGNAL GROUP SIGNAL Default 0 0 0 0 0 0 0 0 0 Description Used for local automation function Used for local automation function Steady signal for block of the command Positive acknowledge that all reservations are made Reservation is made externally Synchronizing function in progress Closing is permitted by the synchronism-check Enables open operation Enables close operation Group signal from XCBR/XSWI per phase Group signal from XCBR/XSWI per phase Group signal from XCBR/XSWI per phase
Table 276:
Name EXE_OP EXE_CL SELECTED RES_RQ START_SY POSITION OPENPOS CLOSEPOS POLEDISC CMD_BLK L_CAUSE XOUT POS_INTR
Section 12 Control
12.2.6.5
Table 277:
Name CtlModel PosDependent tSelect tResResponse tSynchrocheck tSynchronizing tExecutionFB tPoleDiscord
Setting parameters
SCSWI Non group settings (basic)
Values (Range) Dir Norm SBO Enh Always permitted Not perm at 00/11 0.00 - 600.00 0.000 - 60.000 0.00 - 600.00 0.00 - 600.00 0.00 - 600.00 0.000 - 60.000 Unit s s s s s s Step 0.01 0.001 0.01 0.01 0.01 0.001 Default SBO Enh Always permitted 30.00 5.000 10.00 0.00 30.00 2.000 Description Specifies control model type Permission to operate depending on the position Maximum time between select and execute signals Allowed time from reservation request to reservation granted Allowed time for synchronism-check to fulfil close conditions Supervision time to get the signal synchronizing in progress Maximum time from command execution to termination Allowed time to have discrepancy between the poles
12.2.7
12.2.7.1
12.2.7.2
Principle of operation
The users of the Circuit breaker function (SXCBR) is other functions such as for example, switch controller, protection functions, autorecloser function or an IEC 61850 client residing in another IED or the operator place. This switch function executes commands, evaluates block conditions and evaluates different time supervision conditions. Only if all conditions indicate a switch operation to be allowed, the function performs the execution command. In case of erroneous conditions, the function indicates an appropriate "cause" value. SXCBR has an operation counter for closing and opening commands. The counter value can be read remotely from the operator place. The value is reset from a binary
Section 12 Control
input or remotely from the operator place by configuring a signal from the Single Point Generic Control 8 signals (SPC8GGIO) for example.
Local/Remote switch
One binary input signal LR_SWI is included in SXCBR to indicate the local/remote switch position from switchyard provided via the I/O board. If this signal is set to TRUE it means that change of position is allowed only from switchyard level. If the signal is set to FALSE it means that command from IED or higher level is permitted. When the signal is set to TRUE all commands (for change of position) from internal IED clients are rejected, even trip commands from protection functions are rejected. The functionality of the local/remote switch is described in figure 261.
Local= Operation at switch yard level
TR
UE
From I/O
switchLR
FAL SE
Figure 261:
Local/Remote switch
Blocking principles
SXCBR includes several blocking principles. The basic principle for all blocking signals is that they will affect commands from all other clients for example, operators place, protection functions, autoreclosure and so on. The IEC 61850 communication has always priority over binary inputs, e.g. a block command on binary inputs will not prevent commands over IEC 61850. The blocking possibilities are: Block/deblock for open command. It is used to block operation for open command. Note that this block signal also affects the input OPEN for immediate command. Block/deblock for close command. It is used to block operation for close command. Note that this block signal also affects the input CLOSE for immediate command. Update block/deblock of positions. It is used to block the updating of position values. Other signals related to the position will be reset. Blocking of function, BLOCK, signal from DO (Data Object) Behavior (IEC 61850). If DO Behavior is set to "blocked" it means that the function is active, but
565 Technical reference manual
Section 12 Control
no outputs are generated, no reporting, control commands are rejected and functional and configuration data is visible. The above blocking outputs are stored in a non-volatile memory.
Substitution
The substitution part in SXCBR is used for manual set of the position for the switch. The typical use of substitution is that an operator enters a manual value because that the real process value is erroneous for some reason. SXCBR will then use the manually entered value instead of the value for positions determined by the process. It is always possible to make a substitution, independently of the position indication and the status information of the I/O board. When substitution is enabled, the position values are blocked for updating and other signals related to the position are reset. The substituted values are stored in a non-volatile memory.
Time diagrams
There are two timers for supervising of the execute phase, tStartMove and tIntermediate. tStartMove supervises that the primary device starts moving after the execute output pulse is sent. tIntermediate defines the maximum allowed time for intermediate position. Figure 262 explains these two timers during the execute phase.
Section 12 Control
AdaptivePulse = TRUE
OPENPOS
CLOSEPOS
en05000097.vsd
IEC05000097 V1 EN
Figure 262:
The timers tOpenPulse and tClosePulse are the length of the execute output pulses to be sent to the primary equipment. Note that the output pulses for open and close command can have different pulse lengths. The pulses can also be set to be adaptive with the configuration parameter AdaptivePulse. Figure 263 shows the principle of the execute output pulse. The AdaptivePulse parameter will have affect on both execute output pulses.
OPENPOS
CLOSEPOS
EXE_CL tClosePulse
AdaptivePulse=FALSE
EXE_CL tClosePulse
AdaptivePulse=TRUE
en05000098.vsd
IEC05000098 V1 EN
Figure 263:
Section 12 Control
If the pulse is set to be adaptive, it is not possible for the pulse to exceed tOpenPulse or tClosePulse. The execute output pulses are reset when: the new expected final position is reached and the configuration parameter AdaptivePulse is set to true the timer tOpenPulse or tClosePulse has elapsed an error occurs due to the switch does not start moving, that is, tStartMove has elapsed.
There is one exception from the first item above. If the primary device is in open position and an open command is executed or if the primary device is in closed position and a close command is executed. In these cases, with the additional condition that the configuration parameter AdaptivePulse is true, the execute output pulse is always activated and resets when tStartMove has elapsed. If the configuration parameter AdaptivePulse is set to false the execution output remains active until the pulse duration timer has elapsed. If the start position indicates bad state (OPENPOS=1 and CLOSEPOS =1) when a command is executed the execute output pulse resets only when timer tOpenPulse or tClosePulse has elapsed. An example of when a primary device is open and an open command is executed is shown in figure 264 .
OPENPOS
CLOSEPOS
AdaptivePulse=FALSE
AdaptivePulse=TRUE
en05000099.vsd
IEC05000099 V1 EN
Figure 264:
Section 12 Control
Function block
SXCBR BLOCK LR_SWI OPEN CLOSE BL_OPEN BL_CLOSE BL_UPD POSOPEN POSCLOSE TR_OPEN TR_CLOSE RS_CNT XIN XPOS EXE_OP EXE_CL SUBSTED OP_BLKD CL_BLKD UPD_BLKD POSITION OPENPOS CLOSEPOS TR_POS CNT_VAL L_CAUSE IEC05000338-2-en.vsd
IEC05000338 V2 EN
12.2.7.3
Figure 265:
12.2.7.4
Table 279:
Name XPOS EXE_OP EXE_CL
Section 12 Control
Name SUBSTED OP_BLKD CL_BLKD UPD_BLKD POSITION OPENPOS CLOSEPOS TR_POS CNT_VAL L_CAUSE Type BOOLEAN BOOLEAN BOOLEAN BOOLEAN INTEGER BOOLEAN BOOLEAN INTEGER INTEGER INTEGER Description
Indication that the position is substituted Indication that the function is blocked for open commands Indication that the function is blocked for close commands Update of position indication is blocked Apparatus position indication Apparatus open position Apparatus closed position Truck position indication Operation counter value Latest value of the error indication during command
12.2.7.5
Table 280:
Name tStartMove tIntermediate AdaptivePulse tOpenPulse tClosePulse SuppressMidPos
Setting parameters
SXCBR Non group settings (basic)
Values (Range) 0.000 - 60.000 0.000 - 60.000 Not adaptive Adaptive 0.000 - 60.000 0.000 - 60.000 Disabled Enabled Unit s s s s Step 0.001 0.001 0.001 0.001 Default 0.100 0.150 Not adaptive 0.200 0.200 Enabled Description Supervision time for the apparatus to move after a command Allowed time for intermediate position Output resets when a new correct end position is reached Output pulse length for open command Output pulse length for close command Mid-position is suppressed during the time tIntermediate
12.2.8
12.2.8.1
Section 12 Control
Principle of operation
The users of the Circuit switch (SXSWI) is other functions such as for example, switch controller, protection functions, autorecloser function, or a 61850 client residing in another IED or the operator place. SXSWI executes commands, evaluates block conditions and evaluates different time supervision conditions. Only if all conditions indicate a switch operation to be allowed, SXSWI performs the execution command. In case of erroneous conditions, the function indicates an appropriate "cause" value. SXSWI has an operation counter for closing and opening commands. The counter value can be read remotely from the operator place. The value is reset from a binary input or remotely from the operator place by configuring a signal from the Single Point Generic Control 8 signals (SPC8GGIO) for example.
12.2.8.2
Local/Remote switch
One binary input signal LR_SWI is included in SXSWI to indicate the local/remote switch position from switchyard provided via the I/O board. If this signal is set to TRUE it means that change of position is allowed only from switchyard level. If the signal is set to FALSE it means that command from IED or higher level is permitted. When the signal is set to TRUE all commands (for change of position) from internal IED clients are rejected, even trip commands from protection functions are rejected. The functionality of the local/remote switch is described in figure 266.
Local= Operation at switch yard level
TR
UE
From I/O
switchLR
FAL SE
Figure 266:
Local/Remote switch
Blocking principles
SXSWI includes several blocking principles. The basic principle for all blocking signals is that they will affect commands from all other clients for example, operators place, protection functions, autorecloser and so on. The blocking possibilities are:
Section 12 Control
Block/deblock for open command. It is used to block operation for open command. Note that this block signal also affects the input OPEN for immediate command. Block/deblock for close command. It is used to block operation for close command. Note that this block signal also affects the input CLOSE for immediate command. Update block/deblock of positions. It is used to block the updating of position values. Other signals related to the position will be reset. Blocking of function, BLOCK, signal from DO (Data Object) Behavior (IEC 61850). If DO Behavior is set to "blocked" it means that the function is active, but no outputs are generated, no reporting, control commands are rejected and functional and configuration data is visible.
Substitution
The substitution part in SXSWI is used for manual set of the position for the switch. The typical use of substitution is that an operator enters a manual value because the real process value is erroneous of some reason. SXSWI will then use the manually entered value instead of the value for positions determined by the process. It is always possible to make a substitution, independently of the position indication and the status information of the I/O board. When substitution is enabled, the position values are blocked for updating and other signals related to the position are reset. The substituted values are stored in a non-volatile memory.
Time diagrams
There are two timers for supervising of the execute phase, tStartMove and tIntermediate. tStartMove supervises that the primary device starts moving after the execute output pulse is sent. tIntermediate defines the maximum allowed time for intermediate position. Figure 267 explains these two timers during the execute phase.
Section 12 Control
AdaptivePulse = TRUE
OPENPOS
CLOSEPOS
en05000097.vsd
IEC05000097 V1 EN
Figure 267:
The timers tOpenPulse and tClosePulse are the length of the execute output pulses to be sent to the primary equipment. Note that the output pulses for open and close command can have different pulse lengths. The pulses can also be set to be adaptive with the configuration parameter AdaptivePulse. Figure 268 shows the principle of the execute output pulse. The AdaptivePulse parameter will have affect on both execute output pulses.
OPENPOS
CLOSEPOS
EXE_CL tClosePulse
AdaptivePulse=FALSE
EXE_CL tClosePulse
AdaptivePulse=TRUE
en05000098.vsd
IEC05000098 V1 EN
Figure 268:
Section 12 Control
If the pulse is set to be adaptive, it is not possible for the pulse to exceed tOpenPulse or tClosePulse. The execute output pulses are reset when: If the start position indicates bad state (OPENPOS=1 and CLOSEPOS =1) when a command is executed the execute output pulse resets only when timer tOpenPulse or tClosePulse has elapsed. the new expected final position is reached and the configuration parameter AdaptivePulse is set to true the timer tOpenPulse or tClosePulse has elapsed an error occurs due to the switch does not start moving, that is, tStartMove has elapsed.
There is one exception from the first item above. If the primary device is in open position and an open command is executed or if the primary device is in close position and a close command is executed. In these cases, with the additional condition that the configuration parameter AdaptivePulse is true, the execute output pulse is always activated and resets when tStartMove has elapsed. If the configuration parameter AdaptivePulse is set to false the execution output remains active until the pulse duration timer has elapsed. An example when a primary device is open and an open command is executed is shown in figure 269.
OPENPOS
CLOSEPOS
AdaptivePulse=FALSE
AdaptivePulse=TRUE
en05000099.vsd
IEC05000099 V1 EN
Figure 269:
Section 12 Control
Function block
SXSWI BLOCK LR_SWI OPEN CLOSE BL_OPEN BL_CLOSE BL_UPD POSOPEN POSCLOSE RS_CNT XIN XPOS EXE_OP EXE_CL SUBSTED OP_BLKD CL_BLKD UPD_BLKD POSITION OPENPOS CLOSEPOS CNT_VAL L_CAUSE IEC05000339-2-en.vsd
IEC05000339 V2 EN
12.2.8.3
Figure 270:
12.2.8.4
Table 282:
Name XPOS EXE_OP EXE_CL SUBSTED OP_BLKD
Section 12 Control
Name CL_BLKD UPD_BLKD POSITION OPENPOS CLOSEPOS CNT_VAL L_CAUSE Type BOOLEAN BOOLEAN INTEGER BOOLEAN BOOLEAN INTEGER INTEGER Description
Indication that the function is blocked for close commands Update of position indication is blocked Apparatus position indication Apparatus open position Apparatus closed position Operation counter value Latest value of the error indication during command
12.2.8.5
Table 283:
Name tStartMove tIntermediate AdaptivePulse tOpenPulse tClosePulse SwitchType
Setting parameters
SXSWI Non group settings (basic)
Values (Range) 0.000 - 60.000 0.000 - 60.000 Not adaptive Adaptive 0.000 - 60.000 0.000 - 60.000 Load Break Disconnector Grounding Switch HS Groundg. Switch Disabled Enabled Unit s s s s Step 0.001 0.001 0.001 0.001 Default 3.000 15.000 Not adaptive 0.200 0.200 Disconnector Description Supervision time for the apparatus to move after a command Allowed time for intermediate position Output resets when a new correct end position is reached Output pulse length for open command Output pulse length for close command 1=LoadBreak,2=Disconnector,3=EarthSw, 4=HighSpeedEarthSw
SuppressMidPos
Enabled
12.2.9
12.2.9.1
Section 12 Control
Principle of operation
The Bay reserve (QCRSV) function handles the reservation. QCRSV function starts to operate in two ways. It starts when there is a request for reservation of the own bay or if there is a request for reservation from another bay. It is only possible to reserve the function if it is not currently reserved. The signal that can reserve the own bay is the input signal RES_RQx (x=1-8) coming from switch controller (SCWI). The signals for request from another bay are the outputs RE_RQ_B and V_RE_RQ from function block RESIN. These signals are included in signal EXCH_OUT from RESIN and are connected to RES_DATA in QCRSV. The parameters ParamRequestx (x=1-8) are chosen at reservation of the own bay only (TRUE) or other bays (FALSE). To reserve the own bay only means that no reservation request RES_BAYS is created.
12.2.9.2
If the reservation request comes from the own bay, the function QCRSV has to know which apparatus the request comes from. This information is available with the input signal RES_RQx and parameter ParamRequestx (where x=1-8 is the number of the requesting apparatus). In order to decide if a reservation request of the current bay can be permitted QCRSV has to know whether the own bay already is reserved by itself or another bay. This information is available in the output signal RESERVED. If the RESERVED output is not set, the selection is made with the output RES_GRTx (where x=1-8 is the number of the requesting apparatus), which is connected to switch controller SCSWI. If the bay already is reserved the command sequence will be reset and the SCSWI will set the attribute "1-of-n-control" in the "cause" signal.
When the function QCRSV receives a request from an apparatus in the own bay that requires other bays to be reserved as well, it checks if it already is reserved. If not, it will send a request to the other bays that are predefined (to be reserved) and wait for their response (acknowledge). The request of reserving other bays is done by activating the output RES_BAYS. When it receives acknowledge from the bays via the input RES_DATA, it sets the output RES_GRTx (where x=1-8 is the number of the requesting apparatus). If not acknowledgement from all bays is received within a certain time defined in SCSWI (tResResponse), the SCSWI will reset the reservation and set the attribute "1-of-ncontrol" in the "cause" signal.
When another bay requests for reservation, the input BAY_RES in corresponding function block RESIN is activated. The signal for reservation request is grouped into the output signal EXCH_OUT in RESIN, which is connected to input RES_DATA in
Section 12 Control
QCRSV. If the bay is not reserved, the bay will be reserved and the acknowledgment from output ACK_T_B is sent back to the requested bay. If the bay already is reserved the reservation is kept and no acknowledgment is sent.
If QCRSV function is blocked (input BLK_RES is set to true) the reservation is blocked. That is, no reservation can be made from the own bay or any other bay. This can be set, for example, via a binary input from an external device to prevent operations from another operator place at the same time. The reservation function can also be overridden in the own bay with the OVERRIDE input signal, that is, reserving the own bay without waiting for the external acknowledge.
If only one instance of QCRSV is used for a bay that is, use of up to eight apparatuses, the input EXCH_IN must be set to FALSE. If there are more than eight apparatuses in the bay there has to be one additional QCRSV. The two QCRSV functions have to communicate and this is done through the input EXCH_IN and EXCH_OUT according to figure 271. If more then one QCRSV are used, the execution order is very important. The execution order must be in the way that the first QCRSV has a lower number than the next one.
Section 12 Control
QCRSV EXCH_IN RES_ GRT1 RES_RQ1 RES_ GRT2 RES_RQ2 RES_ GRT3 RES_RQ3 RES_ GRT4 RES_RQ4 RES_ GRT5 RES_RQ5 RES_ GRT6 RES_RQ6 RES_ GRT7 RES_RQ7 RES_ GRT8 RES_RQ8 RES_ BAYS BLK_ RES ACK_TO_B OVERRIDE RESERVED RES_ DATA EXCH_ OUT
QCRSV EXCH_IN RES_ GRT1 RES_RQ1 RES_ GRT2 RES_RQ2 RES_ GRT3 RES_RQ3 RES_ GRT4 RES_RQ4 RES_ GRT5 RES_RQ5 RES_ GRT6 RES_RQ6 RES_ GRT7 RES_RQ7 RES_ GRT8 RES_RQ8 RES_ BAYS BLK_ RES ACK_TO_B OVERRIDE RESERVED RES_ DATA EXCH_ OUT
OR
RES_ BAYS
OR
ACK_TO_B
OR
RESERVED
ANSI05000088_2_en.vsd
ANSI05000088 V2 EN
Figure 271:
12.2.9.3
Function block
QCRSV EXCH_IN RES_RQ1 RES_RQ2 RES_RQ3 RES_RQ4 RES_RQ5 RES_RQ6 RES_RQ7 RES_RQ8 BLK_RES OVERRIDE RES_DATA RES_GRT1 RES_GRT2 RES_GRT3 RES_GRT4 RES_GRT5 RES_GRT6 RES_GRT7 RES_GRT8 RES_BAYS ACK_TO_B RESERVED EXCH_OUT IEC05000340-2-en.vsd
IEC05000340 V2 EN
Figure 272:
Section 12 Control
12.2.9.4 Input and output signals
Table 284:
Name EXCH_IN RES_RQ1 RES_RQ2 RES_RQ3 RES_RQ4 RES_RQ5 RES_RQ6 RES_RQ7 RES_RQ8 BLK_RES OVERRIDE RES_DATA
Table 285:
Name RES_GRT1 RES_GRT2 RES_GRT3 RES_GRT4 RES_GRT5 RES_GRT6 RES_GRT7 RES_GRT8 RES_BAYS ACK_TO_B RESERVED EXCH_OUT
Section 12 Control
Setting parameters
12.2.9.5
Table 286:
Name tCancelRes ParamRequest1 ParamRequest2 ParamRequest3 ParamRequest4 ParamRequest5 ParamRequest6 ParamRequest7 ParamRequest8
12.2.10
12.2.10.1
12.2.10.2
Principle of operation
The reservation input (RESIN) function is based purely on Boolean logic conditions. The logic diagram in figure 273 shows how the output signals are created. The inputs of the function block are connected to a receive function block representing signals transferred over the station bus from another bay.
Section 12 Control
EXCH_IN
INT BIN
AND FutureUse OR
ACK_F_B
BAY_ACK
OR
ANY_ACK
AND BAY_VAL OR
VALID_TX
OR
RE_RQ_B
BAY_RES
AND OR V _RE_RQ
BIN INT
EXCH_OUT
INT..Integer BIN..Binary
ANSI05000089 V1 EN
en05000089_ansi.vsd
Figure 273:
Figure 274 describes the principle of the data exchange between all RESIN modules in the current bay. There is one RESIN function block per "other bay" used in the reservation mechanism. The output signal EXCH_OUT in the last RESIN functions are connected to the module bay reserve (QCRSV) that handles the reservation function in the own bay. The value to the input EXCH_IN on the first RESIN module in the chain has the integer value 5. This is provided by the use of instance number one of the function block RESIN, where the input EXCH_IN is set to #5, but is hidden for the user.
Section 12 Control
Bay 1
RESIN BAY_ACK ACK_F_B BAY_VAL ANY_ACK BAY_RES VALID_TX RE_RQ_B V_RE_RQ EXCH_OUT
Bay 2
RESIN EXCH_IN ACK_F_B BAY_ACK ANY_ACK BAY_VAL VALID_TX BAY_RES RE_RQ_B V_RE_RQ EXCH_OUT
Bay n
RESIN EXCH_IN ACK_F_B BAY_ACK ANY_ACK BAY_VAL VALID_TX BAY_RES RE_RQ_B V_RE_RQ EXCH_OUT
QCRSV RES_DATA
en05000090.vsd
IEC05000090 V2 EN
Figure 274:
12.2.10.3
Function block
RESIN1 BAY_ACK BAY_VAL BAY_RES ACK_F_B ANY_ACK VALID_TX RE_RQ_B V_RE_RQ EXCH_OUT IEC05000341-2-en.vsd
IEC05000341 V2 EN
Figure 275:
RESIN2 EXCH_IN BAY_ACK BAY_VAL BAY_RES ACK_F_B ANY_ACK VALID_TX RE_RQ_B V_RE_RQ EXCH_OUT IEC09000807_1_en.vsd
IEC09000807 V1 EN
Figure 276:
Section 12 Control
12.2.10.4 Input and output signals
Table 287:
Name BAY_ACK BAY_VAL BAY_RES
Table 288:
Name ACK_F_B ANY_ACK VALID_TX RE_RQ_B V_RE_RQ EXCH_OUT
Table 289:
Name EXCH_IN BAY_ACK BAY_VAL BAY_RES
Section 12 Control
Table 290:
Name ACK_F_B ANY_ACK VALID_TX RE_RQ_B V_RE_RQ EXCH_OUT
12.2.10.5
Table 291:
Name FutureUse
Setting parameters
RESIN1 Non group settings (basic)
Values (Range) Bay in use Bay future use Unit Step Default Bay in use Description The bay for this ResIn block is for future use
Table 292:
Name FutureUse
12.3
12.3.1
Interlocking (3)
Introduction
The interlocking functionality blocks the possibility to operate high-voltage switching devices, for instance when a disconnector is under load, in order to prevent material damage and/or accidental human injury. Each control IED has interlocking functions for different switchyard arrangements, each handling the interlocking of one bay. The interlocking functionality in each IED is not dependent on any central function. For the station-wide interlocking, the IEDs communicate via the station bus or by using hard wired binary inputs/outputs. The interlocking conditions depend on the circuit configuration and status of the system at any given time.
585
The interlocking function consists of software modules located in each control IED. The function is distributed and not dependent on any central function. Communication between modules in different bays is performed via the station bus. The reservation function (see section "Introduction") is used to ensure that HV apparatuses that might affect the interlock are blocked during the time gap, which arises between position updates. This can be done by means of the communication system, reserving all HV apparatuses that might influence the interlocking condition of the intended operation. The reservation is maintained until the operation is performed. After the selection and reservation of an apparatus, the function has complete data on the status of all apparatuses in the switchyard that are affected by the selection. Other operators cannot interfere with the reserved apparatus or the status of switching devices that may affect it. The open or closed positions of the HV apparatuses are inputs to software modules distributed in the control IEDs. Each module contains the interlocking logic for a bay. The interlocking logic in a module is different, depending on the bay function and the switchyard arrangements, that is, double-breaker or breaker-and-a-half bays have different modules. Specific interlocking conditions and connections between standard interlocking modules are performed with an engineering tool. Bay-level interlocking signals can include the following kind of information: Positions of HV apparatuses (sometimes per phase) Valid positions (if evaluated in the control module) External release (to add special conditions for release) Line voltage (to block operation of line grounding switch) Output signals to release the HV apparatus
The interlocking module is connected to the surrounding functions within a bay as shown in figure 277.
Section 12 Control
Interlocking module
152
en04000526_ansi.vsd
ANSI04000526 V1 EN
Figure 277:
Bays communicate via the station bus and can convey information regarding the following: Ungrounded busbars Busbars connected together Other bays connected to a busbar Received data from other bays is valid
Section 12 Control
Station bus
Bay 1 Disc 189 and 289 closed Bay n Disc 189 and 289 closed Bus coupler WA1 ungrounded WA1 ungrounded WA1 and WA2 interconn WA1 and WA2 interconn in other bay
WA1 not grounded WA2 not grounded WA1 and WA2 interconn
... ..
WA1 not grounded WA2 not grounded WA1 and WA2 interconn
WA1 WA2 189 289 189 289 152 989 189 152 152 989 289 189G 289G
en05000494_ansi.vsd
ANSI05000494 V1 EN
Figure 278:
When invalid data such as intermediate position, loss of a control IED, or input board error are used as conditions for the interlocking condition in a bay, a release for execution of the function will not be given. On the local HMI an override function exists, which can be used to bypass the interlocking function in cases where not all the data required for the condition is valid. For all interlocking modules these general rules apply: The interlocking conditions for opening or closing of disconnectors and grounding switches are always identical. Grounding switches on the line feeder end, for example, rapid grounding switches, are normally interlocked only with reference to the conditions in the bay where they are located, not with reference to switches on the other side of the line. So a line voltage indication may be included into line interlocking modules. If there is no line voltage supervision within the bay, then the appropriate inputs must be set to no voltage, and the operator must consider this when operating. Grounding switches can only be operated on isolated sections for example, without load/voltage. Circuit breaker contacts cannot be used to isolate a section, that is, the status of the circuit breaker is irrelevant as far as the grounding switch operation is concerned. Disconnectors cannot break power current or connect different voltage systems. Disconnectors in series with a circuit breaker can only be operated if the circuit breaker is open, or if the disconnectors operate in parallel with other closed connections. Other disconnectors can be operated if one side is completely
Section 12 Control
isolated, or if the disconnectors operate in parallel to other closed connections, or if they are grounding on both sides. Circuit breaker closing is only interlocked against running disconnectors in its bay or additionally in a transformer bay against the disconnectors and grounding switch on the other side of the transformer, if there is no disconnector between CB and transformer. Circuit breaker opening is only interlocked in a bus-coupler bay, if a bus bar transfer is in progress.
To make the implementation of the interlocking function easier, a number of standardized and tested software interlocking modules containing logic for the interlocking conditions are available: Line for double and transfer busbars, ABC_LINE (3) Bus for double and transfer busbars, ABC_BC (3) Transformer bay for double busbars, AB_TRAFO (3) Bus-section breaker for double busbars, A1A2_BS (3) Bus-section disconnector for double busbars, A1A2_DC (3) Busbar grounding switch, BB_ES (3) Double CB Bay, DB_BUS_A(3), DB_LINE(3), DB_BUS_B(3) Breaker-and-a-half diameter, BH_LINE_A, BH_CONN, BH_LINE_B (3)
The interlocking conditions can be altered, to meet the customer specific requirements, by adding configurable logic by means of the graphical configuration tool PCM600. The inputs Qx_EXy on the interlocking modules are used to add these specific conditions. The input signals EXDU_xx shall be set to true if there is no transmission error at the transfer of information from other bays. Required signals with designations ending in TR are intended for transfer to other bays.
12.3.3
12.3.3.1
Section 12 Control
12.3.3.2 Logic diagram
The function contains logic to enable the open and close commands respectively if the interlocking conditions are fulfilled. That means also, if the switch has a defined end position for example, open, then the appropriate enable signal (in this case EN_OPEN) is false. The enable signals EN_OPEN and EN_CLOSE can be true at the same time only in the intermediate and bad position state and if they are enabled by the interlocking function. The position inputs come from the logical nodes Circuit breaker/ Circuit switch (SXCBR/SXSWI) and the enable signals come from the interlocking logic. The outputs are connected to the logical node Switch controller (SCSWI). One instance per switching device is needed.
POSOPEN POSCLOSE SCILO
XOR NOT AND
EN_OPEN OR
AND
OPEN_EN CLOSE_EN
AND
EN_CLOSE OR
AND
en04000525_ansi.vsd
ANSI04000525 V1 EN
Figure 279:
12.3.3.3
Function block
SCILO (3) POSOPEN EN_OPEN POSCLOSE EN_CLOSE OPEN_EN CLOSE_EN ANSI05000359-1-en.vsd
ANSI05000359 V1 EN
Figure 280:
12.3.3.4
Section 12 Control
Table 294:
Name EN_OPEN EN_CLOSE
12.3.4
12.3.4.1
89G
en04000504.vsd
ANSI04000504 V1 EN
Figure 281:
12.3.4.2
Function block
BB_ES (3) 89G_OP 89GREL 89G_CL 89GITL BB_DC_OP BBGSOPTR VP_BB_DC BBGSCLTR EXDU_BB ANSI05000347-2-en.vsd
ANSI05000347 V2 EN
Figure 282:
Section 12 Control
12.3.4.3 Logic diagram
BB_ES VP_BB_DC BB_DC_OP EXDU_BB 89G_OP 89G_CL
AND
NOT
ANSI04000546 V1 EN
12.3.4.4
Table 296:
Name QCREL QCITL BBESOPTR BBESCLTR
12.3.5
12.3.5.1
Section 12 Control
WA1 (A1)
WA2 (A2)
189G
189 152
289
289G
389G
489G
A1A2_BS
en04000516_ansi.vsd
ANSI04000516 V1 EN
Figure 283:
12.3.5.2
Function block
A1A2_BS (3) 152_OP 152OPREL 152_CL 152OPITL 189_OP 152CLREL 189_CL 152CLITL 289_OP 189REL 289_CL 189ITL 389G_OP 289REL 389G_CL 289ITL 489G_OP 389GREL 489G_CL 389GITL S189G_OP 489GREL S189G_CL 489GITL S289G_OP S1S2OPTR S289G_CL S1S2CLTR BBTR_OP 189OPTR VP_BBTR 189CLTR EXDU_12 289OPTR EXDU_89G 289CLTR 152O_EX1 VPS1S2TR 152O_EX2 VP189TR 152O_EX3 VP289TR 189_EX1 189_EX2 289_EX1 289_EX2 ANSI05000348-2-en.vsd
ANSI05000348 V2 EN
Figure 284:
Section 12 Control
12.3.5.3 Logic diagram
152_OP 152_CL 189_OP 189_CL 289_OP 289_CL 389G_OP 389G_CL 489G_OP 489G_CL S1189G_OP S1189G_CL S2289G_OP S2289G_CL VP189 189_OP 152O_EX1 VP289 289_OP 152O_EX2 VP_BBTR BBTR_OP EXDU_12 152O_EX3 VP189 VP289 VP152 VP389G VP489G VPS1189G 152_OP 389G_OP 489G_OP S1189G_OP EXDU_89G 189_EX1 VP389G VPS1189G 389G_CL S1189G_CL EXDU_89G 189_EX2 A1A2_BS
XOR XOR XOR XOR XOR XOR XOR AND AND OR
NOT
AND
AND AND OR
NOT
NOT
AND
en04000542_ansi.vsd
ANSI04000542 V1 EN
Section 12 Control
VP152 VP389G VP489G VPS2289G 152_OP 389G_OP 489G_OP S2289G_OP EXDU_89G 289_EX1 VP489G VPS2289G 489G_CL S2289G_CL EXDU_89G 289_EX2 VP189 VP289 189_OP 289_OP 189_OP 189_CL VP189 289_OP 289_CL VP289 189_OP 289_OP 152_OP VP189 VP289 VP152
AND
OR
NOT
289REL 289ITL
AND
AND
NOT NOT
389GREL 389GITL 489GREL 489GITL 189OPTR 189CLTR VP189TR 289OPTR 289CLTR VP289TR
OR
NOT
AND
en04000543_ansi.vsd
ANSI04000543 V1 EN
12.3.5.4
Section 12 Control
Name S2QC2_CL BBTR_OP VP_BBTR EXDU_12 EXDU_ES QA1O_EX1 QA1O_EX2 QA1O_EX3 QB1_EX1 QB1_EX2 QB2_EX1 QB2_EX2 Type BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN Default 0 0 0 0 0 0 0 0 0 0 0 0 Description
S289G on bus section 2 is in closed position No busbar transfer is in progress Status are valid for apparatuses involved in the busbar transfer No transm error from any bay connected to busbar 1 and 2 No transm error from bays containing ground sw. S189G or S289G External open condition for apparatus 152 External open condition for apparatus 152 External open condition for apparatus 152 External condition for apparatus 189 External condition for apparatus 189 External condition for apparatus 289 External condition for apparatus 289
Table 298:
Name QA1OPREL QA1OPITL QA1CLREL QA1CLITL QB1REL QB1ITL QB2REL QB2ITL QC3REL QC3ITL QC4REL QC4ITL S1S2OPTR S1S2CLTR QB1OPTR QB1CLTR QB2OPTR QB2CLTR
Section 12 Control
Name VPS1S2TR VPQB1TR VPQB2TR Type BOOLEAN BOOLEAN BOOLEAN Description Status of the apparatuses between bus section 1 and 2 are valid Switch status of 189 is valid (open or closed) Switch status of 289 is valid (open or closed)
12.3.6
12.3.6.1
52
189G 289G
A1A2_DC
ANSI04000492 V1 EN
en04000492_ansi.vsd
Figure 285:
12.3.6.2
Function block
A1A2_DC (3) 089_OP 089OPREL 089_CL 089OPITL S189G_OP 089CLREL S189G_CL 089CLITL S289G_OP DCOPTR S289G_CL DCCLTR S1DC_OP VPDCTR S2DC_OP VPS1_DC VPS2_DC EXDU_89G EXDU_BB 089C_EX1 089C_EX2 089O_EX1 089O_EX2 089O_EX3 ANSI05000349-2-en.vsd
ANSI05000349 V2 EN
Figure 286:
Section 12 Control
12.3.6.3 Logic diagram
A1A2_DC 89_OP 89_CL S1189G_OP S1189G_CL S2289G_OP S2289G_CL VPS1189G VPS2289G VPS1_DC S1189G_OP S2289G_OP S1DC_OP EXDU_89G EXDU_BB QBOP_EX1 VPS1189 VPS2289G VPS2_DC S1189G_OP S2289G_OP S2DC_OP EXDU_89G EXDU_BB QBOP_EX2 VPS1189G VPS2289G S1189G_CL S2289G_CL EXDU_89G QBOP_EX3
XOR
VPQB
XOR XOR
VPS1189G VPS2289G
AND
OR
NOT
89OPREL 89OPITL
AND
AND
en04000544_ansi.vsd
ANSI04000544 V1 EN
IEC04000545 V1 EN
Section 12 Control
Input and output signals
Table 299:
Name QB_OP QB_CL S1QC1_OP S1QC1_CL S2QC2_OP S2QC2_CL S1DC_OP S2DC_OP VPS1_DC VPS2_DC EXDU_ES EXDU_BB QBCL_EX1 QBCL_EX2 QBOP_EX1 QBOP_EX2 QBOP_EX3
12.3.6.4
Table 300:
Name QBOPREL QBOPITL QBCLREL QBCLITL DCOPTR DCCLTR VPDCTR
12.3.7
Section 12 Control
12.3.7.1 Introduction
The interlocking for bus-coupler bay (ABC_BC, 3) function is used for a bus-coupler bay connected to a double busbar arrangement according to figure 287. The function can also be used for a single busbar arrangement with transfer busbar or double busbar arrangement without transfer busbar.
WA1 (A) WA2 (B) WA7 (C) 189 289 2089 789
189G
152
289G
en04000514_ansi.vsd
ANSI04000514 V1 EN
Figure 287:
Section 12 Control
Function block
ABC_BC (3) 152_OP 152OPREL 152_CL 152OPITL 189_OP 152CLREL 189_CL 152CLITL 289_OP 189REL 289_CL 189ITL 789_OP 289REL 789_CL 289ITL 2089_OP 789REL 2089_CL 789ITL 189G_OP 2089REL 189G_CL 2089ITL 289G_OP 189GREL 289G_CL 189GITL 1189G_OP 289GREL 1189G_CL 289GITL 2189G_OP 189OPTR 2189G_CL 189CLTR 7189G_OP 22089OTR 7189G_CL 22089CTR BBTR_OP 789OPTR BC_12_CL 789CLTR VP_BBTR 1289OPTR VP_BC_12 1289CLTR EXDU_89G BC12OPTR EXDU_12 BC12CLTR EXDU_BC BC17OPTR 152O_EX1 BC17CLTR 152O_EX2 BC27OPTR 152O_EX3 BC27CLTR 189_EX1 VP189TR 189_EX2 V22089TR 189_EX3 VP789TR 289_EX1 VP1289TR 289_EX2 VPBC12TR 289_EX3 VPBC17TR 2089_EX1 VPBC27TR 2089_EX2 789_EX1 789_EX2 ANSI05000350-2-en.vsd
ANSI05000350 V2 EN
12.3.7.2
Figure 288:
Section 12 Control
12.3.7.3 Logic diagram
152_OP 152_CL 189_OP 189_CL 2089_OP 2089_CL 789_OP 789_CL 289_OP 289_CL 189G_OP 189G_CL 289G_OP 289G_CL 1189G_OP 1189G_CL 2189G_OP 2189G_CL 7189G_OP 7189G_CL VP189 189_OP 152O_EX1 VP2089 2089_OP 152O_EX2 VP_BBTR BBTR_OP EXDU_12 152O_EX3 VP189 VP289 VP789 VP2089
ANSI04000533 V1 EN
ABC_BC
XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR AND AND OR
VP152 VP189 VP2089 VP789 VP289 VP189G VP289G VP1189G VP2189G VP7189G 152OPREL 152OPITL
NOT
AND
AND
NOT
152CLREL 152CLITL
en04000533_ansi.vsd
VP152 VP289 VP189G VP289G VP1189G 152_OP 289_OP 189G_OP 289G_OP 1189G_OP EXDU_89G 189_EX1 VP289 VP_BC_12 289_CL BC_12_CL EXDU_BC 189_EX2 VP189G VP1189G 189G_CL 1189G_CL EXDU_89G 189_EX3
AND
OR
NOT
189REL 189ITL
AND
AND
en04000534_ansi.vsd
ANSI04000534 V1 EN
Section 12 Control
VP152 VP189 VP189G VP289G VP2189G 152_OP 189_OP 189G_OP 289G_OP 2189G_OP EXDU_89G 289_EX1 VP189 VP_BC_12 189_CL BC_12_CL EXDU_BC 289_EX2 VP189G VP2189G 189G_CL 2189G_CL EXDU_89G 289_EX3
AND
OR
NOT
289REL 289ITL
AND
AND
en04000535_ansi.vsd
ANSI04000535 V1 EN
VP152 VP2089 VP189G VP289G VP7189G 152_OP 2089_OP 189G_OP 289G_OP 7189G_OP EXDU_89G 789_EX1 VP289G VP7189G 289G_CL 7189G_CL EXDU_89G 789_EX2 VP152 VP789 VP189G VP289G VP2189G 152_OP 789_OP 189G_OP 289G_OP 2189G_OP EXDU_89G 2089_EX1 VP289G VP2189G 289G_CL 2189G_CL EXDU_89G 2089_EX2
AND
OR
NOT
789REL 789ITL
AND
AND
OR
NOT
2089REL 2089ITL
AND
en04000536_ansi.vsd
ANSI04000536 V1 EN
Section 12 Control
VP189 VP2089 VP789 VP289 189_OP 2089_OP 789_OP 289_OP 189_OP 189_CL VP189 2089_OP 289_OP VP2089 VP289 789_OP 789_CL VP789 189_OP 289_OP VP189 VP289 152_OP 189_OP 2089_OP VP152 VP189 VP2089 152_OP 189_OP 789_OP VP152 VP189 VP789 152_OP 289_OP 789_OP VP152 VP289 VP789
AND
NOT NOT
AND AND
NOT
189OPTR 189CLTR VP189TR 22089OTR 22089CTR V22089TR 789OPTR 789CLTR VP789TR 1289OPTR 1289CLTR VP1289TR BC12OPTR BC12CLTR VPBC12TR BC17OPTR BC17CLTR VPBC17TR BC27OPTR BC27CLTR VPBC27TR
OR AND OR
NOT
NOT
AND
OR
NOT
AND
OR
NOT
AND
en04000537_ansi.vsd
ANSI04000537 V1 EN
12.3.7.4
Section 12 Control
Name QC2_OP QC2_CL QC11_OP QC11_CL QC21_OP QC21_CL QC71_OP QC71_CL BBTR_OP BC_12_CL VP_BBTR VP_BC_12 EXDU_ES EXDU_12 EXDU_BC QA1O_EX1 QA1O_EX2 QA1O_EX3 QB1_EX1 QB1_EX2 QB1_EX3 QB2_EX1 QB2_EX2 QB2_EX3 QB20_EX1 QB20_EX2 QB7_EX1 QB7_EX2 Type BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description 289G is in open position 289G is in closed position Grounding switch 1189G on busbar WA1 is in open position Grounding switch 1189G on busbar WA1 is in closed position Grounding switch 2189G on busbar WA2 is in open position Grounding switch 2189G on busbar WA2 is in closed position Grounding switch 7189G on busbar WA7 is in open position Grounding switch 7189G on busbar WA7 is in closed position No busbar transfer is in progress A bus coupler connection exists between busbar WA1 and WA2 Status are valid for apparatuses involved in the busbar transfer Status of the bus coupler apparatuses between WA1 and WA2 are valid No transm error from any bay containing grounding switches No transm error from any bay connected to WA1/WA2 busbars No transmission error from any other bus coupler bay External open condition for apparatus 152 External open condition for apparatus 152 External open condition for apparatus 152 External condition for apparatus 189 External condition for apparatus 189 External condition for apparatus 189 External condition for apparatus 289 External condition for apparatus 289 External condition for apparatus 289 External condition for apparatus 2089 External condition for apparatus 2089 External condition for apparatus 789 External condition for apparatus 789
Section 12 Control
Table 302:
Name QA1OPREL QA1OPITL QA1CLREL QA1CLITL QB1REL QB1ITL QB2REL QB2ITL QB7REL QB7ITL QB20REL QB20ITL QC1REL QC1ITL QC2REL QC2ITL QB1OPTR QB1CLTR QB220OTR QB220CTR QB7OPTR QB7CLTR QB12OPTR QB12CLTR BC12OPTR BC12CLTR BC17OPTR BC17CLTR BC27OPTR BC27CLTR VPQB1TR
Section 12 Control
Name VQB220TR VPQB7TR VPQB12TR VPBC12TR VPBC17TR VPBC27TR Type BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN Description Switch status of 289 and 2089 are valid (open or closed) Switch status of 789 is valid (open or closed) Switch status of 189 and 289 are valid (open or closed) Status of the bus coupler apparatuses between WA1 and WA2 are valid Status of the bus coupler app. between WA1 and WA7 are valid Status of the bus coupler app. between WA2 and WA7 are valid
12.3.8
12.3.8.1
Section 12 Control
6189
152
6289
989 989G
BH_CONN
en04000513_ansi.vsd
ANSI04000513 V1 EN
Figure 289:
Three types of interlocking modules per diameter are defined. BH_LINE_A (3) and BH_LINE_B (3) are the connections from a line to a busbar. BH_CONN (3) is the connection between the two lines of the diameter in the breaker-and-a-half switchyard layout.
Section 12 Control
Function blocks
BH_LINE_A (3) 152_OP 152CLREL 152_CL 152CLITL 689_OP 689REL 689_CL 689ITL 189_OP 189REL 189_CL 189ITL 189G_OP 189GREL 189G_CL 189GITL 289G_OP 289GREL 289G_CL 289GITL 389G_OP 389GREL 389G_CL 389GITL 989_OP 989REL 989_CL 989ITL 989G_OP 989GREL 989G_CL 989GITL C152_OP 189OPTR C152_CL 189CLTR C6189_OP VP189TR C6189_CL C189G_OP C189G_CL C289G_OP C289G_CL 1189G_OP 1189G_CL VOLT_OFF VOLT_ON EXDU_89G 689_EX1 689_EX2 189_EX1 189_EX2 989_EX1 989_EX2 989_EX3 989_EX4 989_EX5 989_EX6 989_EX7 ANSI05000352-2-en.vsd
ANSI05000352 V2 EN
12.3.8.2
Figure 290:
Section 12 Control
BH_LINE_B (3) 152_OP 152CLREL 152_CL 152CLITL 689_OP 689REL 689_CL 689ITL 289_OP 289REL 289_CL 289ITL 189G_OP 189GREL 189G_CL 189GITL 289G_OP 289GREL 289G_CL 289GITL 389G_OP 389GREL 389G_CL 389GITL 989_OP 989REL 989_CL 989ITL 989G_OP 989GREL 989G_CL 989GITL C152_OP 289OPTR C152_CL 289CLTR C6289_OP VP289TR C6289_CL C189G_OP C189G_CL C289G_OP C289G_CL 2189G_OP 2189G_CL VOLT_OFF VOLT_ON EXDU_89G 689_EX1 689_EX2 289_EX1 289_EX2 989_EX1 989_EX2 989_EX3 989_EX4 989_EX5 989_EX6 989_EX7 ANSI05000353-2-en.vsd
ANSI05000353 V2 EN
Figure 291:
BH_CONN (3) 152_OP 152CLREL 152_CL 152CLITL 6189_OP 6189REL 6189_CL 6189ITL 6289_OP 6289REL 6289_CL 6289ITL 189G_OP 189GREL 189G_CL 189GITL 289G_OP 289GREL 289G_CL 289GITL 1389G_OP 1389G_CL 2389G_OP 2389G_CL 6189_EX1 6189_EX2 6289_EX1 6289_EX2 ANSI05000351-2-en.vsd
ANSI05000351 V2 EN
Figure 292:
610
Section 12 Control
Logic diagrams
152_OP 152_CL 6189_OP 6189_CL 6289_OP 6289_CL 189G_OP 189G_CL 289G_OP 289G_CL 1389G_OP 1389G_CL 2389G_OP 2389G_CL VP6189 VP6289 VP152 VP189G VP289G VP1389G 152_OP 189G_OP 289G_OP 1389G_OP 6189_EX1 VP189G VP1389G 189G_CL 1389G_CL 6189_EX2 VP152 VP189G VP289G VP2389G 152_OP 189G_OP 289G_OP 2389G_OP 6289_EX1 VP289G VP2389G 289G_CL 2389G_CL 6289_EX2 VP6189 VP6289 6189_OP 6289_OP BH_CONN
XOR XOR XOR XOR XOR XOR XOR AND AND OR
NOT
12.3.8.3
VP152 VP6189 VP6289 VP189G VP289G VP1389G VP2389G 152CLREL 152CLITL NOT 6189REL 61891ITL
AND
AND
OR
NOT
6289REL 6289ITL
AND
AND
NOT NOT
ANSI04000560 V1 EN
Section 12 Control
152_OP 152_CL 189_OP 189_CL 689_OP 689_CL 989G_OP 989G_CL 989_OP 989_CL 189G_OP 189G_CL 289G_OP 289G_CL 389G_OP 389G_CL C152_OP C152_CL C189G_OP C189G_CL C289G_OP C289G_CL C6189_OP C6189_CL 1189G_OP 1189G_CL VOLT_OFF VOLT_ON VP189 VP689 VP989 VP152 VP189G VP289G VP389G 152_OP 189G_OP 289G_OP 389G_OP 689_EX1 VP289G VP389G 289G_CL 389G_CL 689_EX2
BH_LINE_A XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR AND
NOT
VP152 VP189 VP689 VP989G VP989 VP189G VP289G VP389G VPC152 VPC189G VPC289G VPC6189 VP1189G VPVOLT 152CLREL 152CLITL
AND
OR
NOT
689REL 689ITL
AND
en04000554_ansi.vsd
ANSI04000554 V1 EN
Section 12 Control
VP152 VP189G VP289G VP1189G 152_OP 189G_OP 289G_OP 1189G_OP EXDU_89G 189_EX1 VP189G VP1189G 189G_CL 1189G_CL EXDU_89G 189_EX2 VP189 VP689 189_OP 689_OP VP689 VP989 VPC6189 689_OP 989_OP C6189_OP VP152 VP689 VP989G VP189G VP289G VP389G VPC152 VPC6189 VPC189G VPC289G 989_EX1 689_OP 989_EX2 152_OP 189G_OP 289G_OP 989_EX3
AND
OR
NOT
189REL 189ITL
AND
AND
NOT NOT
AND
NOT
AND
OR
NOT
989REL 989ITL
OR
AND
en04000555_ansi.vsd
ANSI04000555 V1 EN
C6189_OP 989_EX4 C152_OP C189G_OP C289G_OP 989_EX5 989G_OP 389G_OP 989_EX6 VP989G VP389G 989G_CL 389G_CL 989_EX7 VP989 VPVOLT 989_OP VOLT_OFF 189_OP 189_CL VP189
OR AND
AND
OR
AND
AND
NOT
ANSI04000556 V1 EN
Section 12 Control
152_OP 152_CL 289_OP 289_CL 689_OP 689_CL 989G_OP 989G_CL 989_OP 989_CL 189G_OP 189G_CL 289G_OP 289G_CL 389G_OP 389G_CL C152_OP C152_CL C189G_OP C189G_CL C289G_OP C289G_CL C6289_OP C6289_CL 2189G_OP 2189G_CL VOLT_OFF VOLT_ON VP289 VP689 VP989 VP152 VP189G VP289G VP389G 152_OP 189G_OP 289G_OP 389G_OP 689_EX1 VP289G VP389G 289G_CL 389G_CL 689_EX2
ANSI04000557 V1 EN
BH_LINE_B
XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR AND
NOT
VP152 VP289 VP689 VP989G VP989 VP189G VP289G VP389G VPC152 VPC189G VPC289G VPC6289 VP2189G VPVOLT 152CLREL 152CLITL 689REL 689ITL
AND
OR
NOT
AND
en04000557_ansi.vsd
Section 12 Control
VP152 VP189G VP289G VP2189G 152_OP 189G_OP 289G_OP 2189G_OP EXDU_89G 289_EX1 VP189G VP2189G 189G_CL 2189G_CL EXDU_89G 289_EX2 VP289 VP689 289_OP 689_OP VP689 VP989 VPC6289 689_OP 989_OP C6289_OP VP152 VP689 VP989G VP189G VP289G VP389G VPC152 VPC6289 VPC189G VPC289G 989_EX1 689_OP 989_EX2 152_OP 189G_OP 289G_OP 989_EX3
AND
OR
NOT
289REL 289ITL
AND
AND
NOT NOT
AND
NOT
989REL
AND OR
NOT
989ITL
OR AND
en04000558_ansi.vsd
ANSI04000558 V1 EN
C6289_OP 989_EX4 C152_OP C189G_OP C289G_OP 989_EX5 989G_OP 389G_OP 989_EX6 VP989G VP389G 989G_CL 389G_CL 989_EX7 VP989 VPVOLT 989_OP VOLT_OFF 289_OP 289_CL VP289
OR AND
AND
OR
AND
AND
NOT
ANSI04000559 V1 EN
Section 12 Control
12.3.8.4 Input and output signals
Table 303:
Name QA1_OP QA1_CL QB6_OP QB6_CL QB1_OP QB1_CL QC1_OP QC1_CL QC2_OP QC2_CL QC3_OP QC3_CL QB9_OP QB9_CL QC9_OP QC9_CL CQA1_OP CQA1_CL CQB61_OP CQB61_CL CQC1_OP CQC1_CL CQC2_OP CQC2_CL QC11_OP QC11_CL VOLT_OFF VOLT_ON EXDU_ES QB6_EX1 QB6_EX2 QB1_EX1
Section 12 Control
Name QB1_EX2 QB9_EX1 QB9_EX2 QB9_EX3 QB9_EX4 QB9_EX5 QB9_EX6 QB9_EX7 Type BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN Default 0 0 0 0 0 0 0 0 Description External condition for apparatus 189 External condition for apparatus 989 External condition for apparatus 989 External condition for apparatus 989 External condition for apparatus 989 External condition for apparatus 989 External condition for apparatus 989 External condition for apparatus 989
Table 304:
Name QA1CLREL QA1CLITL QB6REL QB6ITL QB1REL QB1ITL QC1REL QC1ITL QC2REL QC2ITL QC3REL QC3ITL QB9REL QB9ITL QC9REL QC9ITL QB1OPTR QB1CLTR VPQB1TR
Section 12 Control
Table 305:
Name QA1_OP QA1_CL QB6_OP QB6_CL QB2_OP QB2_CL QC1_OP QC1_CL QC2_OP QC2_CL QC3_OP QC3_CL QB9_OP QB9_CL QC9_OP QC9_CL CQA1_OP CQA1_CL CQB62_OP CQB62_CL CQC1_OP CQC1_CL CQC2_OP CQC2_CL QC21_OP QC21_CL VOLT_OFF VOLT_ON EXDU_ES QB6_EX1 QB6_EX2 QB2_EX1 QB2_EX2
Section 12 Control
Name QB9_EX1 QB9_EX2 QB9_EX3 QB9_EX4 QB9_EX5 QB9_EX6 QB9_EX7 Type BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN Default 0 0 0 0 0 0 0 Description External condition for apparatus 989 External condition for apparatus 989 External condition for apparatus 989 External condition for apparatus 989 External condition for apparatus 989 External condition for apparatus 989 External condition for apparatus 989
Table 306:
Name QA1CLREL QA1CLITL QB6REL QB6ITL QB2REL QB2ITL QC1REL QC1ITL QC2REL QC2ITL QC3REL QC3ITL QB9REL QB9ITL QC9REL QC9ITL QB2OPTR QB2CLTR VPQB2TR
Table 307:
Name QA1_OP QA1_CL QB61_OP
Section 12 Control
Name QB61_CL QB62_OP QB62_CL QC1_OP QC1_CL QC2_OP QC2_CL 1QC3_OP 1QC3_CL 2QC3_OP 2QC3_CL QB61_EX1 QB61_EX2 QB62_EX1 QB62_EX2 Type BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description 6189 is in closed position 6289 is in open position 6289 is in closed position 189G is in open position 189G is in closed position 289G is in open position 289G is in closed position
1389G on line 1 is in open position 1389G on line 1 is in closed position 2389G on line 2 is in open position 2389G on line 2 is in closed position External condition for apparatus 6189 External condition for apparatus 6189 External condition for apparatus 6289 External condition for apparatus 6289
Table 308:
Name QA1CLREL QA1CLITL QB61REL QB61ITL QB62REL QB62ITL QC1REL QC1ITL QC2REL QC2ITL
12.3.9
Section 12 Control
Introduction
The interlocking for a double busbar double circuit breaker bay including DB_BUS_A (3), DB_BUS_B (3) and DB_LINE (3) functions are used for a line connected to a double busbar arrangement according to figure 293.
WA1 (A) WA2 (B) 189 289
12.3.9.1
189G
489G
DB_BUS_A
152 289G
252 589G
DB_BUS_B
6189
6289 389G
989 989G
DB_LINE
en04000518_ansi.vsd
ANSI04000518 V1 EN
Figure 293:
Three types of interlocking modules per double circuit breaker bay are defined. DB_LINE (3) is the connection from the line to the circuit breaker parts that are connected to the busbars. DB_BUS_A (3) and DB_BUS_B (3) are the connections from the line to the busbars.
Section 12 Control
12.3.9.2 Function block
DB_BUS_A (3) 152_OP 152CLREL 152_CL 152CLITL 189_OP 6189REL 189_CL 6189ITL 6189_OP 189REL 6189_CL 189ITL 189G_OP 189GREL 189G_CL 189GITL 289G_OP 289GREL 289G_CL 289GITL 389G_OP 189OPTR 389G_CL 189CLTR 1189G_OP VP189TR 1189G_CL EXDU_89G 6189_EX1 6189_EX2 189_EX1 189_EX2 ANSI05000354-2-en.vsd
ANSI05000354 V2 EN
Figure 294:
DB_LINE (3) 152_OP 152_CL 252_OP 252_CL 6189_OP 6189_CL 189G_OP 189G_CL 289G_OP 289G_CL 6289_OP 6289_CL 489G_OP 489G_CL 589G_OP 589G_CL 989_OP 989_CL 389G_OP 389G_CL 989G_OP 989G_CL VOLT_OFF VOLT_ON 989_EX1 989_EX2 989_EX3 989_EX4 989_EX5
ANSI05000356-2-en.vsd
ANSI05000356 V2 EN
Figure 295:
Section 12 Control
DB_BUS_B (3) 252_OP 252CLREL 252_CL 252CLITL 289_OP 6289REL 289_CL 6289ITL 6289_OP 289REL 6289_CL 289ITL 489G_OP 489GREL 489G_CL 489GITL 589G_OP 589GREL 589G_CL 589GITL 389G_OP 289OPTR 389G_CL 289CLTR 2189G_OP VP289TR 2189G_CL EXDU_89G 6289_EX1 6289_EX2 289_EX1 289_EX2 ANSI05000355-2-en.vsd
ANSI05000355 V2 EN
Figure 296:
Section 12 Control
12.3.9.3 Logic diagrams
152_OP 152_CL 6189_OP 6189_CL 189_OP 189_CL 189G_OP 189G_CL 289G_OP 289G_CL 389G_OP 389G_CL 1189G_OP 1189G_CL VP6189 VP189 VP152 VP189G VP289G VP389G 152_OP 189G_OP 289G_OP 389G_OP 6189_EX1 VP289G VP389G 289G_CL 389G_CL 6189_EX2 VP152 VP189G VP289G VP1189G 152_OP 189G_OP 289G_OP 1189G_OP EXDU_89G 189_EX1 VP189G VP1189G 189G_CL 1189G_CL EXDU_89G 189_EX2 DB_BUS_A
XOR XOR XOR XOR XOR XOR XOR AND AND OR
NOT NOT
VP152 VP6189 VP189 VP189G VP289G VP389G VP1189G 152CLREL 152CLITL 6189REL 6189ITL
AND
AND
OR
NOT
189REL 189ITL
AND
en04000547_ansi.vsd
ANSI04000547 V1 EN
AND
NOT NOT
Section 12 Control
252_OP 252_CL 6289_OP 6289_CL 289_OP 289_CL 489G_OP 489G_CL 589G_OP 589G_CL 389G_OP 389G_CL 2189G_OP 2189G_CL VP6289 VP289 VP252 VP489G VP589G VP389G 252_OP 489G_OP 589G_OP 389G_OP 6289_EX1 VP589G VP389G 589G_CL 389G_CL 6289_EX2 VP252 VP489G VP589G VP2189G 252_OP 489G_OP 589G_OP 2189G_OP EXDU_89G 289_EX1 VP489G VP2189G 489G_CL 2189G_CL EXDU_89G 289_EX2
DB_BUS_B
XOR XOR XOR XOR XOR XOR XOR AND AND OR
NOT NOT
VP252 VP6289 VP289 VP489G VP589G VP389G VP2189G 252CLREL 252CLITL 6289REL 6289ITL
AND
AND
OR
NOT
289REL 289ITL
AND
en04000552_ansi.vsd
ANSI04000552 V1 EN
AND
NOT NOT
Section 12 Control
152_OP 152_CL 252_OP 252_CL 6189_OP 6189_CL 189G_OP 189G_CL 289G_OP 289G_CL 6289_OP 6289_CL 489G_OP 489G_CL 589G_OP 589G_CL 989_OP 989_CL 389G_OP 389G_CL 989G_OP 989G_CL VOLT_OFF VOLT_ON VP152 VP252 VP189G VP289G VP389G VP489G VP589G VP989G 152_OP 252_OP 189G_OP 289G_OP 389G_OP 489G_OP 589G_OP 989G_OP 989_EX1
DB_LINE
XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR AND OR
NOT
VP152 VP252 VP6189 VP189G VP289G VP6289 VP489G VP589G VP989 VP389G VP989G VPVOLT 989REL 989ITL
AND
en04000549_ansi.vsd
ANSI04000549 V1 EN
Section 12 Control
VP152 VP189G VP289G VP389G VP989G VP6289 152_OP 189G_OP 289G_OP 389G_OP 989G_OP 6289_OP 989_EX2 VP252 VP6189 VP389G VP489G VP589G VP989G 252_OP 6189_OP 389G_OP 489G_OP 589G_OP 989G_OP 989_EX3 VP389G VP989G VP6189 VP6289 389G_OP 989G_OP 6189_OP 6289_OP 989_EX4 VP389G VP989G 389G_CL 989G_CL 989_EX5
ANSI04000550 V1 EN
AND
OR
AND
AND
AND
en04000550_ansi.vsd
VP6189 VP6289 VP989 6189_OP 6289_OP 989_OP VP989 VPVOLT 989_OP VOLT_OFF
AND
NOT
389GREL 389GITL
AND
NOT
989GREL 989GITL
en04000551_ansi.vsd
ANSI04000551 V1 EN
12.3.9.4
Section 12 Control
Name QB61_OP QB61_CL QC1_OP QC1_CL QC2_OP QC2_CL QC3_OP QC3_CL QC11_OP QC11_CL EXDU_ES QB61_EX1 QB61_EX2 QB1_EX1 QB1_EX2 Type BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description 6189 is in open position 6189 is in closed position 189G is in open position 189G is in closed position 289G is in open position 289G is in closed position 389G is in open position 389G is in closed position
Grounding switch 1189G on busbar WA1 is in open position Grounding switch 1189G on busbar WA1 is in closed position No transm error from bay containing grounding switch 1189G External condition for apparatus 6189 External condition for apparatus 6189 External condition for apparatus 189 External condition for apparatus 189
Table 310:
Name QA1CLREL QA1CLITL QB61REL QB61ITL QB1REL QB1ITL QC1REL QC1ITL QC2REL QC2ITL QB1OPTR QB1CLTR VPQB1TR
Section 12 Control
Table 311:
Name QA1_OP QA1_CL QA2_OP QA2_CL QB61_OP QB61_CL QC1_OP QC1_CL QC2_OP QC2_CL QB62_OP QB62_CL QC4_OP QC4_CL QC5_OP QC5_CL QB9_OP QB9_CL QC3_OP QC3_CL QC9_OP QC9_CL VOLT_OFF VOLT_ON QB9_EX1 QB9_EX2 QB9_EX3 QB9_EX4 QB9_EX5
Section 12 Control
Table 312:
Name QB9REL QB9ITL QC3REL QC3ITL QC9REL QC9ITL
Table 313:
Name QA2_OP QA2_CL QB2_OP QB2_CL QB62_OP QB62_CL QC4_OP QC4_CL QC5_OP QC5_CL QC3_OP QC3_CL QC21_OP QC21_CL EXDU_ES QB62_EX1 QB62_EX2 QB2_EX1 QB2_EX2
Section 12 Control
Table 314:
Name QA2CLREL QA2CLITL QB62REL QB62ITL QB2REL QB2ITL QC4REL QC4ITL QC5REL QC5ITL QB2OPTR QB2CLTR VPQB2TR
12.3.10
12.3.10.1
Section 12 Control
WA1 (A) WA2 (B) WA7 (C) 189 289 189G 789
989G
en04000478_ansi.vsd
ANSI04000478 V1 EN
Figure 297:
Section 12 Control
Function block
ABC_LINE (3) 152CLREL 152_OP 152_CL 152CLITL 989_OP 989REL 989_CL 989ITL 189_OP 189REL 189_CL 189ITL 289_OP 289REL 289_CL 289ITL 789_OP 789REL 789_CL 789ITL 189G_OP 189GREL 189G_CL 189GITL 289G_OP 289GREL 289G_CL 289GITL 989G_OP 989GREL 989G_CL 989GITL 1189G_OP 189OPTR 1189G_CL 189CLTR 2189G_OP 289OPTR 2189G_CL 289CLTR 7189G_OP 789OPTR 7189G_CL 789CLTR BB7_D_OP 1289OPTR BC_12_CL 1289CLTR BC_17_OP VP189TR BC_17_CL VP289TR BC_27_OP VP789TR BC_27_CL VP1289TR VOLT_OFF VOLT_ON VP_BB7_D VP_BC_12 VP_BC_17 VP_BC_27 EXDU_89G EXDU_BPB EXDU_BC 989_EX1 989_EX2 189_EX1 189_EX2 189_EX3 289_EX1 289_EX2 289_EX3 789_EX1 789_EX2 789_EX3 789_EX4 ANSI05000357-2-en.vsd
ANSI05000357 V2 EN
12.3.10.2
Figure 298:
Section 12 Control
12.3.10.3 Logic diagram
152_OP 152_CL 989_OP 989_CL 189_OP 189_CL 289_OP 289_CL 789_OP 789_CL 189G_OP 189G_CL 289G_OP 289G_CL 989G_OP 989G_CL 1189G_OP 1189G_CL 2189G_OP 2189G_CL 7189G_OP 7189G_CL VOLT_OFF VOLT_ON VP152 VP189G VP289G VP989G 152_OP 189G_OP 289G_OP 989G_OP 989_EX1 VP289G VP989G 289G_CL 989G_CL 989_EX2
ABC_LINE
XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR AND
VP152 VP989 VP189 VP289 VP789 VP189G VP289G VP989G VP1189G VP2189G VP7189G VPVOLT
OR
NOT
AND
NOT
152CLREL 152CLITL
989REL 989ITL
AND
en04000527_ansi.vsd
ANSI04000527 V1 EN
Section 12 Control
VP152 VP289 VP189G VP289G VP1189G 152_OP 289_OP 189G_OP 289G_OP 1189G_OP EXDU_89G 189_EX1
AND
OR
NOT
189REL 189ITL
AND
AND
en04000528_ansi.vsd
ANSI04000528 V1 EN
Section 12 Control
VP152 VP189 VP189G VP289G VP2189G 152_OP 189_OP 189G_OP 289G_OP 2189G_OP EXDU_89G
AND
OR
NOT
289REL 289ITL
289_EX1
AND
AND
en04000529_ansi.vsd
ANSI04000529 V1 EN
Section 12 Control
VP989G VP7189G VP_BB7_D VP_BC_17 VP_BC_27 989G_OP 7189G_OP EXDU_89G BB7_D_OP EXDU_BPB BC_17_OP BC_27_OP EXDU_BC 789_EX1 VP152 VP189 VP989G VP989 VP7189G VP_BB7_D VP_BC_17 152_CL 189_CL 989G_OP 989_CL 7189G_OP EXDU_89G BB7_D_OP EXDU_BPB BC_17_CL EXDU_BC 789_EX2
AND
OR
NOT
789REL 789ITL
AND
en04000530_ansi.vsd
ANSI04000530 V1 EN
Section 12 Control
VP152 VP289 VP989G VP989 VP7189G VP_BB7_D VP_BC_27 152_CL 289_CL 989G_OP 989_CL 7189G_OP EXDU_89G BB7_D_OP EXDU_BPB BC_27_CL EXDU_BC 789_EX3 VP989G VP7189G 989G_CL 7189G_CL EXDU_89G 789_EX4 VP189 VP289 VP989 189_OP 289_OP 989_OP VP789 VP989 VPVOLT 789_OP 989_OP VOLT_OFF
ANSI04000531 V1 EN
AND
OR
AND
AND
NOT NOT
AND
NOT
989GREL 989GITL
en04000531_ansi.vsd
Section 12 Control
189_OP 189_CL VP189 289_OP 289_CL VP289 789_OP 789_CL VP789 189_OP 289_OP VP189 VP289
OR AND
189OPTR 189CLTR VP189TR 289OPTR 289CLTR VP289TR 789OPTR 789CLTR VP789TR 1289OPTR 1289CLTR VP1289TR
NOT
en04000532_ansi.vsd
ANSI04000532 V1 EN
12.3.10.4
Section 12 Control
Name QC11_OP QC11_CL QC21_OP QC21_CL QC71_OP QC71_CL BB7_D_OP BC_12_CL BC_17_OP BC_17_CL BC_27_OP BC_27_CL VOLT_OFF VOLT_ON VP_BB7_D VP_BC_12 VP_BC_17 VP_BC_27 EXDU_ES EXDU_BPB EXDU_BC QB9_EX1 QB9_EX2 QB1_EX1 QB1_EX2 Type BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description
Grounding switch 1189G on busbar WA1 is in open position Grounding switch 1189G on busbar WA1 is in closed position Grounding switch 2189G on busbar WA2 is in open position Grounding switch 2189G on busbar WA2 is in closed position Grounding switch 7189G on busbar WA7 is in open position Grounding switch 7189G on busbar WA7 is in closed position Disconnectors on busbar WA7 except in the own bay are open A bus coupler connection exists between busbar WA1 and WA2 No bus coupler connection exists between busbar WA1 and WA7 A bus coupler connection exists between busbar WA1 and WA7 No bus coupler connection exists between busbar WA2 and WA7 A bus coupler connection exists between busbar WA2 and WA7 There is no voltage on the line and not VT (fuse) failure There is voltage on the line or there is a VT (fuse) failure Switch status of the disconnectors on busbar WA7 are valid Status of the bus coupler apparatuses between WA1 and WA2 are valid Status of the bus coupler app. between WA1 and WA7 are valid Status of the bus coupler app. between WA2 and WA7 are valid No transm error from any bay containing grounding switches No transm error from any bay with disconnectors on WA7 No transmission error from any bus coupler bay External condition for apparatus 989 External condition for apparatus 989 External condition for apparatus 189 External condition for apparatus 189
Section 12 Control
Name QB1_EX3 QB2_EX1 QB2_EX2 QB2_EX3 QB7_EX1 QB7_EX2 QB7_EX3 QB7_EX4 Type BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN Default 0 0 0 0 0 0 0 0 Description External condition for apparatus 189 External condition for apparatus 289 External condition for apparatus 289 External condition for apparatus 289 External condition for apparatus 789 External condition for apparatus 789 External condition for apparatus 789 External condition for apparatus 789
Table 316:
Name QA1CLREL QA1CLITL QB9REL QB9ITL QB1REL QB1ITL QB2REL QB2ITL QB7REL QB7ITL QC1REL QC1ITL QC2REL QC2ITL QC9REL QC9ITL QB1OPTR QB1CLTR QB2OPTR QB2CLTR QB7OPTR QB7CLTR QB12OPTR QB12CLTR VPQB1TR
Section 12 Control
Name VPQB2TR VPQB7TR VPQB12TR Type BOOLEAN BOOLEAN BOOLEAN Description
Switch status of 289 is valid (open or closed) Switch status of 789 is valid (open or closed) Switch status of 189 and 289 are valid (open or closed)
12.3.11
12.3.11.1
152
en04000515_ansi.vsd
ANSI04000515 V1 EN
Figure 299:
Section 12 Control
Function block
AB_TRAFO (3) 152_OP 152CLREL 152_CL 152CLITL 189_OP 189REL 189_CL 189ITL 289_OP 289REL 289_CL 289ITL 189G_OP 189GREL 189G_CL 189GITL 289G_OP 289GREL 289G_CL 289GITL 389_OP 189OPTR 389_CL 189CLTR 489_OP 289OPTR 489_CL 289CLTR 389G_OP 1289OPTR 389G_CL 1289CLTR 1189G_OP VP189TR 1189G_CL VP289TR 2189G_OP VP1289TR 2189G_CL BC_12_CL VP_BC_12 EXDU_89G EXDU_BC 152_EX1 152_EX2 152_EX3 189_EX1 189_EX2 189_EX3 289_EX1 289_EX2 289_EX3 ANSI05000358-2-en.vsd
ANSI05000358 V2 EN
12.3.11.2
Figure 300:
Section 12 Control
12.3.11.3 Logic diagram
152_OP 152_CL 189_OP 189_CL 289_OP 289_CL 189G_OP 189G_CL 289G_OP 289G_CL 389_OP 389_CL 489_OP 489_CL 389G_OP 389G_CL 1189G_OP 1189G_CL 2189G_OP 2189G_CL VP189 VP289 VP189G VP289G VP389 VP489 VP389G 152_EX2 389G_OP 152_EX3 189G_CL 289G_CL 389G_CL 152_EX1 AB_TRAFO
XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR AND
VP152 VP189 VP289 VP189G VP289G VP389 VP489 VP389G VP1189G VP2189G 152CLREL 152CLITL
NOT
OR AND
en04000538_ansi.vsd
ANSI04000538 V1 EN
Section 12 Control
VP152 VP289 VP189G VP289G VP389G VP1189G 152_OP 289_OP 189G_OP 289G_OP 389G_OP 1189G_OP EXDU_89G 189_EX1 VP289 VP389G VP_BC_12 289_CL 389G_OP BC_12_CL EXDU_BC 189_EX2 VP189G VP289G VP389G VP1189G 189G_CL 289G_CL 389G_CL 1189G_CL EXDU_89G 189_EX3
AND
OR
NOT
189REL 189ITL
AND
AND
en04000539_ansi.vsd
ANSI04000539 V1 EN
VP152 VP189 VP189G VP289G VP389G VP2189G 152_OP 189_OP 189G_OP 289G_OP 389G_OP 2189G_OP EXDU_89G 289_EX1 VP189 VP389G VP_BC_12 189_CL 389G_OP BC_12_CL EXDU_BC 289_EX2 VP189G VP289G VP389G VP2189G 189G_CL 289G_CL 389G_CL 2189G_CL EXDU_89G 289_EX3
AND
OR
NOT
252REL 252ITL
AND
AND
en04000540_ansi.vsd
ANSI04000540 V1 EN
Section 12 Control
VP189 VP289 VP389 VP489 189_OP 289_OP 389_OP 489_OP 189_OP 189_CL VP189 289_OP 289_CL VP289 189_OP 289_OP VP189 VP289
ANSI04000541 V1 EN
AND
NOT NOT
OR AND
NOT
12.3.11.4
Section 12 Control
Name VP_BC_12 EXDU_ES EXDU_BC QA1_EX1 QA1_EX2 QA1_EX3 QB1_EX1 QB1_EX2 QB1_EX3 QB2_EX1 QB2_EX2 QB2_EX3 Type BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN Default 0 0 0 0 0 0 0 0 0 0 0 0 Description Status of the bus coupler apparatuses between WA1 and WA2 are valid No transm error from any bay containing grounding switches No transmission error from any bus coupler bay External condition for breaker 152 External condition for breaker 152 External condition for breaker 152 External condition for apparatus 189 External condition for apparatus 189 External condition for apparatus 189 External condition for apparatus 289 External condition for apparatus 289 External condition for apparatus 289
Table 318:
Name QA1CLREL QA1CLITL QB1REL QB1ITL QB2REL QB2ITL QC1REL QC1ITL QC2REL QC2ITL QB1OPTR QB1CLTR QB2OPTR QB2CLTR QB12OPTR QB12CLTR VPQB1TR VPQB2TR VPQB12TR
12.3.12.2
Logic diagram
Position including quality
POSITION POS_EVAL OPENPOS CLOSEPOS
IEC08000469-1-en.vsd
IEC08000469-1-EN V1 EN
Only the value, open/close, and status is used in this function. Time information is not used.
Input position (Value) 0 (Breaker intermediate) 1 (Breaker open) 2 (Breaker closed) 3 (Breaker faulty) Any Any Signal quality Good Good Good Good Invalid Oscillatory Output OPENPOS 0 1 0 0 0 0 Output CLOSEPOS 0 0 1 0 0 0
12.3.12.3
Function block
POSITION POS_EVAL OPENPOS CLOSEPOS IEC09000079_1_en.vsd
IEC09000079 V1 EN
Figure 301:
12.3.12.4
Section 12 Control
Table 320:
Name OPENPOS CLOSEPOS
12.4
Logic rotating switch for function selection and LHMI presentation SLGGIO
Function description Logic rotating switch for function selection and LHMI presentation IEC 61850 identification SLGGIO IEC 60617 identification ANSI/IEEE C37.2 device number -
12.4.1
Introduction
The logic rotating switch for function selection and LHMI presentation (SLGGIO) (or the selector switch function block) is used to get a selector switch functionality similar to the one provided by a hardware selector switch. Hardware selector switches are used extensively by utilities, in order to have different functions operating on pre-set values. Hardware switches are however sources for maintenance issues, lower system reliability and an extended purchase portfolio. The logic selector switches eliminate all these problems.
12.4.2
Principle of operation
The logic rotating switch for function selection and LHMI presentation (SLGGIO) function has two operating inputs UP and DOWN. When a signal is received on the UP input, the block will activate the output next to the present activated output, in ascending order (if the present activated output is 3 for example and one operates the UP input, then the output 4 will be activated). When a signal is received on the DOWN input, the block will activate the output next to the present activated output, in descending order (if the present activated output is 3 for example and one operates the DOWN input, then the output 2 will be activated). Depending on the output settings the output signals can be steady or pulsed. In case of steady signals, in case of UP or DOWN operation, the previously active output will be deactivated. Also, depending on the settings one can have a time delay between the UP or DOWN activation signal positive front and the output activation. Besides the inputs visible in the application configuration in the Application Configuration tool, there are other possibilities that will allow an user to set the desired
649
Section 12 Control
position directly (without activating the intermediate positions), either locally or remotely, using a select before execute dialog. One can block the function operation, by activating the BLOCK input. In this case, the present position will be kept and further operation will be blocked. The operator place (local or remote) is specified through the PSTO input. If any operation is allowed the signal INTONE from the Fixed signal function block can be connected. SLGGIO function block has also an integer value output, that generates the actual position number. The positions and the block names are fully settable by the user. These names will appear in the menu, so the user can see the position names instead of a number.
Section 12 Control
Functionality and behaviour
Control Measurements Events Disturbance records Settings Diagnostics Test Reset Authorization Language Control Single Line Diagram Commands Ctrl/Com Single Command Selector Switch (GGIO)
12.4.2.1
1
../Ctrl/Com/Sel Sw SLGGIO1 SLGGIO2 .. .. SLGGIO15
2
../Com/Sel Sw/ SLGGIO3 Damage ctrl
3 4
P:Disc All OK
N: Disc Fe Cancel
4 5
../Com/Sel Sw/ DmgCtrl Damage ctrl:
E
Modify the position with arrows. The pos will not be modified (outputs will not be activated) until you press the E-button for O.K.
IEC06000420 V2 EN
The dialog window that appears shows the present position (P:) and the new position (N:), both in clear names, given by the user (max. 13 characters).
IEC06000420-2-en.vsd
Figure 302: Example 1 on handling the switch from the local HMI. From the local HMI:
1 SLGGIO instances in the ACT application configuration 2 Switch name given by the user (max 13 characters) 3 Position number, up to 32 positions 4 Change position 5 New position
12.4.2.2
Graphical display
There are two possibilities for SLGGIO
651
Section 12 Control
if it is used just for the monitoring, the switches will be listed with their actual position names, as defined by the user (max. 13 characters). if it is used for control, the switches will be listed with their actual positions, but only the first three letters of the name will be used.
In both cases, the switch full name will be shown, but the user has to redefine it when building the Graphical Display Editor, under the "Caption". If used for the control, the following sequence of commands will ensure:
Control Measurements Events Disturbance records Settings Diagnostics Test Reset Authorization Language Control Single Line Diagram Commands
Change to the "Switches" page of the SLD by left-right arrows. Select switch by up-down arrows
../Control/SLD/Switch SMBRREC control WFM Pilot setup OFF Damage control DAL
Open
Close
../Control/SLD/Switch SMBRREC control WFM Pilot setup OFF P: Disc OK N: Disc Fe Cancel
Select switch. Press the Open or Close key. A dialog box appears.
E
The pos will not be modified (outputs will not be activated) until you press the E-button for O.K.
../Control/SLD/Switch SMBRREC control WFM Pilot setup OFF Damage control DFW
ANSI06000421-2-en.vsd
ANSI06000421 V2 EN
Figure 303: Example 2 on handling the switch from the local HMI. From the single line diagram on local HMI.
12.4.3
Figure 304:
12.4.4
Section 12 Control
Table 322:
Name SWPOS01 SWPOS02 SWPOS03 SWPOS04 SWPOS05 SWPOS06 SWPOS07 SWPOS08 SWPOS09 SWPOS10 SWPOS11 SWPOS12 SWPOS13 SWPOS14 SWPOS15 SWPOS16 SWPOS17 SWPOS18 SWPOS19 SWPOS20 SWPOS21 SWPOS22 SWPOS23 SWPOS24 SWPOS25 SWPOS26 SWPOS27 SWPOS28 SWPOS29 SWPOS30 SWPOS31 SWPOS32 SWPOSN
12.4.5
Table 323:
Name Operation NrPos OutType tPulse tDelay StopAtExtremes
12.5
12.5.1
Introduction
The Selector mini switch VSGGIO function block is a multipurpose function used for a variety of applications, as a general purpose switch. VSGGIO can be controlled from the menu or from a symbol on the single line diagram (SLD) on the local HMI.
12.5.2
Principle of operation
Selector mini switch (VSGGIO) function can be used for double purpose, in the same way as switch controller (SCSWI) functions are used: for indication on the single line diagram (SLD). Position is received through the IPOS1 and IPOS2 inputs and distributed in the configuration through the POS1 and POS2 outputs, or to IEC 61850 through reporting, or GOOSE. for commands that are received via the local HMI or IEC 61850 and distributed in the configuration through outputs CMDPOS12 and CMDPOS21. The output CMDPOS12 is set when the function receives a CLOSE command from the local HMI when the SLD is displayed and the object is chosen.
655
Section 12 Control
The output CMDPOS21 is set when the function receives an OPEN command from the local HMI when the SLD is displayed and the object is chosen. It is important for indication in the SLD that the a symbol is associated with a controllable object, otherwise the symbol won't be displayed on the screen. A symbol is created and configured in GDE tool in PCM600. The PSTO input is connected to the Local remote switch to have a selection of operators place, operation from local HMI (Local) or through IEC 61850 (Remote). An INTONE connection from Fixed signal function block (FXDSIGN) will allow operation from local HMI. As it can be seen, both indications and commands are done in double-bit representation, where a combination of signals on both inputs/outputs generate the desired result. The following table shows the relationship between IPOS1/IPOS2 inputs and the name of the string that is shown on the SLD. The value of the strings are set in PST.
IPOS1 0 1 0 1 IPOS2 0 0 1 1 Name of displayed string PosUndefined Position1 Position2 PosBadState Default string value P00 P01 P10 P11
12.5.3
Function block
VSGGIO BLOCK PSTO IPOS1 IPOS2 BLOCKED POSITION POS1 POS2 CMDPOS12 CMDPOS21 IEC06000508-2-en.vsd
IEC06000508 V3 EN
Figure 305:
12.5.4
Table 325:
Name BLOCKED POSITION POS1 POS2 CMDPOS12 CMDPOS21
12.5.5
Table 326:
Name Operation CtlModel Mode tSelect tPulse
Setting parameters
VSGGIO Non group settings (basic)
Values (Range) Disabled Enabled Dir Norm SBO Enh Steady Pulsed 0.000 - 60.000 0.000 - 60.000 Unit s s Step 0.001 0.001 Default Disabled Dir Norm Pulsed 30.000 0.200 Description Disable/Enable Operation Specifies the type for control model according to IEC 61850 Operation mode Max time between select and execute signals Command pulse lenght
12.6
Section 12 Control
Function description IEC 61850 generic communication I/O functions IEC 61850 identification DPGGIO IEC 60617 identification -
12.6.1
Introduction
The IEC 61850 generic communication I/O functions (DPGGIO) function block is used to send double indications to other systems or equipment in the substation. It is especially used in the interlocking and reservation station-wide logics.
12.6.2
Principle of operation
Upon receiving the input signals, the IEC 61850 generic communication I/O functions (DPGGIO) function block will send the signals over IEC 61850-8-1 to the equipment or system that requests these signals. To be able to get the signals, other tools must be used, as described in the application manual, to PCM600 must be used to define which function block in which equipment or system should receive this information.
12.6.3
Function block
DPGGIO OPEN CLOSE VALID POSITION
IEC07000200-2-en.vsd
IEC07000200 V2 EN
Figure 306:
12.6.4
Table 328:
Name POSITION
12.6.5
12.7
12.7.1
Introduction
The Single point generic control 8 signals (SPC8GGIO) function block is a collection of 8 single point commands, designed to bring in commands from REMOTE (SCADA) to those parts of the logic configuration that do not need extensive command receiving functionality (for example, SCSWI). In this way, simple commands can be sent directly to the IED outputs, without confirmation. Confirmation (status) of the result of the commands is supposed to be achieved by other means, such as binary inputs and SPGGIO function blocks. The commands can be pulsed or steady.
12.7.2
Principle of operation
The PSTO input selects the operator place (LOCAL, REMOTE or ALL). One of the eight outputs is activated based on the command sent from the operator place selected. The settings Latchedx and tPulsex (where x is the respective output) will determine if the signal will be pulsed (and how long the pulse is) or latched (steady). BLOCK will block the operation of the function in case a command is sent, no output will be activated. PSTO is the universal operator place selector for all control functions. Although, PSTO can be configured to use LOCAL or ALL operator places only, REMOTE operator place is used in SPC8GGIO function.
Figure 307:
12.7.4
Table 330:
Name OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8
12.7.5
Table 331:
Name Operation Latched1 tPulse1 Latched2 tPulse2 Latched3 tPulse3 Latched4 tPulse4 Latched5 tPulse5 Latched6 tPulse6 Latched7 tPulse7 Latched8 tPulse8
12.8
AutomationBits function for DNP3 (AUTOBITS) is used within PCM600 to get into the configuration of the commands coming through the DNP3 protocol. The AUTOBITS function plays the same role as functions GOOSEBINRCV (for IEC 61850) and MULTICMDRCV (for LON).
12.8.2
Principle of operation
AutomationBits function (AUTOBITS) has 32 individual outputs which each can be mapped as a Binary Output point in DNP3. The output is operated by a "Object 12" in DNP3. This object contains parameters for control-code, count, on-time and off-time. To operate an AUTOBITS output point, send a control-code of latch-On, latch-Off, pulseOn, pulse-Off, Trip or Close. The remaining parameters will be regarded were appropriate. ex: pulse-On, on-time=100, off-time=300, count=5 would give 5 positive 100 ms pulses, 300 ms apart. There is a BLOCK input signal, which will disable the operation of the function, in the same way the setting Operation: Enabled/Disabled does. That means that, upon activation of the BLOCK input, all 32 CMDBITxx outputs will be set to 0. The BLOCK acts like an overriding, the function still receives data from the DNP3 master. Upon deactivation of BLOCK, all the 32 CMDBITxx outputs will be set by the DNP3 master again, momentarily. For AUTOBITS , the PSTO input determines the operator place. The command can be written to the block while in Remote. If PSTO is in Local then no change is applied to the outputs.
12.8.3
Figure 308:
12.8.4
Table 333:
Name CMDBIT1 CMDBIT2 CMDBIT3 CMDBIT4 CMDBIT5
Section 12 Control
Name CMDBIT6 CMDBIT7 CMDBIT8 CMDBIT9 CMDBIT10 CMDBIT11 CMDBIT12 CMDBIT13 CMDBIT14 CMDBIT15 CMDBIT16 CMDBIT17 CMDBIT18 CMDBIT19 CMDBIT20 CMDBIT21 CMDBIT22 CMDBIT23 CMDBIT24 CMDBIT25 CMDBIT26 CMDBIT27 CMDBIT28 CMDBIT29 CMDBIT30 CMDBIT31 CMDBIT32 Type BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN Description Command out bit 6 Command out bit 7 Command out bit 8 Command out bit 9 Command out bit 10 Command out bit 11 Command out bit 12 Command out bit 13 Command out bit 14 Command out bit 15 Command out bit 16 Command out bit 17 Command out bit 18 Command out bit 19 Command out bit 20 Command out bit 21 Command out bit 22 Command out bit 23 Command out bit 24 Command out bit 25 Command out bit 26 Command out bit 27 Command out bit 28 Command out bit 29 Command out bit 30 Command out bit 31 Command out bit 32
12.8.5
Table 334:
Name Operation
Setting parameters
AUTOBITS Non group settings (basic)
Values (Range) Disabled Enabled Unit Step Default Disabled Description Disable/Enable Operation
Section 12 Control
Table 335:
Name Operation
Table 336:
Name Operation BaudRate
WireMode
Two-wire
Table 337:
Name DLinkConfirm
s s -
0.001 1 0.001 1 1 1 -
Data-link confirm timeout in s Data-link maximum retries Rx to Tx minimum delay in s Application layer maximum Rx fragment size Application layer maximum Tx fragment size Stop bits Parity
s s s s
RTS warm-up in s RTS warm-down in s RS485 back-off delay in s RS485 maximum back-off random delay in s
Section 12 Control
Table 338:
Name Operation
1 1 1 1
TCP/IP listen port UDP port to accept UDP datagrams from master UDP port for initial NULL response UDP port to remote client/master
Table 339:
Name ApLayMaxRxSize ApLayMaxTxSize
Table 340:
Name Operation
1 1 1 1
TCP/IP listen port UDP port to accept UDP datagrams from master UDP port for initial NULL response UDP port to remote client/master
Table 341:
Name ApLayMaxRxSize ApLayMaxTxSize
Section 12 Control
Table 342:
Name Operation
1 1 1 1
TCP/IP listen port UDP port to accept UDP datagrams from master UDP port for initial NULL response UDP port to remote client/master
Table 343:
Name ApLayMaxRxSize ApLayMaxTxSize
Table 344:
Name Operation
1 1 1 1
TCP/IP listen port UDP port to accept UDP datagrams from master UDP port for initial NULL response UDP port to remote client/master
Table 345:
Name ApLayMaxRxSize ApLayMaxTxSize
Table 346:
Name Operation SlaveAddress MasterAddres
Section 12 Control
Name Obj1DefVar Obj2DefVar Values (Range) 1:BISingleBit 2:BIWithStatus 1:BIChWithoutTim e 2:BIChWithTime 3:BIChWithRelTim e 1:DIChWithoutTim e 2:DIChWithTime 3:DIChWithRelTim e 1:BO 2:BOStatus 1:BinCnt32 2:BinCnt16 5:BinCnt32WoutF 6:BinCnt16WoutF 1:BinCnt32EvWout T 2:BinCnt16EvWout T 5:BinCnt32EvWith T 6:BinCnt16EvWith T 1:AI32Int 2:AI16Int 3:AI32IntWithoutF 4:AI16IntWithoutF 5:AI32FltWithF 6:AI64FltWithF 1:AI32IntEvWoutF 2:AI16IntEvWoutF 3:AI32IntEvWithFT 4:AI16IntEvWithFT 5:AI32FltEvWithF 6:AI64FltEvWithF 7:AI32FltEvWithFT 8:AI64FltEvWithFT Unit Step Default 1:BISingleBit 3:BIChWithRelTim e Description
Obj4DefVar
3:DIChWithRelTim e
Obj10DefVar Obj20DefVar
2:BOStatus 5:BinCnt32WoutF
Obj22DefVar
1:BinCnt32EvWou tT
Obj30DefVar
3:AI32IntWithoutF
Obj32DefVar
1:AI32IntEvWoutF
Table 347:
Name ValMasterAddr AddrQueryEnbl tApplConfTout
Section 12 Control
Values (Range) No Yes No Yes No Yes No Yes Disabled Class 1 Class 2 Class 1 and 2 Class 3 Class 1 and 3 Class 2 and 3 Class 1, 2 and 3 0 - 10 0.00 - 60.00 0.00 - 60.00 1 - 100 0.00 - 60.00 1 - 100 0.00 - 60.00 1 - 100 0.00 - 60.00 No Yes 30 - 3600 No Yes No Yes No Yes No Yes 1.0 - 60.0 Unit Step Default Yes Yes Yes No Disabled Description Enable application for multiple fragment response Confirm each multiple fragment Unsolicited response enabled Unsolicited response sends when on-line Unsolicited response, event class mask
UROfflineRetry tURRetryDelay tUROfflRtryDel UREvCntThold1 tUREvBufTout1 UREvCntThold2 tUREvBufTout2 UREvCntThold3 tUREvBufTout3 DelOldBufFull tSynchTimeout TSyncReqAfTout DNPToSetTime Averag3TimeReq PairedPoint tSelectTimeout
s s s s s s s
Unsolicited response retries before off-line retry mode Unsolicited response retry delay in s Unsolicited response off-line retry delay in s Unsolicited response class 1 event count report treshold Unsolicited response class 1 event buffer timeout Unsolicited response class 2 event count report treshold Unsolicited response class 2 event buffer timeout Unsolicited response class 3 event count report treshold Unsolicited response class 3 event buffer timeout Delete oldest event when buffer is full Time synch timeout before error status is generated Time synchronization request after timeout Allow DNP to set time in IED Use average of 3 time requests Enable paired point Select timeout
Section 12 Control
Table 348:
Name Operation SlaveAddress MasterAddres ValMasterAddr MasterIP-Addr MasterIPNetMsk Obj1DefVar Obj2DefVar
Obj3DefVar Obj4DefVar
1:DIWithoutFlag 3:DIChWithRelTim e
Obj10DefVar Obj20DefVar
2:BOStatus 5:BinCnt32WoutF
Section 12 Control
Values (Range) 1:BinCnt32EvWout T 2:BinCnt16EvWout T 5:BinCnt32EvWith T 6:BinCnt16EvWith T 1:AI32Int 2:AI16Int 3:AI32IntWithoutF 4:AI16IntWithoutF 5:AI32FltWithF 6:AI64FltWithF 1:AI32IntEvWoutF 2:AI16IntEvWoutF 3:AI32IntEvWithFT 4:AI16IntEvWithFT 5:AI32FltEvWithF 6:AI64FltEvWithF 7:AI32FltEvWithFT 8:AI64FltEvWithFT Unit Step Default 1:BinCnt32EvWou tT Description Object 22, default variation
Name Obj22DefVar
Obj30DefVar
3:AI32IntWithoutF
Obj32DefVar
1:AI32IntEvWoutF
Table 349:
Name AddrQueryEnbl tApplConfTout ApplMultFrgRes ConfMultFrag UREnable UREvClassMask
s s -
1 0.01 0.01 1
5 5.00 30.00 5
Unsolicited response retries before off-line retry mode Unsolicited response retry delay in s Unsolicited response off-line retry delay in s Unsolicited response class 1 event count report treshold
Section 12 Control
Name tUREvBufTout1 UREvCntThold2 tUREvBufTout2 UREvCntThold3 tUREvBufTout3 DelOldBufFull ExtTimeFormat DNPToSetTime tSynchTimeout TSyncReqAfTout Averag3TimeReq PairedPoint tSelectTimeout tBrokenConTout tKeepAliveT Values (Range) 0.00 - 60.00 1 - 100 0.00 - 60.00 1 - 100 0.00 - 60.00 No Yes LocalTime UTC No Yes 30 - 3600 No Yes No Yes No Yes 1.0 - 60.0 0 - 3600 0 - 3600 Unit s s s s s s s Step 0.01 1 0.01 1 0.01 1 0.1 1 1 Default 5.00 5 5.00 5 5.00 No UTC No 1800 No No Yes 30.0 0 10 Description
Unsolicited response class 1 event buffer timeout Unsolicited response class 2 event count report treshold Unsolicited response class 2 event buffer timeout Unsolicited response class 3 event count report treshold Unsolicited response class 3 event buffer timeout Delete oldest event when buffer is full External time format Allow DNP to set time in IED Time synch timeout before error status is generated Time synchronization request after timeout Use average of 3 time requests Enable paired point Select timeout Broken connection timeout Keep-Alive timer
Table 350:
Name Operation SlaveAddress MasterAddres ValMasterAddr MasterIP-Addr MasterIPNetMsk Obj1DefVar
Section 12 Control
Values (Range) 1:BIChWithoutTim e 2:BIChWithTime 3:BIChWithRelTim e 1:DIWithoutFlag 2:DIWithFlag 1:DIChWithoutTim e 2:DIChWithTime 3:DIChWithRelTim e 1:BO 2:BOStatus 1:BinCnt32 2:BinCnt16 5:BinCnt32WoutF 6:BinCnt16WoutF 1:BinCnt32EvWout T 2:BinCnt16EvWout T 5:BinCnt32EvWith T 6:BinCnt16EvWith T 1:AI32Int 2:AI16Int 3:AI32IntWithoutF 4:AI16IntWithoutF 5:AI32FltWithF 6:AI64FltWithF 1:AI32IntEvWoutF 2:AI16IntEvWoutF 3:AI32IntEvWithFT 4:AI16IntEvWithFT 5:AI32FltEvWithF 6:AI64FltEvWithF 7:AI32FltEvWithFT 8:AI64FltEvWithFT Unit Step Default 3:BIChWithRelTim e Description Object 2, default variation
Name Obj2DefVar
Obj3DefVar Obj4DefVar
1:DIWithoutFlag 3:DIChWithRelTim e
Obj10DefVar Obj20DefVar
2:BOStatus 5:BinCnt32WoutF
Obj22DefVar
1:BinCnt32EvWou tT
Obj30DefVar
3:AI32IntWithoutF
Obj32DefVar
1:AI32IntEvWoutF
Table 351:
Name AddrQueryEnbl tApplConfTout ApplMultFrgRes
Section 12 Control
Name ConfMultFrag UREnable UREvClassMask Values (Range) No Yes No Yes Disabled Class 1 Class 2 Class 1 and 2 Class 3 Class 1 and 3 Class 2 and 3 Class 1, 2 and 3 0 - 10 0.00 - 60.00 0.00 - 60.00 1 - 100 0.00 - 60.00 1 - 100 0.00 - 60.00 1 - 100 0.00 - 60.00 No Yes LocalTime UTC No Yes 30 - 3600 No Yes No Yes No Yes 1.0 - 60.0 0 - 3600 0 - 3600 Unit Step Default Yes Yes Disabled Description
Confirm each multiple fragment Unsolicited response enabled Unsolicited response, event class mask
UROfflineRetry tURRetryDelay tUROfflRtryDel UREvCntThold1 tUREvBufTout1 UREvCntThold2 tUREvBufTout2 UREvCntThold3 tUREvBufTout3 DelOldBufFull ExtTimeFormat DNPToSetTime tSynchTimeout TSyncReqAfTout Averag3TimeReq PairedPoint tSelectTimeout tBrokenConTout tKeepAliveT
s s s s s s s s s
Unsolicited response retries before off-line retry mode Unsolicited response retry delay in s Unsolicited response off-line retry delay in s Unsolicited response class 1 event count report treshold Unsolicited response class 1 event buffer timeout Unsolicited response class 2 event count report treshold Unsolicited response class 2 event buffer timeout Unsolicited response class 3 event count report treshold Unsolicited response class 3 event buffer timeout Delete oldest event when buffer is full External time format Allow DNP to set time in IED Time synch timeout before error status is generated Time synchronization request after timeout Use average of 3 time requests Enable paired point Select timeout Broken connection timeout Keep-Alive timer
Section 12 Control
Table 352:
Name Operation SlaveAddress MasterAddres ValMasterAddr MasterIP-Addr MasterIPNetMsk Obj1DefVar Obj2DefVar
Obj3DefVar Obj4DefVar
1:DIWithoutFlag 3:DIChWithRelTim e
Obj10DefVar Obj20DefVar
2:BOStatus 5:BinCnt32WoutF
Section 12 Control
Name Obj22DefVar Values (Range) 1:BinCnt32EvWout T 2:BinCnt16EvWout T 5:BinCnt32EvWith T 6:BinCnt16EvWith T 1:AI32Int 2:AI16Int 3:AI32IntWithoutF 4:AI16IntWithoutF 5:AI32FltWithF 6:AI64FltWithF 1:AI32IntEvWoutF 2:AI16IntEvWoutF 3:AI32IntEvWithFT 4:AI16IntEvWithFT 5:AI32FltEvWithF 6:AI64FltEvWithF 7:AI32FltEvWithFT 8:AI64FltEvWithFT Unit Step Default 1:BinCnt32EvWou tT Description
Obj30DefVar
3:AI32IntWithoutF
Obj32DefVar
1:AI32IntEvWoutF
Table 353:
Name AddrQueryEnbl tApplConfTout ApplMultFrgRes ConfMultFrag UREnable UREvClassMask
s s -
1 0.01 0.01 1
5 5.00 30.00 5
Unsolicited response retries before off-line retry mode Unsolicited response retry delay in s Unsolicited response off-line retry delay in s Unsolicited response class 1 event count report treshold
Section 12 Control
Values (Range) 0.00 - 60.00 1 - 100 0.00 - 60.00 1 - 100 0.00 - 60.00 No Yes LocalTime UTC No Yes 30 - 3600 No Yes No Yes No Yes 1.0 - 60.0 0 - 3600 0 - 3600 Unit s s s s s s s Step 0.01 1 0.01 1 0.01 1 0.1 1 1 Default 5.00 5 5.00 5 5.00 No UTC No 1800 No No Yes 30.0 0 10 Description Unsolicited response class 1 event buffer timeout Unsolicited response class 2 event count report treshold Unsolicited response class 2 event buffer timeout Unsolicited response class 3 event count report treshold Unsolicited response class 3 event buffer timeout Delete oldest event when buffer is full External time format Allow DNP to set time in IED Time synch timeout before error status is generated Time synchronization request after timeout Use average of 3 time requests Enable paired point Select timeout Broken connection timeout Keep-Alive timer
Name tUREvBufTout1 UREvCntThold2 tUREvBufTout2 UREvCntThold3 tUREvBufTout3 DelOldBufFull ExtTimeFormat DNPToSetTime tSynchTimeout TSyncReqAfTout Averag3TimeReq PairedPoint tSelectTimeout tBrokenConTout tKeepAliveT
Table 354:
Name Operation SlaveAddress MasterAddres ValMasterAddr MasterIP-Addr MasterIPNetMsk Obj1DefVar
Section 12 Control
Name Obj2DefVar Values (Range) 1:BIChWithoutTim e 2:BIChWithTime 3:BIChWithRelTim e 1:DIWithoutFlag 2:DIWithFlag 1:DIChWithoutTim e 2:DIChWithTime 3:DIChWithRelTim e 1:BO 2:BOStatus 1:BinCnt32 2:BinCnt16 5:BinCnt32WoutF 6:BinCnt16WoutF 1:BinCnt32EvWout T 2:BinCnt16EvWout T 5:BinCnt32EvWith T 6:BinCnt16EvWith T 1:AI32Int 2:AI16Int 3:AI32IntWithoutF 4:AI16IntWithoutF 5:AI32FltWithF 6:AI64FltWithF 1:AI32IntEvWoutF 2:AI16IntEvWoutF 3:AI32IntEvWithFT 4:AI16IntEvWithFT 5:AI32FltEvWithF 6:AI64FltEvWithF 7:AI32FltEvWithFT 8:AI64FltEvWithFT Unit Step Default 3:BIChWithRelTim e Description
Obj3DefVar Obj4DefVar
1:DIWithoutFlag 3:DIChWithRelTim e
Obj10DefVar Obj20DefVar
2:BOStatus 5:BinCnt32WoutF
Obj22DefVar
1:BinCnt32EvWou tT
Obj30DefVar
3:AI32IntWithoutF
Obj32DefVar
1:AI32IntEvWoutF
Table 355:
Name AddrQueryEnbl tApplConfTout ApplMultFrgRes
Section 12 Control
Values (Range) No Yes No Yes Disabled Class 1 Class 2 Class 1 and 2 Class 3 Class 1 and 3 Class 2 and 3 Class 1, 2 and 3 0 - 10 0.00 - 60.00 0.00 - 60.00 1 - 100 0.00 - 60.00 1 - 100 0.00 - 60.00 1 - 100 0.00 - 60.00 No Yes LocalTime UTC No Yes 30 - 3600 No Yes No Yes No Yes 1.0 - 60.0 0 - 3600 0 - 3600 Unit Step Default Yes Yes Disabled Description Confirm each multiple fragment Unsolicited response enabled Unsolicited response, event class mask
UROfflineRetry tURRetryDelay tUROfflRtryDel UREvCntThold1 tUREvBufTout1 UREvCntThold2 tUREvBufTout2 UREvCntThold3 tUREvBufTout3 DelOldBufFull ExtTimeFormat DNPToSetTime tSynchTimeout TSyncReqAfTout Averag3TimeReq PairedPoint tSelectTimeout tBrokenConTout tKeepAliveT
s s s s s s s s s
Unsolicited response retries before off-line retry mode Unsolicited response retry delay in s Unsolicited response off-line retry delay in s Unsolicited response class 1 event count report treshold Unsolicited response class 1 event buffer timeout Unsolicited response class 2 event count report treshold Unsolicited response class 2 event buffer timeout Unsolicited response class 3 event count report treshold Unsolicited response class 3 event buffer timeout Delete oldest event when buffer is full External time format Allow DNP to set time in IED Time synch timeout before error status is generated Time synchronization request after timeout Use average of 3 time requests Enable paired point Select timeout Broken connection timeout Keep-Alive timer
Section 12 Control
12.9
12.9.1
Introduction
The IEDs can receive commands either from a substation automation system or from the local HMI. The command function block has outputs that can be used, for example, to control high voltage apparatuses or for other user defined functionality.
12.9.2
Principle of operation
Single command, 16 signals (SINGLECMD) function has 16 binary output signals. The outputs can be individually controlled from a substation automation system or from the local HMI. Each output signal can be given a name with a maximum of 13 characters in PCM600. The output signals can be of the types Disabled, Steady, or Pulse. This configuration setting is done via the local HMI or PCM600 and is common for the whole function block. The length of the output pulses are 100 ms. In steady mode, SINGLECMD function has a memory to remember the output values at power interruption of the IED. Also a BLOCK input is available used to block the updating of the outputs. The output signals, OUT1 to OUT16, are available for configuration to built-in functions or via the configuration logic circuits to the binary outputs of the IED.
12.9.3
Figure 309:
12.9.4
Table 357:
Name OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13
Section 12 Control
Name OUT14 OUT15 OUT16 Type BOOLEAN BOOLEAN BOOLEAN Description Single command output 14 Single command output 15 Single command output 16
12.9.5
Table 358:
Name Mode
Setting parameters
SINGLECMD Non group settings (basic)
Values (Range) Disabled Steady Pulsed Unit Step Default Disabled Description Operation mode
Section 13 Logic
Section 13
Logic
13.1
I->O
SYMBOL-K V1 EN
13.1.1
Introduction
A function block for protection tripping is provided for each circuit breaker involved in the tripping of the fault. It provides pulse prolongation to ensure a trip pulse of sufficient length, as well as all functionality necessary for correct co-operation with autoreclosing functions. The trip function block also includes functionality for evolving faults and breaker lockout.
13.1.2
Principle of operation
The duration of a trip output signal from tripping logic SMPPTRC (94) is settable (tTripMin). The pulse length should be long enough to secure the breaker opening. For three-pole tripping, SMPPTRC (94) has a single input (TRINP_3P) through which all trip output signals from the protection functions within the IED, or from external protection functions via one or more of the IEDs binary inputs, are routed. It has a single trip output (TRIP) for connection to one or more of the IEDs binary outputs, as well as to other functions within the IED requiring this signal.
Section 13 Logic
ANSI05000789 V2 EN
Figure 310:
SMPPTRC (94) function for single-pole and two-pole tripping has additional phase segregated inputs for this, as well as inputs for faulted phase selection. The latter inputs enable single- pole and two-pole tripping for those functions which do not have their own phase selection capability, and therefore which have just a single trip output and not phase segregated trip outputs for routing through the phase segregated trip inputs of the expanded SMPPTRC (94) function. Examples of such protection functions are the residual overcurrent protections. The expanded SMPPTRC (94) function has two inputs for these functions, one for impedance tripping (for example, carrier-aided tripping commands from the scheme communication logic), and one for ground fault tripping (for example, tripping output from a residual overcurrent protection). Additional logic, including a timer tWaitForPHS, secures a three-phase trip command for these protection functions in the absence of the required phase selection signals. The expanded SMPPTRC (94) function has three trip outputs TR_A, TR_B, TR_C (besides the trip output TRIP), one per phase, for connection to one or more of the IEDs binary outputs, as well as to other functions within the IED requiring these signals. There are also separate output signals indicating single-pole, two-pole or threepole trip. These signals are important for cooperation with the autorecloser SMBRREC (79) function. The expanded SMPPTRC (94) function is equipped with logic which secures correct operation for evolving faults as well as for reclosing on to persistent faults. A special input is also provided which disables single- pole and two-pole tripping, forcing all tripping to be three-pole. In multi-breaker arrangements, one SMPPTRC (94) function block is used for each breaker. This can be the case if single pole tripping and autoreclosing is used. The breaker close lockout function can be activated from an external trip signal from another protection function via input (SETLKOUT) or internally at a three-pole trip, if desired.
Section 13 Logic
It is possible to lockout seal in the tripping output signals or use blocking of closing only the choice is by setting TripLockout.
13.1.2.1
Logic diagram
TRINP -A TRINP -B TRINP -C 1 PTRZ 1 PTRGF TRINP -3P Program= 3 p
OR OR OR AND
. INTL_ABCTRIP - cont
Figure 311:
TRINP_3P TRINP_A PS_A
AND
OR
ATRIP
TRINP_B PS_B
AND
OR
BTRIP
TRINP_C PS_C
AND OR
OR
CTRIP
OR
-loop
OR
-loop
OR AND
1PTRGF 1PTRZ
AND AND OR
0 - tWaitForPHS 0
AND
ANSI10000056-1-en.vsd
ANSI10000056 V1 EN
Figure 312:
Section 13 Logic
ATRIP
150 ms
t
0 2000 ms
OR OR
INTL_ATRIP
OR
AND
BTRIP
150 ms
t
0 2000 ms
OR OR
INTL_BTRIP
OR
AND
CTRIP
150 ms
t
0 2000 ms
OR OR
INTL_CTRIP
OR
AND
OR AND
P3PTR
OR OR
-loop
en05000519_ansi.vsd
ANSI05000519 V1 EN
Figure 313:
Section 13 Logic
ATRIP - cont.
150 ms
t
0 2000 ms
OR
OR
INTL_ATRIP
AND
BTRIP
150 ms
t
0 2000 ms
OR
OR
INTL_BTRIP
AND AND
CTRIP
150 ms
t
0 2000 ms
OR
OR
INTL_CTRIP
AND
OR AND
TRIP
OR OR
-loop
en05000520_ansi.vsd
ANSI05000520 V1 EN
Figure 314:
Section 13 Logic
BLOCK INTL_ATRIP
OR
INTL_BTRIP
AND
TR_A
OR
INTL_CTRIP
AND
TR_B
OR
ABC_TRIP
AND OR
TR_C
TRIP
AND
OR
AND
-loop
TR3P
AND
10 ms 0 5 ms 0
TR1P
TR2P
-loop
en05000521_ansi.vsd
ANSI05000521 V1 EN
Figure 315:
13.1.3
Function block
SMPPTRC (94) BLOCK TRIP BLKLKOUT TR_A TRINP_3P TR_B TRINP_A TR_C TRINP_B TR1P TRINP_C TR2P PS_A TR3P PS_B CLLKOUT PS_C 1PTRZ 1PTRGF P3PTR SETLKOUT RSTLKOUT ANSI05000707-2-en.vsd
ANSI05000707 V2 EN
Figure 316:
13.1.4
Table 360:
Name TRIP TR_A TR_B TR_C TR1P TR2P TR3P CLLKOUT
Setting parameters
SMPPTRC (94) Group settings (basic)
Values (Range) Disabled Enabled 3 phase 1p/3p 1p/2p/3p 0.000 - 60.000 0.020 - 0.500 Unit Step Default Enabled 1p/3p Description Disable/Enable Operation Three pole; single or three pole; single, two or three pole trip Minimum duration of trip output signal Secures 3-pole trip when phase selection failed
tTripMin tWaitForPHS
s s
0.001 0.001
0.150 0.050
Table 362:
Name TripLockout
AutoLock
Disabled
13.1.6
Technical data
Table 363:
Function Trip action Minimum trip pulse length Timers
13.2
13.2.1
13.2.2
Principle of operation
Trip matrix logic (TMAGGIO) block is provided with 32 input signals and 3 output signals. The function block incorporates internal logic OR gates in order to provide the necessary grouping of connected input signals (for example, for tripping and alarming purposes) to the three output signals from the function block. Internal built-in OR logic is made in accordance with the following three rules: 1. 2. 3. when any one of first 16 inputs signals (INPUT1 to INPUT16) has logical value 1 (TRUE) the first output signal (OUTPUT1) will get logical value 1 (TRUE). when any one of second 16 inputs signals (INPUT17 to INPUT32) has logical value 1 (TRUE) the second output signal (OUTPUT2) will get logical value 1 (TRUE). when any one of all 32 input signals (INPUT1 to INPUT32) has logical value 1 (TRUE) the third output signal (OUTPUT3) will get logical value 1 (TRUE).
By use of the settings ModeOutput1, ModeOutput2, ModeOutput3, PulseTime, OnDelay and OffDelay the behavior of each output can be customized. The OnDelay is always active and will delay the input to output transition by the set time. The ModeOutput for respective output decides whether the output shall be steady with an drop-off delay as set by OffDelay or if it shall give a pulse with duration set by PulseTime. Note that for pulsed operation since the inputs are connected in an ORfunction a new pulse will only be given on the output if all related inputs are reset and then one is activated again. And for steady operation the OffDelay will start when all related inputs have reset. Detailed logical diagram is shown in figure 317
Section 13 Logic
PulseTime
t ModeOutput1
AND
Input 1
OR
Input 16
0-OnDelay 0
0 0-OffDelay
AND
OR
Output 1
PulseTime
t ModeOutput2
AND
Input 17
OR
Input 32
0-OnDelay 0
0 0-OffDelay
AND
OR
Output 2
PulseTime
t ModeOutput3
AND
OR
0-OnDelay 0
0 0-OffDelay
AND
OR
Output 3
ANSI10000055-1-en.vsd
ANSI10000055 V2 EN
Figure 317:
Output signals from TMAGGIO are typically connected to other logic blocks or directly to output contacts in the IED. When used for direct tripping of the circuit breaker(s) the pulse time delay shall be set to approximately 0.150 seconds in order to obtain satisfactory minimum duration of the trip pulse to the circuit breaker trip coils.
13.2.3
IEC09000830-1-en.vsd
IEC09000830 V1 EN
Figure 318:
13.2.4
Section 13 Logic
Name INPUT18 INPUT19 INPUT20 INPUT21 INPUT22 INPUT23 INPUT24 INPUT25 INPUT26 INPUT27 INPUT28 INPUT29 INPUT30 INPUT31 INPUT32 Type BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description Binary input 18 Binary input 19 Binary input 20 Binary input 21 Binary input 22 Binary input 23 Binary input 24 Binary input 25 Binary input 26 Binary input 27 Binary input 28 Binary input 29 Binary input 30 Binary input 31 Binary input 32
Table 365:
Name OUTPUT1 OUTPUT2 OUTPUT3
13.2.5
Table 366:
Name Operation PulseTime OnDelay OffDelay ModeOutput1 ModeOutput2 ModeOutput3
Setting parameters
TMAGGIO Group settings (basic)
Values (Range) Disabled Enabled 0.050 - 60.000 0.000 - 60.000 0.000 - 60.000 Steady Pulsed Steady Pulsed Steady Pulsed Unit s s s Step 0.001 0.001 0.001 Default Enabled 0.150 0.000 0.000 Steady Steady Steady Description Operation Disable / Enable Output pulse time Output on delay time Output off delay time Mode for output ,1 steady or pulsed Mode for output 2, steady or pulsed Mode for output 3, steady or pulsed
Section 13 Logic
13.3
13.3.1
Figure 319:
Table 367:
Name INPUT
Table 368:
Name OUT
13.3.3
OR function block OR
The OR function is used to form general combinatory expressions with boolean variables. The OR function block has six inputs and two outputs. One of the outputs is inverted.
OR INPUT1 INPUT2 INPUT3 INPUT4 INPUT5 INPUT6 OUT NOUT
IEC04000405_2_en.vsd
IEC04000405 V2 EN
Figure 320:
Table 369:
Name INPUT1 INPUT2 INPUT3 INPUT4 INPUT5 INPUT6
OR function block
OR Input signals
Type BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN Default 0 0 0 0 0 0 Description Input 1 to OR gate Input 2 to OR gate Input 3 to OR gate Input 4 to OR gate Input 5 to OR gate Input 6 to OR gate
Section 13 Logic
Table 370:
Name OUT NOUT
OR Output signals
Type BOOLEAN BOOLEAN Description Output from OR gate Inverted output from OR gate
13.3.4
IEC04000406_2_en.vsd
IEC04000406 V2 EN
Figure 321:
Table 371:
Name INPUT1 INPUT2 INPUT3 INPUT4N
Table 372:
Name OUT NOUT
13.3.5
Section 13 Logic
Figure 322:
Table 373:
Name INPUT
Table 374:
Name ON OFF
Table 375:
Name T
13.3.6
IEC04000407-2-en.vsd
IEC04000407 V2 EN
Figure 323:
Table 376:
Name INPUT
Table 377:
Name OUT
Section 13 Logic
Table 378:
Name T
13.3.7
Figure 324:
Table 379:
Name INPUT1 INPUT2
Table 380:
Name OUT NOUT
13.3.8
Figure 325:
Section 13 Logic
Table 381:
Name INPUT
Table 382:
Name OUT
13.3.9
Figure 326:
Table 384:
Name SET RESET
Section 13 Logic
Table 385:
Name OUT NOUT
Table 386:
Name Memory
13.3.10
Figure 327:
Table 388:
Name SET RESET
Section 13 Logic
Table 389:
Name OUT NOUT
Table 390:
Name Memory
13.3.11
Figure 328:
Table 391:
Name INPUT
Table 392:
Name OUT
Table 393:
Name Operation
13.3.12
Figure 329:
Table 394:
Name INPUT
Table 395:
Name ON OFF
Table 396:
Name Operation t
13.3.13
Technical data
Table 397:
Logic block LogicAND LogicOR LogicXOR LogicInverter LogicSRMemory LogicRSMemory
Section 13 Logic
Logic block LogicGate LogicTimer LogicPulseTimer LogicTimerSet LogicLoopDelay Trip Matrix Logic Boolean 16 to Integer Boolean 16 to integer with Logic Node Integer to Boolean 16 Integer to Boolean 16 with Logic Node Quantity with cycle time fast medium 10 10 10 10 10 6 4 4 10 10 10 10 10 6 4 4 Range or value (0.000 90000.000) s (0.000 90000.000) s (0.000 90000.000) s (0.000 90000.000) s -
normal 20 20 20 20 20 8 8
4 4
4 4
8 8
13.4
The Fixed signals function (FXDSIGN) generates a number of pre-set (fixed) signals that can be used in the configuration of an IED, either for forcing the unused inputs in other function blocks to a certain level/value, or for creating certain logic.
13.4.1
Principle of operation
There are eight outputs from FXDSIGN function block: OFF is a boolean signal, fixed to OFF (boolean 0) value ON is a boolean signal, fixed to ON (boolean 1) value INTZERO is an integer number, fixed to integer value 0 INTONE is an integer number, fixed to integer value 1 INTALONE is an integer value FFFF (hex) REALZERO is a floating point real number, fixed to 0.0 value
Section 13 Logic
STRNULL is a string, fixed to an empty string (null) value ZEROSMPL is a channel index, fixed to 0 value GRP_OFF is a group signal, fixed to 0 value
13.4.2
Function block
FXDSIGN OFF ON INTZERO INTONE INTALONE REALZERO STRNULL ZEROSMPL GRP_OFF IEC05000445-3-en.vsd
IEC05000445 V3 EN
Figure 330:
13.4.3
13.4.4
Setting parameters
The function does not have any parameters available in the local HMI or PCM600.
Section 13 Logic
13.5
13.5.1
Introduction
Boolean 16 to integer conversion function (B16I) is used to transform a set of 16 binary (logical) signals into an integer.
13.5.2
Principle of operation
Boolean 16 to integer conversion function (B16I) is used to transform a set of 16 binary (logical) signals into an integer. The BLOCK input will freeze the output at the last value.
13.5.3
Function block
B16I BLOCK IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 IN11 IN12 IN13 IN14 IN15 IN16 OUT
IEC07000128-2-en.vsd
IEC07000128 V2 EN
Figure 331:
13.5.4
Table 400:
Name OUT
13.5.5
Setting parameters
The function does not have any parameters available in the local HMI or PCM600.
13.6
Boolean 16 to integer conversion with logic node representation function (B16IFCVI) is used to transform a set of 16 binary (logical) signals into an integer. B16IFCVI can receive remote values via IEC 61850 depending on the operator position input (PSTO).
13.6.2
Principle of operation
Boolean 16 to integer conversion with logic node representation function (B16IFCVI) is used to transform a set of 16 binary (logical) signals into an integer. The BLOCK input will freeze the output at the last value.
13.6.3
Function block
B16IFCVI BLOCK IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 IN11 IN12 IN13 IN14 IN15 IN16 OUT
IEC09000624-1-en.vsd
IEC09000624 V1 EN
Figure 332:
13.6.4
Section 13 Logic
Name IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 IN11 IN12 IN13 IN14 IN15 IN16 Type BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description Input 3 Input 4 Input 5 Input 6 Input 7 Input 8 Input 9 Input 10 Input 11 Input 12 Input 13 Input 14 Input 15 Input 16
Table 402:
Name OUT
13.6.5
Setting parameters
The function does not have any parameters available in the local HMI or PCM600.
13.7
13.7.1
Introduction
Integer to boolean 16 conversion function (IB16) is used to transform an integer into a set of 16 binary (logical) signals.
Integer to boolean 16 conversion function (IB16) is used to transform an integer into a set of 16 binary (logical) signals. IB16 function is designed for receiving the integer input locally. The BLOCK input will freeze the logical outputs at the last value.
13.7.3
Function block
IB16 BLOCK INP OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 ANSI06000501-1-en.vsd
ANSI06000501 V1 EN
Figure 333:
13.7.4
Table 404:
Name OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7
Section 13 Logic
Name OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 Type BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN Description Output 8 Output 9 Output 10 Output 11 Output 12 Output 13 Output 14 Output 15 Output 16
13.7.5
Setting parameters
The function does not have any parameters available in the local HMI or PCM600.
13.8
13.8.1
Introduction
Integer to boolean conversion with logic node representation function (IB16FCVB) is used to transform an integer to 16 binary (logic) signals. IB16FCVB function can receive remote values over IEC61850 depending on the operator position input (PSTO).
13.8.2
Principle of operation
Integer to boolean conversion with logic node representation function (IB16FCVB) is used to transform an integer into a set of 16 binary (logical) signals. IB16FCVB function can receive an integer from a station computer for example, over IEC 61850. The BLOCK input will freeze the logical outputs at the last value.
Section 13 Logic
The operator position input (PSTO) determines the operator place. The integer number can be written to the block while in Remote. If PSTO is in Off or Local, then no change is applied to the outputs.
13.8.3
Function block
IB16FCVB BLOCK PSTO OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 IEC09000399-1-en.vsd
IEC09000399 V1 EN
Figure 334:
13.8.4
Table 406:
Name OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8
Section 13 Logic
Name OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 Type BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN BOOLEAN Description Output 9 Output 10 Output 11 Output 12 Output 13 Output 14 Output 15 Output 16
13.8.5
Setting parameters
This function does not have any setting parameters.
714
Section 14 Monitoring
Section 14
Monitoring
14.1
Measurements
Function description Measurements IEC 61850 identification CVMMXN
P, Q, S, I, U, f
SYMBOL-RR V1 EN
CMMXU
I
SYMBOL-SS V1 EN
VMMXU
U
SYMBOL-UU V1 EN
CMSQI
I1, I2, I0
SYMBOL-VV V1 EN
VMSQI
U1, U2, U0
SYMBOL-TT V1 EN
VNMMXU
U
SYMBOL-UU V1 EN
Measurement functions is used for power system measurement, supervision and reporting to the local HMI, monitoring tool within PCM600 or to station level for example, via IEC 61850. The possibility to continuously monitor measured values of active power, reactive power, currents, voltages, frequency, power factor etc. is vital for efficient production, transmission and distribution of electrical energy. It provides to the system operator fast and easy overview of the present status of the power system. Additionally, it can be used during testing and commissioning of protection and control IEDs in order to verify proper operation and connection of instrument transformers (CTs and VTs). During normal service by periodic comparison of the measured value from the IED with other independent meters the proper operation of the IED analog measurement chain can be verified. Finally, it can be used to verify proper direction orientation for distance or directional overcurrent protection function. The available measured values of an IED are depending on the actual hardware (TRM) and the logic configuration made in PCM600. All measured values can be supervised with four settable limits that is, low-low limit, low limit, high limit and high-high limit. A zero clamping reduction is also supported, that is, the measured value below a settable limit is forced to zero which reduces the impact of noise in the inputs. Dead-band supervision can be used to report measured signal value to station level when change in measured value is above set threshold limit or time integral of all changes since the last time value updating exceeds the threshold limit. Measure value can also be based on periodic reporting. The measurement function, CVMMXN, provides the following power system quantities: P, Q and S: three phase active, reactive and apparent power PF: power factor V: phase-to-phase voltage magnitude I: phase current magnitude F: power system frequency
Main menu/Measurement/Monitoring/Service values/CVMMXN The measuring functions CMMXU, VNMMXU and VMMXU provide physical quantities: I: phase currents (magnitude and angle) (CMMXU) V: voltages (phase-to-ground and phase-to-phase voltage, magnitude and angle) (VMMXU, VNMMXU)
Section 14 Monitoring
It is possible to calibrate the measuring function above to get better then class 0.5 presentation. This is accomplished by angle and magnitude compensation at 5, 30 and 100% of rated current and at 100% of rated voltage. The power system quantities provided, depends on the actual hardware, (TRM) and the logic configuration made in PCM600. The measuring functions CMSQI and VMSQI provide sequence component quantities: I: sequence currents (positive, zero, negative sequence, magnitude and angle) V: sequence voltages (positive, zero and negative sequence, magnitude and angle).
The CVMMXN function calculates three-phase power quantities by using fundamental frequency phasors (DFT values) of the measured current respectively voltage signals. The measured power quantities are available either, as instantaneously calculated quantities or, averaged values over a period of time (low pass filtered) depending on the selected settings.
14.1.2
14.1.2.1
Principle of operation
Measurement supervision
The protection, control, and monitoring IEDs have functionality to measure and further process information for currents and voltages obtained from the pre-processing blocks. The number of processed alternate measuring quantities depends on the type of IED and built-in options. The information on measured quantities is available for the user at different locations: Locally by means of the local HMI Remotely using the monitoring tool within PCM600 or over the station bus Internally by connecting the analog output signals to the Disturbance Report function
All phase angles are presented in relation to a defined reference channel. The General setting parameter PhaseAngleRef defines the reference.
Measured value below zero point clamping limit is forced to zero. This allows the noise in the input signal to be ignored. The zero point clamping limit is a general setting (XZeroDb where X equals S, P, Q, PF, V, I, F, IA, IB, IC, VA, VB, VC, VAB, VBC, VCA, I1, I2, 3I0, V1, V2 or 3V0). Observe that this measurement supervision
Section 14 Monitoring
zero point clamping might be overridden by the zero point clamping used for the measurement values within CVMMXU. Users can continuously monitor the measured quantity available in each function block by means of four defined operating thresholds, see figure 335. The monitoring has two different modes of operating: Overfunction, when the measured current exceeds the High limit (XHiLim) or Highhigh limit (XHiHiLim) pre-set values Underfunction, when the measured current decreases under the Low limit (XLowLim) or Low-low limit (XLowLowLim) pre-set values.
Hysteresis
en05000657.vsd
IEC05000657 V1 EN
Figure 335:
Each analog output has one corresponding supervision level output (X_RANGE). The output signal is an integer in the interval 0-4 (0: Normal, 1: High limit exceeded, 3: Highhigh limit exceeded, 2: below Low limit and 4: below Low-low limit). The output may be connected to a measurement expander block (XP (RANGE_XP)) to get measurement supervision as binary signals. The logical value of the functional output signals changes according to figure 335. The user can set the hysteresis (XLimHyst), which determines the difference between the operating and reset value at each operating point, in wide range for each measuring channel separately. The hysteresis is common for all operating values within one channel.
Section 14 Monitoring
Actual value of the measured quantity
The actual value of the measured quantity is available locally and remotely. The measurement is continuous for each measured quantity separately, but the reporting of the value to the higher levels depends on the selected reporting mode. The following basic reporting modes are available: Cyclic reporting (Cyclic) Magnitude dead-band supervision (Dead band) Integral dead-band supervision (Int deadband)
Cyclic reporting
The cyclic reporting of measured value is performed according to chosen setting (XRepTyp). The measuring channel reports the value independent of magnitude or integral dead-band reporting. In addition to the normal cyclic reporting the IED also report spontaneously when measured value passes any of the defined threshold limits.
Y Value Reported (1st) Value Reported Value Reported Value Reported
Y3 Y2 Y4
Value Reported
Y1
Y5
t (*)
t (*)
t (*)
t (*)
Value 1
Value 2
Value 3
Value 4
Value 5
en05000500.vsd
Figure 336:
Periodic reporting
Section 14 Monitoring
Magnitude dead-band supervision
If a measuring value is changed, compared to the last reported value, and the change is larger than the Y pre-defined limits that are set by user (XZeroDb), then the measuring channel reports the new value to a higher level, if this is detected by a new measured value. This limits the information flow to a minimum necessary. Figure 337 shows an example with the magnitude dead-band supervision. The picture is simplified: the process is not continuous but the values are evaluated with a time interval of one execution cycle from each other.
Y Value Reported (1st) Value Reported Y3 Y2 DY DY DY DY DY DY Value Reported Value Reported
Y1
t
99000529.vsd
IEC99000529 V1 EN
Figure 337:
After the new value is reported, the Y limits for dead-band are automatically set around it. The new value is reported only if the measured quantity changes more than defined by the Y set limits. The measured value is reported if the time integral of all changes exceeds the pre-set limit (XDbRepInt), figure 338, where an example of reporting with integral dead-band supervision is shown. The picture is simplified: the process is not continuous but the values are evaluated with a time interval of one execution cycle from each other. The last value reported, Y1 in figure 338 serves as a basic value for further measurement. A difference is calculated between the last reported and the newly measured value and is multiplied by the time increment (discrete integral). The
720 Technical reference manual
Section 14 Monitoring
absolute values of these integral values are added until the pre-set value is exceeded. This occurs with the value Y2 that is reported and set as a new base for the following measurements (as well as for the values Y3, Y4 and Y5). The integral dead-band supervision is particularly suitable for monitoring signals with small variations that can last for relatively long periods.
Y A >= pre-set value A1 >= pre-set value Y3 Y2 Value Reported (1st) A1 Value Reported A2 Y4 Value Reported
Value Reported
A7
Y5 Value Reported t
99000530.vsd
Y1
IEC99000530 V1 EN
Figure 338:
14.1.2.2
The measurement function must be connected to three-phase current and three-phase voltage input in the configuration tool (group signals), but it is capable to measure and calculate above mentioned quantities in nine different ways depending on the available VT inputs connected to the IED. The end user can freely select by a parameter setting, which one of the nine available measuring modes shall be used within the function. Available options are summarized in the following table:
Section 14 Monitoring
Set value for Formula used for complex, threeparameter phase power calculation Mode 1 A, B, C
* * * S = VA I A + VB I B + VC I C
EQUATION1561 V1 EN
Comment
V = VA + VB + VC
A
( I =( I
+ IB + IC
)/ )/3
EQUATION1562 V1 EN
Arone
S = VAB I A - VBC I C
* *
EQUATION1563 V1 EN
V = VAB + VBC / 2
A
(Equation 130)
( I =( I
+ IC / 2
(Equation 131)
EQUATION1564 V1 EN
PosSeq
S = 3 VPosSeq I PosSeq
*
EQUATION1565 V1 EN
V =
3 VPosSeq
(Equation 132)
I = I PosSeq
EQUATION1566 V1 EN
AB
S = VAB I A - I B
* *
EQUATION1567 V1 EN
)
)
)
V = VAB I = IA + IB / 2
EQUATION1568 V1 EN
(Equation 134)
BC
S = VBC I B - I C
* *
EQUATION1569 V1 EN
V = VBC I = I B + IC / 2
EQUATION1570 V1 EN
(Equation 136)
CA
S = VCA I C - I A
* *
EQUATION1571 V1 EN
V = VCA I = IC + I A / 2
EQUATION1572 V1 EN
(Equation 138)
S = 3 VA I A
*
EQUATION1573 V1 EN
V =
3 VA
(Equation 140)
I = IA
EQUATION1574 V1 EN
(Equation 141)
Section 14 Monitoring
Set value for Formula used for complex, threeparameter phase power calculation Mode 8 B Formula used for voltage and current magnitude calculation Comment
S = 3 VB I B
*
EQUATION1575 V1 EN
V = I = IB
3 VB
(Equation 142)
EQUATION1576 V1 EN
S = 3 VC I C
*
EQUATION1577 V1 EN
V = I = IC
3 VC
(Equation 144)
EQUATION1578 V1 EN
(Equation 145)
It shall be noted that only in the first two operating modes that is, 1 & 2 the measurement function calculates exact three-phase power. In other operating modes that is, from 3 to 9 it calculates the three-phase power under assumption that the power system is fully symmetrical. Once the complex apparent power is calculated then the P, Q, S, & PF are calculated in accordance with the following formulas:
P = Re( S )
EQUATION1403 V1 EN
(Equation 146)
Q = Im( S )
EQUATION1404 V1 EN
(Equation 147)
S = S =
EQUATION1405 V1 EN
P +Q
2
(Equation 148)
PF = cosj = P S
EQUATION1406 V1 EN
(Equation 149)
Additionally to the power factor value the two binary output signals from the function are provided which indicates the angular relationship between current and voltage phasors. Binary output signal ILAG is set to one when current phasor is lagging behind voltage phasor. Binary output signal ILEAD is set to one when current phasor is leading the voltage phasor.
723 Technical reference manual
Section 14 Monitoring
Each analog output has a corresponding supervision level output (X_RANGE). The output signal is an integer in the interval 0-4, see section "Measurement supervision".
Measured currents and voltages used in the CVMMXN function can be calibrated to get class 0.5 measuring accuracy. This is achieved by magnitude and angle compensation at 5, 30 and 100% of rated current and voltage. The compensation below 5% and above 100% is constant and linear in between, see example in figure 339.
% of In +10 IMagComp5 IMagComp30 IMagComp100 -10 5 30 0-5%: Constant 5-30-100%: Linear >100%: Constant 100 Measured current % of In Magnitude compensation
Angle compensation
ANSI05000652_3_en.vsd
ANSI05000652 V3 EN
Figure 339:
Calibration curves
The first current and voltage phase in the group signals will be used as reference and the magnitude and angle compensation will be used for related input signals.
In order to minimize the influence of the noise signal on the measurement it is possible to introduce the recursive, low pass filtering of the measured values for P, Q, S, V, I and power factor. This will make slower measurement response to the step changes in
Section 14 Monitoring
the measured quantity. Filtering is performed in accordance with the following recursive formula:
X = k X Old + (1 - k ) X Calculated
EQUATION1407 V1 EN
(Equation 150)
where: X XOld is a new measured value (that is P, Q, S, V, I or PF) to be given out from the function is the measured value given from the measurement function in previous execution cycle
XCalculated is the new calculated value in the present execution cycle k is settable parameter by the end user which influence the filter properties
Default value for parameter k is 0.00. With this value the new calculated value is immediately given out without any filtering (that is, without any additional delay). When k is set to value bigger than 0, the filtering is enabled. Appropriate value of k shall be determined separately for every application. Some typical value for k =0.14.
In order to avoid erroneous measurements when either current or voltage signal is not present, it is possible for the end user to set the magnitudeIGenZeroDb level for current and voltage measurement VGenZeroDb is forced to zero. When either current or voltage measurement is forced to zero automatically the measured values for power (P, Q and S) and power factor are forced to zero as well. Since the measurement supervision functionality, included in CVMMXN, is using these values the zero clamping will influence the subsequent supervision (observe the possibility to do zero point clamping within measurement supervision, see section "Measurement supervision"). In order to compensate for small magnitude and angular errors in the complete measurement chain (CT error, VT error, IED input transformer errors and so on.) it is possible to perform on site calibration of the power measurement. This is achieved by setting the complex constant which is then internally used within the function to multiply the calculated complex apparent power S. This constant is set as magnitude (setting parameter PowMagFact, default value 1.000) and angle (setting parameter PowAngComp, default value 0.0 degrees). Default values for these two parameters are done in such way that they do not influence internally calculated value (complex constant has default value 1). In this way calibration, for specific operating range (for example, around rated power) can be done at site. However, to perform this calibration it is necessary to have an external power meter with high accuracy class available.
Compensation facility
Section 14 Monitoring
Directionality
If CT grounding parameter is set as described in section "Analog inputs", active and reactive power will be measured always towards the protected object. This is shown in the following figure 340.
Busbar
52
IED Q
Protected Object
ANSI05000373_2_en.vsd
ANSI05000373 V2 EN
Figure 340:
Practically, it means that active and reactive power will have positive values when they flow from the busbar towards the protected object and they will have negative values when they flow from the protected object towards the busbar. In some application, for example, when power is measured on the secondary side of the power transformer it might be desirable, from the end client point of view, to have actually opposite directional convention for active and reactive power measurements. This can be easily achieved by setting parameter PowAngComp to value of 180.0 degrees. With such setting the active and reactive power will have positive values when they flow from the protected object towards the busbar.
Frequency
Frequency is actually not calculated within measurement block. It is simply obtained from the pre-processing block and then just given out from the measurement block as an output.
14.1.2.3
Section 14 Monitoring
outputs and IEC 61850. This is achieved by magnitude and angle compensation at 5, 30 and 100% of rated current. The compensation below 5% and above 100% is constant and linear in between, see figure 339. Phase currents (magnitude and angle) are available on the outputs and each magnitude output has a corresponding supervision level output (Ix_RANGE). The supervision output signal is an integer in the interval 0-4, see section "Measurement supervision".
14.1.2.4
14.1.2.5
14.1.3
Function block
The available function blocks of an IED are depending on the actual hardware (TRM) and the logic configuration made in PCM600.
Section 14 Monitoring
CVMMXN I3P* U3P* S S_RANGE P_INST P P_RANGE Q_INST Q Q_RANGE PF PF_RANGE ILAG ILEAD U U_RANGE I I_RANGE F F_RANGE IEC10000016-1-en.vsd
IEC10000016 V1 EN
Figure 341:
CMMXU I3P*
I_A IA_RANGE IA_ANGL I_B IB_RANGE IB_ANGL I_C IC_RANGE IC_ANGL ANSI05000699-2-en.vsd
ANSI05000699 V2 EN
Figure 342:
VNMMXU V3P* V_A VA_RANGE VA_ANGL V_B VB_RANGE VB_ANGL V_C VC_RANGE VC_ANGL ANSI09000850-1-en.vsd
ANSI09000850 V1 EN
Figure 343:
Section 14 Monitoring
VMMXU V3P* V_AB VAB_RANG VAB_ANGL V_BC VBC_RANG VBC_ANGL V_CA VCA_RANG VCA_ANGL ANSI05000701-2-en.vsd
ANSI05000701 V2 EN
Figure 344:
CMSQI I3P*
IEC05000703 V2 EN
Figure 345:
VMSQI V3P*
ANSI05000704 V2 EN
Figure 346:
14.1.4
Section 14 Monitoring
Table 408:
Name S S_RANGE P_INST P P_RANGE Q_INST Q Q_RANGE PF PF_RANGE ILAG ILEAD V V_RANGE I I_RANGE F F_RANGE
Table 409:
Name I3P
Table 410:
Name I_A IA_RANGE IA_ANGL I_B IB_RANGE IB_ANGL I_C IC_RANGE IC_ANGL
Section 14 Monitoring
Table 411:
Name V3P
Table 412:
Name V_A VA_RANGE VA_ANGL V_B VB_RANGE VB_ANGL V_C VC_RANGE VC_ANGL
Table 413:
Name V3P
Table 414:
Name V_AB VAB_RANG VAB_ANGL V_BC VBC_RANG VBC_ANGL V_CA VCA_RANG VCA_ANGL
Section 14 Monitoring
Table 415:
Name I3P
Table 416:
Name 3I0 3I0RANG 3I0ANGL I1 I1RANG I1ANGL I2 I2RANG I2ANGL
Table 417:
Name V3P
Table 418:
Name 3V0 3V0RANG 3V0ANGL V1 V1RANG V1ANGL V2 V2RANG V2ANGL
14.1.5
Table 419:
Name SLowLim SLowLowLim SMin SMax SRepTyp
%SB %SB -
0.1 0.1 -
%SB %SB -
0.1 0.1 -
0.001 0.001 -
%VB %VB -
0.1 0.1 -
%IB %IB -
0.1 0.1 -
FrMin FrMax
Hz Hz
0.001 0.001
0.000 70.000
Section 14 Monitoring
Name FrRepTyp Values (Range) Cyclic Dead band Int deadband Disabled Enabled 1 - 99999 0.05 - 2000.00 0.05 - 200000.00 A, B, C Arone Pos Seq AB BC CA A B C 0.000 - 6.000 -180.0 - 180.0 0.000 - 1.000 Unit Step Default Cyclic Description Reporting type
A kV MVA -
1 0.05 0.05 -
Disable/Enable Operation Base setting for current values in A Base setting for voltage value in kV Base setting for power values in MVA Selection of measured current and voltage
PowMagFact PowAngComp k
Deg -
Magnitude factor to scale power calculations Angle compensation for phase shift between measured I & V Low pass filter coefficient for power measurement, V and I
Table 420:
Name SDbRepInt SZeroDb SHiHiLim SHiLim SLimHyst PDbRepInt PZeroDb PHiHiLim PHiLim PLowLim PLowLowLim PLimHyst QDbRepInt
Section 14 Monitoring
Values (Range) 0 - 100000 -2000.0 - 2000.0 -2000.0 - 2000.0 -2000.0 - 2000.0 -2000.0 - 2000.0 0.000 - 100.000 1 - 300 0 - 100000 -1.000 - 1.000 -1.000 - 1.000 -1.000 - 1.000 -1.000 - 1.000 0.000 - 100.000 1 - 300 0 - 100000 0.0 - 200.0 0.0 - 200.0 0.0 - 200.0 0.0 - 200.0 0.000 - 100.000 1 - 300 0 - 100000 0.0 - 500.0 0.0 - 500.0 0.0 - 500.0 0.0 - 500.0 0.000 - 100.000 1 - 300 0 - 100000 0.000 - 100.000 0.000 - 100.000 Unit m% %SB %SB %SB %SB % Type m% % Type m% %VB %VB %VB %VB % Type m% %IB %IB %IB %IB % Type m% Hz Hz Step 1 0.1 0.1 0.1 0.1 0.001 1 1 0.001 0.001 0.001 0.001 0.001 1 1 0.1 0.1 0.1 0.1 0.001 1 1 0.1 0.1 0.1 0.1 0.001 1 1 0.001 0.001 Default 500 150.0 120.0 -120.0 -150.0 5.000 10 500 1.000 0.800 -0.800 -1.000 5.000 10 500 150.0 120.0 80.0 60.0 5.000 10 500 150.0 120.0 80.0 60.0 5.000 10 500 65.000 63.000 Description Zero point clamping in 0.001% of range High High limit in % of SBase High limit in % of SBase Low limit in % of SBase Low Low limit in % of SBase Hysteresis value in % of range (common for all limits) Cycl: Report interval (s), Db: In % of range, Int Db: In %s Zero point clamping in 0.001% of range High High limit (physical value) High limit (physical value) Low limit (physical value) Low Low limit (physical value) Hysteresis value in % of range (common for all limits) Cycl: Report interval (s), Db: In % of range, Int Db: In %s Zero point clamping in 0.001% of range High High limit in % of UBase High limit in % of UBase Low limit in % of UBase Low Low limit in % of UBase Hysteresis value in % of range (common for all limits) Cycl: Report interval (s), Db: In % of range, Int Db: In %s Zero point clamping in 0.001% of range High High limit in % of IBase High limit in % of IBase Low limit in % of IBase Low Low limit in % of IBase Hysteresis value in % of range (common for all limits) Cycl: Report interval (s), Db: In % of range, Int Db: In %s Zero point clamping in 0.001% of range High High limit (physical value) High limit (physical value)
Name QZeroDb QHiHiLim QHiLim QLowLim QLowLowLim QLimHyst PFDbRepInt PFZeroDb PFHiHiLim PFHiLim PFLowLim PFLowLowLim PFLimHyst VDbRepInt VZeroDb VHiHiLim VHiLim VLowLim VLowLowLim VLimHyst IDbRepInt IZeroDb IHiHiLim IHiLim ILowLim ILowLowLim ILimHyst FrDbRepInt FrZeroDb FrHiHiLim FrHiLim
Section 14 Monitoring
Name FrLowLim FrLowLowLim FrLimHyst VGenZeroDb IGenZeroDb VMagComp5 VMagComp30 VMagComp100 IMagComp5 IMagComp30 IMagComp100 IAngComp5 IAngComp30 IAngComp100 Values (Range) 0.000 - 100.000 0.000 - 100.000 0.000 - 100.000 1 - 100 1 - 100 -10.000 - 10.000 -10.000 - 10.000 -10.000 - 10.000 -10.000 - 10.000 -10.000 - 10.000 -10.000 - 10.000 -10.000 - 10.000 -10.000 - 10.000 -10.000 - 10.000 Unit Hz Hz % %VB %IB % % % % % % Deg Deg Deg Step 0.001 0.001 0.001 1 1 0.001 0.001 0.001 0.001 0.001 0.001 0.001 0.001 0.001 Default 47.000 45.000 5.000 5 5 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 Description
Low limit (physical value) Low Low limit (physical value) Hysteresis value in % of range (common for all limits) Zero point clamping in % of VBase Zero point clamping in % of IBase Magnitude factor to calibrate voltage at 5% of Vn Magnitude factor to calibrate voltage at 30% of Vn Magnitude factor to calibrate voltage at 100% of Vn Magnitude factor to calibrate current at 5% of In Magnitude factor to calibrate current at 30% of In Magnitude factor to calibrate current at 100% of In Angle calibration for current at 5% of In Angle calibration for current at 30% of In Angle calibration for current at 100% of In
Table 421:
Name IA_DbRepInt Operation IBase IA_Max IA_RepTyp
Type Type A
1 1 0.001
10 10 1000.000
Cycl: Report interval (s), Db: In % of range, Int Db: In %s Cycl: Report interval (s), Db: In % of range, Int Db: In %s Maximum value
Section 14 Monitoring
Values (Range) Cyclic Dead band Int deadband 1 - 300 1 - 300 0.000 10000000000.000 Cyclic Dead band Int deadband 1 - 300 Unit Step Default Cyclic Description Reporting type
Name IB_RepTyp
Type Type A -
1 1 0.001 -
10 10 1000.000 Cyclic
Cycl: Report interval (s), Db: In % of range, Int Db: In %s Cycl: Report interval (s), Db: In % of range, Int Db: In %s Maximum value Reporting type
IC_AngDbRepInt
Type
10
Table 422:
Name IA_ZeroDb IA_HiHiLim IA_HiLim IMagComp5 IMagComp30 IA_LowLim IA_LowLowLim IMagComp100 IAngComp5 IA_Min IAngComp30 IAngComp100 IA_LimHys IB_ZeroDb IB_HiHiLim
Section 14 Monitoring
Name IB_HiLim IB_LowLim IB_LowLowLim IB_Min IB_LimHys IC_ZeroDb IC_HiHiLim IC_HiLim IC_LowLim IC_LowLowLim IC_Min IC_LimHys Values (Range) 0.000 10000000000.000 0.000 10000000000.000 0.000 10000000000.000 0.000 10000000000.000 0.000 - 100.000 0 - 100000 0.000 10000000000.000 0.000 10000000000.000 0.000 10000000000.000 0.000 10000000000.000 0.000 10000000000.000 0.000 - 100.000 Unit A A A A % m% A A A A A % Step 0.001 0.001 0.001 0.001 0.001 1 0.001 0.001 0.001 0.001 0.001 0.001 Default 800.000 0.000 0.000 0.000 5.000 0 900.000 800.000 0.000 0.000 0.000 5.000 Description
High limit (physical value) Low limit (physical value) Low Low limit (physical value) Minimum value Hysteresis value in % of range and is common for all limits Zero point clamping in 0.001% of range High High limit (physical value) High limit (physical value) Low limit (physical value) Low Low limit (physical value) Minimum value Hysteresis value in % of range and is common for all limits
Table 423:
Name VA_DbRepInt Operation VBase VA_Max VA_RepTyp
% Type Type
0.001 1 1
5.000 10 10
Hysteresis value in % of range and is common for all limits Cycl: Report interval (s), Db: In % of range, Int Db: In %s Cycl: Report interval (s), Db: In % of range, Int Db: In %s
Section 14 Monitoring
Values (Range) 0.000 10000000000.000 Cyclic Dead band Int deadband 0.000 - 100.000 1 - 300 1 - 300 0.000 10000000000.000 Cyclic Dead band Int deadband 0.000 - 100.000 1 - 300 Unit V Step 0.001 Default 300000.000 Cyclic Description Maximum value Reporting type
% Type Type V -
0.001 1 1 0.001 -
Hysteresis value in % of range and is common for all limits Cycl: Report interval (s), Db: In % of range, Int Db: In %s Cycl: Report interval (s), Db: In % of range, Int Db: In %s Maximum value Reporting type
VC_LimHys VC_AnDbRepInt
% Type
0.001 1
5.000 10
Hysteresis value in % of range and is common for all limits Cycl: Report interval (s), Db: In % of range, Int Db: In %s
Table 424:
Name VA_ZeroDb VA_HiHiLim VA_HiLim VA_LowLim VA_LowLowLim VMagComp100 VA_Min VB_ZeroDb VB_HiHiLim VB_HiLim VB_LowLim
Section 14 Monitoring
Name VB_LowLowLim VB_Min VC_ZeroDb VC_HiHiLim VC_HiLim VC_LowLim VC_LowLowLim VC_Min Values (Range) 0.000 10000000000.000 0.000 10000000000.000 0 - 100000 0.000 10000000000.000 0.000 10000000000.000 0.000 10000000000.000 0.000 10000000000.000 0.000 10000000000.000 Unit V V m% V V V V V Step 0.001 0.001 1 0.001 0.001 0.001 0.001 0.001 Default 200000.000 0.000 0 260000.000 240000.000 220000.000 200000.000 0.000 Description
Low Low limit (physical value) Minimum value Zero point clamping in 0.001% of range High High limit (physical value) High limit (physical value) Low limit (physical value) Low Low limit (physical value) Minimum value
Table 425:
Name VAB_DbRepInt Operation VBase VAB_Max VAB_RepTyp
Type Type V -
1 1 0.001 -
10 10 500000.000 Cyclic
Cycl: Report interval (s), Db: In % of range, Int Db: In %s Cycl: Report interval (s), Db: In % of range, Int Db: In %s Maximum value Reporting type
VBC_AnDbRepInt VCA_DbRepInt
Type Type
1 1
10 10
Cycl: Report interval (s), Db: In % of range, Int Db: In %s Cycl: Report interval (s), Db: In % of range, Int Db: In %s
Section 14 Monitoring
Values (Range) 0.000 10000000000.000 Cyclic Dead band Int deadband 1 - 300 Unit V Step 0.001 Default 500000.000 Cyclic Description Maximum value Reporting type
VCA_AnDbRepInt
Type
10
Table 426:
Name VAB_ZeroDb VAB_HiHiLim VAB_HiLim VAB_LowLim VAB_LowLowLim VMagComp100 VAB_Min VAB_LimHys VBC_ZeroDb VBC_HiHiLim VBC_HiLim VBC_LowLim VBC_LowLowLim VBC_Min VBC_LimHys VCA_ZeroDb VCA_HiHiLim VCA_HiLim
Section 14 Monitoring
Name VCA_LowLim VCA_LowLowLim VCA_Min VCA_LimHys Values (Range) 0.000 10000000000.000 0.000 10000000000.000 0.000 10000000000.000 0.000 - 100.000 Unit V V V % Step 0.001 0.001 0.001 0.001 Default 380000.000 350000.000 0.000 5.000 Description
Low limit (physical value) Low Low limit (physical value) Minimum value Hysteresis value in % of range and is common for all limits
Table 427:
Name 3I0DbRepInt 3I0Min 3I0Max 3I0RepTyp
Hysteresis value in % of range and is common for all limits Cycl: Report interval (s), Db: In % of range, Int Db: In %s Disbled/Enabled operation Minimum value Maximum value Reporting type
Type A A -
1 0.001 0.001 -
Cycl: Report interval (s), Db: In % of range, Int Db: In %s Minimum value Maximum value Reporting type
I1AngDbRepInt I1AngMax
Type Deg
1 0.001
10 180.000
Cycl: Report interval (s), Db: In % of range, Int Db: In %s Maximum value
Section 14 Monitoring
Values (Range) Cyclic Dead band Int deadband 1 - 300 0.000 10000000000.000 0.000 10000000000.000 Cyclic Dead band Int deadband 0.000 - 100.000 1 - 300 -180.000 - 180.000 Cyclic Dead band Int deadband Unit Step Default Cyclic Description Reporting type
Name I1AngRepTyp
Type A A -
1 0.001 0.001 -
Cycl: Report interval (s), Db: In % of range, Int Db: In %s Minimum value Maximum value Reporting type
% Type Deg -
0.001 1 0.001 -
Hysteresis value in % of range and is common for all limits Cycl: Report interval (s), Db: In % of range, Int Db: In %s Minimum value Reporting type
Table 428:
Name 3I0ZeroDb 3I0HiHiLim 3I0HiLim 3I0LowLim 3I0LowLowLim 3I0AngZeroDb I1ZeroDb I1HiHiLim I1HiLim I1LowLim I1LowLowLim
Section 14 Monitoring
Name I1LimHys I1AngZeroDb I1AngMin I2ZeroDb I2HiHiLim I2HiLim I2LowLim I2LowLowLim I2AngZeroDb I2AngMax Values (Range) 0.000 - 100.000 0 - 100000 -180.000 - 180.000 0 - 100000 0.000 10000000000.000 0.000 10000000000.000 0.000 10000000000.000 0.000 10000000000.000 0 - 100000 -180.000 - 180.000 Unit % m% Deg m% A A A A m% Deg Step 0.001 1 0.001 1 0.001 0.001 0.001 0.001 1 0.001 Default 5.000 0 -180.000 0 900.000 800.000 0.000 0.000 0 180.000 Description
Hysteresis value in % of range and is common for all limits Zero point clamping in 0.001% of range Minimum value Zero point clamping in 0.001% of range High High limit (physical value) High limit (physical value) Low limit (physical value) Low Low limit (physical value) Zero point clamping in 0.001% of range Maximum value
Table 429:
Name 3V0DbRepInt 3V0Min 3V0Max 3V0RepTyp
Hysteresis value in % of range and is common for all limits Cycl: Report interval (s), Db: In % of range, Int Db: In %s Disbled/Enabled operation Zero point clamping in 0.001% of range Minimum value Maximum value Reporting type
V1DbRepInt
Type
10
Section 14 Monitoring
Values (Range) 0.000 10000000000.000 0.000 10000000000.000 Cyclic Dead band Int deadband 0.000 - 100.000 1 - 300 1 - 300 0.000 10000000000.000 0.000 10000000000.000 Cyclic Dead band Int deadband 0.000 - 100.000 1 - 300 -180.000 - 180.000 -180.000 - 180.000 Cyclic Dead band Int deadband -10.000 - 10.000 -10.000 - 10.000 -10.000 - 10.000 Unit V V Step 0.001 0.001 Default 0.000 300000.000 Cyclic Description Minimum value Maximum value Reporting type
% Type Type V V -
Hysteresis value in % of range and is common for all limits Cycl: Report interval (s), Db: In % of range, Int Db: In %s Cycl: Report interval (s), Db: In % of range, Int Db: In %s Minimum value Maximum value Reporting type
Hysteresis value in % of range and is common for all limits Cycl: Report interval (s), Db: In % of range, Int Db: In %s Minimum value Maximum value Reporting type
% % %
Amplitude factor to pre-calibrate voltage at 5% of Ir Amplitude factor to pre-calibrate voltage at 30% of Ir Amplitude factor to pre-calibrate voltage at 100% of Ir
Table 430:
Name 3V0ZeroDb 3V0HiHiLim 3V0HiLim
Section 14 Monitoring
Name 3V0LowLim 3V0LowLowLim V1ZeroDb V1HiHiLim V1HiLim V1LowLim V1LowLowLim V1AngZeroDb V1AngMin V1AngMax V1AngRepTyp Values (Range) 0.000 10000000000.000 0.000 10000000000.000 0 - 100000 0.000 10000000000.000 0.000 10000000000.000 0.000 10000000000.000 0.000 10000000000.000 0 - 100000 -180.000 - 180.000 -180.000 - 180.000 Cyclic Dead band Int deadband 0 - 100000 0.000 10000000000.000 0.000 10000000000.000 0.000 10000000000.000 0.000 10000000000.000 0 - 100000 Unit V V m% V V V V m% Deg Deg Step 0.001 0.001 1 0.001 0.001 0.001 0.001 1 0.001 0.001 Default 220000.000 200000.000 0 260000.000 240000.000 220000.000 200000.000 0 -180.000 180.000 Cyclic Description
Low limit (physical value) Low Low limit (physical value) Zero point clamping in 0.001% of range High High limit (physical value) High limit (physical value) Low limit (physical value) Low Low limit (physical value) Zero point clamping in 0.001% of range Minimum value Maximum value Reporting type
m% V V V V m%
Zero point clamping in 0.001% of range High High limit (physical value) High limit (physical value) Low limit (physical value) Low Low limit (physical value) Zero point clamping in 0.001% of range
14.1.6
Technical data
Table 431:
Function Frequency Voltage Connected current Table continues on next page
Section 14 Monitoring
Function Active power, P Reactive power, Q Apparent power, S Power factor, cos () Range or value 0.1 x Vn< V < 1.5 x Vn 0.2 x In < I < 4.0 x In 0.1 x Vn< V < 1.5 x Vn 0.2 x In < I < 4.0 x In 0.1 x Vn < V < 1.5 x Vn 0.2 x In< I < 4.0 x In 0.1 x Vn < V < 1.5 x Vn 0.2 x In< I < 4.0 x In 0.02 Accuracy 1.0% of Sn at S Sn 1.0% of S at S > Sn Conditions: 0.8 x Vn < V < 1.2 Vn 0.2 x In < I < 1.2 In
Table 432:
Function Current Phase angle
Table 433:
Function Voltage Phase angle
Table 434:
Function Voltage Phase angle
Section 14 Monitoring
Table 435:
Function
Current positive sequence, I1 Three phase settings Current zero sequence, 3I0 Three phase settings Current negative sequence, I2 Three phase settings Phase angle
Table 436:
Function
Voltage positive sequence, U1 Voltage zero sequence, 3U0 Voltage negative sequence, U2 Phase angle
14.2
14.2.1
14.2.2
Introduction
Event counter (CNTGGIO) has six counters which are used for storing the number of times each counter input has been activated.
14.2.3
14.2.3.1
Reporting
The content of the counters can be read in the local HMI. Reset of counters can be performed in the local HMI and a binary input. Reading of content can also be performed remotely, for example from a IEC 61850 client. The value can also be presented as a measuring value on the local HMI graphical display.
14.2.3.2
Design
The function block has six inputs for increasing the counter values for each of the six counters respectively. The content of the counters are stepped one step for each positive edge of the input respectively. The function block also has an input BLOCK. At activation of this input all six counters are blocked and are not updated. Valid number is held. The function block has an input RESET. At activation of this input all six counters are set to 0.
IEC05000345-2-en.vsd
IEC05000345 V2 EN
Figure 347:
14.2.5
Input signals
Table 437:
Name BLOCK COUNTER1 COUNTER2 COUNTER3 COUNTER4 COUNTER5 COUNTER6 RESET
Table 438:
Name VALUE1 VALUE2 VALUE3 VALUE4 VALUE5 VALUE6
14.2.6
Table 439:
Name Operation
14.2.7
Technical data
Table 440:
Function Counter value Max. count up speed
14.3
14.3.1
Introduction
When using a Substation Automation system with LON or SPA communication, timetagged events can be sent at change or cyclically from the IED to the station level. These events are created from any available signal in the IED that is connected to the Event function (EVENT). The event function block is used for remote communication. Analog and double indication values are also transferred through EVENT function.
14.3.2
Principle of operation
The main purpose of the event function (EVENT) is to generate events when the state or value of any of the connected input signals is in a state, or is undergoing a state transition, for which event generation is enabled. Each EVENT function has 16 inputs INPUT1 - INPUT16. Each input can be given a name from the Application Configuration tool. The inputs are normally used to create single events, but are also intended for double indication events.
751
Section 14 Monitoring
EVENT function also has an input BLOCK to block the generation of events. The events that are sent from the IED can originate from both internal logical signals and binary input channels. The internal signals are time-tagged in the main processing module, while the binary input channels are time-tagged directly on the input module. The time-tagging of the events that are originated from internal logical signals have a resolution corresponding to the execution cyclicity of EVENT function. The timetagging of the events that are originated from binary input signals have a resolution of 1 ms. The outputs from EVENT function are formed by the reading of status, events and alarms by the station level on every single input. The user-defined name for each input is intended to be used by the station level. All events according to the event mask are stored in a buffer, which contains up to 1000 events. If new events appear before the oldest event in the buffer is read, the oldest event is overwritten and an overflow alarm appears. The events are produced according to the set-event masks. The event masks are treated commonly for both the LON and SPA communication. The EventMask can be set individually for each input channel. These settings are available: NoEvents OnSet OnReset OnChange AutoDetect
It is possible to define which part of EVENT function generates the events. This can be performed individually for the SPAChannelMask and LONChannelMask respectively. For each communication type these settings are available: Disabled Channel 1-8 Channel 9-16 Channel 1-16
For LON communication the events normally are sent to station level at change. It is possibly also to set a time for cyclic sending of the events individually for each input channel. To protect the SA system from signals with a high change rate that can easily saturate the event system or the communication subsystems behind it, a quota limiter is implemented. If an input creates events at a rate that completely consume the granted quota then further events from the channel will be blocked. This block will be removed
Section 14 Monitoring
when the input calms down and the accumulated quota reach 66% of the maximum burst quota. The maximum burst quota per input channel is 45 events per second.
14.3.3
Function block
EVENT BLOCK ^INPUT1 ^INPUT2 ^INPUT3 ^INPUT4 ^INPUT5 ^INPUT6 ^INPUT7 ^INPUT8 ^INPUT9 ^INPUT10 ^INPUT11 ^INPUT12 ^INPUT13 ^INPUT14 ^INPUT15 ^INPUT16 IEC05000697-2-en.vsd
IEC05000697 V2 EN
Figure 348:
14.3.4
Section 14 Monitoring
Name INPUT10 INPUT11 INPUT12 INPUT13 INPUT14 INPUT15 INPUT16 Type GROUP SIGNAL GROUP SIGNAL GROUP SIGNAL GROUP SIGNAL GROUP SIGNAL GROUP SIGNAL GROUP SIGNAL Default 0 0 0 0 0 0 0 Description Input 10 Input 11 Input 12 Input 13 Input 14 Input 15 Input 16
14.3.5
Table 442:
Name SPAChannelMask
Setting parameters
EVENT Non group settings (basic)
Values (Range) Disabled Channel 1-8 Channel 9-16 Channel 1-16 Disabled Channel 1-8 Channel 9-16 Channel 1-16 NoEvents OnSet OnReset OnChange AutoDetect NoEvents OnSet OnReset OnChange AutoDetect NoEvents OnSet OnReset OnChange AutoDetect NoEvents OnSet OnReset OnChange AutoDetect Unit Step Default Disabled Description SPA channel mask
LONChannelMask
Disabled
EventMask1
AutoDetect
EventMask2
AutoDetect
EventMask3
AutoDetect
EventMask4
AutoDetect
Section 14 Monitoring
Values (Range) NoEvents OnSet OnReset OnChange AutoDetect NoEvents OnSet OnReset OnChange AutoDetect NoEvents OnSet OnReset OnChange AutoDetect NoEvents OnSet OnReset OnChange AutoDetect NoEvents OnSet OnReset OnChange AutoDetect NoEvents OnSet OnReset OnChange AutoDetect NoEvents OnSet OnReset OnChange AutoDetect NoEvents OnSet OnReset OnChange AutoDetect NoEvents OnSet OnReset OnChange AutoDetect NoEvents OnSet OnReset OnChange AutoDetect Unit Step Default AutoDetect Description Reporting criteria for input 5
Name EventMask5
EventMask6
AutoDetect
EventMask7
AutoDetect
EventMask8
AutoDetect
EventMask9
AutoDetect
EventMask10
AutoDetect
EventMask11
AutoDetect
EventMask12
AutoDetect
EventMask13
AutoDetect
EventMask14
AutoDetect
Section 14 Monitoring
Name EventMask15 Values (Range) NoEvents OnSet OnReset OnChange AutoDetect NoEvents OnSet OnReset OnChange AutoDetect 0 - 3600 0 - 3600 0 - 3600 0 - 3600 0 - 3600 0 - 3600 0 - 3600 0 - 3600 0 - 3600 0 - 3600 0 - 3600 0 - 3600 0 - 3600 0 - 3600 0 - 3600 0 - 3600 Unit Step Default AutoDetect Description
EventMask16
AutoDetect
MinRepIntVal1 MinRepIntVal2 MinRepIntVal3 MinRepIntVal4 MinRepIntVal5 MinRepIntVal6 MinRepIntVal7 MinRepIntVal8 MinRepIntVal9 MinRepIntVal10 MinRepIntVal11 MinRepIntVal12 MinRepIntVal13 MinRepIntVal14 MinRepIntVal15 MinRepIntVal16
s s s s s s s s s s s s s s s s
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Minimum reporting interval input 1 Minimum reporting interval input 2 Minimum reporting interval input 3 Minimum reporting interval input 4 Minimum reporting interval input 5 Minimum reporting interval input 6 Minimum reporting interval input 7 Minimum reporting interval input 8 Minimum reporting interval input 9 Minimum reporting interval input 10 Minimum reporting interval input 11 Minimum reporting interval input 12 Minimum reporting interval input 13 Minimum reporting interval input 14 Minimum reporting interval input 15 Minimum reporting interval input 16
14.4
14.4.1
Introduction
The Logical signal status report (BINSTATREP) function makes it possible for a SPA master to poll signals from various other functions.
14.4.2
INPUTn OUTPUTn t t
IEC09000732-1-en.vsd
IEC09000732 V1 EN
Figure 349:
14.4.3
Function block
BINSTATREP OUTPUT1 BLOCK ^INPUT1 OUTPUT2 ^INPUT2 OUTPUT3 ^INPUT3 OUTPUT4 ^INPUT4 OUTPUT5 ^INPUT5 OUTPUT6 ^INPUT6 OUTPUT7 ^INPUT7 OUTPUT8 ^INPUT8 OUTPUT9 ^INPUT9 OUTPUT10 ^INPUT10 OUTPUT11 ^INPUT11 OUTPUT12 ^INPUT12 OUTPUT13 ^INPUT13 OUTPUT14 ^INPUT14 OUTPUT15 ^INPUT15 OUTPUT16 ^INPUT16 IEC09000730-1-en.vsd
IEC09000730 V1 EN
Figure 350:
Table 444:
Name OUTPUT1 OUTPUT2 OUTPUT3 OUTPUT4 OUTPUT5 OUTPUT6 OUTPUT7 OUTPUT8 OUTPUT9 OUTPUT10 OUTPUT11 OUTPUT12 OUTPUT13
Section 14 Monitoring
Name OUTPUT14 OUTPUT15 OUTPUT16 Type BOOLEAN BOOLEAN BOOLEAN Description Logical status report output 14 Logical status report output 15 Logical status report output 16
14.4.5
Table 445:
Name t
Setting parameters
BINSTATREP Non group settings (basic)
Values (Range) 0.000 - 60000.000 Unit s Step 0.001 Default 10.000 Description Time delay of function
14.5
14.5.1
Introduction
The current and voltage measurements functions (CVMMXN, CMMXU, VMMXU and VNMMXU), current and voltage sequence measurement functions (CMSQI and VMSQI) and IEC 61850 generic communication I/O functions (MVGGIO) are provided with measurement supervision functionality. All measured values can be supervised with four settable limits: low-low limit, low limit, high limit and high-high limit. The measure value expander block (RANGE_XP) has been introduced to enable translating the integer output signal from the measuring functions to 5 binary signals: below low-low limit, below low limit, normal, above high-high limit or above high limit. The output signals can be used as conditions in the configurable logic or for alarming purpose.
14.5.2
Principle of operation
The input signal must be connected to a range output of a measuring function block (CVMMXN, CMMXU, VMMXU, VNMMXU, CMSQI, VMSQ or MVGGIO). The function block converts the input integer value to five binary output signals according to table 446.
Section 14 Monitoring
Table 446:
Measured supervised value is: Output: LOWLOW LOW NORMAL HIGH HIGHHIGH
14.5.3
Function block
RANGE* RANGE_XP HIGHHIGH HIGH NORMAL LOW LOWLOW IEC05000346-2-en.vsd
IEC05000346 V2 EN
Figure 351:
14.5.4
Table 448:
Name HIGHHIGH HIGH NORMAL LOW LOWLOW
14.6
Section 14 Monitoring
Function description Analog input signals Disturbance report Disturbance report Disturbance report Disturbance report IEC 61850 identification A41RADR DRPRDRE A1RADR A4RADR B1RBDR IEC 60617 identification ANSI/IEEE C37.2 device number -
14.6.1
Introduction
Complete and reliable information about disturbances in the primary and/or in the secondary system together with continuous event-logging is accomplished by the disturbance report functionality. Disturbance report DRPRDRE, always included in the IED, acquires sampled data of all selected analog input and binary signals connected to the function block with a, maximum of 40 analog and 96 binary signals. The Disturbance report functionality is a common name for several functions: Sequential of events Indications Event recorder Trip value recorder Disturbance recorder
The Disturbance report function is characterized by great flexibility regarding configuration, initiating conditions, recording times, and large storage capacity. A disturbance is defined as an activation of an input to the AxRADR or BxRBDR function blocks, which are set to trigger the disturbance recorder. All signals from start of pre-fault time to the end of post-fault time will be included in the recording. Every disturbance report recording is saved in the IED in the standard Comtrade format. The same applies to all events, which are continuously saved in a ring-buffer. The local HMI is used to get information about the recordings. The disturbance report files may be uploaded to PCM600 for further analysis using the disturbance handling tool.
Disturbance report DRPRDRE is a common name for several functions to supply the operator, analysis engineer, and so on, with sufficient information about events in the system. The functions included in the disturbance report are: Sequential of events (SOE) Indications (IND) Event recorder (ER) Trip value recorder(TVR) Disturbance recorder (DR)
Figure 352 shows the relations between Disturbance Report, included functions and function blocks. Sequential of events (SOE), Event recorder (ER) and Indications (IND) uses information from the binary input function blocks (BxRBDR). Trip value recorder (TVR) uses analog information from the analog input function blocks (AxRADR). Disturbance recorder DRPRDRE acquires information from both AxRADR and BxRBDR.
A1-4RADR Disturbance Report
B1-6RBDR
Disturbance recorder
Binary signals
ANSI09000337-1-en.vsd
ANSI09000337 V1 EN
Figure 352:
Section 14 Monitoring
The whole disturbance report can contain information for a number of recordings, each with the data coming from all the parts mentioned above. The sequential of events function is working continuously, independent of disturbance triggering, recording time, and so on. All information in the disturbance report is stored in non-volatile flash memories. This implies that no information is lost in case of loss of auxiliary power. Each report will get an identification number in the interval from 0-999.
Disturbance report
Record no. N
Indications
Trip values
Event recordings
Disturbance recording
ANSI05000161 V1 EN
Figure 353:
Up to 100 disturbance reports can be stored. If a new disturbance is to be recorded when the memory is full, the oldest disturbance report is overwritten by the new one. The total recording capacity for the disturbance recorder is depending of sampling frequency, number of analog and binary channels and recording time. Figure 354 shows the number of recordings versus the total recording time tested for a typical configuration, that is, in a 60 Hz system it is possible to record 80 where the average recording time is 3.4 seconds. The memory limit does not affect the rest of the disturbance report (Event list (EL), Event recorder (ER), Indications (IND) and Trip value recorder (TVR)).
Section 14 Monitoring
6.3s 50 Hz
40
6.3s 60 Hz
Figure 354:
The maximum number of recordings depend on each recordings total recording time. Long recording time will reduce the number of recordings to less than 100.
The IED flash disk should NOT be used to store any user files. This might cause disturbance recordings to be deleted due to lack of disk space.
Disturbance information
Date and time of the disturbance, the indications, events, fault location and the trip values are available on the local HMI. To acquire a complete disturbance report the user must use a PC and - either the PCM600 Disturbance handling tool - or a FTP or MMS (over 61850) client. The PC can be connected to the IED front, rear or remotely via the station bus (Ethernet ports).
Indications (IND)
Indications is a list of signals that were activated during the total recording time of the disturbance (not time-tagged), see section "Indications" for more detailed information.
764 Technical reference manual
Section 14 Monitoring
Event recorder (ER)
The event recorder may contain a list of up to 150 time-tagged events, which have occurred during the disturbance. The information is available via the local HMI or PCM600, see section "Event recorder" for more detailed information.
The sequetial of events may contain a list of totally 1000 time-tagged events. The list information is continuously updated when selected binary signals change state. The oldest data is overwritten. The logged signals may be presented via local HMI or PCM600, see section "Sequential of events" for more detailed information.
The recorded trip values include phasors of selected analog signals before the fault and during the fault, see section "Trip value recorder" for more detailed information.
Disturbance recorder records analog and binary signal data before, during and after the fault, see section "Disturbance recorder" for more detailed information.
Time tagging
The IED has a built-in real-time calendar and clock. This function is used for all time tagging within the disturbance report
Recording times
Disturbance report DRPRDRE records information about a disturbance during a settable time frame. The recording times are valid for the whole disturbance report. Disturbance recorder (DR), event recorder (ER) and indication function register disturbance data and events during tRecording, the total recording time. The total recording time, tRecording, of a recorded disturbance is:
tRecording =
PreFaultrecT + tFault + PostFaultrecT or PreFaultrecT + TimeLimit, depending on which criterion stops the current disturbance recording
Section 14 Monitoring
3
en05000487.vsd
IEC05000487 V1 EN
Figure 355:
PreFaultRecT, 1 tFault, 2
PostFaultRecT, 3 Post fault recording time. The time the disturbance recording continues after all activated triggers are reset. Use the setting PostFaultRecT to set this time. TimeLimit Limit time. The maximum allowed recording time after the disturbance recording was triggered. The limit time is used to eliminate the consequences of a trigger that does not reset within a reasonable time interval. It limits the maximum recording time of a recording and prevents subsequent overwriting of already stored disturbances. Use the setting TimeLimit to set this time.
Analog signals
Up to 40 analog signals can be selected for recording by the Disturbance recorder and triggering of the Disturbance report function. Out of these 40, 30 are reserved for external analog signals from analog input modules (TRM) and line data communication module (LDCM) via preprocessing function blocks (SMAI) and summation block (3PHSUM). The last 10 channels may be connected to internally calculated analog signals available as function block output signals (mA input signals, phase differential currents, bias currents and so on).
Section 14 Monitoring
SMAI Block ^GRP2_A ^GRP2_B ^GRP2_C ^GRP2_N Type AI3P AI1 AI2 AI3 AI4 AIN
A1RADR A2RADR INPUT1 INPUT2 INPUT3 INPUT4 INPUT5 INPUT6 ... A4RADR INPUT31 INPUT32 INPUT33 INPUT34 INPUT35 INPUT36 ... INPUT40
ANSI10000029-1-en.vsd
A3RADR
ANSI10000029 V1 EN
Figure 356:
The external input signals will be acquired, filtered and skewed and (after configuration) available as an input signal on the AxRADR function block via the SMAI function block. The information is saved at the Disturbance report base sampling rate (1000 or 1200 Hz). Internally calculated signals are updated according to the cycle time of the specific function. If a function is running at lower speed than the base sampling rate, Disturbance recorder will use the latest updated sample until a new updated sample is available. If the IED is preconfigured the only tool needed for analog configuration of the Disturbance report is the Signal Matrix Tool (SMT, external signal configuration). In case of modification of a preconfigured IED or general internal configuration the Application Configuration tool within PCM600 is used. The preprocessor function block (SMAI) calculates the residual quantities in cases where only the three phases are connected (AI4-input not used). SMAI makes the information available as a group signal output, phase outputs and calculated residual output (AIN-output). In situations where AI4-input is used as an input signal the corresponding information is available on the non-calculated output (AI4) on the SMAI function block. Connect the signals to the AxRADR accordingly.
Section 14 Monitoring
For each of the analog signals, Operation = Enabled means that it is recorded by the disturbance recorder. The trigger is independent of the setting of Operation, and triggers even if operation is set to Disabled. Both undervoltage and overvoltage can be used as trigger conditions. The same applies for the current signals. If Operation = Disabled, no waveform (samples) will be recorded and reported in graph. However, Trip value, pre-fault and fault value will be recorded and reported. The input channel can still be used to trig the disturbance recorder. If Operation = Enabled, waveform (samples) will also be recorded and reported in graph. The analog signals are presented only in the disturbance recording, but they affect the entire disturbance report when being used as triggers.
Binary signals
Up to 96 binary signals can be selected to be handled by disturbance report. The signals can be selected from internal logical and binary input signals. A binary signal is selected to be recorded when: the corresponding function block is included in the configuration the signal is connected to the input of the function block
Each of the 96 signals can be selected as a trigger of the disturbance report (Operation = Operation>TrigDR =Disabled). A binary signal can be selected to activate the red LED on the local HMI (SetLED = Enabled/Disabled). The selected signals are presented in the event recorder, sequential of events and the disturbance recording. But they affect the whole disturbance report when they are used as triggers. The indications are also selected from these 96 signals with local HMI IndicationMask=Show/Hide.
Trigger signals
The trigger conditions affect the entire disturbance report, except the sequential of events, which runs continuously. As soon as at least one trigger condition is fulfilled, a complete disturbance report is recorded. On the other hand, if no trigger condition is fulfilled, there is no disturbance report, no indications, and so on. This implies the importance of choosing the right signals as trigger conditions. A trigger can be of type: Manual trigger Binary-signal trigger Analog-signal trigger (over/under function)
Section 14 Monitoring
Manual trigger
A disturbance report can be manually triggered from the local HMI, PCM600 or via station bus (IEC 61850). When the trigger is activated, the manual trigger signal is generated. This feature is especially useful for testing. Refer to the operator's manual for procedure.
Binary-signal trigger
Any binary signal state (logic one or a logic zero) can be selected to generate a trigger (Triglevel = Trig on 0/Trig on 1). When a binary signal is selected to generate a trigger from a logic zero, the selected signal will not be listed in the indications list of the disturbance report.
Analog-signal trigger
All analog signals are available for trigger purposes, no matter if they are recorded in the disturbance recorder or not. The settings are OverTrigOp, UnderTrigOp, OverTrigLe and UnderTrigLe. The check of the trigger condition is based on peak-to-peak values. When this is found, the absolute average value of these two peak values is calculated. If the average value is above the threshold level for an overvoltage or overcurrent trigger, this trigger is indicated with a greater than (>) sign with the user-defined name. If the average value is below the set threshold level for an undervoltage or undercurrent trigger, this trigger is indicated with a less than (<) sign with its name. The procedure is separately performed for each channel. This method of checking the analog trigger conditions gives a function which is insensitive to DC offset in the signal. The operate time for this initiation is typically in the range of one cycle, 16 2/3 ms for a 60 Hz network. All under/over trig signal information is available on the local HMI and PCM600.
Post Retrigger
Disturbance report function does not automatically respond to any new trig condition during a recording, after all signals set as trigger signals have been reset. However, under certain circumstances the fault condition may reoccur during the post-fault recording, for instance by automatic reclosing to a still faulty power line. In order to capture the new disturbance it is possible to allow retriggering (PostRetrig = Enabled) during the post-fault time. In this case a new, complete recording will start and, during a period, run in parallel with the initial recording. When the retrig parameter is disabled (PostRetrig = Disabled), a new recording will not start until the post-fault (PostFaultrecT or TimeLimit) period is terminated. If a new trig occurs during the post-fault period and lasts longer than the proceeding recording a new complete recording will be started.
769 Technical reference manual
Section 14 Monitoring
14.6.3
Function block
DRPRDRE DRPOFF RECSTART RECMADE CLEARED MEMUSED IEC05000406-3-en.vsd
IEC05000406 V3 EN
Figure 357:
A1RADR ^INPUT1 ^INPUT2 ^INPUT3 ^INPUT4 ^INPUT5 ^INPUT6 ^INPUT7 ^INPUT8 ^INPUT9 ^INPUT10 IEC05000430-3-en.vsd
IEC05000430 V3 EN
Figure 358:
A4RADR ^INPUT31 ^INPUT32 ^INPUT33 ^INPUT34 ^INPUT35 ^INPUT36 ^INPUT37 ^INPUT38 ^INPUT39 ^INPUT40 IEC05000431-3-en.vsd
IEC05000431 V3 EN
Figure 359:
Section 14 Monitoring
B1RBDR ^INPUT1 ^INPUT2 ^INPUT3 ^INPUT4 ^INPUT5 ^INPUT6 ^INPUT7 ^INPUT8 ^INPUT9 ^INPUT10 ^INPUT11 ^INPUT12 ^INPUT13 ^INPUT14 ^INPUT15 ^INPUT16 IEC05000432-3-en.vsd
IEC05000432 V3 EN
Figure 360:
14.6.4
Table 450:
Name INPUT1 INPUT2 INPUT3 INPUT4 INPUT5 INPUT6 INPUT7
Section 14 Monitoring
Name INPUT8 INPUT9 INPUT10 Type GROUP SIGNAL GROUP SIGNAL GROUP SIGNAL Default Description Group signal for input 8 Group signal for input 9 Group signal for input 10
Table 451:
Name INPUT31 INPUT32 INPUT33 INPUT34 INPUT35 INPUT36 INPUT37 INPUT38 INPUT39 INPUT40
Table 452:
Name INPUT1 INPUT2 INPUT3 INPUT4 INPUT5 INPUT6 INPUT7 INPUT8 INPUT9 INPUT10 INPUT11 INPUT12 INPUT13
Section 14 Monitoring
Name INPUT14 INPUT15 INPUT16 Type BOOLEAN BOOLEAN BOOLEAN Default 0 0 0 Description Binary channel 14 Binary channel 15 Binary channel 16
14.6.5
Table 453:
Name Operation PreFaultRecT PostFaultRecT TimeLimit PostRetrig ZeroAngleRef OpModeTest
Setting parameters
DRPRDRE Non group settings (basic)
Values (Range) Disabled Enabled 0.05 - 9.90 0.1 - 10.0 0.5 - 10.0 Disabled Enabled 1 - 30 Disabled Enabled Unit s s s Ch Step 0.01 0.1 0.1 1 Default Disabled 0.10 0.5 1.0 Disabled 1 Disabled Description Operation Enable/Disable Pre-fault recording time Post-fault recording time Fault recording time limit Post-fault retrig enabled (On) or not (Off) Reference channel (voltage), phasors, frequency measurement Operation mode during test mode
Table 454:
Name Operation01 NomValue01 UnderTrigOp01 UnderTrigLe01 OverTrigOp01 OverTrigLe01 Operation02 NomValue02 UnderTrigOp02 UnderTrigLe02
Section 14 Monitoring
Name OverTrigOp02 OverTrigLe02 Operation03 NomValue03 UnderTrigOp03 UnderTrigLe03 OverTrigOp03 OverTrigLe03 Operation04 NomValue04 UnderTrigOp04 UnderTrigLe04 OverTrigOp04 OverTrigLe04 Operation05 NomValue05 UnderTrigOp05 UnderTrigLe05 OverTrigOp05 OverTrigLe05 Operation06 NomValue06 UnderTrigOp06 UnderTrigLe06 OverTrigOp06 OverTrigLe06 Values (Range) Disabled Enabled 0 - 5000 Disabled Enabled 0.0 - 999999.9 Disabled Enabled 0 - 200 Disabled Enabled 0 - 5000 Disabled Enabled 0.0 - 999999.9 Disabled Enabled 0 - 200 Disabled Enabled 0 - 5000 Disabled Enabled 0.0 - 999999.9 Disabled Enabled 0 - 200 Disabled Enabled 0 - 5000 Disabled Enabled 0.0 - 999999.9 Disabled Enabled 0 - 200 Disabled Enabled 0 - 5000 Unit % % % % % % % % % Step 1 0.1 1 1 0.1 1 1 0.1 1 1 0.1 1 1 Default Disabled 200 Disabled 0.0 Disabled 50 Disabled 200 Disabled 0.0 Disabled 50 Disabled 200 Disabled 0.0 Disabled 50 Disabled 200 Disabled 0.0 Disabled 50 Disabled 200 Description
Use over level trig for analog cha 2 (on) or not (off) Over trigger level for analog cha 2 in % of signal Operation On/Off Nominal value for analog channel 3 Use under level trig for analog cha 3 (on) or not (off) Under trigger level for analog cha 3 in % of signal Use over level trig for analog cha 3 (on) or not (off) Overtrigger level for analog cha 3 in % of signal Operation On/Off Nominal value for analog channel 4 Use under level trig for analog cha 4 (on) or not (off) Under trigger level for analog cha 4 in % of signal Use over level trig for analog cha 4 (on) or not (off) Over trigger level for analog cha 4 in % of signal Operation On/Off Nominal value for analog channel 5 Use under level trig for analog cha 5 (on) or not (off) Under trigger level for analog cha 5 in % of signal Use over level trig for analog cha 5 (on) or not (off) Over trigger level for analog cha 5 in % of signal Operation On/Off Nominal value for analog channel 6 Use under level trig for analog cha 6 (on) or not (off) Under trigger level for analog cha 6 in % of signal Use over level trig for analog cha 6 (on) or not (off) Over trigger level for analog cha 6 in % of signal
Section 14 Monitoring
Values (Range) Disabled Enabled 0.0 - 999999.9 Disabled Enabled 0 - 200 Disabled Enabled 0 - 5000 Disabled Enabled 0.0 - 999999.9 Disabled Enabled 0 - 200 Disabled Enabled 0 - 5000 Disabled Enabled 0.0 - 999999.9 Disabled Enabled 0 - 200 Disabled Enabled 0 - 5000 Disabled Enabled 0.0 - 999999.9 Disabled Enabled 0 - 200 Disabled Enabled 0 - 5000 Unit % % % % % % % % Step 0.1 1 1 0.1 1 1 0.1 1 1 0.1 1 1 Default Disabled 0.0 Disabled 50 Disabled 200 Disabled 0.0 Disabled 50 Disabled 200 Disabled 0.0 Disabled 50 Disabled 200 Disabled 0.0 Disabled 50 Disabled 200 Description Operation On/Off Nominal value for analog channel 7 Use under level trig for analog cha 7 (on) or not (off) Under trigger level for analog cha 7 in % of signal Use over level trig for analog cha 7 (on) or not (off) Over trigger level for analog cha 7 in % of signal Operation On/Off Nominal value for analog channel 8 Use under level trig for analog cha 8 (on) or not (off) Under trigger level for analog cha 8 in % of signal Use over level trig for analog cha 8 (on) or not (off) Over trigger level for analog cha 8 in % of signal Operation On/Off Nominal value for analog channel 9 Use under level trig for analog cha 9 (on) or not (off) Under trigger level for analog cha 9 in % of signal Use over level trig for analog cha 9 (on) or not (off) Over trigger level for analog cha 9 in % of signal Operation On/Off Nominal value for analog channel 10 Use under level trig for analog cha 10 (on) or not (off) Under trigger level for analog cha 10 in % of signal Use over level trig for analog cha 10 (on) or not (off) Over trigger level for analog cha 10 in % of signal
Name Operation07 NomValue07 UnderTrigOp07 UnderTrigLe07 OverTrigOp07 OverTrigLe07 Operation08 NomValue08 UnderTrigOp08 UnderTrigLe08 OverTrigOp08 OverTrigLe08 Operation09 NomValue09 UnderTrigOp09 UnderTrigLe09 OverTrigOp09 OverTrigLe09 Operation10 NomValue10 UnderTrigOp10 UnderTrigLe10 OverTrigOp10 OverTrigLe10
Section 14 Monitoring
Table 455:
Name Operation31 NomValue31 UnderTrigOp31 UnderTrigLe31 OverTrigOp31 OverTrigLe31 Operation32 NomValue32 UnderTrigOp32 UnderTrigLe32 OverTrigOp32 OverTrigLe32 Operation33 NomValue33 UnderTrigOp33 UnderTrigLe33 OverTrigOp33 OverTrigLe33 Operation34 NomValue34 UnderTrigOp34 UnderTrigLe34 OverTrigOp34
Section 14 Monitoring
Values (Range) 0 - 5000 Disabled Enabled 0.0 - 999999.9 Disabled Enabled 0 - 200 Disabled Enabled 0 - 5000 Disabled Enabled 0.0 - 999999.9 Disabled Enabled 0 - 200 Disabled Enabled 0 - 5000 Disabled Enabled 0.0 - 999999.9 Disabled Enabled 0 - 200 Disabled Enabled 0 - 5000 Disabled Enabled 0.0 - 999999.9 Disabled Enabled 0 - 200 Disabled Enabled Unit % % % % % % % % Step 1 0.1 1 1 0.1 1 1 0.1 1 1 0.1 1 Default 200 Disabled 0.0 Disabled 50 Disabled 200 Disabled 0.0 Disabled 50 Disabled 200 Disabled 0.0 Disabled 50 Disabled 200 Disabled 0.0 Disabled 50 Disabled Description Over trigger level for analog cha 34 in % of signal Operation On/off Nominal value for analog channel 35 Use under level trig for analog cha 35 (on) or not (off) Under trigger level for analog cha 35 in % of signal Use over level trig for analog cha 35 (on) or not (off) Over trigger level for analog cha 35 in % of signal Operation On/off Nominal value for analog channel 36 Use under level trig for analog cha 36 (on) or not (off) Under trigger level for analog cha 36 in % of signal Use over level trig for analog cha 36 (on) or not (off) Over trigger level for analog cha 36 in % of signal Operation On/off Nominal value for analog channel 37 Use under level trig for analog cha 37 (on) or not (off) Under trigger level for analog cha 37 in % of signal Use over level trig for analog cha 37 (on) or not (off) Over trigger level for analog cha 37 in % of signal Operation On/off Nominal value for analog channel 38 Use under level trig for analog cha 38 (on) or not (off) Under trigger level for analog cha 38 in % of signal Use over level trig for analog cha 38 (on) or not (off)
Name OverTrigLe34 Operation35 NomValue35 UnderTrigOp35 UnderTrigLe35 OverTrigOp35 OverTrigLe35 Operation36 NomValue36 UnderTrigOp36 UnderTrigLe36 OverTrigOp36 OverTrigLe36 Operation37 NomValue37 UnderTrigOp37 UnderTrigLe37 OverTrigOp37 OverTrigLe37 Operation38 NomValue38 UnderTrigOp38 UnderTrigLe38 OverTrigOp38
Section 14 Monitoring
Name OverTrigLe38 Operation39 NomValue39 UnderTrigOp39 UnderTrigLe39 OverTrigOp39 OverTrigLe39 Operation40 NomValue40 UnderTrigOp40 UnderTrigLe40 OverTrigOp40 OverTrigLe40 Values (Range) 0 - 5000 Disabled Enabled 0.0 - 999999.9 Disabled Enabled 0 - 200 Disabled Enabled 0 - 5000 Disabled Enabled 0.0 - 999999.9 Disabled Enabled 0 - 200 Disabled Enabled 0 - 5000 Unit % % % % % Step 1 0.1 1 1 0.1 1 1 Default 200 Disabled 0.0 Disabled 50 Disabled 200 Disabled 0.0 Disabled 50 Disabled 200 Description
Over trigger level for analog cha 38 in % of signal Operation On/off Nominal value for analog channel 39 Use under level trig for analog cha 39 (on) or not (off) Under trigger level for analog cha 39 in % of signal Use over level trig for analog cha 39 (on) or not (off) Over trigger level for analog cha 39 in % of signal Operation On/off Nominal value for analog channel 40 Use under level trig for analog cha 40 (on) or not (off) Under trigger level for analog cha 40 in % of signal Use over level trig for analog cha 40 (on) or not (off) Over trigger level for analog cha 40 in % of signal
Table 456:
Name Operation01 TrigLevel01 IndicationMa01 SetLED01 Operation02 TrigLevel02 IndicationMa02 SetLED02
Section 14 Monitoring
Values (Range) Disabled Enabled Trig on 0 Trig on 1 Hide Show Disabled Enabled Disabled Enabled Trig on 0 Trig on 1 Hide Show Disabled Enabled Disabled Enabled Trig on 0 Trig on 1 Hide Show Disabled Enabled Disabled Enabled Trig on 0 Trig on 1 Hide Show Disabled Enabled Disabled Enabled Trig on 0 Trig on 1 Hide Show Disabled Enabled Disabled Enabled Trig on 0 Trig on 1 Unit Step Default Disabled Trig on 1 Hide Disabled Disabled Trig on 1 Hide Disabled Disabled Trig on 1 Hide Disabled Disabled Trig on 1 Hide Disabled Disabled Trig on 1 Hide Disabled Disabled Trig on 1 Description Trigger operation On/Off Trig on positiv (1) or negative (0) slope for binary inp 3 Indication mask for binary channel 3 Set red-LED on HMI for binary channel 3 Trigger operation On/Off Trig on positiv (1) or negative (0) slope for binary inp 4 Indication mask for binary channel 4 Set red-LED on HMI for binary channel 4 Trigger operation On/Off Trig on positiv (1) or negative (0) slope for binary inp 5 Indication mask for binary channel 5 Set red-LED on HMI for binary channel 5 Trigger operation On/Off Trig on positiv (1) or negative (0) slope for binary inp 6 Indication mask for binary channel 6 Set red-LED on HMI for binary channel 6 Trigger operation On/Off Trig on positiv (1) or negative (0) slope for binary inp 7 Indication mask for binary channel 7 Set red-LED on HMI for binary channel 7 Trigger operation On/Off Trig on positiv (1) or negative (0) slope for binary inp 8
Name Operation03 TrigLevel03 IndicationMa03 SetLED03 Operation04 TrigLevel04 IndicationMa04 SetLED04 Operation05 TrigLevel05 IndicationMa05 SetLED05 Operation06 TrigLevel06 IndicationMa06 SetLED06 Operation07 TrigLevel07 IndicationMa07 SetLED07 Operation08 TrigLevel08
Section 14 Monitoring
Name IndicationMa08 SetLED08 Operation09 TrigLevel09 IndicationMa09 SetLED09 Operation10 TrigLevel10 IndicationMa10 SetLED10 Operation11 TrigLevel11 IndicationMa11 SetLED11 Operation12 TrigLevel12 IndicationMa12 SetLED12 Operation13 TrigLevel13 IndicationMa13 SetLED13 Values (Range) Hide Show Disabled Enabled Disabled Enabled Trig on 0 Trig on 1 Hide Show Disabled Enabled Disabled Enabled Trig on 0 Trig on 1 Hide Show Disabled Enabled Disabled Enabled Trig on 0 Trig on 1 Hide Show Disabled Enabled Disabled Enabled Trig on 0 Trig on 1 Hide Show Disabled Enabled Disabled Enabled Trig on 0 Trig on 1 Hide Show Disabled Enabled Unit Step Default Hide Disabled Disabled Trig on 1 Hide Disabled Disabled Trig on 1 Hide Disabled Disabled Trig on 1 Hide Disabled Disabled Trig on 1 Hide Disabled Disabled Trig on 1 Hide Disabled Description
Indication mask for binary channel 8 Set red-LED on HMI for binary channel 8 Trigger operation On/Off Trig on positiv (1) or negative (0) slope for binary inp 9 Indication mask for binary channel 9 Set red-LED on HMI for binary channel 9 Trigger operation On/Off Trig on positiv (1) or negative (0) slope for binary inp 10 Indication mask for binary channel 10 Set red-LED on HMI for binary channel 10 Trigger operation On/Off Trig on positiv (1) or negative (0) slope for binary inp 11 Indication mask for binary channel 11 Set red-LED on HMI for binary channel 11 Trigger operation On/Off Trig on positiv (1) or negative (0) slope for binary inp 12 Indication mask for binary channel 12 Set red-LED on HMI for binary input 12 Trigger operation On/Off Trig on positiv (1) or negative (0) slope for binary inp 13 Indication mask for binary channel 13 Set red-LED on HMI for binary channel 13
Section 14 Monitoring
Values (Range) Disabled Enabled Trig on 0 Trig on 1 Hide Show Disabled Enabled Disabled Enabled Trig on 0 Trig on 1 Hide Show Disabled Enabled Disabled Enabled Trig on 0 Trig on 1 Hide Show Disabled Enabled 0 - 255 0 - 255 0 - 255 0 - 255 0 - 255 0 - 255 0 - 255 0 - 255 0 - 255 0 - 255 Unit FunT FunT FunT FunT FunT FunT FunT FunT FunT FunT Step 1 1 1 1 1 1 1 1 1 1 Default Disabled Trig on 1 Hide Disabled Disabled Trig on 1 Hide Disabled Disabled Trig on 1 Hide Disabled 0 0 0 0 0 0 0 0 0 0 Description Trigger operation On/Off Trig on positiv (1) or negative (0) slope for binary inp 14 Indication mask for binary channel 14 Set red-LED on HMI for binary channel 14 Trigger operation On/Off Trig on positiv (1) or negative (0) slope for binary inp 15 Indication mask for binary channel 15 Set red-LED on HMI for binary channel 15 Trigger operation On/Off Trig on positiv (1) or negative (0) slope for binary inp 16 Indication mask for binary channel 16 Set red-LED on HMI for binary channel 16 Function type for binary channel 1 (IEC -60870-5-103) Function type for binary channel 2 (IEC -60870-5-103) Function type for binary channel 3 (IEC -60870-5-103) Function type for binary channel 4 (IEC -60870-5-103) Function type for binary channel 5 (IEC -60870-5-103) Function type for binary channel 6 (IEC -60870-5-103) Function type for binary channel 7 (IEC -60870-5-103) Function type for binary channel 8 (IEC -60870-5-103) Function type for binary channel 9 (IEC -60870-5-103) Function type for binary channel 10 (IEC -60870-5-103)
Name Operation14 TrigLevel14 IndicationMa14 SetLED14 Operation15 TrigLevel15 IndicationMa15 SetLED15 Operation16 TrigLevel16 IndicationMa16 SetLED16 FUNT1 FUNT2 FUNT3 FUNT4 FUNT5 FUNT6 FUNT7 FUNT8 FUNT9 FUNT10
Section 14 Monitoring
Name FUNT11 FUNT12 FUNT13 FUNT14 FUNT15 FUNT16 INFNO1 INFNO2 INFNO3 INFNO4 INFNO5 INFNO6 INFNO7 INFNO8 INFNO9 INFNO10 INFNO11 INFNO12 INFNO13 INFNO14 INFNO15 INFNO16 Values (Range) 0 - 255 0 - 255 0 - 255 0 - 255 0 - 255 0 - 255 0 - 255 0 - 255 0 - 255 0 - 255 0 - 255 0 - 255 0 - 255 0 - 255 0 - 255 0 - 255 0 - 255 0 - 255 0 - 255 0 - 255 0 - 255 0 - 255 Unit FunT FunT FunT FunT FunT FunT InfNo InfNo InfNo InfNo InfNo InfNo InfNo InfNo InfNo InfNo InfNo InfNo InfNo InfNo InfNo InfNo Step 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description
Function type for binary channel 11 (IEC -60870-5-103) Function type for binary channel 12 (IEC -60870-5-103) Function type for binary channel 13 (IEC -60870-5-103) Function type for binary channel 14 (IEC -60870-5-103) Function type for binary channel 15 (IEC -60870-5-103) Function type for binary channel 16 (IEC -60870-5-103) Information number for binary channel 1 (IEC -60870-5-103) Information number for binary channel 2 (IEC -60870-5-103) Information number for binary channel 3 (IEC -60870-5-103) Information number for binary channel 4 (IEC -60870-5-103) Information number for binary channel 5 (IEC -60870-5-103) Information number for binary channel 6 (IEC -60870-5-103) Information number for binary channel 7 (IEC -60870-5-103) Information number for binary channel 8 (IEC -60870-5-103) Information number for binary channel 9 (IEC -60870-5-103) Information number for binary channel 10 (IEC -60870-5-103) Information number for binary channel 11 (IEC -60870-5-103) Information number for binary channel 12 (IEC -60870-5-103) Information number for binary channel 13 (IEC -60870-5-103) Information number for binary channel 14 (IEC -60870-5-103) Information number for binary channel 15 (IEC -60870-5-103) Information number for binary channel 16 (IEC -60870-5-103)
14.6.6
14.7
14.7.1
Sequential of events
Introduction
Continuous event-logging is useful for monitoring the system from an overview perspective and is a complement to specific disturbance recorder functions. The sequential of events logs all binary input signals connected to the Disturbance report function. The list may contain up to 1000 time-tagged events stored in a ring-buffer.
14.7.2
Principle of operation
When a binary signal, connected to the disturbance report function, changes status, the sequential of events function stores input name, status and time in the sequential of
783
Section 14 Monitoring
events in chronological order. The list can contain up to 1000 events from both internal logic signals and binary input channels. If the list is full, the oldest event is overwritten when a new event arrives. The list can be configured to show oldest or newest events first with a setting on the local HMI. The sequential of events function runs continuously, in contrast to the event recorder function, which is only active during a disturbance, and each event record is an integral part of its associated DR. The name of the binary signal that appears in the event recording is the user-defined name assigned when the IED is configured. The same name is used in the disturbance recorder function (DR), indications (IND) and the event recorder function (ER). The sequential of events is stored and managed separate from the disturbance report information(ER, DR, IND, TVR and FL).
14.7.3
Function block
The Sequential of events has no function block of its own.It is included in the DRPRDRE block and uses information from the BxRBDR block.
14.7.4
Input signals
The Sequential of events logs the same binary input signals as configured for the Disturbance report function.
14.7.5
Technical data
Table 458:
Function Buffer capacity Resolution Accuracy Maximum number of events in the list
technical data
Value 1000 1 ms Depending on time synchronizing
Section 14 Monitoring
14.8
14.8.1
Indications
Introduction
To get fast, condensed and reliable information about disturbances in the primary and/ or in the secondary system it is important to know, for example binary signals that have changed status during a disturbance. This information is used in the short perspective to get information via the local HMI in a straightforward way. There are three LEDs on the local HMI (green, yellow and red), which will display status information about the IED and the Disturbance report function (triggered). The Indication list function shows all selected binary input signals connected to the Disturbance report function that have changed status during a disturbance.
14.8.2
Principle of operation
The LED indications display this information: Green LED:
Steady light Flashing light Dark In Service Internal fail No power supply
Yellow LED:
Steady light Flashing light A disturbance report is triggered The IED is in test mode or in configuration mode
Red LED:
Steady light Trigged on binary signal N with SetLEDN=On
Indication list: The possible indication signals are the same as the ones chosen for the disturbance report function and disturbance recorder.
Section 14 Monitoring
The indication function tracks 0 to 1 changes of binary signals during the recording period of the collection window. This means that constant logic zero, constant logic one or state changes from logic one to logic zero will not be visible in the list of indications. Signals are not time tagged. In order to be recorded in the list of indications the: the signal must be connected to binary input(DRB1-6) the DRP parameter Operation must be set Enabled the DRP must be trigged (binary or analog)
Indications are selected with the indication mask (IndicationMask) when setting the binary inputs. The name of the binary signal that appears in the Indication function is the user-defined name assigned at configuration of the IED. The same name is used in disturbance recorder function (DR), indications (IND) and event recorder function (ER).
14.8.3
Function block
The Indications function has no function block of its own. It is included in the DRPRDRE block and uses information from the BxRBDR block.
14.8.4
Input signals
The Indications function logs the same binary input signals as the Disturbance report function.
14.8.5
Technical data
Table 459:
Function Buffer capacity Maximum number of indications presented for single disturbance Maximum number of recorded disturbances
technical data
Value 96 100
14.9
14.9.1
Event recorder
Introduction
Quick, complete and reliable information about disturbances in the primary and/or in the secondary system is vital, for example, time-tagged events logged during
Section 14 Monitoring
disturbances. This information is used for different purposes in the short term (for example corrective actions) and in the long term (for example functional analysis). The event recorder logs all selected binary input signals connected to the Disturbance report function. Each recording can contain up to 150 time-tagged events. The event recorder information is available for the disturbances locally in the IED. The event recording information is an integrated part of the disturbance record (Comtrade file).
14.9.2
Principle of operation
When one of the trig conditions for the disturbance report is activated, the event recorder logs every status change in the 96 selected binary signals. The events can be generated by both internal logical signals and binary input channels. The internal signals are time-tagged in the main processor module, while the binary input channels are time-tagged directly in each I/O module. The events are collected during the total recording time (pre-, post-fault and limit time), and are stored in the disturbance report flash memory at the end of each recording. In case of overlapping recordings, due to PostRetrig = Enabled and a new trig signal appears during post-fault time, events will be saved in both recording files. The name of the binary input signal that appears in the event recording is the userdefined name assigned when configuring the IED. The same name is used in the disturbance recorder function (DR), indications (IND) and event recorder function(ER). The event record is stored as a part of the disturbance report information (ER, DR, IND, TVR and FL) and managed via the local HMI or PCM600. Events can not be read from the IED if more than one user is accessing the IED simultaneously.
14.9.3
Function block
The Event recorder has no function block of its own. It is included in the DRPRDRE block and uses information from the BxRBDR block.
14.9.4
Input signals
The Event recorder function logs the same binary input signals as the Disturbance report function.
787
technical data
Value 150 100 1 ms Depending on time synchronizing
14.10
14.10.1
14.10.2
Principle of operation
Trip value recorder (TVR)calculates and presents both fault and pre-fault magnitudes as well as the phase angles of all the selected analog input signals. The parameter ZeroAngleRef points out which input signal is used as the angle reference. When the disturbance report function is triggered the sample for the fault interception is searched for, by checking the non-periodic changes in the analog input signals. The channel search order is consecutive, starting with the analog input with the lowest number. When a fault interception point is found, the Fourier estimation of the pre-fault values of the complex values of the analog signals starts 1.5 cycle before the fault sample. The estimation uses samples during one period. The post-fault values are calculated using the Recursive Least Squares (RLS) method. The calculation starts a few samples after the fault sample and uses samples during 1/2 - 2 cycles depending on the shape of the signals.
Section 14 Monitoring
If no starting point is found in the recording, the disturbance report trig sample is used as the start sample for the Fourier estimation. The estimation uses samples during one cycle before the trig sample. In this case the calculated values are used both as pre-fault and fault values. The name of the analog signal that appears in the Trip value recorder function is the userdefined name assigned when the IED is configured. The same name is used in the Disturbance recorder function (DR). The trip value record is stored as a part of the disturbance report information (ER, DR, IND, TVR and fault locator) and managed in PCM600 or via the local HMI.
14.10.3
Function block
The Trip value recorder has no function block of its own. It is included in the DRPRDRE block and uses information from the BxRBDR block.
14.10.4
Input signals
The trip value recorder function uses analog input signals connected to A1RADR to A3RADR (not A4RADR).
14.10.5
Technical data
Table 461:
Function Buffer capacity Maximum number of analog inputs Maximum number of disturbance reports
technical data
Value 30 100
14.11
14.11.1
Disturbance recorder
Introduction
The Disturbance recorder function supplies fast, complete and reliable information about disturbances in the power system. It facilitates understanding system behavior and related primary and secondary equipment during and after a disturbance. Recorded information is used for different purposes in the short perspective (for example corrective actions) and long perspective (for example functional analysis). The Disturbance recorder acquires sampled data from selected analog- and binary signals connected to the Disturbance report function (maximum 40 analog and 96
789
Section 14 Monitoring
binary signals). The binary signals available are the same as for the event recorder function. The function is characterized by great flexibility and is not dependent on the operation of protection functions. It can record disturbances not detected by protection functions. Up to ten seconds of data before the trigger instant can be saved in the disturbance file. The disturbance recorder information for up to 100 disturbances are saved in the IED and the local HMI is used to view the list of recordings.
14.11.2
Principle of operation
Disturbance recording (DR) is based on the acquisition of binary and analog signals. The binary signals can be either true binary input signals or internal logical signals generated by the functions in the IED. The analog signals to be recorded are input channels from the Transformer Input Module (TRM), Line Differential communication Module (LDCM) through the Signal Matrix Analog Input (SMAI) and possible summation (Sum3Ph) function blocks and some internally derived analog signals.For details, refer to section "Disturbance report DRPRDRE". Disturbance recorder collects analog values and binary signals continuously, in a cyclic buffer. The pre-fault buffer operates according to the FIFO principle; old data will continuously be overwritten as new data arrives when the buffer is full. The size of this buffer is determined by the set pre-fault recording time. Upon detection of a fault condition (triggering), the disturbance is time tagged and the data storage continues in a post-fault buffer. The storage process continues as long as the fault condition prevails - plus a certain additional time. This is called the post-fault time and it can be set in the disturbance report. The above mentioned two parts form a disturbance recording. The whole memory, intended for disturbance recordings, acts as a cyclic buffer and when it is full, the oldest recording is overwritten. Up to the last 100 recordings are stored in the IED. The time tagging refers to the activation of the trigger that starts the disturbance recording. A recording can be trigged by, manual start, binary input and/or from analog inputs (over-/underlevel trig). A user-defined name for each of the signals can be set. These names are common for all functions within the disturbance report functionality.
Section 14 Monitoring
Memory and storage
The maximum number of recordings depend on each recordings total recording time. Long recording time will reduce the number of recordings to less than 100.
14.11.2.1
The IED flash disk should NOT be used to store any user files. This might cause disturbance recordings to be deleted due to lack of disk space. When a recording is completed, a post recording processing occurs. This post-recording processing comprises: Saving the data for analog channels with corresponding data for binary signals Add relevant data to be used by the Disturbance handling tool (part of PCM 600) Compression of the data, which is performed without losing any data accuracy Storing the compressed data in a non-volatile memory (flash memory)
The recorded disturbance is now ready for retrieval and evaluation. The recording files comply with the Comtrade standard IEC 60255-24 and are divided into three files; a header file (HDR), a configuration file (CFG) and a data file (DAT). The header file (optional in the standard) contains basic information about the disturbance, that is, information from the Disturbance report sub-functions(ER, TVR). The Disturbance handling tool use this information and present the recording in a userfriendly way. General: Station name, object name and unit name Date and time for the trig of the disturbance Record number Sampling rate Time synchronization source Recording times Activated trig signal Active setting group
Analog: Signal names for selected analog channels Information e.g. trig on analog inputs Primary and secondary instrument transformer rating
791 Technical reference manual
Section 14 Monitoring
Over- or Undertrig: level and operation Over- or Undertrig status at time of trig CT direction
The configuration file is a mandatory file containing information needed to interpret the data file. For example sampling rate, number of channels, system frequency, channel info etc. The data file, which also is mandatory, containing values for each input channel for each sample in the record (scaled value). The data file also contains a sequence number and time stamp for each set of samples.
14.11.2.2
IEC 60870-5-103
The communication protocol IEC 60870-5-103 may be used to poll disturbance recordings from the IED to a master (station HSI). The standard describes how to handle 8 disturbance recordings, 8 analog channels (4 currents and 4 voltages) using the public range and binary signals. The last 8 recordings, out of maximum 100, are available for transfer to the master. When the last one is transferred and acknowledged new recordings in the IED will appear, in the master points of view (even if they already where stored in the IED). To be able to report 40 analog channels from the IED using IEC 60870-5-103 the first 8 channels are placed in the public range and the next 32 are placed in the private range. To comply the standard the first 8 must be configured according to table 462.
Table 462:
Signal IA IB IC IN VA VB VC VN
Section 14 Monitoring
The binary signals connected to BxRBDR are reported by polling. The function blocks include function type and information number.
14.11.3
Function block
The Disturbance recorder has no function block of its own. It is included in the DRPRDRE, AxRADR and BxRBDR block.
14.11.4
14.11.5
Setting parameters
For Setting parameters see section "Disturbance report DRPRDRE".
14.11.6
Technical data
Table 463:
Function Buffer capacity Maximum number of analog inputs Maximum number of binary inputs Maximum number of disturbance reports Maximum total recording time (3.4 s recording time and maximum number of channels, typical value)
technical data
Value 40 96 100 340 seconds (100 recordings) at 50 Hz 280 seconds (80 recordings) at 60 Hz
794
Section 15 Metering
Section 15
Metering
15.1
S00947 V1 EN
15.1.1
Introduction
Pulse counter (PCGGIO) function counts externally generated binary pulses, for instance pulses coming from an external energy meter, for calculation of energy consumption values. The pulses are captured by the binary input module and then read by the function. A scaled service value is available over the station bus. The special Binary input module with enhanced pulse counting capabilities must be ordered to achieve this functionality.
15.1.2
Principle of operation
The registration of pulses is done for positive transitions (0->1) on one of the 16 binary input channels located on the Binary Input Module (BIM). Pulse counter values are sent to the station HMI with predefined cyclicity without reset. The reporting time period can be set in the range from 1 second to 60 minutes and is synchronized with absolute system time. Interrogation of additional pulse counter values can be done with a command (intermediate reading) for a single counter. All
795
Section 15 Metering
active counters can also be read by the LON General Interrogation command (GI) or IEC 61850. Pulse counter (PCGGIO) function in the IED supports unidirectional incremental counters. That means only positive values are possible. The counter uses a 32 bit format, that is, the reported value is a 32-bit, signed integer with a range 0...+2147483647. The counter is reset at initialization of the IED. The reported value to station HMI over the station bus contains Identity, Scaled Value (pulse count x scale), Time, and Pulse Counter Quality. The Pulse Counter Quality consists of: Invalid (board hardware error or configuration error) Wrapped around Blocked Adjusted
The transmission of the counter value by SPA can be done as a service value, that is, the value frozen in the last integration cycle is read by the station HMI from the database. PCGGIO updates the value in the database when an integration cycle is finished and activates the NEW_VAL signal in the function block. This signal can be connected to an Event function block, be time tagged, and transmitted to the station HMI. This time corresponds to the time when the value was frozen by the function. The pulse counter function requires a binary input card, BIMp, that is specially adapted to the pulse counter function. Figure 361 shows the pulse counter function block with connections of the inputs and outputs.
Section 15 Metering
SingleCmdFunc OUTx SingleCmdFunc OUTx I/Omodule Pulse INPUT OUT Pulse length >1s Reset counter
PulseCounter BLOCK INVALID RESTART READ_VAL BLOCKED NEW_VAL BI_PULSE RS_CNT NAME SCAL_VAL
IEC EVENT
SMS settings 1.Operation = Off/On 2.tReporting = 0s...60min 3.Event Mask = No Events/Report Events 4.Scale = 1-90000
ANSI05000744 V1 EN
Figure 361:
The BLOCK and READ_VAL inputs can be connected to Single Command blocks, which are intended to be controlled either from the station HMI or/and the local HMI. As long as the BLOCK signal is set, the pulse counter is blocked. The signal connected to READ_VAL performs one additional reading per positive flank. The signal must be a pulse with a length >1 second. The BI_PULSE input is connected to the used input of the function block for the Binary Input Module (BIM). The RS_CNT input is used for resetting the counter. Each pulse counter function block has four binary output signals that can be connected to an Event function block for event recording: INVALID, RESTART, BLOCKED and NEW_VAL. The SCAL_VAL signal can be connected to the IEC Event function block. The INVALID signal is a steady signal and is set if the Binary Input Module, where the pulse counter input is located, fails or has wrong configuration. The RESTART signal is a steady signal and is set when the reported value does not comprise a complete integration cycle. That is, in the first message after IED start-up, in the first message after deblocking, and after the counter has wrapped around during last integration cycle. The BLOCKED signal is a steady signal and is set when the counter is blocked. There are two reasons why the counter is blocked:
Section 15 Metering
The BLOCK input is set, or The Binary Input Module, where the counter input is situated, is inoperative.
The NEW_VAL signal is a pulse signal. The signal is set if the counter value was updated since last report. Note, the pulse is short, one cycle.
The SCAL_VAL signal consists of scaled value (according to parameter Scale), time and status information.
15.1.3
Function block
PCGGIO BLOCK READ_VAL BI_PULSE* RS_CNT INVALID RESTART BLOCKED NEW_VAL SCAL_VAL IEC05000709-2-en.vsd
IEC05000709 V3 EN
Figure 362:
15.1.4
Table 465:
Name INVALID RESTART BLOCKED NEW_VAL SCAL_VAL
15.1.5
Table 466:
Name Operation EventMask CountCriteria
Scale Quantity
0.001 -
1.000 Count
Scaling value for SCAL_VAL output to unit per counted value Measured quantity for SCAL_VAL output
tReporting
60
15.1.6
Technical data
Table 467:
Function Input frequency Cycle time for report of counter value
15.2
Outputs from the Measurements (CVMMXN) function can be used to calculate energy consumption. Active as well as reactive values are calculated in import and export direction. Values can be read or generated as pulses. Maximum demand power values are also calculated by the function.
15.2.2
Principle of operation
The instantaneous output values of active and reactive power from the Measurements (CVMMXN) function block are used and integrated over a selected time tEnergy to measure the integrated energy. The energy values (in MWh and MVarh) are available as output signals and also as pulsed output which can be connected to a pulse counter. Outputs are available for forward as well as reverse direction. The accumulated energy values can be reset from the local HMI reset menu or with input signal RSTACC. The maximum demand values for active and reactive power are calculated for the set time tEnergy and the maximum value is stored in a register available over communication and from outputs MAXPAFD, MAXPARD, MAXPRFD, MAXPRRD for the active and reactive power forward and reverse direction until reset with input signal RSTDMD or from the local HMI reset menu.
CVMMXN
P_INST Q_INST P Q
ETPMMTR
IEC09000106.vsd
IEC09000106 V1 EN
Figure 363:
Connection of Energy calculation and demand handling function (ETPMMTR) to the Measurements function (CVMMXN)
15.2.3
Figure 364:
15.2.4
Table 469:
Name ACCST EAFPULSE EARPULSE ERFPULSE ERRPULSE EAFALM EARALM
Section 15 Metering
Name ERFALM ERRALM EAFACC EARACC ERFACC ERRACC MAXPAFD MAXPARD MAXPRFD MAXPRRD Type BOOLEAN BOOLEAN REAL REAL REAL REAL REAL REAL REAL REAL Description
Alarm for reactive forward energy exceed limit in set interval Alarm for reactive reverse energy exceed limit in set interval Accumulated forward active energy value in Ws Accumulated reverse active energy value in Ws Accumulated forward reactive energy value in VArS Accumulated reverse reactive energy value in VArS Maximum forward active power demand value for set interval Maximum reverse active power demand value for set interval Maximum forward reactive power demand value for set interval Maximum reactive power demand value in reverse direction
15.2.5
Table 470:
Name Operation StartAcc tEnergy
Setting parameters
ETPMMTR Non group settings (basic)
Values (Range) Disabled Enabled Disabled Enabled 1 Minute 5 Minutes 10 Minutes 15 Minutes 30 Minutes 60 Minutes 180 Minutes 0.000 - 60.000 0.000 - 60.000 0.001 - 10000.000 0.001 - 10000.000 0.001 - 10000.000 0.001 - 10000.000 Unit Step Default Disabled Disabled 1 Minute Description Operation Enable/Disable Activate the accumulation of energy values Time interval for energy calculation
Energy accumulated pulse ON time in secs Energy accumulated pulse OFF time in secs Pulse quantity for active forward accumulated energy value Pulse quantity for active reverse accumulated energy value Pulse quantity for reactive forward accumulated energy value Pulse quantity for reactive reverse accumulated energy value
Section 15 Metering
Table 471:
Name EALim ERLim DirEnergyAct DirEnergyReac EnZeroClamp LevZeroClampP LevZeroClampQ EAFPrestVal EARPrestVal ERFPresetVal ERVPresetVal
804
Section 16
Station communication
16.1
Overview
Each IED is provided with a communication interface, enabling it to connect to one or many substation level systems or equipment, either on the Substation Automation (SA) bus or Substation Monitoring (SM) bus. Following communication protocols are available: IEC 61850-8-1 communication protocol LON communication protocol SPA or IEC 60870-5-103 communication protocol DNP3.0 communication protocol
16.2
16.2.1
Table 472:
Name Operation GOOSE
16.2.3
16.2.3.1
16.2.3.2
Principle of operation
Upon receiving a signal at its input, IEC61850 generic communication I/O functions (SPGGIO) function sends the signal over IEC 61850-8-1 to the equipment or system that requests this signal. To get the signal, PCM600 must be used to define which function block in which equipment or system should receive this information.
16.2.3.3
Function block
SPGGIO BLOCK ^IN IEC07000124-2-en.vsd
IEC07000124 V2 EN
Figure 365:
SP16GGIO BLOCK ^IN1 ^IN2 ^IN3 ^IN4 ^IN5 ^IN6 ^IN7 ^IN8 ^IN9 ^IN10 ^IN11 ^IN12 ^IN13 ^IN14 ^IN15 ^IN16 IEC07000125-2-en.vsd
IEC07000125 V2 EN
Figure 366:
16.2.3.4
Table 475:
Name BLOCK IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 IN11 IN12 IN13
16.2.3.5
Setting parameters
The function does not have any parameters available in the local HMI or PCM600.
16.2.4
16.2.4.1
Principle of operation
Upon receiving an analog signal at its input, IEC61850 generic communication I/O functions (MVGGIO) will give the instantaneous value of the signal and the range, as output values. In the same time, it will send over IEC 61850-8-1 the value, to other IEC 61850 clients in the substation.
16.2.4.2
Function block
MVGGIO BLOCK ^IN ^VALUE RANGE IEC05000408-2-en.vsd
IEC05000408 V2 EN
Figure 367:
16.2.4.3
Table 477:
Name VALUE RANGE
16.2.4.4
Table 478:
Name MV db MV zeroDb MV hhLim MV hLim MV lLim MV llLim MV min MV max MV dbType
Setting parameters
MVGGIO Non group settings (basic)
Values (Range) 1 - 300 0 - 100000 -10000000000.000 - 10000000000.000 -10000000000.000 - 10000000000.000 -10000000000.000 - 10000000000.000 -10000000000.000 - 10000000000.000 -10000000000.000 - 10000000000.000 -10000000000.000 - 10000000000.000 Cyclic Dead band Int deadband 0.000 - 100.000 Unit Type m% Step 1 1 0.001 0.001 0.001 0.001 0.001 0.001 Default 10 500 90.000 80.000 -80.000 -90.000 -100.000 100.000 Dead band Description Cycl: Report interval (s), Db: In % of range, Int Db: In %s Zero point clamping in 0.001% of range High High limit High limit Low limit Low Low limit Minimum value Maximum value Reporting type
MV limHys
0.001
5.000
16.2.5
16.2.5.1
Introduction
Redundant station bus communication according to IEC 62439-3 Edition 1 and IEC 62439-3 Edition 2 are available as options in 670 series IEDs. IEC 62439-3 parallel
809
redundant protocol is an optional quantity and the selection is made at ordering. Redundant station bus communication according to IEC 62439-3 uses both port AB and port CD on the OEM module. Select IEC 62439-3 Edition 1 protocol at the time of ordering when an existing redundant station bus DuoDriver installation is extended. Select IEC 62439-3 Edition 2 protocol at the time of ordering for new installations with redundant station bus. IEC 62439-3 Edition 1 is NOT compatible with IEC 62439-3 Edition 2.
16.2.5.2
Principle of operation
The redundant station bus communication (DUODRV) is configured using the local HMI. The settings for DUODRV are also visible in PST in PCM600. The communication is performed in parallel, that is the same data package is transmitted on both channels simultaneously. The received package identity from one channel is compared with data package identity from the other channel, if the same, the last package is discarded. PRPSTATUS function block supervise the redundant communication on the two channels. If no data package has been received on one (or both) channels within the last 10 s, the output LAN-A-STATUS and/or LAN-B-STATUS is set to indicate error.
Data
Data
Switch A 1 2
Switch B 1 2
Data
Data
AB Configuration
CD
IED
OEM
DUODRV
PRPSTATUS
IEC09000758-2-en.vsd
IEC09000758 V2 EN
Figure 368:
Figure 369:
16.2.5.4
Output signals
Table 479:
Name LAN-A-Status LAN-B-Status
16.2.5.5
Table 480:
Name Operation IPAddress IPMask
Setting parameters
DUODRV Non group settings (basic)
Values (Range) Disabled Enabled 0 - 18 0 - 18 Unit IP Address IP Address Step 1 1 Default Disabled 192.168.7.10 255.255.255.0 Description Disable/Enable Operation IP-Address IP-Mask
16.3
16.3.1
applications that cover a range of requirements. The protocol follows the reference model for open system interconnection (OSI) designed by the International Standardization Organization (ISO). In this document the most common addresses for commands and events are available. For other addresses, refer to section "Related documents". It is assumed that the reader is familiar with LON communication protocol in general.
16.3.2
Principle of operation
The speed of the network depends on the medium and transceiver design. With protection and control devices, fibre optic media is used, which enables the use of the maximum speed of 1.25 Mbits/s. The protocol is a peer-to-peer protocol where all the devices connected to the network can communicate with each other. The own subnet and node number are identifying the nodes (max. 255 subnets, 127 nodes per one subnet). The LON bus links the different parts of the protection and control system. The measured values, status information, and event information are spontaneously sent to the higher-level devices. The higher-level devices can read and write memorized values, setting values, and other parameter data when required. The LON bus also enables the bay level devices to communicate with each other to deliver, for example, interlocking information among the terminals without the need of a bus master. The LonTalk protocol supports two types of application layer objects: network variables and explicit messages. Network variables are used to deliver short messages, such as measuring values, status information, and interlocking/blocking signals. Explicit messages are used to transfer longer pieces of information, such as events and explicit read and write messages to access device data. The benefits achieved from using the LON bus in protection and control systems include direct communication among all terminals in the system and support for multimaster implementations. The LON bus also has an open concept, so that the terminals can communicate with external devices using the same standard of network variables.
For more information, refer to LON bus, LonWorks Network in Protection and Control, Users manual and Technical description.
LON protocol
Configuration of LON Lon Network Tool (LNT 505) is a multi-purpose tool for LonWorks network configuration. All the functions required for setting up and configuring a LonWorks network, is easily accessible on a single tool program. For more information, refer to the operator's manual.
813 Technical reference manual
Activate LON Communication Activate LON communication in the Parameter Setting tool under Main menu/ Communication/ SLM configuration/ Rear optical LON port/ Horizontal communication, where Operation must be set to ON. Add LON Device Types LNT A new device is added to LON Network Tool from the Device menu or by installing the device from the ABB LON Device Types package for LNT 505, with the SLDT 670 series package version 1p2 r03. LON net address To establish a LON connection with the 670 series IEDs, the IED has to be given a unique net address. The net address consists of a subnet and node number. This is accomplished with the LON Network Tool by creating one device for each IED. Vertical communication Vertical communication describes communication between the monitoring devices and protection and control IEDs. This communication includes sending of changed process data to monitoring devices as events and transfer of commands, parameter data and disturbance recorder files. This communication is implemented using explicit messages. Events and indications Events sent to the monitoring devices are using explicit messages (message code 44H) with unacknowledged transport service of the LonTalk protocol. When a signal is changed in the IED, one message with the value, quality and time is transmitted from terminal. Binary events Binary events are generated in event function blocks EVENT:1 to EVENT:20 in the 670 series IEDs. The event function blocks have predefined LON addresses. table 481 shows the LON addresses to the first input on the event function blocks. The addresses to the other inputs on the event function block are consecutive after the first input. For example, input 15 on event block EVENT:17 has the address 1280 + 14 (15-1) = 1294. For double indications only the first eight inputs 18 must be used. Inputs 916 can be used for other type of events at the same event block. As basic, three event function blocks EVENT:1 to EVENT:3 running with a fast loop time (3 ms) is available in the 670 series IEDs. The remaining event function blocks EVENT:4 to EVENT:9 runs with a loop time on 8 ms and EVENT:10 to EVENT:20 runs with a loop time on 100 ms. The event blocks are used to send binary signals, integers, real time values like analogue data from measuring functions and mA input modules as well as pulse counter signals.
16 pulse counter value function blocks PCGGIO:1 to PCGGIO:16 and 24 mA input service values function blocks SMMI1_In1 to 6 SMMI4_In1 to 6 are available in the 670 series IEDs. The first LON address in every event function block is found in table 481
Table 481:
Function block EVENT:1 EVENT:2 EVENT:3 EVENT:4 EVENT:5 EVENT:6 EVENT:7 EVENT:8 EVENT:9 EVENT:10 EVENT:11 EVENT:12 EVENT:13 EVENT:14 EVENT:15 EVENT:16 EVENT:17 EVENT:18 EVENT:19 EVENT:20
Event masks The event mask for each input can be set individually from Parameter Setting Tool (PST) under: Settings/ General Settings/ Monitoring / EventFunction as follows: No events OnSet, at pick-up of the signal OnReset, at drop-out of the signal OnChange, at both pick-up and drop-out of the signal AutoDetect, event system itself make the reporting decision, (reporting criteria for integers has no semantic, prefer to be set by the user)
The following type of signals from application functions can be connected to the event function block. Single indication Directly connected binary IO signal via binary input function block (SMBI) is always reported on change, no changed detection is done in the event function block. Other Boolean signals, for example a start or a trip signal from a protection function is event masked in the event function block. Double indications Double indications can only be reported via switch-control (SCSWI) functions, the event reporting is based on information from switch-control, no change detection is done in the event function block. Directly connected binary IO signal via binary input function block (SMBI) is not possible to handle as double indication. Double indications can only be reported for the first 8 inputs on an event function block. 00 generates an intermediate event with the read status 0 01 generates an open event with the read status 1 10 generates a close event with the read status 2 11 generates an undefined event with the read status 3
Analog value All analog values are reported cyclic, the reporting interval is taken from the connected function if there is a limit supervised signal, otherwise it is taken from the event function block. Command handling Commands are transferred using transparent SPA-bus messages. The transparent SPAbus message is an explicit LON message, which contains an ASCII character message following the coding rules of the SPA-bus protocol. The message is sent using explicit messages with message code 41H and using acknowledged transport service. Both the SPA-bus command messages (R or W) and the reply messages (D, A or N) are sent using the same message code. It is mandatory that one device sends out only one SPA-bus message at a time to one node and waits for the reply before sending the next message. For commands from the operator workplace to the IED for apparatus control, That is, the function blocks type SCSWI 1 to 32, SXCBR 1 to 18 and SXSWI 1 to 28; the SPA addresses are according to table 482.
Network variables are used for communication between 500 series and 670 series IEDs. The supported network variable type is SNVT_state (NV type 83). SNVT_state is used to communicate the state of a set of 1 to 16 Boolean values. Multiple command send function block (MULTICMDSND) is used to pack the information to one value. This value is transmitted to the receiving node and presented for the application by a multiple command function block (MULTICMDRCV). At horizontal communication the input BOUND on the event function block (MULTICMDSND) must be set to 1. There are 10 MULTICMDSND and 60 MULTICMDRCV function blocks available. The MULTICMDSND and MULTICMDRCV function blocks are connected using Lon Network Tool (LNT 505). This tool also defines the service and addressing on LON. This is an overview for configuring the network variables for 670 series IEDs. Configuration of LON network variables Configure the Network variables according to the specific application using the LON network Tool. For more information, refer to LNT 505 in Operation manual. The following is an example of how to configure network variables concerning, for example, interlocking between two IEDs.
LON BAY E1
MULTICMDSND: 7
BAY E3
MULTICMDSND: 9
BAY E4
MULTICMDSND: 9
en05000718.vsd
IEC05000718 V2 EN
Figure 370:
Examples connections between MULTICMDSND and MULTICMDRCV function blocks in three IEDs
The network variable connections are done from the NV Connection window. From LNT window select Connections/ NVConnections/ New.
en05000719.vsd
IEC05000719 V1 EN
Figure 371:
There are two ways of downloading NV connections. Either the users can use the dragand-drop method where they can select all nodes in the device window, drag them to the Download area in the bottom of the program window and drop them there; or, they can perform it by selecting the traditional menu, Configuration/ Download.
en05000720.vsd
IEC05000720 V1 EN
Figure 372:
Communication ports
The serial communication module (SLM) is used for SPA/IEC60870-5-103/DNP and LON communication. This module is a mezzanine module, and can be placed on the Main Processing Module (NUM). The serial communication module can have connectors for two plastic fibre cables (snap-in) or two glass fibre cables (ST, bayonet) or a combination of plastic and glass fibre. Three different types are available depending on type of fibre. The incoming optical fibre is connected to the RX receiver input, and the outgoing optical fibre to the TX transmitter output. When the fibre optic cables are laid out, pay special attention to the instructions concerning the handling and connection of the optical fibres. The module is identified with a number on the label on the module.
Table 482:
Name BL_CMD BL_CMD BL_CMD BL_CMD Table continues on next page
SPA addresses for commands from the operator workplace to the IED for apparatus control
Function block SCSWI01 SCSWI02 SCSWI02 SCSWI04 SPA address 1 I 5115 1 I 5139 1 I 5161 1 I 5186 Description SPA parameters for block command SPA parameters for block command SPA parameters for block command SPA parameters for block command
SPA parameters for block command SPA parameters for block command SPA parameters for block command SPA parameters for block command SPA parameters for block command SPA parameters for block command SPA parameters for block command SPA parameters for block command SPA parameters for block command SPA parameters for block command SPA parameters for block command SPA parameters for block command SPA parameters for block command SPA parameters for block command SPA parameters for block command SPA parameters for block command SPA parameters for block command SPA parameters for block command SPA parameters for block command SPA parameters for block command SPA parameters for block command SPA parameters for block command
SPA parameters for cancel command SPA parameters for cancel command SPA parameters for cancel command SPA parameters for cancel command SPA parameters for cancel command SPA parameters for cancel command SPA parameters for cancel command SPA parameters for cancel command SPA parameters for cancel command SPA parameters for cancel command SPA parameters for cancel command SPA parameters for cancel command SPA parameters for cancel command SPA parameters for cancel command SPA parameters for cancel command SPA parameters for cancel command SPA parameters for select (Open/ Close) command Note: Send select command before operate command
SPA parameters for select (Open/ Close) command SPA parameters for select (Open/ Close) command SPA parameters for select (Open/ Close) command
SPA parameters for select (Open/ Close) command SPA parameters for select (Open/ Close) command SPA parameters for select (Open/ Close) command SPA parameters for select (Open/ Close) command SPA parameters for select (Open/ Close) command SPA parameters for select (Open/ Close) command SPA parameters for operate (Open/ Close) command Note: Send select command before operate command
SCSWI02 SCSWI02 SCSWI04 SCSWI05 SCSWI06 SCSWI07 SCSWI08 SCSWI09 SCSWI10 SCSWI11 SCSWI12 SCSWI13 SCSWI14
1 I 5130 1 I 5152 1 I 5177 1 I 5201 1 I 5225 1 I 5249 1 I 5274 1 I 5298 1 I 5322 1 I 5346 1 I 5370 1 I 5394 1 I 5418
SPA parameters for operate (Open/ Close) command SPA parameters for operate (Open/ Close) command SPA parameters for operate (Open/ Close) command SPA parameters for operate (Open/ Close) command SPA parameters for operate (Open/ Close) command SPA parameters for operate (Open/ Close) command SPA parameters for operate (Open/ Close) command SPA parameters for operate (Open/ Close) command SPA parameters for operate (Open/ Close) command SPA parameters for operate (Open/ Close) command SPA parameters for operate (Open/ Close) command SPA parameters for operate (Open/ Close) command SPA parameters for operate (Open/ Close) command
Sub Value Sub Value Sub Value Table continues on next page
SPA parameter for position to be substituted SPA parameter for position to be substituted SPA parameter for position to be substituted SPA parameter for position to be substituted SPA parameter for position to be substituted SPA parameter for position to be substituted SPA parameter for position to be substituted SPA parameter for position to be substituted SPA parameter for position to be substituted SPA parameter for position to be substituted SPA parameter for position to be substituted SPA parameter for position to be substituted SPA parameter for position to be substituted SPA parameter for position to be substituted SPA parameter for position to be substituted SPA parameter for position to be substituted SPA parameter for position to be substituted SPA parameter for position to be substituted SPA parameter for position to be substituted SPA parameter for position to be substituted SPA parameter for position to be substituted SPA parameter for position to be substituted
SPA parameter for substitute enable command SPA parameter for substitute enable command SPA parameter for substitute enable command SPA parameter for substitute enable command SPA parameter for substitute enable command SPA parameter for substitute enable command SPA parameter for substitute enable command SPA parameter for substitute enable command SPA parameter for substitute enable command SPA parameter for substitute enable command SPA parameter for substitute enable command SPA parameter for substitute enable command SPA parameter for substitute enable command SPA parameter for substitute enable command SPA parameter for substitute enable command SPA parameter for substitute enable command SPA parameter for substitute enable command SPA parameter for substitute enable command SPA parameter for substitute enable command SPA parameter for substitute enable command SPA parameter for substitute enable command SPA parameter for substitute enable command
SPA parameter for substitute enable command SPA parameter for update block command SPA parameter for update block command SPA parameter for update block command SPA parameter for update block command SPA parameter for update block command SPA parameter for update block command SPA parameter for update block command SPA parameter for update block command SPA parameter for update block command SPA parameter for update block command SPA parameter for update block command SPA parameter for update block command SPA parameter for update block command SPA parameter for update block command SPA parameter for update block command SPA parameter for update block command SPA parameter for update block command SPA parameter for update block command SPA parameter for update block command SPA parameter for update block command SPA parameter for update block command
SPA parameter for update block command SPA parameter for update block command SPA parameter for update block command
16.3.3
Table 483:
Name Operation
Setting parameters
HORZCOMM Non group settings (basic)
Values (Range) Disabled Enabled Unit Step Default Disabled Description Operation
Table 484:
Name Operation TimerClass
16.3.4
Technical data
Table 485:
Function Protocol Communication speed
16.4
16.4.1
16.4.2
The basic construction of the protocol assumes that the slave has no self-initiated need to talk to the master but the master is aware of the data contained in the slaves and, consequently, can request required data. In addition, the master can send data to the slave. Requesting by the master can be performed either by sequenced polling (for example, for event information) or only on demand. The master requests slave information using request messages and sends information to the slave in write messages. Furthermore, the master can send all slaves in common a broadcast message containing time or other data. The inactive state of bus transmit and receive lines is a logical "1".
SPA protocol
The tables below specify the SPA addresses for reading data from and writing data to an IED with the SPA communication protocol implemented. The SPA addresses for the mA input service values (MIM3 to MIM16) are found in table 486.
Table 486:
Function block MIM3-CH1 MIM3-CH2 MIM3-CH3 MIM3-CH4 MIM3-CH5 MIM3-CH6 MIM4-CH1 MIM4-CH2 MIM4-CH3 MIM4-CH4 MIM4-CH5 MIM4-CH6 MIM5-CH1 MIM5-CH2 Table continues on next page 833 Technical reference manual
The SPA addresses for the pulse counter values PCGGIO:1 to PCGGIO:16 are found in table 487.
Table 487:
Function block PCGGIO:1 PCGGIO:2 PCGGIO:3 PCGGIO:4 PCGGIO:5 PCGGIO:6 PCGGIO:7 PCGGIO:8 PCGGIO:9 PCGGIO:10 PCGGIO:11 PCGGIO:12 PCGGIO:13 PCGGIO:14 PCGGIO:15 PCGGIO:16
I/O modules To read binary inputs, the SPA-addresses for the outputs of the I/O-module function block are used, that is, the addresses for BI1 BI16. For SPA addresses, refer to section "Related documents". Single command, 16 signals The IEDs can be provided with a function to receive signals either from a substation automation system or from the local HMI. That receiving function block has 16 outputs that can be used, for example, to control high voltage apparatuses in switchyards. For local control functions, the local HMI can also be used. Single command, 16 signals function consists of three function blocks; SINGLECMD: 1 to SINGLECMD:3 for 16 binary output signals each. The signals can be individually controlled from the operator station, remote-control gateway, or from the local HMI on the IED. For Single command, 16 signals function block, SINGLECMD:1 to SINGLECMD:3, the address is for the first output. The other
outputs follow consecutively after the first one. For example, output 7 on the SINGLECMD:2 function block has the 5O533 address. The SPA addresses for Single command, 16 signals functions SINGLECMD:1 to SINGLECMD:3 are found in table 488.
Table 488:
Function block SINGLECMD1-Cmd1 SINGLECMD1-Cmd2 SINGLECMD1-Cmd3 SINGLECMD1-Cmd4 SINGLECMD1-Cmd5 SINGLECMD1-Cmd6 SINGLECMD1-Cmd7 SINGLECMD1-Cmd8 SINGLECMD1-Cmd9 SINGLECMD1-Cmd10 SINGLECMD1-Cmd11 SINGLECMD1-Cmd12 SINGLECMD1-Cmdt13 SINGLECMD1-Cmd14 SINGLECMD1-Cmd15 SINGLECMD1-Cmd16 SINGLECMD2-Cmd1 SINGLECMD2-Cmd2 SINGLECMD2-Cmdt3 SINGLECMD2-Cmd4 SINGLECMD2-Cmd5 SINGLECMD2-Cmd6 SINGLECMD2-Cmd7 SINGLECMD2-Cmd8 SINGLECMD2-Cmd9 SINGLECMD2-Cmd10 SINGLECMD2-Cmd11 SINGLECMD2-Cmd12 SINGLECMD2-Cmd13 SINGLECMD2-Cmd14 Table continues on next page
SPA address CMD output 5-O-541 5-O-542 5-O-543 5-O-544 5-O-545 5-O-546 5-O-547 5-O-548 5-O-549 5-O-550 5-O-551 5-O-552 5-O-553 5-O-554 5-O-555 5-O-556 5-O-557 5-O-558
Figure 373 shows an application example of how the user can, in a simplified way, connect the command function via the configuration logic circuit in a protection IED for control of a circuit breaker. A pulse via the binary outputs of the IED normally performs this type of command control. The SPA addresses to control the outputs OUT1 OUT16 in SINGLECMD:1 are shown in table 488.
SINGLECMD BLOCK ^OUT1 ^OUT2 ^OUT3 ^OUT4 ^OUT5 ^OUT6 ^OUT7 ^OUT8 ^OUT9 ^OUT10 ^OUT11 ^OUT12 ^OUT13 ^OUT14 ^OUT15 ^OUT16 INPUT1 INPUT2 INPUT3 INPUT4N AND OUT NOUT INPUT #1.000 T INPUT #1.000 T
SYNCH OK
IEC05000717-2-en.vsd
IEC05000717 V2 EN
Figure 373:
Application example showing a simplified logic diagram for control of a circuit breaker
The MODE input defines if the output signals from SINGLECMD:1 is off, steady or pulsed signals. This is set in Parameter Setting Tool (PST) under: Setting / General Settings / Control / Commands / Single Command. Event function Event function is intended to send time-tagged events to the station level (for example, operator workplace) over the station bus. The events are there presented in an event list. The events can be created from both internal logical signals and binary input channels. All the internal signals are time tagged in the main processing module, while the binary input channels are time tagged directly on each I/O module. The events are produced according to the set event masks. The event masks are treated commonly for both the LON and SPA channels. All events according to the event mask are stored in a buffer, which contains up to 1000 events. If new events appear before the oldest event in the buffer is read, the oldest event is overwritten and an overflow alarm appears. Two special signals for event registration purposes are available in the IED, Terminal Restarted (0E50) and Event buffer overflow (0E51). The input parameters can be set individually from the Parameter Setting Tool (PST) under: Setting / General Setting / Monitoring / Event Function as follows: No events OnSet, at pick-up of the signal OnReset, at drop-out of the signal OnChange, at both pick-up and drop-out of the signal AutoDetect, event system itself make the reporting decision, (reporting criteria for integers has no semantic, prefer to be set by the user)
The Status and event codes for the Event functions are found in table 489.
Table 489:
Event block EVENT:1 Input 1 Input 2 Input 3 Input 4 Input 5 Input 6 Input 7 Input 8 Input 9 Input 10 Input 11 Input 12 Input 13 Input 14 Input 15 Input 16 EVENT:2 EVENT:3 EVENT:20
22O1 22O2 22O3 22O4 22O5 22O6 22O7 22O8 22O9 22O10 22O11 22O12 22O13 22O14 22O15 22O16 230.. 240.. 410..
These values are only applicable if the Event mask is masked OFF. Connection of signals as events Signals coming from different protection and control functions and must be sent as events to the station level over the SPA-bus (or LON-bus) are connected to the Event function block according to figure 374.
EVENT Block ILRANG PSTO UL12RANG UL23RANG UL31RANG 3I0RANG 3U0RANG FALSE BLOCK ^INPUT1 ^INPUT2 ^INPUT3 ^INPUT4 ^INPUT5 ^INPUT6 ^INPUT7 ^INPUT8 ^INPUT9 ^INPUT10 ^INPUT11 ^INPUT12 ^INPUT13 ^INPUT14 ^INPUT15 ^INPUT16
IEC07000065-2-en.vsd
IEC07000065 V2 EN
Figure 374:
16.4.2.1
Communication ports
The serial communication module (SLM) is used for SPA /IEC 60870-5-103/DNP and LON communication. This module is a mezzanine module, and can be placed on the Analog/Digital conversion module (ADM). The serial communication module can have connectors for two plastic fibre cables (snap-in) or two glass fibre cables (ST, bayonet) or a combination of plastic and glass fibre. Three different types are available depending on type of fibre. The incoming optical fibre is connected to the RX receiver input, and the outgoing optical fibre to the TX transmitter output. When the fibre optic cables are laid out, pay special attention to the instructions concerning the handling and connection of the optical fibres. The module is identified with a number on the label on the module. The procedure to set the transfer rate and slave number can be found in the Installation and commissioning manual for respective IEDs.
16.4.3
Design
When communicating locally with a computer (PC) in the station, using the rear SPA port, the only hardware needed for a station monitoring system is: Optical fibres Opto/electrical converter for the PC PC
When communicating remotely with a PC using the rear SPA port, the same hardware and telephone modems are needed.
The software needed in the PC, either local or remote, is PCM600. When communicating between the local HMI and a PC, the only hardware required is a front-connection cable.
16.4.4
Table 490:
Name SlaveAddress BaudRate
Setting parameters
SPA Non group settings (basic)
Values (Range) 1 - 899 300 Bd 1200 Bd 2400 Bd 4800 Bd 9600 Bd 19200 Bd 38400 Bd Unit Step 1 Default 30 9600 Bd Description Slave address Baudrate on serial line
Table 491:
Name Operation SlaveAddress
16.4.5
Technical data
Table 492:
Function Protocol Communication speed Slave number
16.5
16.5.1
16.5.2
16.5.2.1
IEC 60870-5-103 protocol functionality consists of the following functions: Event handling Report of analog service values (measurements) Fault location Command handling Autorecloser ON/OFF Teleprotection ON/OFF Protection ON/OFF LED reset Characteristics 1 - 4 (Setting groups)
For detailed information about IEC 60870-5-103, refer to the IEC 60870 standard part 5: Transmission protocols, and to the section 103: Companion standard for the informative interface of protection equipment.
The signal and setting tables specify the information types supported by the IEDs with the communication protocol IEC 60870-5-103 implemented. The information types are supported when corresponding functions are included in the protection and control IED. Commands in control direction Commands in control direction, I103IEDCMD Command block in control direction with defined output signals. Number of instances: 1
Function type is selected with parameter FunctionType. Information number is defined for each output signals.
Info. no 19 23 24 25 26 Message LED Reset Activate setting group 1 Activate setting group 2 Activate setting group 3 Activate setting group 4 Supported Yes Yes Yes Yes Yes
Function commands in control direction, pre-defined I103CMD Function command block in control direction with defined output signals. Number of instances: 1 Function type is selected with parameter FunctionType. Information number is defined for each output signals.
Info. no. 16 17 18 Message Auto-recloser on/off Teleprotection on/off Protection on/off Supported Yes Yes Yes
Function commands in control direction, user-defined, I103UserCMD Function command blocks in control direction with user-defined output signals. Number of instances: 4 Function type for each function block instance in private range is selected with parameter FunctionType. Default values are defined in private range 1 - 4. One for each instance. Information number must be selected for each output signal. Default values are 1 - 8.
Info. no. 1 2 3 4 5 Message Output signal 01 Output signal 02 Output signal 03 Output signal 04 Output signal 05 Supported Yes Yes Yes Yes Yes
Status Terminal status indications in monitor direction, I103IED Indication block for status in monitor direction with defined IED functions. Number of instances: 1 Function type is selected with parameter FunctionType. Information number is defined for each input signals.
Info. no. 19 20 21 22 23 24 25 26 Message LED reset Monitor direction blocked TestMode Local Parameter setting Setting group 1 active Setting group 2 active Setting group 3 active Setting group 4 active Yes Yes Yes Yes Supported Yes No
Function status indications in monitor direction, user-defined, I103UserDef Function indication blocks in monitor direction with user-defined input signals. Number of instances: 20 Function type is selected with parameter FunctionType for each function block instance in private range. Default values are defined in private range 5 - 24. One for each instance. Information number is required for each input signal. Default values are defined in range 1 - 8. Supervision indications in monitor direction, I103Superv Indication block for supervision in monitor direction with defined functions. Number of instances: 1 Function type is selected with parameter FunctionType.
845 Technical reference manual
Information number is defined for output signals. Ground fault indications in monitor direction, I103EF Indication block for ground fault in monitor direction with defined functions. Number of instances: 1 Function type is selected with parameter FunctionType. Information number is defined for each output signal.
Info. no. 48 49 50 51 52 Message Ground fault A Ground fault B Ground fault C Ground fault forward Ground fault reverse Supported No No No Yes Yes
Fault indications in monitor direction, type 1, I103FltDis Fault indication block for faults in monitor direction with defined functions. The instance type is suitable for distance protection function. FUNCTION TYPE parameter for each block. INFORMATION NUMBER is defined for each input signal. Number of instances: 1
Info. no. 64 65 66 67 84 69 70 71 68 74 75 78 Message Start L1 Start L2 Start L3 Start IN General start Trip L1 Trip L2 Trip L3 General trip Fault forward/line Fault reverse/busbar Zone 1 Supported Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Fault indications in monitor direction, type 2, I103FltStd Fault indication block for faults in monitor direction with defined functions. The instance type is suitable for line differential, transformer differential, overcurrent and ground fault protection functions. FUNCTION TYPE setting for each block. INFORMATION NUMBER is defined for each input signal. Number of instances: 1
Info. no. 64 65 66 67 84 69 70 71 68 74 75 85 86 87 88 89 90 Message Start L1 Start L2 Start L3 Start IN General start Trip L1 Trip L2 Trip L3 General trip Fault forward/line Fault reverse/busbar Breaker failure Trip measuring system L1 Trip measuring system L2 Trip measuring system L3 Trip measuring system N Over current trip I> Supported Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Autorecloser indications in monitor direction, I103AR Indication block for autorecloser in monitor direction with defined functions. Number of instances: 1 Function type is selected with parameter FunctionType. Information number is defined for each output signal.
Info. no. 16 17 18 128 129 130 Message Autorecloser active Teleprotection active Protection active CB on by Autorecloser CB on by long-time AR Autorecloser blocked Supported Yes No No Yes No Yes
Measurands Function blocks in monitor direction for input measurands. Typically connected to monitoring function, for example to power measurement CVMMXN. Measurands in public range, I103Meas Number of instances: 1 The IED reports all valid measuring types depending on connected signals. Upper limit for measured currents, active/reactive-power is 2.4 times rated value. Upper limit for measured voltages and frequency is 1.2 times rated value.
Info. no. 148 144, 145, 148 148 147 Message I_A I_B I_C IN, Neutral current Supported Yes Yes Yes Yes
Measurands in private range, I103MeasUsr Number of instances: 3 Function type parameter for each block in private range. Default values are defined in private range 25 27. One for each instance. Information number must be selected for measurands.
Info. *1) * * * * * * * * Message Meas1 Meas2 Meas3 Meas4 Meas5 Meas6 Meas7 Meas8 Meas9 Supported Yes Yes Yes Yes Yes Yes Yes Yes Yes
Disturbance recordings The following elements are used in the ASDUs (Application Service Data Units) defined in the standard. Analog signals, 40-channels: the channel number for each channel has to be specified. Channels used in the public range are 1 to 8 and with: IA connected to channel 1 on disturbance function block A1RADR IB connected to channel 2 on disturbance function block A1RADR IC connected to channel 3 on disturbance function block A1RADR
849 Technical reference manual
IN connected to channel 4 on disturbance function block A1RADR VAE connected to channel 5 on disturbance function block A1RADR VBE connected to channel 6 on disturbance function block A1RADR VCE connected to channel 7 on disturbance function block A1RADR VEN connected to channel 8 on disturbance function block A1RADR
Channel number used for the remaining 32 analog signals are numbers in the private range 64 to 95. Binary signals, 96-channels: for each channel the user can specify a FUNCTION TYPE and an INFORMATION NUMBER. Disturbance upload All analog and binary signals that are recorded with disturbance recorder can be reported to the master. The last eight disturbances that are recorded are available for transfer to the master. A successfully transferred disturbance (acknowledged by the master) will not be reported to the master again. When a new disturbance is recorded by the IED a list of available recorded disturbances will be sent to the master, an updated list of available disturbances can be sent whenever something has happened to disturbances in this list. For example, when a disturbance is deteceted (by other client, for example, SPA) or when a new disturbance has been recorded or when the master has uploaded a disturbance. Deviations from the standard Information sent in the disturbance upload is specified by the standard; however, some of the information are adapted to information available in disturbance recorder in 670 series. This section describes all data that is not exactly as specified in the standard. ASDU23 In list of recorded disturbances (ASDU23) an information element named SOF (status of fault) exists. This information element consists of 4 bits and indicates whether: Bit TP: the protection equipment has tripped during the fault Bit TM: the disturbance data are currently being transmitted Bit TEST: the disturbance data have been recorded during normal operation or test mode. Bit OTEV: the disturbance data recording has been initiated by another event than pick-up
The only information that is easily available is test-mode status. The other information is always set (hard coded) to:
TP TM OTEV Recorded fault with trip. [1] Disturbance data waiting for transmission [0] Disturbance data initiated by other events [1]
Another information element in ASDU23 is the FAN (fault number). According to the standard this is a number that is incremented when a protection function takes action. In 670 series FAN is equal to disturbance number, which is incremented for each disturbance. ASDU26 When a disturbance has been selected by the master; (by sending ASDU24), the protection equipment answers by sending ASDU26, which contains an information element named NOF (number of grid faults). This number must indicate fault number in the power system,that is, a fault in the power system with several trip and autoreclosing has the same NOF (while the FAN must be incremented). NOF is in 670 series, just as FAN, equal to disturbance number. To get INF and FUN for the recorded binary signals there are parameters on the disturbance recorder for each input. The user must set these parameters to whatever he connects to the corresponding input.
Selection of standard ASDUs in control direction ASDU 6 7 10 20 21 24 25 Time synchronization General interrogation Generic data General command Generic command Order for disturbance data transmission Acknowledgement for distance data transmission Yes Yes Yes No Yes No Yes Yes
Selection of basic application functions Test mode Blocking of monitoring direction Disturbance data Private data Generic services No Yes Yes Yes No
16.5.2.2
16.5.3
Function block
BLOCK FUNTYPE I103IEDCMD 19-LEDRS 23-GRP1 24-GRP2 25-GRP3 26-GRP4 IEC05000689-2-en.vsd
IEC05000689 V2 EN
I103USRCMD BLOCK OUTPUT1 PULSEMOD OUTPUT2 T OUTPUT3 FUNTYPE OUTPUT4 INFNO_1 OUTPUT5 INFNO_2 OUTPUT6 INFNO_3 OUTPUT7 INFNO_4 OUTPUT8 INFNO_5 INFNO_6 INFNO_7 INFNO_8 IEC05000693-2-en.vsd
IEC05000693 V2 EN
I103IED BLOCK 19_LEDRS 23_GRP1 24_GRP2 25_GRP3 26_GRP4 21_TESTM FUNTYPE IEC05000688-2-en.vsd
IEC05000688 V2 EN
I103USRDEF BLOCK INPUT1 INPUT2 INPUT3 INPUT4 INPUT5 INPUT6 INPUT7 INPUT8 FUNTYPE INFNO_1 INFNO_2 INFNO_3 INFNO_4 INFNO_5 INFNO_6 INFNO_7 INFNO_8 IEC05000694-2-en.vsd
IEC05000694 V2 EN
I103SUPERV BLOCK 32_MEASI 33_MEASU 37_IBKUP 38_VTFF 46_GRWA 47_GRAL FUNTYPE IEC05000692-2-en.vsd
IEC05000692 V2 EN
I103FLTDIS BLOCK 64_STL1 65_STL2 66_STL3 67_STIN 84_STGEN 69_TRL1 70_TRL2 71_TRL3 68_TRGEN 74_FW 75_REV 78_ZONE1 79_ZONE2 80_ZONE3 81_ZONE4 82_ZONE5 76_TRANS 77_RECEV 73_SCL FLTLOC ARINPROG FUNTYPE IEC05000686-2-en.vsd
IEC05000686 V2 EN
I103FLTSTD BLOCK 64_STL1 65_STL2 66_STL3 67_STIN 84_STGEN 69_TRL1 70_TRL2 71_TRL3 68_TRGEN 74_FW 75_REV 85_BFP 86_MTRL1 87_MTRL2 88_MTRL3 89_MTRN 90_IOC 91_IOC 92_IEF 93_IEF ARINPROG FUNTYPE IEC05000687-2-en.vsd
IEC05000687 V2 EN
I103MEAS BLOCK I_A I_B I_C IN V_A V_B V_C V_AB V_N P Q F FUNTYPE ANSI05000690-2-en.vsd
ANSI05000690 V2 EN
16.5.4
Table 494:
Name 19-LEDRS 23-GRP1 24-GRP2 25-GRP3 26-GRP4
Table 495:
Name BLOCK
Table 496:
Name 16-AR 17-DIFF 18-PROT
Table 497:
Name BLOCK
Table 498:
Name OUTPUT1 OUTPUT2 OUTPUT3 OUTPUT4 OUTPUT5 OUTPUT6 OUTPUT7 OUTPUT8
Table 499:
Name BLOCK 19_LEDRS 23_GRP1 24_GRP2 25_GRP3 26_GRP4 21_TESTM
Table 500:
Name BLOCK INPUT1 INPUT2 INPUT3 INPUT4 INPUT5 INPUT6 INPUT7 INPUT8
Table 501:
Name BLOCK 32_MEASI 33_MEASU 37_IBKUP 38_VTFF 46_GRWA 47_GRAL
Table 502:
Name BLOCK 51_EFFW 52_EFREV
Table 503:
Name BLOCK 64_PU_A 65_PU_B 66_PU_C 67_STIN 84_STGEN 69_TR_A 70_TR_B 71_TR_C 68_TRGEN 74_FW 75_REV 78_ZONE1 79_ZONE2 80_ZONE3 81_ZONE4 82_ZONE5 76_TRANS
Table 504:
Name BLOCK 64_PU_A 65_PU_B 66_PU_C 67_STIN 84_STGEN 69_TR_A 70_TR_B 71_TR_C 68_TRGEN 74_FW 75_REV 85_BFP 86_MTR_A 87_MTR_B 88_MTR_C 89_MTRN 90_IOC 91_IOC 92_IEF 93_IEF ARINPROG
Table 505:
Name BLOCK 16_ARACT 128_CBON 130_UNSU
Table 506:
Name BLOCK I_A I_B I_C IN V_A V_B V_C V_AB V_N P Q F
Table 507:
Name BLOCK INPUT1 INPUT2 INPUT3 INPUT4 INPUT5 INPUT6 INPUT7 INPUT8 INPUT9
16.5.5
Table 508:
Name SlaveAddress BaudRate RevPolarity CycMeasRepTime
Table 509:
Name FUNTYPE
Table 510:
Name FUNTYPE
Table 511:
Name PULSEMOD T FUNTYPE INFNO_1 INFNO_2 INFNO_3 INFNO_4 INFNO_5 INFNO_6 INFNO_7 INFNO_8
Table 512:
Name FUNTYPE
Table 513:
Name FUNTYPE INFNO_1 INFNO_2 INFNO_3 INFNO_4 INFNO_5 INFNO_6 INFNO_7 INFNO_8
Table 514:
Name FUNTYPE
Table 515:
Name FUNTYPE
Table 516:
Name FUNTYPE
Table 517:
Name FUNTYPE
Table 518:
Name FUNTYPE
Table 519:
Name RatedI_A RatedI_B RatedI_C RatedI_N RatedV_A RatedV_B RatedV_C RatedV_AB RatedV_N RatedP RatedQ RatedF FUNTYPE
Table 520:
Name FUNTYPE INFNO RatedMeasur1 RatedMeasur2 RatedMeasur3 RatedMeasur4 RatedMeasur5 RatedMeasur6 RatedMeasur7 RatedMeasur8 RatedMeasur9
16.6
16.6.1
Figure 375:
Table 523:
Name RESREQ RESGRANT APP1_OP APP1_CL APP1VAL APP2_OP APP2_CL APP2VAL APP3_OP APP3_CL APP3VAL APP4_OP APP4_CL APP4VAL APP5_OP APP5_CL APP5VAL APP6_OP APP6_CL APP6VAL APP7_OP APP7_CL APP7VAL APP8_OP APP8_CL APP8VAL APP9_OP APP9_CL APP9VAL
16.6.3
Table 524:
Name Operation
Setting parameters
GOOSEINTLKRCV Non group settings (basic)
Values (Range) Disabled Enabled Unit Step Default Disabled Description Operation Disabled/Enabled
16.7
16.7.1
Figure 376:
16.7.2
Table 526:
Name OUT1 OUT1VAL OUT2
16.7.3
Table 527:
Name Operation
Setting parameters
GOOSEBINRCV Non group settings (basic)
Values (Range) Disabled Enabled Unit Step Default Disabled Description Operation Disabled/Enabled
16.8
16.8.1
Introduction
The IED can be provided with a function to send and receive signals to and from other IEDs via the interbay bus. The send and receive function blocks has 16 outputs/inputs that can be used, together with the configuration logic circuits, for control purposes within the IED or via binary outputs. When it is used to communicate with other IEDs, these IEDs have a corresponding Multiple transmit function block with 16 outputs to send the information received by the command block.
16.8.2
Principle of operation
Two multiple transmit function blocks MULTICMDSND:1 and MULTICMDSND:2 and 8 slow multiple transmit function blocks MULTICMDSND:3 to MULTICMDSND: 10 are available in the IED. Sixteen signals can be connected and they will then be sent to the multiple command block in the other IED. The connections are set with the LON Network Tool (LNT). Twelve multiple command function blocks MULTICMDRCV:1 to MULTICMDRCV: 12 with fast execution time and 48 multiple command function blocks MULTICMDRCV: 13 to MULTICMDRCV:60 with slower execution time are available in the IED. Multiple command function block MULTICMDRCV has 16 outputs combined in one block, which can be controlled from other IEDs. The output signals, here OUTPUT1 to OUTPUT16, are then available for configuration to built-in functions or via the configuration logic circuits to the binary outputs of the IED. MULTICMDRCV also has a supervision function, which sets the output VALID to 0 if the block does not receive data within set maximum time.
16.8.3
16.8.3.1
16.8.4
Function block
MULTICMDRCV BLOCK ERROR NEWDATA OUTPUT1 OUTPUT2 OUTPUT3 OUTPUT4 OUTPUT5 OUTPUT6 OUTPUT7 OUTPUT8 OUTPUT9 OUTPUT10 OUTPUT11 OUTPUT12 OUTPUT13 OUTPUT14 OUTPUT15 OUTPUT16 VALID IEC06000007-2-en.vsd
IEC06000007 V2 EN
Figure 377:
MULTICMDSND BLOCK ERROR INPUT1 INPUT2 INPUT3 INPUT4 INPUT5 INPUT6 INPUT7 INPUT8 INPUT9 INPUT10 INPUT11 INPUT12 INPUT13 INPUT14 INPUT15 INPUT16 IEC06000008-2-en.vsd
IEC06000008 V2 EN
Figure 378:
16.8.5
Table 529:
Name BLOCK INPUT1 INPUT2 INPUT3 INPUT4 INPUT5 INPUT6 INPUT7 INPUT8 INPUT9 INPUT10 INPUT11 INPUT12 INPUT13
Table 530:
Name ERROR NEWDATA OUTPUT1 OUTPUT2 OUTPUT3 OUTPUT4 OUTPUT5 OUTPUT6 OUTPUT7 OUTPUT8 OUTPUT9 OUTPUT10 OUTPUT11 OUTPUT12 OUTPUT13 OUTPUT14 OUTPUT15 OUTPUT16 VALID
Table 531:
Name ERROR
Setting parameters
MULTICMDRCV Non group settings (basic)
Values (Range) 0.050 - 200.000 0.000 - 200.000 Steady Pulsed 0.000 - 60.000 Unit s s s Step 0.001 0.001 0.001 Default 11.000 0.000 Steady 0.200 Description Maximum cycle time between receptions of input data Minimum cycle time between receptions of input data Mode for output signals Pulse length for multi command outputs
Table 533:
Name tMaxCycleTime tMinCycleTime
Section 17
Remote communication
17.1
17.1.1
Introduction
The remote end data communication is used either for the transmission of current values together with maximum 8 binary signals in the line differential protection, or for transmission of only binary signals, up to 192 signals, in the other 670 series IEDs. The binary signals are freely configurable and can, thus, be used for any purpose, for example, communication scheme related signals, transfer trip and/or other binary signals between IEDs. Communication between two IEDs requires that each IED is equipped with an LDCM (Line Data Communication Module). The LDCMs are then interfaces to a 64 kbit/s communication channel for duplex communication between the IEDs. The IED can be equipped with up to two short range or medium range LDCM.
17.1.2
Principle of operation
The communication is made on standard ITU (CCITT) PCM digital 64 kbit/s channels. It is a two-way communication where telegrams are sent every 5 ms (same in 50 Hz and 60 Hz), exchanging information between two IEDs. The format used is C37.94 and one telegram consists of start and stop flags, address, data to be transmitted, Cyclic Redundancy Check (CRC) and Yellow bit (which is associated with C37.94).
Information n x 16 bits
CRC 16 bits
en01000134.vsd
IEC01000134 V1 EN
Figure 379:
The start and stop flags are the 0111 1110 sequence (7E hexadecimal), defined in the HDLC standard. The CRC is designed according to the standard CRC16 definition. The optional address field in the HDLC frame is not used instead a separate addressing is included in the data field. The address field is used for checking that the received message originates from the correct equipment. There is always a risk that multiplexers occasionally mix the messages up. Each terminal in the system is given a number. The terminal is then programmed to accept messages from a specific terminal number. If the CRC function detects a faulty message, the message is thrown away and not used in the evaluation. When the communication is used for line differential purpose, the transmitted data consists of three currents, clock information, trip-, block- and alarm-signals and eight binary signals which can be used for any purpose. The three currents are represented as sampled values. When the communication is used exclusively for binary signals, the full data capacity of the communication channel is used for the binary signal purpose which gives the capacity of 192 signals.
17.1.3
Table 534:
Name ChannelMode
Setting parameters
LDCMRecBinStat1 Non group settings (basic)
Values (Range) Disabled Enabled OutOfService 0 - 255 0 - 255 Slave Master LowPower HighPower Unit Step Default Enabled Description Channel mode of LDCM, 0=OFF, 1=ON, 2=OutOfService Terminal number used for line differential communication Terminal number on remote terminal Com Synchronization mode of LDCM, 0=Slave, 1=Master Transmission power for LDCM, 0=Low, 1=High
1 1 -
0 0 Slave LowPower
Table 535:
Name ChannelMode
NAMECH1 TerminalNo RemoteTermNo NAMECH2 DiffSync GPSSyncErr CommSync NAMECH3 OptoPower NAMECH4 TransmCurr
1 1 1 1 1 1 -
ms ms ms ms ms
5 5 5 5 0.01
Time delay before communication error signal is activated Reset delay before communication error signal is reset Time delay before switching in redundant channel Time delay before switching back from redundant channel Asymmetric delay when communication use echo synch.
Latency between local analogue data and transmitted Analog latency of remote terminal Max allowed transmission delay Compression range
us us -
1 1 -
Maximum time diff for ECHO back-up Deadband for t Diff Invert polarization for X21 communication
Table 536:
Name ChannelMode
NAMECH1 TerminalNo RemoteTermNo NAMECH2 DiffSync GPSSyncErr CommSync NAMECH3 OptoPower NAMECH4 TransmCurr
1 1 1 1 1 1 -
ComFailAlrmDel ComFailResDel
ms ms
5 5
100 100
Time delay before communication error signal is activated Reset delay before communication error signal is reset
us us -
1 1 -
Maximum time diff for ECHO back-up Deadband for t Diff Invert polarization for X21 communication
17.2
17.2.1
Figure 380:
The function blocks are not represented in the Application Configuration tool except for the LDCMTRN function block that is visible in ACT. The signals appear only in the Signal Matrix tool when a LDCM is included in the configuration with the function selector tool.
Section 18
IED hardware
18.1
18.1.1
Overview
Variants of case and local HMI display size
Close
Open
xx04000458_ansi.e
ANSI04000458 V1 EN
Figure 381:
Close
Open
xx05000762_ansi.eps
ANSI05000762 V1 EN
Figure 382:
Close
Open
xx04000460_ansi.e
ANSI04000460 V1 EN
Figure 383:
18.1.2
Table 538:
Module PSM BIM, BOM, SOM, IOM or MIM SLM LDCM, IRIG-B or RS485 LDCM or RS485 OEM LDCM, RS485 or GTM TRM
Rear Positions X11 X31 and X32 etc. to X51 and X52 X301:A, B, C, D X302 X303 X311:A, B, C, D X312, 313 X401
1MRK002801-AC-2-670-1.2-PG V1 EN
Table 539:
Module PSM BIM, BOM, SOM, IOM or MIM SLM LDCM, IRIG-B or RS485 LDCM or RS485 OEM LDCM, RS485 or GTM TRM
Rear Positions X11 X31 and X32 etc. to X101 and X102 X301:A, B, C, D X302 X303 X311:A, B, C, D X312, X313 X401
1MRK002801-AC-3-670-1.2-PG V1 EN
Table 540:
Module PSM BIM, BOM, SOM, IOM or MIM SLM LDCM, IRIG-B or RS485 LDCM or RS485 OEM LDCM, RS485 or GTM TRM 1 TRM 2
Rear Positions X11 X31 and X32 etc. to X71 and X72 X301:A, B, C, D X302 X303 X311:A, B, C, D X312, X313, X322, X323 X401 X411
1MRK002801-AC-4-670-1.2-PG V1 EN
Table 541:
Module PSM BIM, BOM, SOM, IOM or MIM SLM LDCM, IRIG-B or RS485 LDCM or RS485 OEM LDCM,RS485 or GTM TRM
Rear Positions X11 X31 and X32 etc. to X161 and X162 X301:A, B, C, D X302 X303 X311:A, B, C, D X312, X313 X401
1MRK002801-AC-5-670-1.2-PG V1 EN
Table 542:
Module PSM BIM, BOM, SOM, IOM or MIM SLM LDCM, IRIG-B or RS485 LDCM or RS485 OEM LDCM, RS485 or GTM TRM 1 TRM 2
Rear Positions X11 X31 and X32 etc. to X131 and X132 X301:A, B, C, D X302 X303 X311:A, B, C, D X312, X313, X322, X323 X401 X411
1MRK002801-AC-6-670-1.2-PG V1 EN
18.2
18.2.1
Hardware modules
Overview
Table 543:
Module Combined backplane module (CBM)
Basic modules
Description A backplane PCB that carries all internal signals between modules in an IED. Only the TRM (when included) is not connected directly to this board. A backplane PCB that forms part of the IED backplane with connectors for TRM (when included), ADM etc. Including a regulated DC/DC converter that supplies auxiliary voltage to all static circuits. An internal fail alarm output is available.
Module for overall application control. All information is processed or passed through this module, such as configuration, settings and communication. The module consists of LED:s, an LCD, a push button keyboard and an ethernet connector used to connect a PC to the IED. Transformer module that galvanically separates the internal circuits from the VT and CT circuits. It has 12 analog inputs. Slot mounted PCB with A/D conversion.
Table 544:
Module
Binary input module (BIM) Binary output module (BOM) Binary I/O module (IOM) Line data communication modules (LDCM), short range, medium range, long range, X21 Serial SPA/LON/IEC 60870-5-103/DNP3 communication modules (SLM) Optical ethernet module (OEM) mA input module (MIM) IRIG-B Time synchronization module (IRIG-B)
18.2.2
18.2.2.1
18.2.2.2
Functionality
The Compact PCI makes 3.3V or 5V signaling in the backplane possible. The CBM backplane and connected modules are 5V PCI-compatible.
Some pins on the Compact PCI connector are connected to the CAN bus, to be able to communicate with CAN based modules. If a modules self test discovers an error it informs other modules using the Internal Fail signal IRF.
18.2.2.3
Design
There are two basic versions of the CBM: with 3 Compact PCI connectors and a number of euro connectors depending on the IED case size. One Compact PCI connector is used by NUM and two are used by other PCI modules, for example two ADMs in IEDs with two TRMs. See figure 385 with 2 Compact PCI connectors and a number of euro connectors depending on the IED case size. One Compact PCI connector is used by NUM and one is used by for example an ADM in IEDs with one TRM. See figure 384
Each PCI connector consists of 2 compact PCI receptacles. The euro connectors are connected to the CAN bus and used for I/O modules and power supply.
1
IEC05000516 V1 EN
2
en05000516.vsd
Figure 384:
Pos Description 1 2 CAN slots CPCI slots
2 en05000755.vsd
IEC05000755 V1 EN
Figure 385:
Pos Description 1 2 CAN slots CPCI slots
en05000756.vsd
IEC05000756 V1 EN
Figure 386:
Pos Description 1 CBM
18.2.3
18.2.3.1
18.2.3.2
Functionality
The Universal Backplane Module connects the CT and VT analog signals from the transformer input module to the analog digital converter module. The Numerical processing module (NUM) is also connected to the UBM. The ethernet contact on the front panel as well as the internal ethernet contacts are connected to the UBM which provides the signal path to the NUM board.
18.2.3.3
Design
It connects the Transformer input module (TRM) to the Analog digital conversion module (ADM) and the Numerical module (NUM). The UBM exists in 2 versions. for IEDs with two TRM and two ADM. It has four 48 pin euro connectors and one 96 pin euro connector, see figure 388 for IEDs with one TRM and one ADM. It has two 48 pin euro connectors and one 96 pin euro connector, see figure 389.
The 96 pin euro connector is used to connect the NUM board to the backplane. The 48 pin connectors are used to connect the TRM and ADM.
TRM
ADM
NUM
AD Data
X1 X2 X4
X3
Front port
Ethernet
LHMI connection
Ethernet X5
en05000489.vsd
IEC05000489 V1 EN
Figure 387:
en05000757.vsd
IEC05000757 V1 EN
Figure 388:
en05000758.vsd
IEC05000758 V1 EN
Figure 389:
en05000759.vsd
IEC05000759 V1 EN
Figure 390:
Pos Description 1 UBM
18.2.4
18.2.4.1
The NUM, Numeric processing module is a high performance, standard off-the-shelf compact-PCI CPU module. It is 6U high and occupies one slot. Contact with the backplane is via two compact PCI connectors and an euro connector. The NUM has one PMC slot (32-bit IEEE P1386.1 compliant) and two PC-MIP slots onto which mezzanine cards such as SLM or LDCM can be mounted. To reduce bus loading of the compact PCI bus in the backplane the NUM has one internal PCI bus for internal resources and the PMC/PC-MIP slots and external PCI accesses through the backplane are buffered in a PCI/PCI bridge. The application code and configuration data are stored in flash memory using a flash file system. The NUM is equipped with a real time clock. It uses a capacitor for power backup of the real time clock. No forced cooling is used on this standard module because of the low power dissipation.
18.2.4.3
Compact Flash
Logic
Memory
Ethernet
CPU
Figure 391:
18.2.5
18.2.5.1
UBM connector
There are two types of the power supply module. They are designed for different DC input voltage ranges see table 545. The power supply module contains a built-in, selfregulated DC/DC converter that provides full isolation between the terminal and the external battery system.
Block diagram
Input connector
Filter
Power supply
Supervision
99000516.vsd
IEC99000516 V1 EN
Figure 392:
18.2.5.3
Technical data
Table 545:
Quantity Auxiliary dc voltage, EL (input) Power consumption Auxiliary DC power in-rush
18.2.6
Backplane connector
18.2.7
18.2.7.1
18.2.7.2
Design
The transformer module has 12 input transformers. There are several versions of the module, each with a different combination of voltage and current input transformers. Basic versions: 6 current channels and 6 voltage channels 7 current channels and 5 voltage channels 9 current channels and 3 voltage channels 12 current channels 6 current channels
The rated values and channel type, measurement or protection, of the current inputs are selected at order. Transformer input module for measuring should not be used with current transformers intended for protection purposes, due to limitations in overload characteristics. The TRM is connected to the ADM and NUM via the UBM. For configuration of the input and output signals, refer to section "Signal matrix for analog inputs SMAI".
TRM - Energizing quantities, rated values and limits for protection transformer modules
Rated value In = 1 or 5 A (0-100) x In 4 In cont. 100 In for 1 s *) < 150 mVA at In = 5 A < 20 mVA at In = 1 A Vn = 120 V (0340) V 420 V cont. 450 V 10 s < 20 mVA at 110 V fn = 60/50 Hz 5% 0.5288 V Nominal range (0.2-40) In
Table 547:
Quantity Current
TRM - Energizing quantities, rated values and limits for measuring transformer modules
Rated value In = 1 or 5 A 1.1 In cont. 1.8 In for 30 min at In = 1 A 1.6 In for 30 min at In = 5 A < 350 mVA at In = 5 A < 200 mVA at In = 1 A Vn = 120 V (0340) V 420 V cont. 450 V 10 s < 20 mVA at 110 V fn = 60/50 Hz 5% 0.5288 V Nominal range (0-1.8) In at In = 1 A (0-1.6) In at In = 5 A
Permissive overload
Section 18 IED hardware Analog digital conversion module, with time synchronization (ADM)
Introduction
The Analog/Digital module has twelve analog inputs, 2 PC-MIP slots and 1 PMC slot. The PC-MIP slot is used for PC-MIP cards and the PMC slot for PMC cards according to table 548. The OEM card should always be mounted on the ADM board. The UBM connects the ADM to the transformer input module (TRM).
Table 548:
PC-MIP cards LDCM LR-LDCM MR-LDCM X21-LDCM IRIG-B RS485
18.2.8
18.2.8.1
18.2.8.2
Design
The Analog digital conversion module input signals are voltage and current from the transformer module. Shunts are used to adapt the current signals to the electronic voltage level. To gain dynamic range for the current inputs, two shunts with separate A \D channels are used for each input current. In this way a 20 bit dynamic range is obtained with a 16 bit A\D converter. Input signals are sampled with a sampling freqency of 5 kHz at 50 Hz system frequency and 6 kHz at 60 Hz system frequency. The A\D converted signals goes through a filter with a cut off frequency of 500 Hz and are reported to the numerical module (NUM) with 1 kHz at 50 Hz system frequency and 1,2 kHz at 60 Hz system frequency.
AD1 AD2
1.2v
AD3 AD4
Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 Channel 9 Channel 10 Channel 11 Channel 12
PMC
level shift
PC-MIP
2.5v
en05000474.vsd
IEC05000474 V1 EN
Figure 393:
18.2.9
18.2.9.1
18.2.9.2
Design
The Binary input module contains 16 optical isolated binary inputs. The voltage level of the binary input is selected at order. For configuration of the input signals, refer to section "Signal matrix for binary inputs SMBI". A signal discriminator detects and blocks oscillating signals. When blocked, a hysteresis function may be set to release the input at a chosen frequency, making it possible to use the input for pulse counting. The blocking frequency may also be set. Well defined input high and input low voltages ensure normal operation at battery supply earth faults, see figure 394 The figure shows the typical operating characteristics of the binary inputs of the four voltage levels. The standard version of binary inputs gives an improved capability to withstand disturbances and should generally be used when pulse counting is not required. Inputs are debounced by software. I/O events are time stamped locally on each module for minimum time deviance and stored by the event recorder if present.
[V] 300
Figure 394:
Operation uncertain
No operation
IEC99000517-ABC V1 EN
This binary input module communicates with the Numerical module (NUM) via the CAN-bus on the backplane. The design of all binary inputs enables the burn off of the oxide of the relay contact connected to the input, despite the low, steady-state power consumption, which is shown in figure 395 and 396.
[mA] 50
55
[ms]
en07000104-3.vsd
IEC07000104 V3 EN
Figure 395:
[mA] 50
Approximate binary input inrush current for the standard version of BIM.
5.5
[ms]
en07000105-1.vsd
IEC07000105 V2 EN
Figure 396:
Approximate binary input inrush current for the BIM version with enhanced pulse counting capabilities.
Process connector
Opto isolated input Opto isolated input Opto isolated input Opto isolated input Opto isolated input Opto isolated input Opto isolated input Opto isolated input Opto isolated input
Microcontroller
Process connector
Opto isolated input Opto isolated input Opto isolated input Opto isolated input
99000503-2.vsd
IEC99000503 V2 EN
Figure 397:
Backplane connector
18.2.9.3
Power consumption 24/30 V 48/60 V 125 V 220/250 V Counter input frequency Oscillating signal discriminator
Table 550:
Quantity Binary inputs DC voltage, RL
Power consumption 24/30 V 48/60 V 125 V 220/250 V Counter input frequency Balanced counter input frequency Oscillating signal discriminator
18.2.10
18.2.10.1
The binary output module (BOM) has 24 software supervised output relays. Each pair of relays have a common power source input to the contacts, see figure 398. This should be considered when connecting the wiring to the connection terminal on the back of the IED. The high closing and carrying current capability allows connection directly to breaker trip and closing coils. If breaking capability is required to manage fail of the breaker auxiliary contacts normally breaking the trip coil current, a parallel reinforcement is required. For configuration of the output signals, refer to section "Signal matrix for binary outputs SMBO".
Output module
3
ANSI_xx00000299.vsd
ANSI00000299 V1 EN
Figure 398:
1 Output connection from relay 1 2 Output signal power source connection 3 Output connection from relay 2
Relay
Relay
Relay
Relay
Process connector
Relay Relay Relay Relay Relay Relay Relay Relay Relay Relay Relay Relay Relay Relay Relay Relay Relay Relay Relay
Relay
Microcontroller
99000505-2-en.vsd
IEC99000505 V2 EN
Figure 399:
18.2.10.3
Technical data
Table 551:
Binary outputs Max system voltage Test voltage across open contact, 1 min Current carrying capacity Per relay, continuous Per relay, 1 s Per process connector pin, continuous Table continues on next page
BOM - Binary output module contact data (reference standard: IEC 61810-2)
Trip and Signal relays 24 250 V AC, DC 1000 V rms 8A 10 A 12 A
Function or quantity
Backplane connector
Process connector
CAN
Trip and Signal relays 30 A 10 A 250 V/8.0 A 48 V/1 A 110 V/0.4 A 125 V/0.35 A 220 V/0.2 A 250 V/0.15 A
18.2.11
18.2.11.1
18.2.11.2
Design
The binary input/output module is available in two basic versions, one with unprotected contacts and one with MOV (Metal Oxide Varistor) protected contacts. Inputs are designed to allow oxide burn-off from connected contacts, and increase the disturbance immunity during normal protection operate times. This is achieved with a high peak inrush current while having a low steady-state current, see figure 395. Inputs are debounced by software. Well defined input high and input low voltages ensures normal operation at battery supply ground faults, see figure 394. The voltage level of the inputs is selected when ordering. I/O events are time stamped locally on each module for minimum time deviance and stored by the event recorder if present. The binary I/O module, IOM, has eight optically isolated inputs and ten output relays. One of the outputs has a change-over contact. The nine remaining output contacts are connected in two groups. One group has five contacts with a common and the other group has four contacts with a common, to be used as single-output channels, see figure 400.
The binary I/O module also has two high speed output channels where a reed relay is connected in parallel to the standard output relay. For configuration of the input and output signals, refer to sections "Signal matrix for binary inputs SMBI" and "Signal matrix for binary outputs SMBO". The making capacity of the reed relays are limited.
IEC1MRK002801-AA11-UTAN-RAM V1 EN
IEC1MRK002802-AA-13 V1 EN
Figure 400:
Binary in/out module (IOM), input contacts named XA corresponds to rear position X31, X41, and so on, and output contacts named XB to rear position X32, X42, and so on
The binary input/output module version with MOV protected contacts can for example be used in applications where breaking high inductive load would cause excessive wear of the contacts.
The test voltage across open contact is lower for this version of the binary input/output module.
xx04000069.vsd
IEC04000069 V1 EN
Figure 401:
18.2.11.3
Technical data
Table 552:
Quantity Binary inputs DC voltage, RL
Table 553:
IOM - Binary input/output module contact data (reference standard: IEC 61810-2)
Trip and signal relays 10 250 V AC, DC 1000 V rms 8A 10 A 12 A Fast signal relays (parallel reed relay) 2 250 V DC 800 V DC 8A 10 A 12 A
Function or quantity Binary outputs Max system voltage Test voltage across open contact, 1 min Current carrying capacity Per relay, continuous Per relay, 1 s Per process connector pin, continuous Table continues on next page
220250 V/0,4 A 110125 V/0,4 A 4860 V/0.2 A 2430 V/0.1 A 250 V/8.0 A 48 V/1 A 110 V/0.4 A 125 V/0.35 A 220 V/0.2 A 250 V/0.15 A 10 nF
Table 554:
Function or quantity Binary outputs Max system voltage Test voltage across open contact, 1 min Current carrying capacity Per relay, continuous Per relay, 1 s Per process connector pin, continuous Making capacity at inductive loadwith L/R>10 ms 0.2 s 1.0 s Making capacity at resistive load 0.2 s 1.0 s Breaking capacity for AC, cos j>0.4 Breaking capacity for DC with L/ R < 40 ms
8A 10 A 12 A
8A 10 A 12 A
30 A 10 A
0.4 A 0.4 A 220250 V/0,4 A 110125 V/0,4 A 4860 V/0.2 A 2430 V/0.1 A 250 V/8.0 A 48 V/1 A 110 V/0.4 A 220 V/0.2 A 250 V/0.15 A 10 nF
18.2.12
18.2.12.1
18.2.12.2
Design
The Milliampere Input Module has six independent analog channels with separated protection, filtering, reference, A/D-conversion and optical isolation for each input making them galvanically isolated from each other and from the rest of the module. For configuration of the input signals, refer to section "Signal matrix for mA inputs SMMI". The analog inputs measure DC current in the range of +/- 20 mA. The A/D converter has a digital filter with selectable filter frequency. All inputs are calibrated separately The filter parameters and the calibration factors are stored in a non-volatile memory on the module. The calibration circuitry monitors the module temperature and starts an automatical calibration procedure if the temperature drift is outside the allowed range. The module communicates, like the other I/O-modules on the serial CAN-bus.
Process connector
Optoisolation DC/DC
Optoisolation DC/DC
Optoisolation DC/DC
Memory
Microcontroller
99000504.vsd
IEC99000504 V1 EN
Figure 402:
18.2.12.3
Technical data
Table 555:
Quantity: Input resistance Input range Power consumption each mA-board each mA input
Backplane connector
CAN
18.2.13
18.2.13.1
18.2.13.2
Design
The SLM is a PMC card and it is factory mounted as a mezzanine card on the NUM module. Three variants of the SLM is available with different combinations of optical fiber connectors, see figure 403. The plastic fiber connectors are of snap-in type and the glass fiber connectors are of ST type.
IEC05000760 V1 EN
Figure 403:
A B 1 2
IEC05000761 V1 EN
Figure 404:
1 2 3 4
Observe that when the SLM connectors are viewed from the rear side of the IED, contact 4 above is in the uppermost position and contact 1 in the lowest position.
18.2.13.3
Technical data
Table 556:
Quantity Optical connector Fiber, optical budget Fiber diameter
Table 557:
Quantity Optical connector
18.2.14
18.2.14.1
18.2.14.2
Functionality
The Optical Ethernet module (OEM) is used when communication systems according to IEC6185081 have been implemented.
18.2.14.3
Design
The Optical Ethernet module (OEM) is a PMC card and mounted as a mezzanine card on the ADM. The OEM is a 100base Fx module and available as a single channel or double channel unit.
PCI - bus Connector EEPROM Ethernet Controller 100Base-FX Receiver PCI - PCI Bridge 100Base-FX Transmitter
en04000472.vsd
IEC04000472 V1 EN
Figure 405:
ID chip
LED
25MHz oscillator
Ethernet cont.
Transmitter
Receiver
Ethernet cont.
Transmitter
25MHz oscillator
en05000472.vsd
IEC05000472 V1 EN
Figure 406:
18.2.14.4
Technical data
Table 558:
Quantity Number of channels Standard Type of fiber Wave length Optical connector Communication speed
18.2.15
18.2.15.1
PCI bus
LED
IO bus
Receiver
Each module has one optical port, one for each remote end to which the IED communicates. Alternative cards for Medium range (1310 nm single mode) and Short range (850 nm multi mode) are available. Class 1 laser product. Take adequate measures to protect the eyes. Never look into the laser beam.
18.2.15.2
Design
The LDCM is a PCMIP type II single width format module. The LDCM can be mounted on: the ADM the NUM
ID
ST
IO-connector
ST
32,768 MHz
16.000 MHz
en07000087.vsd
IEC07000087 V1 EN
Figure 407:
The SR-LDCM layout. PCMIP type II single width format with two PCI connectors and one I/O ST type connector
X1
ADN 2841 2.5V ID
DS 3904
DS 3904
PCI9054 TQ176
MAX 3645
3 2
en06000393.vsd
IEC06000393 V1 EN
Figure 408:
The MR-LDCM and LR-LDCM layout. PCMIP type II single width format with two PCI connectors and one I/O FC/PC type connector
18.2.15.3
Technical data
Table 559:
Characteristic Type of LDCM Type of fiber
Wave length Optical budget Graded-index multimode 62.5/125 mm, Graded-index multimode 50/125 mm
Medium range (MR) 2 Mb/s / 64 kbit/s Internal or derived from received signal
Long range (LR) 2 Mb/s / 64 kbit/s Internal or derived from received signal
*) depending on optical budget calculation **) C37.94 originally defined just for multimode; using same header, configuration and data format as C37.94
18.2.16
18.2.16.1
GPS antenna
Introduction
In order to receive GPS signals from the satellites orbiting the earth a GPS antenna with applicable cable must be used.
18.2.16.2
Design
The antenna with a console for mounting on a horizontal or vertical flat surface or on an antenna mast. See figure 409
2 3
xx04000155.vsd
IEC04000155 V2 EN
Figure 409:
where: 1 2 3 4 5 6 7 GPS antenna TNC connector Console, (2'6.7"x4'11') Mounting holes about 1/5" Tab for securing of antenna cable Vertical mounting position Horizontal mounting position
Antenna cable Use a 50 ohm coaxial cable with a male TNC connector in the antenna end and a male SMA connector in the receiver end to connect the antenna to GTM. Choose cable type and length so that the total attenuation is max. 26 dB at 1.6 GHz. Make sure that the antenna cable is not charged when connected to the antenna or to the receiver. Short-circuit the end of the antenna cable with some metal device, when first connected to the antenna. When the antenna is connected to the cable, connect the cable to the receiver. REx670 must be switched off when the antenna cable is connected.
18.2.16.3
Technical data
Table 560:
Function Max antenna cable attenuation Antenna cable impedance Lightning protection Antenna cable connector Accuracy
18.2.17
18.2.17.1
Electrical (BNC) and optical connection (ST) for 0XX and 12X IRIG-B support.
18.2.17.2
Design
The IRIG-B module have two inputs. One input is for the IRIG-B that can handle both a pulse-width modulated signal (also called unmodulated) and an amplitude modulated signal (also called sine wave modulated). The other is an optical input type ST for PPS to synchronize the time between several protections.
32 MHz FPGA OPTO_INPUT PCI-bus PCI-Controller
Registers
PCI-con
4 mm barrier
ZXING
IO-con
en06000303.vsd
IEC06000303 V1 EN
Figure 410:
BNCconnector
IRIGDecoder
IRIG_INPUT
STconnector
PCI-con
A1
C C
Y2
3 2
en06000304.vsd
IEC06000304 V1 EN
Figure 411:
IRIG-B PC-MIP board with top left ST connector for PPS 820 nm multimode fibre optic signal input and lower left BNC connector for IRIGB signal input
18.2.17.3
Technical data
Table 561:
Quantity Number of channels IRIG-B Number of channels PPS Electrical connector: Electrical connector IRIG-B Pulse-width modulated Amplitude modulated low level high level Supported formats Accuracy Input impedance Optical connector: Optical connector PPS and IRIG-B Type of fibre Supported formats Accuracy Type ST 62.5/125 m multimode fibre IRIG-B 00x, PPS +/- 2s BNC 5 Vpp 1-3 Vpp 3 x low level, max 9 Vpp IRIG-B 00x, IRIG-B 12x +/-10s for IRIG-B 00x and +/-100s for IRIG-B 12x 100 k ohm
IRIG-B
Rated value 1 1
ST
DC//DC
A1
O O
18.3
18.3.1
Dimensions
Case without rear cover
A D
B
IEC08000164 V1 EN
C
xx08000164.vsd
Figure 412:
K F
G H
J
xx08000166.vsd
IEC08000166 V1 EN
Figure 413:
Case size (inches) 6U, 1/2 x 19 6U, 3/4 x 19 6U, 1/1 x 19 A 10.47 10.47 10.47 B 8.81 13.23 17.65 C 7.92 7.92 7.92 D 9.96 9.96 9.96
18.3.2
C
xx08000163.vsd
IEC08000163 V1 EN
Figure 414:
K F
G H
J
xx08000165.vsd
IEC08000165 V1 EN
Figure 415:
xx05000503.vsd
IEC05000503 V1 EN
Figure 416:
18.3.3
A B
E D
xx08000162.vsd
IEC08000162 V1 EN
Figure 417:
Flush mounting
Cut-out dimensions (inches) A +/0.04 8.27 12.69 17.11 B +/0.04 10.01 10.01 10.01 C 0.160.39 0.160.39 0.160.39 D 0.49 0.49 0.49
E = 188.6 mm without rear protection cover, 229.6 mm with rear protection cover
18.3.4
xx06000182.vsd
IEC06000182 V1 EN
Figure 418:
A
G
C
xx05000505.vsd
IEC05000505 V1 EN
Figure 419:
Case size (inches) Tolerance 6U, 1/2 x 19 6U, 3/4 x 19 6U, 1/1 x 19
A B E
en04000471.vsd
IEC04000471 V1 EN
Figure 420:
Wall mounting
18.3.6
standard enclose the plate with resistors with a protective cover or in a separate box!
[1.48] [6.97] [4.02]
[0.33]
[18.31] [18.98]
[0.79]
[7.68]
Dimension mm [inches]
xx06000232.eps
IEC06000232 V2 EN
Figure 421:
[10.47]
[7.50]
[1.50]
[0.33]
[18.31] [18.98]
[0.79]
[7.68]
[inches]
en06000234.eps
IEC06000234 V2 EN
Figure 422:
89 [3.5] 57 [2.24]
Dimension
mm [inches]
xx06000233.vsd
IEC06000233 V1 EN
Figure 423:
18.4
18.4.1
18.4.1.1
Mounting alternatives
Flush mounting
Overview
The flush mounting kit are utilized for case sizes: 1/2 x 19 3/4 x 19 1/1 x 19 1/4 x 19 (RHGS6 6U)
Only a single case can be mounted in each cut-out on the cubicle panel, for class IP54 protection. Flush mounting cannot be used for side-by-side mounted IEDs when IP54 class must be fulfilled. Only IP20 class can be obtained when mounting two cases side-by-side in one (1) cut-out.
To obtain IP54 class protection, an additional factory mounted sealing must be ordered when ordering the IED.
18.4.1.2
5 2
6 3
xx08000161.vsd
IEC08000161 V1 EN
Figure 424:
PosNo Description 1 2 3 4 5 6 Sealing strip, used to obtain IP54 class. The sealing strip is factory mounted between the case and front plate. Fastener Groove Screw, self tapping Joining point of sealing strip Panel
When mounting the mounting angles, be sure to use screws that follows the recommended dimensions. Using screws with other dimensions than the original may damage the PCBs inside the IED.
18.4.2.2
1b
xx08000160.vsd
IEC08000160 V1 EN
Figure 425:
Pos 1a, 1b 2
Wall mounting
Overview
All case sizes, 1/2 x 19, 3/4 x 19,1/1 x 19, can be wall mounted. It is also possible to mount the IED on a panel or in a cubicle. When mounting the side plates, be sure to use screws that follows the recommended dimensions. Using screws with other dimensions than the original may damage the PCBs inside the IED.
If fiber cables are bent too much, the signal can be weakened. Wall mounting is therefore not recommended for communication modules with fiber connection; Serial SPA/IEC 60870-5-103, DNP3 and LON communication module (SLM),Optical Ethernet module (OEM) and Line data communication module (LDCM).
18.4.3.2
5 6
DOCUMENT127716-IMG2265 V1 EN
xx04000453.vs d
Figure 426:
PosNo 1 2 3 4 5 6
Quantity 4 8 4 2 6 2
18.4.3.3
ANSI_en06000135.vsd
ANSI06000135 V1 EN
Figure 427:
PosNo 1 2 3
18.4.4.2
xx04000456.vsd
IEC04000456 V1 EN
Figure 428:
PosNo 1 2, 3 4
18.4.4.3
xx06000180.vsd
IEC06000180 V1 EN
Figure 429:
IED in the 670 series (1/2 x 19) mounted with a RHGS6 case containing a test switch module equipped with only a test switch and a RX2 terminal base
18.4.5
18.4.5.1
When mounting the plates and the angles on the IED, be sure to use screws that follows the recommended dimensions. Using screws with other dimensions than the original may damage the PCBs inside the IED.
Please contact factory for special add on plates for mounting FT switches on the side (for 1/2 19" case) or bottom of the relay.
18.4.5.2
3 4
xx06000181.vsd
IEC06000181 V1 EN
Figure 430:
PosNo 1 2, 3 4
18.5
18.5.1
Technical data
Enclosure
Table 562:
Material Front plate Surface treatment Finish
Case
Steel sheet Steel sheet profile with cut-out for HMI Aluzink preplated steel Light grey (RAL 7035)
Table 563:
Front
Table 564:
Case size 6U, 1/2 x 19 6U, 3/4 x 19 6U, 1/1 x 19
Weight
Weight 22 lb 33 lb 40 lb
18.5.2
Connection system
Table 565:
Connector type Screw compression type Terminal blocks suitable for ring lug terminals
Table 566:
Connector type
Screw compression type Terminal blocks suitable for ring lug terminals
Because of limitations of space, when ring lug terminal is ordered for Binary I/O connections, one blank slot is necessary between two adjacent IO cards. Please refer to the ordering particulars for details.
18.5.3
Influencing factors
Table 567:
Parameter Ambient temperature, operate value Relative humidity Operative range Storage temperature
Table 568:
Dependence on
Ripple, in DC auxiliary voltage Operative range Auxiliary voltage dependence, operate value Interrupted auxiliary DC voltage Interruption interval 050 ms 0 s Restart time
Table 569:
Dependence on
Frequency dependence, operate value Harmonic frequency dependence (20% content) Harmonic frequency dependence for high impedance differential protection (10% content)
18.5.4
Electromagnetic compatibility
Type test values 2.5 kV 2.5 kV 2-4 kV 2.5 kV, oscillatory 4.0 kV, fast transient 15 kV air discharge 8 kV contact discharge 8 kV contact discharge 15 kV air discharge 8 kV contact discharge 8 kV contact discharge 4 kV 1-2 kV, 1.2/50 ms high energy 150-300 V 15 Hz-150 kHz 1000 A/m, 3 s 100 A/m, cont. 100 A/m 20 V/m, 80-1000 MHz 1.4-2.7 GHz 35 V/m 26-1000 MHz 10 V, 0.15-80 MHz 30-1000 MHz 0.15-30 MHz IEEE/ANSI C37.90.2 IEC 60255-22-6 IEC 60255-25 IEC 60255-25 Reference standards IEC 60255-22-1 IEC 61000-4-18, Class III IEC 61000-4-12, Class IV IEEE/ANSI C37.90.1 IEC 60255-22-2, Class IV IEC 61000-4-2, Class IV IEEE/ANSI C37.90.1
IEC 60255-22-4, Class A IEC 60255-22-5 IEC 60255-22-7, Class A IEC 61000-4-16, Class IV IEC 61000-4-8, Class V IEC 61000-4-10, Class V IEC 60255-22-3
Table 571:
Test Dielectric test
Insulation
Type test values 2.0 kV AC, 1 min. 5 kV, 1.2/50 ms, 0.5 J >100 MW at 500 VDC Reference standard ANSI C37.90
Table 572:
Test Cold test Storage test Dry heat test
Environmental tests
Type test value Test Ad for 16 h at -25C Test Ad for 16 h at -40C Test Bd for 16 h at +70C Test Ca for 4 days at +40 C and humidity 93% Test Db for 6 cycles at +25 to +55 C and humidity 93 to 95% (1 cycle = 24 hours) Reference standard IEC 60068-2-1 IEC 60068-2-1 IEC 60068-2-2 IEC 60068-2-78 IEC 60068-2-30
Table 573:
Test Immunity Emissivity
CE compliance
According to EN 50263 EN 50263 EN 50178
Table 574:
Test
Mechanical tests
Type test values Class II Class I Class II Class I Class I Class II Reference standards IEC 60255-21-1 IEC 60255-21-1 IEC 60255-21-2 IEC 60255-21-2 IEC 60255-21-2 IEC 60255-21-3
Vibration response test Vibration endurance test Shock response test Shock withstand test Bump test Seismic test
Section 19
This chapter describes the hardware equipment used for sensitive rotor earth fault protection and 100% stator earth fault protection by injection. The descriptions includes diagrams from different elevations indicating the location of connection terminals and modules as well as dimensions and drilling plan.
19.1
19.1.1
19.1.1.1
Overview
Front view of injection unit, coupling capacitor and shunt resitor unit
Injection unit REX060
The injection unit REX060 is used to inject voltage and current signals to the generator or motor stator and rotor circuits. REX060 generates two square wave signals with different frequencies for injection into the stator and rotor circuits respectively. The response from the injected voltage and currents are then measured by the REX060 unit and amplified to a level suitable for the analog voltage inputs of IED. For local operation, the REX060 unit is provided with a control panel on the front. Local operation shall only be performed according to the operation regulations set up by the relevant operation authority of the plant.
IEC11000053-1-en.vsd
IEC11000053 V1 EN
Figure 431:
Table 575:
Key
The Key-lock button enables/disables the keypad. Hold the Key-lock button for a period of 1.2 s to 4 s to lock or unlock the keys. A key-lock LED indicates when the keypad is unlocked. Moves the cursor in the direction of the arrows With the cursor is in value change state, pressing the up button increases the value and pressing the down button decreases the value.
Pressing the clear button cancels changes that have not been stored.
Pressing the enter button stores the changed value. If the value is outside range, the limit value is stored.
X1
X2
IEC11000019-2-en.vsd
IEC11000019 V1 EN
Figure 432:
IEC11000037-1-en.vsd
IEC11000037 V1 EN
Figure 433:
REX061 shall be mounted close to the generator in order to limit the exposure of the field circuit. Alternatively it can be located in the excitation cubicle.
19.1.1.4
X1
IEC11000038-1-en.vsd
IEC11000038 V1 EN
Figure 434:
IEC11000039-1-en.vsd
IEC11000039 V1 EN
Figure 435:
REX062 shall be mounted close to the IED. It is recommended that REX060 and REX062 are mounted in the same cubicle as the IED.
19.1.2
19.1.2.1
Top view
Front view
1 5
X81
Stator Injection
Rotor Injection
Power Supply
18
X62
18
1 5
X82
Power
Stator
Rotor
Injection switch
Figure 436:
19.2
19.2.1
19.2.2
Design
REX060 consists of a standard enclosure (6U, 1/2 x 19"). In this enclosure, the modules for stator (SIM) and/or rotor (RIM) earth fault protection are installed. The stator injection transformer is also installed inside the enclosure.
On the front of the enclosure there is a backlit LCD, control buttons and a key switch. In figure 437 below the content of display is shown for a REX060 with one SIM and one RIM module. Row 1 contains mains frequency information. Row 2-3 contains stator information and row 4-5 rotor. Column 1 (empty) gives status, column 2 and 3 are informative and column 4 contains variables, settable by the keypad.
Column 1 Row 1 2 3 4 5
IEC10000334 V1 EN
IEC10000334-1-en.vsd
Figure 437:
When the injection unit REX060 is energized, the ABB logotype is shown followed by current REX060 revision status. When the start up sequence is completed, the main menu (normal display content) is shown. The duration of the start up sequence is a few seconds. LCD backlight is active during a period of 30 seconds after pressing any button. Backlight activation by pressing a button will not cause any normal button action. Column 1 is a status column (empty in the above picture), where the following symbols are displayed when applicable:
Table 576:
Status symbol
IEC10000329 V1 EN
IEC10000330 V1 EN
2 Over voltage blocked status overrides displaying of this status 3 Injection switch and over voltage blocked overrides displaying of this status Not applicable
Injection blocked by binary input. Blocked injection will be shown in the status column (column 1) depending on binary in status. This can occur on both X61/62 then shown in row 2 and X81/82 then shown in row 4 (Stator & Rotor) simultaneously or on ether of them.
IEC10000332 V1 EN
Analog output saturation. This status is set when the analog signal, current and or voltage, to REG670 IED is too high and may thereby be incorrect due to saturation in amplifier stage. Saturation status will be shown in the status column (column 1) in row 3 or 5 depending on the saturation occurrence
Overvoltage reset Stator module (SIM) and rotor module (RIM) injection outputs are protected against voltages exceeding maximum operating range (10% of rated VT/DT for the stator and 75 % of max voltage during gain dependent time for the rotor) by a relay blocking the injection circuit. This blocking is controlled by measuring the sense voltage, and remains blocked by stored status in non-volatile memory. Injection block is released by performing the following sequence: 1. 2. 3. Power off the REX060 Simultaneous press the C and key buttons Power on the REX060 and wait until status indication Over-voltage is removed from display
Stator and rotor overvoltage protection of injection circuit Both rotor and stator have two levels of protection, injection circuit interruption controlled by the voltage sense input and a fuse for over-current protection. The voltage controlled interruption, overvoltage, will normally occur prior to interruption by fuse and the reset sequence is described above. A blown fuse requires module disassembling to replace the fuse (F 4 A 250 V for stator and F 160 mA 250 V for rotor). However, if this occurs it is recommended to identify the reason for the over954 Technical reference manual
current and take necessary actions to reduce the current before restarting the unit. The problem must be outside the injection unit since this unit cannot provide enough energy to blow the fuse. Saturation When the voltage or current amplifiers in an injection module saturates due to high voltage level, it is indicated with a warning symbol in the status column in the REX060 display . Besides this a binary out for the specific module is set active to indicate to the IED that the signal may not be reliable due to saturation and could cause incorrect measurements. Binary in The injection can be blocked by application in the IED. For this purpose, two binary inputs to the REX060 exist: BLOCK on X61 terminal 1, 2 or 3: Prohibits injection on the injection unit inserted in X62 BLOCK on X81 terminal 1, 2 or 3: Prohibits injection on the injection unit inserted in X82
The used terminal is depending on actual binary voltage, pin 1 for 220 V, 2 for 110 V, 3 for 48 V and 4 for return (common). Binary out The following binary outputs exist on the REX060: INJ_BLOCKED_NC on X61 terminal 5: Indicates to the IED that the injection on X62 is blocked. The reason for blocking is indicated in the REX060 LCD. SAT_NO on X61 pin 6: Indicates to the IED that there is a risk of saturated amplifier on voltage and/or current output at X61, indication is also given in the REX060 LCD. COMMON on X61 terminal 7: Common return for X61 terminal 5 and 6 INJ_BLOCKED_NC on X81 pin 5: Indicates to the IED that the injection on X82 is blocked. The reason for blocking is indicated in the REX060 LCD. SAT_NO on X81 pin 6: Indicates to the IED that there is a risk of saturated amplifier on voltage and/or current output at X81, indication is also given in the REX060 LCD. COMMON on X81 terminal 7: Common return for X81 terminal 5 and 6
Power status X11 terminal 3: Fail, power off NC X11 terminal 1: Ready, power off NO X11 terminal 2: Common
19.3
19.3.1
19.3.2
Design
Measure points are added to the capacitor box that enables the measuring of rotor voltages without any connection to a hazardous voltage, by the use of protective impedance. This enables the usage of standard oscilloscope or handheld DVM. The measure ports cause an additional rotor impedance of 20 M per terminal to ground. However, the rotor calibration procedure extracts this impedance.
RotorMeasuring point PE
IEC11000040-3-en.vsd
IEC11000040 V1 EN
Figure 438:
19.4
19.4.1
19.4.2
Design
REX062 for stator protection is used when either injection via a grounding transformer (i.e. not via a VT) is used or when maximum voltage posed on injection equipment by the generator is bigger than 120V.
IEC11000041-2-en.vsd
IEC11000041 V1 EN
Figure 439:
REX062 input protection REX062 limits overvoltage by a varistor at the injection output to stator. Normally , REX060 will interrupt the injection circuit in case of excessive over-current in the injection chain. Fuse within REX062 is an additional protection in case of failure within REX062 during over-voltage condition. A blown REX062 fuse requires a module disassembling to replace the fuse (F 6.3 A 250 V). However, if this occurs it is recommended to identify the reason for the overcurrent and do needed actions to reduce the current.
REX060 Injection unit Power Supply Module Exciter source X1:1 ; Rotor + REX061 Coupling Capacitor unit REG670 X11:4 X11:5 Ready; X11:1 Common; X11:2 Fail; X11:3 X82:1 ; InjA X82:3 ; InjA X82:4 ; InjB X82:5 ; InjB X82:2 ; InjShB X81:16; IA sense X81:14; IA sense X81:15; IB sense X81:12; VA sense X81:13; VB sense Rotor Module ( RIM) Block 220V ; X81:1 Block 110V ; X81:2 Block48V ; X81:3 Block Common ; X81:4 IA Out; X81:10 IB Out; X81:11 UA Out; X81:8 UB Out; X81:9 Blocked; X81:5 Saturation; X81:6 Common; X81:7 X62:1 ; InjExtA X62:3 ; InjA X62:4 ; InjB X62:5 ; InjB X62:2 ; InjExtB X61:14 ; IA sense X61:15 ; IB sense X61:12 ; VA sense X61:13 ; VB sense Stator Module ( SIM) Block 220V ; X61:1 Block 110V ; X61:2 Block48V ; X61:3 Block Common ; X61:4 IA Out; X61:10 IB Out; X61:11 VA Out; X61:8 VB Out; X61:9 Blocked; X61:5 Saturation; X61:6 Common; X61:7 BI BI RL+ + EL BI RL+ (BI)
Rotor
Injection; X1:9 Ground; X1:10 X1:7 ; RotorPE
BO RL-
REX062 Shunt Resistor unit X1:2 ; Injection A External A; X1:9 External B; X1:10 I sense A; X1:6 PE I sense B; X1:8
Stator
R Distribution Transformer
X1:4 ; Injection B
BO RL-
PE
ANSI11000017-1-en.vsd
ANSI11000017 V1 EN
Figure 440:
19.5
19.5.1
Technical data
Hardware
Table 577:
Specifications Case size Weight Firmware
Table 578:
Function
For machines with: rated field voltage up to static exciter with rated supply voltage up to
Values 8.58 x 5.91 x 9.57 inches (W x D x H) 10.58 lbs 6 x 0.20 inch screws (3 at bottom and 3 at top)
Table 579:
Specifications Case size Weight Assembling
Table 580:
Description
Degree of protection
Values IP40 IP54 IP20 IP41 IP20
REX060 Front side Panel mounted, front Rear side, connection terminals REX061 and REX062 Front and side Bottom side
IEC 60255-22-4, Class A IEC 60255-22-5 IEC 60255-22-7, Class A IEC 61000-4-8 IEC 60255-22-3 IEEE/ANSI C37.90.2 IEC 60255-22-6 IEC 60255-11
Table 582:
Test Dielectric test
Table 583:
Test Dielectric test
12.0 kV, 1.2/50 s, 0.5 J (connections to rotor) 5.0 kV, 1.2/50 s, 0.5 J
Insulation resistance
>100 M at 500V DC
Table 584:
Test
Mechanical tests
Reference standards IEC 60255-21-1 IEC 60255-21-1 Requirements Class 2 Class 1 Class 2 Class 2 Class 1 Class 2 Class 1 Class 2 Class 2 Class 2 extended
Vibration response test Vibration endurance test REG670 and REX060 REX061 and REX062 Shock response test Shock withstand test REG670 and REX060 REX061 and REX062 Bump test REG670 and REX060 REX061 and REX062 Seismic test REG670 and REX060 REX061 and REX062
IEC 60255-21-2
IEC 60255-21-3
Table 585:
Test Cold test operation storage Dry heat test operation storage Damp heat test steady state cyclic
Environmental tests
Type test value 16 h at -25C 16 h at -40C 16 h at +70C 16 h at +85C 240 h at +40C humidity 93% 6 cycles at +25 to +55C humidity 93-95% Reference standard IEC 60068-2-1
IEC 60068-2-2
Table 587:
Test
Temperature influence
Type test values -25 C to +55C -40 C to +85C Influence 0.01% /C -
Section 20 Labels
Section 20
Labels
20.1
Labels on IED
Front view of IED
1 2 3 4 5 6 6 7
xx06000574.ep
IEC06000574 V1 EN
Section 20 Labels
1 2 3 4 5 6
Product type, description and serial number Order number, dc supply voltage and rated frequency Optional, customer specific information Manufacturer Transformer input module, rated currents and voltages Transformer designations
IEC06000577-CUSTOMER-SPECIFIC V1 EN
7
IEC06000576-POS-NO V1 EN
Section 20 Labels
Rear view of IED
1 2 3
4
en06000573.ep
IEC06000573 V1 EN
1 2 3
IEC06000575 V1 EN
Warning label
Section 20 Labels
20.2
IEC11000226 V1 EN
1a
1a 1b
Product type, description and serial number Order number and dc supply voltage Stator and rotor input module designations Manufacturer
1b 1c
1c
1d
1d
IEC11000233-1-en.vsd
IEC11000233 V1 EN
Section 20 Labels
2
IEC11000234-1-en.vsd
IEC11000234 V1 EN
IEC11000227 V1 EN
1 2 3 4
Section 20 Labels
Front view of coupling capacitor unit REX061
IEC11000229 V1 EN
1 2
IEC11000228 V1 EN
1 2 3 4
Section 20 Labels
Front view of shunt resistor unit REX062
IEC11000231 V1 EN
1 2
IEC11000230 V1 EN
1 2 3 4
970
Section 21
Connection diagrams
This chapter includes diagrams of the IED with all slot, terminal block and optical connector designations. It is a necessary guide when making electrical and optical connections to the IED.
1MRK002802-AB-1-670-1.2-PG-ANSI V1 EN
1MRK002802-AB-2-670-1.2-PG-ANSI V1 EN
1MRK002802-AB-3-670-1.2-PG-ANSI V1 EN
1MRK002802-AB-4-670-1.2-PG-ANSI V1 EN
1MRK002802-AB-5-670-1.2-ANSI V1 EN
1MRK002802-AB-6-670-1.2-ANSI V1 EN
1MRK002802-AB-7-670-1.2-ANSI V1 EN
1MRK002802-AB-8-670-1.2-ANSI V1 EN
1MRK002802-AB-9-670-1.2-ANSI V1 EN
1MRK002802-AB-10-670-1.2-ANSI V1 EN
1MRK002802-AB-11-670-1.2-ANSI V1 EN
1MRK002802-AB-12-670-1.2-ANSI V1 EN
1MRK002802-AB-13-670-1.2-ANSI V1 EN
1MRK002802-AB-14-670-1.2-ANSI V1 EN
1MRK002802-AB-15-670-1.2-ANSI V1 EN
21.1
Injection equipment
Injection unit REX060
1MRK002501-BA-1 V1 EN
1MRK002501-BA-2 V1 EN
1MRK002501-BA-3 V1 EN
1MRK002501-BA-4 V1 EN
1MRK002501-BA-5 V1 EN
1MRK002551-BA-1 V1 EN
1MRK002551-BA-2 V1 EN
1MRK002556-BA-1 V1 EN
1MRK002556-BA-2 V1 EN
1MRK002504-AA V1 EN
1MRK002504-BA-1 V2 EN
1MRK002504-BA-2 V2 EN
1MRK002504-BA-3 V2 EN
1MRK002504-BA-4 V2 EN
1MRK002504-BA-5 V2 EN
1MRK002504-BA-6 V1 EN
1MRK002504-CA-1 V1 EN
1MRK002504-CA-2 V1 EN
1MRK002504-CA-3 V1 EN
1MRK002504-CA-4 V1 EN
1MRK002504-DA-1 V1 EN
1MRK002504-DA-2 V1 EN
1MRK002504-DA-3 V1 EN
1MRK002504-DA-4 V1 EN
1MRK002504-DA-5 V1 EN
1MRK002504-DA-6 V1 EN
1MRK002504-DA-7 V1 EN
1014
Section 22
22.1
Application
In order to assure time selectivity between different overcurrent protections at different points in the network different time delays for the different protections are normally used. The simplest way to do this is to use definite time-lag. In more sophisticated applications current dependent time characteristics are used. Both alternatives are shown in a simple application with three overcurrent protections operating in series.
IPickup
IPickup
IPickup
xx05000129_ansi.vsd
ANSI05000129 V1 EN
Figure 441:
Stage 1
Stage 1
Stage 1
en05000130.vsd
IEC05000130 V1 EN
Figure 442:
Time
Figure 443:
The inverse time characteristic makes it possible to minimize the fault clearance time and still assure the selectivity between protections. To assure selectivity between protections there must be a time margin between the operation time of the protections. This required time margin is dependent of following factors, in a simple case with two protections in series: Difference between pickup time of the protections to be co-ordinated Opening time of the breaker closest to the studied fault Reset times of the protections Margin dependent of the time delay inaccuracy of the protections
A1
B1
Feeder
51
51
Time axis
t=0
t=t1
t=t2
t=t3
en05000132_ansi.vsd
ANSI05000132 V1 EN
Figure 444:
where: t=0 t=t1 t=t2 t=t3
In the case protection B1 shall operate without any intentional delay (instantaneous). When the fault occurs the protections pickup to detect the fault current. After the time t1 the protection B1 send a trip signal to the circuit breaker. The protection A1 starts its delay timer at the same time, with some deviation in time due to differences between the two protections. There is a possibility that A1 will start before the trip is sent to the B1 circuit breaker. At the time t2 the circuit breaker B1 has opened its primary contacts and thus the fault current is interrupted. The breaker time (t2 - t1) can differ between different faults. The maximum opening time can be given from manuals and test protocols. Still at t2 the timer of protection A1 is active. At time t3 the protection A1 is reset, that is the timer is stopped. In most applications it is required that the times shall reset as fast as possible when the current fed to the protection drops below the set current level, the reset time shall be minimized. In some applications it is however beneficial to have some type of delayed reset time of the overcurrent function. This can be the case in the following applications:
If there is a risk of intermittent faults. If the current IED, close to the faults, picks up and resets there is a risk of unselective trip from other protections in the system. Delayed resetting could give accelerated fault clearance in case of automatic reclosing to a permanent fault. Overcurrent protection functions are sometimes used as release criterion for other protection functions. It can often be valuable to have a reset delay to assure the release function.
22.2
22.2.1
Principle of operation
Mode of operation
The function can operate in a definite time-lag mode or in a current definite inverse time mode. For the inverse time characteristic both ANSI and IEC based standard curves are available. Also programmable curve types are supported via the component inputs: p, A, B, C pr, tr, and cr. Different characteristics for reset delay can also be chosen. If current in any phase exceeds the set pickup current value (here internal signal pickupValue), a timer, according to the selected operating mode, is started. The component always uses the maximum of the three phase current values as the current level used in timing calculations. In case of definite time-lag mode the timer will run constantly until the time is reached or until the current drops below the reset value (pickup value minus the hysteresis) and the reset time has elapsed. For definite time delay curve ANSI/IEEE Definite time or IEC Definite time are chosen. The general expression for inverse time curves is according to equation 151.
A t [s ] = P i Pickupn
EQUATION1640 V1 EN
-C
+ B td
(Equation 151)
where: p, A, B, C Pickupn td i are constants defined for each curve type, is the set pickup current for step n, is set time multiplier for step n and is the measured current.
For inverse time characteristics a time will be initiated when the current reaches the set pickup level. From the general expression of the characteristic the following can be seen:
i ( top - B td ) Pickupn
-C
= A td
(Equation 152)
EQUATION1642 V1 EN
The time elapsed to the moment of trip is reached when the integral fulfils according to equation 153, in addition to the constant time delay:
P i Pickupn 0
- C dt A td
EQUATION1643 V1 EN
(Equation 153)
For the numerical protection the sum below must fulfil the equation for trip.
Dt
i ( j ) P - C A td Pickupn j =1
n
EQUATION1644 V1 EN
(Equation 154)
where: j=1 is the first protection execution cycle when a fault has been detected, that is, when
i Pickupn
Dt n i (j)
>1
EQUATION1646 V1 EN
is the time interval between two consecutive executions of the protection algorithm, is the number of the execution of the algorithm when the trip time equation is fulfilled, that is, when a trip is given and is the fault current at time j
For inverse time operation, the inverse time characteristic is selectable. Both the IEC and ANSI/IEEE standardized inverse time characteristics are supported. For the IEC curves there is also a setting of the minimum time-lag of operation, see figure 445.
Operate time
tMin
IMin
IEC05000133 V2 EN
Current
IEC05000133-3-en.vsd
Figure 445:
In order to fully comply with IEC curves definition setting parameter tMin shall be set to the value which is equal to the operating time of the selected IEC inverse time curve for measured current of twenty times the set current pickup value. Note that the operating time value is dependent on the selected setting value for time multiplier k. In addition to the ANSI and IEC standardized characteristics, there are also two additional inverse curves available; the RI curve and the RD curve. The RI inverse time curve emulates the characteristic of the electromechanical ASEA relay RI. The curve is described by equation 156:
td t [s ] = Pickupn 0.339 - 0.235 i
EQUATION1647 V1 EN
(Equation 156)
where: Pickupn is the set pickup current for step n td i is set time multiplier for step n is the measured current
The RD inverse curve gives a logarithmic delay, as used in the Combiflex protection RXIDG. The curve enables a high degree of selectivity required for sensitive residual ground-fault current protection, with ability to detect high-resistive ground faults. The curve is described by equation 157:
t s = 5.8 - 1.35 ln
EQUATION1648 V1 EN
[ ]
td Pickupn
i
(Equation 157)
where: Pickupn is the set pickup current for step n, td i is set time multiplier for step n and is the measured current
If the curve type programmable is chosen, the user can make a tailor made inverse time curve according to the general equation 158.
A t [s ] = P i Pickupn
EQUATION1640 V1 EN
-C
+ B td
(Equation 158)
Also the reset time of the delayed function can be controlled. There is the possibility to choose between three different reset time-lags. Instantaneous Reset IEC Reset ANSI Reset.
If instantaneous reset is chosen the timer will be reset directly when the current drops below the set pickup current level minus the hysteresis. If IEC reset is chosen the timer will be reset after a set constant time when the current drops below the set pickup current level minus the hysteresis. If ANSI reset time is chosen the reset time will be dependent of the current after fault clearance (when the current drops below the pickup current level minus the hysteresis). The timer will reset according to equation 159.
tr td t [s] = i 2 -1 pickupn
ANSIEQUATION1197 V1 EN
(Equation 159)
where: The set value tr is the reset time in case of zero current after fault clearance.
The possibility of choice of reset characteristics is to some extent dependent of the choice of time delay characteristic. For the definite time delay characteristics the possible reset time settings are instantaneous and IEC constant time reset. For ANSI inverse time delay characteristics all three types of reset time characteristics are available; instantaneous, IEC constant time reset and ANSI current dependent reset time. For IEC inverse time delay characteristics the possible delay time settings are instantaneous and IEC set constant time reset). For the programmable inverse time delay characteristics all three types of reset time characteristics are available; instantaneous, IEC constant time reset and ANSI current dependent reset time. If the current dependent type is used settings pr, tr and cr must be given, see equation 160:
tr td t [s] = i pr - cr pickupn
ANSIEQUATION1198 V1 EN
(Equation 160)
For RI and RD inverse time delay characteristics the possible delay time settings are instantaneous and IEC constant time reset. When inverse time overcurrent characteristic is selected, the operate time of the stage will be the sum of the inverse time delay and the set
definite time delay. Thus, if only the inverse time delay is required, it is of utmost importance to set the definite time delay for that stage to zero.
22.3
Inverse characteristics
Table 588:
Function Operating characteristic:
t =
A P ( I - 1)
+ B td
EQUATION1651 V1 EN
Reset characteristic:
t = tr
2
(I
-1
td
EQUATION1652 V1 EN
I = Imeasured/Iset ANSI Extremely Inverse ANSI Very inverse ANSI Normal Inverse ANSI Moderately Inverse ANSI Long Time Extremely Inverse ANSI Long Time Very Inverse ANSI Long Time Inverse A=28.2, B=0.1217, P=2.0 , tr=29.1 A=19.61, B=0.491, P=2.0 , tr=21.6 A=0.0086, B=0.0185, P=0.02, tr=0.46 A=0.0515, B=0.1140, P=0.02, tr=4.85 A=64.07, B=0.250, P=2.0, tr=30 A=28.55, B=0.712, P=2.0, tr=13.46 A=0.086, B=0.185, P=0.02, tr=4.6 ANSI/IEEE C37.112, 5% + 40 ms
Table 589:
Function
Operating characteristic:
t =
A P td ( I - 1)
EQUATION1653 V1 EN
I = Imeasured/Iset Time delay to reset, IEC inverse time IEC Normal Inverse IEC Very inverse IEC Inverse IEC Extremely inverse IEC Short time inverse IEC Long time inverse Programmable characteristic Operate characteristic: (0.000-60.000) s A=0.14, P=0.02 A=13.5, P=1.0 A=0.14, P=0.02 A=80.0, P=2.0 A=0.05, P=0.04 A=120, P=1.0 td = (0.05-999) in steps of 0.01 A=(0.005-200.000) in steps of 0.001 B=(0.00-20.00) in steps of 0.01 C=(0.1-10.0) in steps of 0.1 P=(0.005-3.000) in steps of 0.001 TR=(0.005-100.000) in steps of 0.001 CR=(0.1-10.0) in steps of 0.1 PR=(0.005-3.000) in steps of 0.001 0.5% of set time 10 ms IEC 60255-151, 5% + 40 ms
t =
A P (I - C )
+ B td
EQUATION1654 V1 EN
Reset characteristic:
t = TR
PR
(I
- CR
td
EQUATION1655 V1 EN
I = Imeasured/Iset
Table 590:
Function
0.339 EQUATION1656 V1 EN
0.236 I
td
I
I = Imeasured/Iset
Table 591:
Function Type A curve:
t =
td
V - VPickup VPickup
EQUATION1661 V1 EN
- 0.035
EQUATION1662 V1 EN
Type C curve:
t =
- 0.035
EQUATION1663 V1 EN
Programmable curve:
t =
td A
V - VPickup B VPickup
-C
+D
EQUATION1664 V1 EN
td = (0.05-1.10) in steps of 0.01 A = (0.005-200.000) in steps of 0.001 B = (0.50-100.00) in steps of 0.01 C = (0.0-1.0) in steps of 0.1 D = (0.000-60.000) in steps of 0.001 P = (0.000-3.000) in steps of 0.001
Table 592:
Function Type A curve:
t =
td
VPickup - V
VPickup
EQUATION1658 V1 EN
t =
- 0.5
2.0
+ 0.055
EQUATION1659 V1 EN
V = Vmeasured Programmable curve: td = (0.05-1.10) in steps of 0.01 A = (0.005-200.000) in steps of 0.001 B = (0.50-100.00) in steps of 0.01 C = (0.0-1.0) in steps of 0.1 D = (0.000-60.000) in steps of 0.001 P = (0.000-3.000) in steps of 0.001
t =
td A VPickup - V B VPickup
+D P -C
EQUATION1660 V1 EN
V = Vmeasured
Table 593:
Function Type A curve:
t =
td
V - VPickup VPickup
EQUATION1661 V1 EN
- 0.035
EQUATION1662 V1 EN
Type C curve:
t =
- 0.035
EQUATION1663 V1 EN
Programmable curve:
t =
td A
V - VPickup B VPickup
-C
+D
EQUATION1664 V1 EN
td = (0.05-1.10) in steps of 0.01 A = (0.005-200.000) in steps of 0.001 B = (0.50-100.00) in steps of 0.01 C = (0.0-1.0) in steps of 0.1 D = (0.000-60.000) in steps of 0.001 P = (0.000-3.000) in steps of 0.001
A070750 V2 EN
Figure 446:
A070751 V2 EN
Figure 447:
A070752 V2 EN
Figure 448:
A070753 V2 EN
Figure 449:
A070817 V2 EN
Figure 450:
A070818 V2 EN
Figure 451:
A070819 V2 EN
Figure 452:
A070820 V2 EN
Figure 453:
A070821 V2 EN
Figure 454:
A070822 V2 EN
Figure 455:
A070823 V2 EN
Figure 456:
A070824 V2 EN
Figure 457:
A070825 V2 EN
Figure 458:
A070826 V2 EN
Figure 459:
A070827 V2 EN
Figure 460:
GUID-ACF4044C-052E-4CBD-8247-C6ABE3796FA6 V1 EN
Figure 461:
GUID-F5E0E1C2-48C8-4DC7-A84B-174544C09142 V1 EN
Figure 462:
GUID-A9898DB7-90A3-47F2-AEF9-45FF148CB679 V1 EN
Figure 463:
GUID-35F40C3B-B483-40E6-9767-69C1536E3CBC V1 EN
Figure 464:
GUID-B55D0F5F-9265-4D9A-A7C0-E274AA3A6BB1 V1 EN
Figure 465:
1050
Section 23 Glossary
Section 23
Glossary
Section 23 Glossary
Controller Area Network. ISO standard (ISO 11898) for serial communication Circuit breaker Combined backplane module Consultative Committee for International Telegraph and Telephony. A United Nations-sponsored standards body within the International Telecommunications Union. CAN carrier module Capacitive Coupled Voltage Transformer Protection Current Transformer class as per IEEE/ ANSI Combined megapulses per second Communication Management tool in PCM600 Close-open cycle Way of transmitting G.703 over a balanced line. Involves two twisted pairs making it possible to transmit information in both directions Standard Common Format for Transient Data Exchange format for Disturbance recorder according to IEEE/ANSI C37.111, 1999 / IEC60255-24 Way of transmitting G.703 over a balanced line. Involves four twisted pairs, two of which are used for transmitting data in both directions and two for transmitting clock signals Central processor unit Carrier receive Cyclic redundancy check Control relay output block Carrier send Current transformer Capacitive voltage transformer Delayed autoreclosing Defense Advanced Research Projects Agency (The US developer of the TCP/IP protocol etc.) Dead bus dead line Dead bus live line Direct current
Technical reference manual
COMTRADE
Contra-directional
Section 23 Glossary
DFC DFT DHCP DIP-switch DI DLLB DNP DR DRAM DRH DSP DTT EHV network EIA EMC EMF EMI EnFP EPA ESD FCB FOX 20 FOX 512/515 FOX 6Plus G.703
Data flow control Discrete Fourier transform Dynamic Host Configuration Protocol Small switch mounted on a printed circuit board Digital input Dead line live bus Distributed Network Protocol as per IEEE/ANSI Std. 1379-2000 Disturbance recorder Dynamic random access memory Disturbance report handler Digital signal processor Direct transfer trip scheme Extra high voltage network Electronic Industries Association Electromagnetic compatibility (Electric Motive Force) Electromagnetic interference End fault protection Enhanced performance architecture Electrostatic discharge Flow control bit; Frame count bit Modular 20 channel telecommunication system for speech, data and protection signals Access multiplexer Compact time-division multiplexer for the transmission of up to seven duplex channels of digital data over optical fibers Electrical and functional description for digital lines used by local telephone companies. Can be transported over balanced and unbalanced lines Communication interface module with carrier of GPS receiver module Graphical display editor within PCM600
1053
GCM GDE
Section 23 Glossary
General interrogation command Gas-insulated switchgear Generic object-oriented substation event Global positioning system Generic security application GPS Time Module High-level data link control, protocol based on the HDLC standard Human-machine interface High speed autoreclosing High-voltage High-voltage direct current Installation and Commissioning Tool for injection based protection in REG670 Integrating deadband supervision International Electrical Committee IEC Standard, Instrument transformers Part 6: Requirements for protective current transformers for transient performance Communication standard for protective equipment. A serial master/slave protocol for point-to-point communication Substation automation communication standard Communication protocol standard Institute of Electrical and Electronics Engineers A network technology standard that provides 100 Mbits/s on twisted-pair or optical fiber cable PCI Mezzanine Card (PMC) standard for local bus modules. References the CMC (IEEE P1386, also known as Common Mezzanine Card) standard for the mechanics and the PCI specifications from the PCI SIG (Special Interest Group) for the electrical EMF (Electromotive force). Standard for Substation Intelligent Electronic Devices (IEDs) Cyber Security Capabilities Intelligent electronic device Intelligent gas-insulated switchgear
Technical reference manual
HFBR connector type Plastic fiber connector HMI HSAR HV HVDC ICT IDBS IEC IEC 60044-6 IEC 60870-5-103 IEC 61850 IEC 6185081 IEEE IEEE 802.12 IEEE P1386.1
Section 23 Glossary
IOM Instance
Binary input/output module When several occurrences of the same function are available in the IED, they are referred to as instances of that function. One instance of a function is identical to another of the same kind but has a different number in the IED user interfaces. The word "instance" is sometimes defined as an item of information that is representative of a type. In the same way an instance of a function in the IED is representative of a type of function. 1. Internet protocol. The network layer for the TCP/IP protocol suite widely used on Ethernet networks. IP is a connectionless, best-effort packet-switching protocol. It provides packet routing, fragmentation and reassembly through the data link layer. 2. Ingression protection, according to IEC standard Ingression protection, according to IEC standard, level IP20- Protected against solidforeign objects of12.5mm diameter andgreater. Ingression protection, according to IEC standard, level IP40Protected against solid foreign objects of 1mm diameter and greater. Ingression protection, according to IEC standard, level IP54-Dust-protected,protected againstsplashing water. Internal failure signal InterRange Instrumentation Group Time code format B, standard 200 International Telecommunications Union Local area network High-voltage software module Liquid crystal display Line differential communication module Local detection device Light-emitting diode LON network tool Local operating network Miniature circuit breaker
IP
IP 20
IP 40
IP 54 IRF IRIG-B: ITU LAN LIB 520 LCD LDCM LDD LED LNT LON MCB
Section 23 Glossary
MCM MIM MPM MVB NCC NUM OCO cycle OCP OEM OLTC OV Overreach
Mezzanine carrier module Milli-ampere module Main processing module Multifunction vehicle bus. Standardized serial bus originally developed for use in trains. National Control Centre Numerical module Open-close-open cycle Overcurrent protection Optical ethernet module On-load tap changer Over-voltage A term used to describe how the relay behaves during a fault condition. For example, a distance relay is overreaching when the impedance presented to it is smaller than the apparent impedance to the fault applied to the balance point, that is, the set reach. The relay sees the fault but perhaps it should not have seen it. Peripheral component interconnect, a local data bus Pulse code modulation Protection and control IED manager Mezzanine card standard PCI Mezzanine card Permissive overreach Permissive overreach transfer trip Bus or LAN used at the process level, that is, in near proximity to the measured and/or controlled components Power supply module Parameter setting tool within PCM600 Potential transformer or voltage transformer ratio Permissive underreach transfer trip Synchrocheck relay, COMBIFLEX Relay characteristic angle Resistance for phase-to-phase faults
Technical reference manual
PCI PCM PCM600 PC-MIP PMC POR POTT Process bus PSM PST PT ratio PUTT RASC RCA RFPP
1056
Section 23 Glossary
Resistance for phase-to-ground faults RISC RMS value RS422 RS485 RTC RTU SA SBO SC SCS SCADA SCT SDU SLM SMA connector SMT SMS SNTP Reduced instruction set computer Root mean square value A balanced serial interface for the transmission of digital data in point-to-point connections Serial link according to EIA standard RS485 Real-time clock Remote terminal unit Substation Automation Select-before-operate Switch or push button to close Station control system Supervision, control and data acquisition System configuration tool according to standard IEC 61850 Service data unit Serial communication module. Used for SPA/LON/IEC/ DNP3 communication. Subminiature version A, A threaded connector with constant impedance. Signal matrix tool within PCM600 Station monitoring system Simple network time protocol is used to synchronize computer clocks on local area networks. This reduces the requirement to have accurate hardware clocks in every embedded system in a network. Each embedded node can instead synchronize with a remote clock, providing the required accuracy. Strmberg protection acquisition, a serial master/slave protocol for point-to-point communication Switch for CB ready condition Switch or push button to trip Neutral/Wye point of transformer or generator Static VAr compensation Trip coil
1057 Technical reference manual
Section 23 Glossary
Trip circuit supervision Transmission control protocol. The most common transport layer protocol used on Ethernet and the Internet. Transmission control protocol over Internet Protocol. The de facto standard Ethernet protocols incorporated into 4.2BSD Unix. TCP/IP was developed by DARPA for Internet working and encompasses both network layer and transport layer protocols. While TCP and IP specify two protocols at specific protocol layers, TCP/IP is often used to refer to the entire US Department of Defense protocol suite based upon these, including Telnet, FTP, UDP and RDP. Time delayed gound-fault protection function Threaded Neill-Concelman, a threaded constant impedance version of a BNC connector User management tool A term used to describe how the relay behaves during a fault condition. For example, a distance relay is underreaching when the impedance presented to it is greater than the apparent impedance to the fault applied to the balance point, that is, the set reach. The relay does not see the fault but perhaps it should have seen it. See also Overreach. Coordinated Universal Time. A coordinated time scale, maintained by the Bureau International des Poids et Mesures (BIPM), which forms the basis of a coordinated dissemination of standard frequencies and time signals. UTC is derived from International Atomic Time (TAI) by the addition of a whole number of "leap seconds" to synchronize it with Universal Time 1 (UT1), thus allowing for the eccentricity of the Earth's orbit, the rotational axis tilt (23.5 degrees), but still showing the Earth's irregular rotation, on which UT1 is based. The Coordinated Universal Time is expressed using a 24-hour clock, and uses the Gregorian calendar. It is used for aeroplane and ship navigation, where it is also sometimes known by the military name, "Zulu time." "Zulu" in the phonetic alphabet stands for "Z", which stands for longitude zero. Undervoltage Weak end infeed logic Voltage transformer
TPZ, TPY, TPX, TPS Current transformer class according to IEC UMT Underreach
UTC
UV WEI VT
1058
Section 23 Glossary
A digital signalling interface primarily used for telecom equipment Three times zero-sequence current. Often referred to as the residual or the -fault current Three times the zero sequence voltage. Often referred to as the residual voltage or the neutral point voltage
1060
1061
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