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International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN INTERNATIONAL JOURNAL OF ADVANCED RESEARCH IN 0976 6480(Print),

, ISSN 0976 6499(Online) Volume 4, Issue 3, April (2013), IAEME ENGINEERING AND TECHNOLOGY (IJARET) ISSN 0976 - 6480 (Print) ISSN 0976 - 6499 (Online) Volume 4, Issue 3, April 2013, pp. 257-263 IAEME: Journal Impact Factor (2013): 5.8376 (Calculated by GISI)



Mohammed Arifuddin Sohel 1, Dr. K. Chennakeshava Reddy 2 Dr. Syed Abdul Sattar3 (Associate Professor, Department of Electronics and Communication Engineering, Muffakham Jah College of Engineering and Technology, Hyderabad, A.P., India) 2 (Principal, TKR College of Engineering and Technology, Meerpet, Ranga Reddy Dist,A.P., INDIA) 3 (Professor, Royal institute of Technology and Science, Chevella, Ranga Reddy Dist,A.P., INDIA)

ABSTRACT The signal to noise ratio and resolution of an analog to digital converter is governed by the linearity constraints of the basic building block, which is the Operational Transconductance Amplifier (OTA). The OTA design is based on MOS transistors that are inherently non linear and lead to performance deterioration. To overcome the non-linearities imposed by the OTA a resistive source degeneration technique is proposed. The use of linearization techniques leads to a tradeoff between transconductance and gain of the amplifier. The proposed Source Degenerated OTA (SDOTA) achieves Third order Intermodulation (IM3) of -62dB at a high frequency range of 70 MHz with an effective Transconductance of 655.8 A/V. The SDOTA offers a gain of 14dB at a Unity Gain Frequency of 4.7 GHz and is implemented in 180nm CMOS technology. Keywords: Analog and Mixed Signal IC Design, Operational Transconductance Amplifier (OTA), Linearization, Source Degeneration 1. INTRODUCTION The modern day Analog and Mixed Signal IC designs like filters, oscillators and Data Converters (ADC, DAC) are implemented using the operational amplifiers (OPAMPs) as basic building block. The design, analysis, and implementation of these applications is simplified by using OPAMPs. The OPAMPs work well for low-frequency applications, such as audio and video systems but at Radio Frequency range, OPAMP designs become difficult due to their frequency limitation [1]. The OTA is an amplifier that produces an output current which is proportional to the differential input voltage. They are very simple to design and require small area when compared to most of the operational amplifiers. Due to the simple circuitry there are no high impedance internal nodes, where parasitic capacitors can results in long time constants that limit bandwidth [2]. 257

International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 6480(Print), ISSN 0976 6499(Online) Volume 4, Issue 3, April (2013), IAEME Therefore, OTAs are more suitable for high frequency applications that operate in the Radio frequency range [3]. The major disadvantage of OTAs is the input stage nonlinearity at higher differential input voltages due to the nonlinear characteristics of the input transistors. This problem leads to occurrence of intermodulation components at the output and degrades Dynamic Range(DR) and Signal to Noise Ratio (SNR) of the analog application. Consequently, a good number of techniques have been reported to improve the linearity of OTAs [4] [5]. Owing to continuous reduction in transistor size, supply voltages, and increase in the frequency of operation there has been a steady decrease in linearity of OTA. Hence, it is important to revisit these techniques, and also to come up with new methods for linearization. The main focus of this paper is the design and implementation of a 70 MHz, low distortion OTA with IM3 (Third Intermodulation product) below -65 dB using source degeneration technique in 0.18m CMOS technology. The above specifications are derived so that the OTA can be used for the implementation of a continuous time filter for the Band Pass Sigma Delta ADC, operating at Intermediate Frequency of 70 MHz and a bandwidth of 5 MHz. The Paper is organized as follows: section 2 introduces the design aspects of basic and balanced OTA. Section 3 discusses the issue of non linearity and proposed technique of source degeneration to improve this non linearity. Section 4 describes the circuit level implementation of proposed OTA and the improvement achieved in performance metrics. A comparison of results and conclusions are given in section 5. 2. OTA DESIGN The CMOS implementation of OTA consists of a source-coupled differential-pair input stage as shown in figure 1, which provides high input impedance, high gain, and high common-mode rejection [6]. In Figure 1(a) a differential input single ended output basic OTA is depicted. Here, the current mirror CMp transfers the left output current of the input differential pair, id+ , to the right to combine with its right output current id- , from which the transconductor output current is doubled, the transconductance is given in equation1 . (1) where and are the differential input voltages, and gmM1 is the transconductance of each

transistor in the differential pair. The balanced implementation of an OTA is shown in Figure 1(b), it consists of two PMOS current mirrors in order to improve the balance between its two differential input paths. Furthermore, these two PMOS current mirrors can be set in such way that they have a size ratio of B between their reference transistor and controlled transistor. This boosts their output currents by B times [7].

Figure 1: Differential-input single ended output CMOS OTAs (a) Simple OTA (b) Current boosted OTA [7]


International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 6480(Print), ISSN 0976 6499(Online) Volume 4, Issue 3, April (2013), IAEME The boosted currents are combined at the output using a NMOS current mirror at the bottom, resulting in a transconductance as large as B times of the basic OTA as shown in equation 2. (2)

The transconductance in equation 1 and 2 can be tuned by changing the DC tail currents Itail in Figure 1(a) and 1(b). The CMOS OTAs in Figure 2 illustrate two OTA implementations of fullydifferential topology [8]. The structure is similar to that of figure 1 and the aforementioned size ratio of B can also be applied in the current mirrors to increase their transconductance and therefore their current efficiency. Fully differential architectures are preferred over single ended ones as they support noise cancellation at the input and output side.

Figure 2: Fully Differential CMOS OTA (a) Simple OTA and (b) Balanced OTA. Compared to the OTA in Figure 2(a), the balanced OTA in Figure 2(b) has an additional common-mode feed forward (CMFF) circuit comprising MC1, MC2 and MC3 to further enhance its common-mode rejection [8]. The sizes of MC1, MC2, and MC3 are selected to achieve a commonmode transconductance gain of BgmM1, in order to optimize its common-mode cancellation with the B-size PMOS transistors at the outputs. 3. LINEARIZATION TECHNIQUES FOR OTA The OTA structure consists of Active devices in the form of MOS transistors which are nonlinear in operation. When a large signal is applied, the device slips into non linear region of operation and will generate spurious signals that are highly undesirable. This results in increase of third order intermodulation (IM3) which is a measure of circuit non linearity. There are two techniques used commonly for linearization - (a) nonlinear term cancellation and (b) signal attenuation through Source degeneration. In the first method, the linear range is very restricted and a good cancellation is hard to achieve especially under process, voltage, Temperature (PVT) variations [9]. Hence, the Source Degeneration Technique is adopted in this paper and appropriate transistor sizing is performed to optimize the IM3.


International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 6480(Print), ISSN 0976 6499(Online) Volume 4, Issue 3, April (2013), IAEME

Figure 3: (a) Resistive Source Degeneration at low frequency (b) Effect of Parasitic Capacitance (Cp) at high frequency on resistive degeneration Figure 3(a) depicts Resistive Source Degeneration Technique at low and high frequency. This technique involves the use of a linear resistor, which reduces the signal swing between the gate and source of the transistor, thereby making input/output characteristics more linear. The effective transconductance Gmeff is given in equation 3 and it depends on resistor as well as transconductance of the transistor. In this equation If gm1. R >>1, then the effective transconductance (Gmeff) is equivalent to 1/R and thereby less sensitive to nonlinear device parameters.

The source degeneration factor is N = 1 + gm1.R. Therefore, in order to achieve higher linearity, it is desirable to increase gm (and to increase the degeneration factor, N), so that Gmeff is only dependent on linear resistor R, and gm nonlinear contribution is small. One method to increase gm is to increase W/L ratio of input transistor and increase bias current Ib[10], but it increases power and area. Further, at high frequencies, as shown in figure 3(b), the parasitic capacitor at the source terminal of the input transistor (M1) decreases the effective impedance at that node, and thereby decreases the source degeneration factor (N). The effect of parasitic capacitor is modeled in equation 4 (4)

The parasitic capacitance at source terminal of input transistor (Cp) is mainly due to the source capacitance of the input transistor, M1 and the drain capacitance of M2. Therefore, if width of M1 is increased to increase gm (proportional to sqrt(W/L)), then Cp also increases proportional to W and overall degeneration factor does not improve. Furthermore, the parasitic capacitor effect becomes dominant at higher frequencies decreasing degeneration factor with frequency[11]. In order to solve this problem an appropriate balancing of W/L ratios with the resistor value is required and this paper proposes a balanced design that is able to overcome the effects of parasitic capacitor at high frequency, thus achieving high linearity at higher frequencies of 70MHz. 4. IMPLEMENTATION OF CONVENTIONAL AND PROPOSED OTA The transistor schematic of conventional OTA is shown in figure 4. This OTA when implemented on Cadence virtuoso simulation platform provides a transconductance of 788.4A/V and gain of about 26dB at a UGB of 7.25 GHz as depicted in figure 5(a). 260

International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 6480(Print), ISSN 0976 6499(Online) Volume 4, Issue 3, April (2013), IAEME

Figure 4: Transistor schematic of conventional OTA

Figure 5: Simulation Results of Non Linear conventional OTA (a) Response of AC analysis showing gain and UGB (b) Response of PSS analysis for a two tone test

But there were more harmonic distortions introduced due to the non-linearity of the OTA. This non linearity is measured by conducting a two tone test[12]. Two sine wave input with 0.1 V (amplitude) at 70 MHz and 71 MHz are applied, and the IM3 distortion is obtained by performing PSS analysis on Cadence. It is measured to give an IM3 value of -26dB and the overall noise floor is also very high, as seen in figure 5(b). The proposed SDOTA is much similar in design to the one in Figure 4 except that it makes use of source degeneration resistors as shown in Figure 6. The proposed OTA provides a reduced gain of 14 dB at a UGB of 4.76GHz as shown in figure 7(a). The transconductance also reduces to 655.8A/V, which is a direct consequence of using resistor degeneration. But on the other hand, the proposed OTA has reduced the harmonic distortions to greater amount and improved the linearity of the OTA to -62 dB and the noise floor has reduced significantly as depicted in figure 7(b).


International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 6480(Print), ISSN 0976 6499(Online) Volume 4, Issue 3, April (2013), IAEME

Figure 6: Transistor schematic of Proposed Source Degenerated OTA(SDOTA)

Figure 7: Simulation Results of Proposed SDOTA (a) Response of AC analysis showing gain and UGB (b) Response of PSS analysis for a two tone test 5. CONCLUSIONS AND FUTURE SCOPE The Performance Comparison of conventional and Proposed OTA is shown in table 1. It can be seen that though the gain and UGB of proposed OTA have reduced, it also reduces the IM3 distortion to -62dB and is hence preferred in design of Analog and mixed signal applications. Table 1 Performance Comparison of Conventional OTA and Proposed SDOTA OTA Parameters DC Gain Unity Gain Bandwidth (UGB) Effective Transconductance Gmeff Third Order Intermodulation(IM3) Conventional OTA 26dB 7.25Ghz 788.4A/V -26dB Proposed SDOTA 14dB 4.76Ghz 655.8A/V -62dB


International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 6480(Print), ISSN 0976 6499(Online) Volume 4, Issue 3, April (2013), IAEME REFERENCES 1. L. H. C. Ferreira, T. C. Pimenta, and R. L. Moreno, An ultra-low-voltage ultralow power CMOS Miller OTA with rail-to-rail input/output swing, IEEE Trans. Circuits and Systems II: Express Briefs, vol. 54, no. 10, pp. 843-847, Oct. 2007 2. R. L. Geiger and E. Sanchez-Sinencio, Active filter design using operational transconductance amplifiers: A tutorial, IEEE Circuit and Device Magazine, vol. 1, pp. 20-32, Mar. 1985 3. X. Zhang and E. I. El-Masry, A novel CMOS OTA based on body-driven MOSFETs and its applications in OTA-C filters, IEEE Trans. Circuits and Systems I: Regular Papers, vol. 54, no. 6, pp. 1204-1212, Jun. 2007 4. T. Lin, C. Wu, and M. Tsai, A 0.8-V 0.25-mW current-mirror OTA with 160- MHz GBW in 0.18-um CMOS, IEEE Trans. Circuits and Systems II: Express Briefs, vol. 54, no. 2, pp. 131135, Feb. 5. D. Grasso, G. Palumbo, and S. Pennisi, Three-stage CMOS OTA for large capacitive loads with efficient frequency compensation scheme, IEEE Trans. Circuits and Systems II: Express Briefs, vol. 53, no.10, pp. 1044-1048, Oct. 2006. 6. F. A. P. Baruqui and A. Petraglia, Linear tunable CMOS OTA with constant dynamic range using source-degenerated current mirrors, IEEE Trans. Circuits and Systems II: Express Briefs, vol. 53, no. 9, pp. 797-801, Sep. 2006. 7. B. K. Thandri and J. SilvaMartinez, A 63 dB 75 mW bandpass sigmadelta RF ADC at 950 MHz using 3.8 GHz clock in 0.25 mm SiGe BiCMOS technology, IEEE Journal of SolidState Circuits, vol. 42, pp. 269-279, Feb. 2007 8. E. Sanchez-Sinencio and J. Silva-Martinez, CMOS transconductance amplifiers, architectures and active filters: a tutorial, IEE Proceedings - Circuits, Devices and Systems, vol. 147, no. 1, pp. 3-12, Feb. 2000. 9. W. Huang and E. Sanchez-Sinencio, Robust highly linear high-frequency CMOS OTA with IM3 below -70 dB at 26 MHz, IEEE Trans. Circuits and Systems I: Fundamental Theory and Applications, vol. 53, no. 7, pp. 1433-1447, Jul. 2006. 10. A. J. Lopez-Martin, S. Baswa, J. Ramirez-Angulo, and R. G. Carvajal, Low voltage super classAB CMOS OTA cells with very high slew rate and power efficiency, IEEE Journal of SolidState Circuits, vol. 40, no. 5, pp. 1068-1077, May 2005. 11. J. Chen, E. SanchezSinencio, and J. SilvaMartinez, Frequencydependent harmonic distortion analysis of a linearized crosscoupled CMOS OTA and its application to OTAC filters, IEEE Transactions on Circuits and Systems, vol. 53, no. 3, Mar. 2006. 12. A. Lewinski and J. Silva-Martinez, OTA linearity enhancement technique for high frequency applications with IM3 below -65 dB, IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 51, no. 10, pp. 542-548, Oct. 2004. 13. Aswathy G Nair and Gopakumar M G, CS-CMOS: A Low-Noise Logic Family for Mixed Signal Socs, International journal of Electronics and Communication Engineering & Technology (IJECET), Volume 4, Issue 2, 2013, pp. 180 - 190, ISSN Print: 0976- 6464, ISSN Online: 0976 6472. 14. P.Sreenivasulu, Krishnna veni, Dr. K.Srinivasa Rao and Dr.A.VinayaBabu, Low Power Design Techniques of CMOS Digital Circuits, International Journal of Electronics and Communication Engineering & Technology (IJECET), Volume 3, Issue 2, 2012, pp. 199 - 208, ISSN Print: 0976- 6464, ISSN Online: 0976 6472.