1.

INTRODUCTION
Single-electron transistors [1] have been made with critical dimensions of just a few nanometers using metals, semiconductors, carbon nanotubes, and individual molecules. Some of the smallest transistors operate at room temperature. In this paper, first some basics of singleelectron transistors are introduced and then a few different kinds of SET's are described. The real problems preventing the use of SET's in most applications are the low gain, the high output impedance, and the background charges. Each of these problems is discussed and the circuits where SET's show the most promise are described. The single-electron transistor, a small metallic or semiconducting quantum box connected to two separate leads, is among the basic elements of mesoscopic devices. Due to the finite energy barrier for charging the box with a single electron, the so-called Coulomb blockade,1,2 charge inside the box is nearly quantized at low temperatures for weak tunneling between the box and the leads. As a result, transport through the box is strongly suppressed unless the two lowest lying charge configurations in the box are tuned to be degenerate. As a function of gate voltage, the conductance thus shows a sequence of narrow peaks, each corresponding to the crossing of the ground state from n to n11 excess electrons inside the box. At the degeneracy points, the system is subject to strong charge fluctuations. The corresponding low-energy physics is governed by the non-Fermi-liquid fixed point of the multichannel Kondo effect,35 where the two degenerate charge configurations in the box play the role of the impurity spin. Whichmultichannel Kondo effect is realized depends on microscopic details such as the number of transverse modes in the junctions, and the nature of electron transport inside the box. Two opposing scenarios were considered to date for the single-electron transistor, distinguished by whether or not electrons can propagate coherently between the two tunnel junctions. Focusing on wide tunnel junctions, Konig et al.6 considered the case where electrons can propagate coherently between the two leads ~see also Refs. 7 and 8!. Extending the work Grabert9 to nonequilibrium transport, these authors analyzed in detail all second-order contributions to the current in the dimensionless tunneling conductance, obtaining good agreement with experiment.10 However, based on perturbation theory, this approach breaks down near the degeneracy points, where transport is governed at low temperature by the strong electronic correlations of the multichannel Kondo effect. An alternative scenario was
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considered by Furusaki and Matveev,11 and later by Zarand et al.12 and Le Hur and .13 Noting that elastic cotunneling is strongly suppressed at temperatures above the level spacing,14 these authors omitted altogether coherent electron transport between the leads, by coupling each lead to independent conductionelectron modes within the box. For symmetric single-mode junctions, the resulting low-temperature physics is governed at the degeneracy point by the four-channel Kondo effect,11 in contrast to the two-channel Kondo effect that takes place when electrons can propagate coherently between the leads. Any asymmetry in the coupling to the two leads drives the system away from the four-channel fixed point to a twochannel fixed point, where one lead is decoupled from the box. Consequently, the zero temperature conductance vanishes, as shown by Furusaki and Matveev in the limit of both a large asymmetry and strong tunneling to one lead11 ~i.e., a nearly open tunneling mode!. A quantitative description of the temperature and asymmetry dependence of the conductance in this case remains lacking. Despite considerable efforts,68,1113 the understanding of the low-temperature transport at the degeneracy points is far from complete for either scenario. For weak single-mode tunnel junctions, there is no quantitative theory for the temperature dependence of the conductance in the Kondo regime, while the nonequilibrium differential conductance is practically unexplored in this regime for either scenario.15 The goal of this paper is to provide a detailed analysis of the linear and nonlinear transport at resonance, for weak singlemode tunnel junctions. Both scenarios where electrons either can or cannot propagate coherently between the two junctions are considered. Our aim is to provide a host of signatures that can be used to experimentally discern the two pictures, and to detect which multichannel Kondo effect is realized in actual systems.16 To this end, we employ the noncrossing approximation17 ~NCA!. The NCA is a self consistent perturbation theory about the atomic limit. Originally designed to study dilute magnetic alloys, this approach was successfully applied to the out-of-equilibrium Kondo effect both for the single-channel18 20 and two-channel21 Anderson impurity model. Recently, the NCA was generalized to the multichannel Kondo spin Hamiltonian with arbitrary spin-exchange and potential-scattering couplings.

2. SET BASICS
A single-electron transistor consists of a small conducting island coupled to source and drain leads by tunnel junctions and capacitively coupled to one or more gates. The geometry of a SET
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is shown in Fig. 1(a) and the equivalent electrical circuit is shown in Fig. 1(b). A stray capacitance C0 from the island to ground and a random background charge on the island Q0 are also included in the model. There are two gates in the equivalent circuit because two gates are often used in practice. For example, one gate can be used to tune the background charge while the other is used as the input of the SET. A straightforward electrostatic calculation shows that the voltage of the island as a function of the number of electrons on the island is,

Here n is the number of electrons on the island, e is the positive elementary charge, and C is the total capacitance of the island C = C1 + C2 + Cg1 + Cg2 + C0. The energy it takes to move an infinitesimally small charge dq from ground at a potential V = 0 to the island is Vdq. As soon as charge is added to the island, the voltage of the island changes. The energy needed to take a whole electron from ground and put it on the island is,

Here n is the number of electrons on the island before the final electron is added. The term Ec =
2

e /(2C) is called the charging energy and it sets the energy scale for single-electron effects. The charging energy is typically in the range 1 - 100 meV. There are four single-electron tunneling events that can take place. An electron can tunnel left through junction 1, right through junction 1, left through junction 2 or right through junction 2. The energies associated with these four tunnel events can be calculated using Eq. 2,

If any of these energies are negative, an electron will tunnel. If all four of these energies are positive, a condition known as the Coulomb blockade is achieved and no electrons will tunnel. Figure 2 shows a calculation of the conductance of a SET as a function of the gate voltage and the bias voltage. The straight lines that form the edges of the diamond shaped regions are given by setting E = 0 in Eqs. 3. The diamond labeled 0 is a region of Coulomb blockade where there are zero excess electrons on the island and the diamond labeled 1 is a region of Coulomb blockade with one excess electron on the island, etc. When a bias voltage is applied that is great enough to overcome the Coulomb blockade, current flows as electrons tunnel from the source onto the island and then from the island to the drain. In the region labeled (0,1), only one electron at a time can pass through the SET at low temperatures. Exact formulas for the current in each diamond can be derived in the limit of low temperature. For all of the diamonds labeled with just a single number n, the current is zero. In the diamonds labeled by two numbers (n,n+1) the charge on the island is alternately n and n+1 as current flows through the SET. The formula for the current in this case is,

Fig. 2 (a) The calculated conductance (dI/dV) through a SET plotted as a function of the gate voltage and the bias voltage. The diamonds are labeled with the charge states that are occupied at low temperature. (b) The experimental current-voltage characteristics of a SET are shown for two values of the gate. The solid line is for an induced gate charge of zero; this is the condition for maximum Coulomb blockade. The dashed line is for an induced gate charge of e/2; this is the minimum Coulomb blockade. ( ) bRaRCabI12+=, [4] where a = CV1 + ne - Q0 - C1V1 - C2V2 - Cg1Vg1 - Cg2Vg2 + e/2 and b = CV2 - ne + Q0 + C1V1 + C2V2 + Cg1Vg1 + Cg2Vg2 - e/2. This is a useful formula because in most applications a SET is biased in the (n,n+1) diamond. From this formula, the voltage gain can be determined. For a current biased SET, the maximum voltage gain is -Cg1/C1 if junction 2 is grounded and Cg1/C2 if junction 1 is grounded. The maximum transconductance (dI/dVg1) at low temperatures can also be determined from Eq. 4. Near the boundary between the diamonds labeled n and n,n+1; the quantity b 0 and the transconductance is dI/dVg1 Cg/(R2C). Near the boundaries between the diamond labeled n,n+1 and n+1; the quantity a 0 and the transconductance is dI/dVg1 -Cg/(R1C). The individual resistances of the two junctions in a SET are typically determined by measuring the transconductance. As more charge states are included, the formula for the current gets more complicated. The formula for the current in the diamonds labeled (n-1,n,n+1) is,

3. TYPES OF SINGLE-ELECTRON TRANSISTORS

Single-electron transistors can be made using metals, semiconductors, carbon nanotubes, or single molecules. Aluminum SET's made with Al/AlOx/Al tunnel junctions are the SET's that have been used most often in applications. This kind of SET is used in metrology to measure currents, capacitance, and charge. [8] They are used in astronomical measurements [9] and they have been used to make primary thermometers. [10] However, many fundamental single-electron measurements have been made using GaAs heterostructures. The island of this kind of SET is often called a quantum dot. Quantum dots have been very important in contributing to our understanding of single-electron
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effects because it is possible to have just one or a few conduction electrons on a quantum dot. The quantum states that the electrons occupy are similar to electron states in an atom and quantum dots are therefore sometimes called artificial atoms. The energy necessary to add an electron to a quantum dot depends not just on the electrostatic energy of Eq. 2 but also on the quantum confinement energy and the magnetic energy associated with the spin of the electron states. By measuring the current that flows thorough a quantum dot as a function of the gate voltage, magnetic field, and temperature allows one understand the quantum states of the dot in quite some detail. [11] The SET's described so far are all relatively large and have to be measured at low temperature, typically below 100 mK. For higher temperature operation, the SET's have to be made smaller. Ono et al. [3] used a technique called pattern dependent oxidation (PADOX) to make small silicon SET's. These SET's had junction capacitances of about 1 aF and a charging energy of 20 meV. The silicon SET's have the distinction of being the smallest SET's that have been incorporated into circuits involving more than one transistor. Specifically, Ono et al. constructed an inverter that operated at 27 K. Postma et al. [4] made a SET that operates at room temperature by using an AFM to buckle a metallic carbon nanotube in two places. The tube buckles much the same way as a drinking straw buckles when it is bent too far. Using this technique, a 25 nm section of the nanotube between the buckles was used as the island of the SET and a conducting substrate was used as the gate. The total capacitance achievable in this case is also about 1 aF. Pashkin et al. [2] used e-beam lithography to fabricate a SET with an aluminum island that had a diameter of only 2 nm. This SET had junction capacitances of 0.7 aF, a charging energy of 115 meV, and operated at room temperature. SET's have also been made by placing just a single molecule between closely spaced electrodes. Park et al. [5] built a SET by placing a C60 molecule between electrodes spaced 1.4 nm apart. The total capacitance of the C60 molecule in this configuration was about 0.3 aF. Individual molecules containing a Co ion bonded to polypyridyl ligands were also placed between electrodes only 1-2 nm apart to fabricate a SET. [6] In similar work, Liang et al. [7] placed a single divanadium molecule between closely spaced electrodes to make a SET. In the last two experiments, the Kondo effect was observed as well as the Coulomb blockade. The charging energy in the molecular devices was above 100 meV. One of the conclusions that can be drawn from this review of SET devices is that small SET's can be made out a of variety of materials. Single electron transistors with a total capacitance of
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about 1 aF were made with aluminum, silicon, carbon nanotubes and individual molecules. It seems unlikely that SET's with capacitances smaller than the capacitances of the molecular devices can be made. This sets a lower limit on the smallest capacitances that can be achieved at about 0.1 aF. Achieving small capacitances such as this has been a goal of many groups working on SET's. However, while some of the device characteristics improve as a SET is made smaller, some of the device characteristics get worse as SET's are made smaller. For some applications, the single molecule SET's are too small to be useful. As SET's are made smaller, there is an increase in the operating temperature, the operating frequency, and the device packing density. These are desirable consequences of the shrinking of SET devices. The undesirable consequences of the shrinking of SET's are that the electric fields increase, the current densities increase, the operating voltage increases, the energy dissipated per switching event increases, and the power dissipated per unit area increases, the voltage gain decreases, the charge gain decreases, and the number of Coulomb oscillations that can be observed decrease.

4. THE PROBLEMS: GAIN, HIGH OUTPUT IMPEDANCE, AND BACKGROUND CHARGES

Voltage gain is one of the properties of a SET that decreases as SET's are made smaller. This is because voltage gain decreases with decreasing gate capacitance. It is difficult to achieve a large gate capacitance when the island of a SET consists of a single molecule. For the single molecule devices, the gate capacitance can be as small as a few zeptoFarads. In this case, tens of volts have to be applied at the input to modulate the output by tens of millivolts. This results in a voltage gain on the order of 0.001; the transistors attenuate the signals by a factor of about 1000. The voltage gain in a SET is the ratio of the gate capacitance to the junction capacitance. As the gate capacitance is increased for fixed junction capacitance and fixed temperature, the voltage gain first increases and then it decreases. This is illustrated in Fig. 3(a) where the voltage gain is plotted as a function of gate capacitance for different temperatures. In all of the curves the junction capacitance is assumed to be 0.1 aF. The voltage gain increases with increasing gate capacitance until the charging energy is on the order of kBT and then the voltage gain drops sharply.

Thus for every junction capacitance and temperature, there is a maximum voltage gain. Figure 3(b) is a plot of the maximum gain. To determine the maximum gain, both the gate capacitance and the bias current of the SET were varied. The graph shows that it will be very difficult to make SET's with voltage gain greater than one that operate at room temperature. It will be even harder to get them to operate in a dense integrated circuit, which usually has a temperature of about 400 K. For room temperature voltage gain, the junction capacitance will have to be about 0.1 aF with a gat capacitance of 0.3 aF. This kind of SET has not yet been fabricated. So far, the largest voltage gain that has been observed is 5.2 and that was measured at 100 mK. [12] The highest temperature

Fig. 3(a) The voltage gain is plotted as a function of the gate capacitance and temperature for a junction capacitance of 0.1 aF. The voltage gain depends on the bias current. The bias current was adjusted to achieve maximum gain. The bias currents that were used were I = 1 nA at 4.2 K, I = 20 nA at 50 K, I = 50 nA at 100 K, I = 100 nA at 200 K, I = 200 nA at 300 K, I = 200 nA at 400 K, I = 300 nA at 500 K. (b) The maximum voltage gain possible for a given junction capacitance is plotted as a function of temperature. The currents which resulted in the maximum gain are given in the plot. where voltage gain greater than one was observed is 27 K. [3] While voltage gain at room temperature seems difficult, a voltage gain of 10 would be possible at 77 K, a voltage gain of 100 should be possible at 4.2 K, and a voltage gain of 1000 should be possible
8

at 100 mK. The low temperature SET's could be useful for sensitive low temperature measurements. Some of the circuit architectures that have been proposed for single-electron transistors are basically copies of the semiconducting architectures and require SET's with voltage gain. [13] Because of the limited gain of room temperature SET's, it now seems unlikely that dense integrated circuits based on these principles will ever be made. However, a transistor does not necessarily have to exhibit voltage gain to be useful. For single-electron transistors it is more relevant to consider the charge gain. The charge gain is the modulation of the charge that passes through the SET divided by the change in charge on the gate. This is a frequency dependent quantity. By waiting long enough, it is always possible to transport more charge through the SET than was added to the gate. Charge gain greater than one can easily be achieved at room temperature. The charge gain is maximum at low bias voltages and low temperatures where it is gcharge = (dI/dVg1)/(2fCg) = 1/(2fRC). Here f is the frequency at which the charge is modulated and R is the lower of the two junction resistances. This result can be derived from Eq. 4. Charge gain would be used in situations where charge needs to be measured, for instance to readout a memory cell or to readout a charge coupled device. The speed of the charge readout would be limited by the RC-delay formed by the resistance of the SET and the capacitance at the output of the SET. This capacitance depends on the parasitic capacitance of the wire at the output of the SET and the input capacitance of any devices connected to the SET. The parasitic capacitance of a wire is approximately 100 aF/m. The large output impedance of a SET of at least 100 k makes the SET an intrinsically slow device. To speed up the charge measurement, conventional field-effect transistors (FET's) should be placed as close as possible to the SET. The field-effect transistor can then buffer the high output impedance of the SET. Using both SET's and FET's in a circuit is a retreat from the idea that small SET's will someday replace FET's entirely. However, it now seems unlikely that SET's could ever replace FET's. Perhaps twenty different logic schemes that utilize single-electron transistors exclusively have been proposed but none is widely accepted as being practical. Until a practical scheme in developed, the best way to proceed is to use SET's only as sensitive charge sensors and perform all other functions with conventional FET's. The background charge problem is another important issue that is inhibiting the widespread use of SET's. The origin of the background charge problem is the extreme charge
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sensitivity of SET's. A single charged vacancy or an interstitial ion in the oxide near a SET can be enough to switch the transistor from the being conducting to being nonconducting. The same kinds of charged defects are present and move in field-effect transistors but most field-effect transistors are not as sensitive to charge so the consequences of these background charges are not as great. The only effective way to compensate for this problem is to use field-effect transistors to tune the background charges away. One circuit that accomplishes this is the charge-locked loop shown in Fig. 4(a). A charge-locked loop uses feedback to keep the charge on the island of a SET constant. This improves the speed, the linearity and the dynamic range of the charge measurements. The three problems of low gain, high output impedance, and sensitivity to background can all be remedied by combining SET's with FET's. In such hybrid

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Fig. 4. (a) A charged lock loop that automatically tunes away the background charge. Provided that the amplifier has enough gain, the voltage gain in this circuit is set by the ratio of the input and output capacitors Cin/Cout. The linearity and the dynamic range of the charge measurement are also improved by the charge-locked loop. The FET is used to current bias the SET. (b) The schematic of a current biased SET with a FET output stage and the corresponding SPICE simulation. The solid line is the voltage at the output voltage of the SET stage (node 2), and the dashed line is the voltage at the output of the FET stage (node 4). A voltage of 0.4 V has been subtracted from the voltage at node 4 to remove a dc offset. The SPICE source code for simulating the circuits shown can be found at http://qt.tn.tudelft.nl/research/set/spice/. circuits, the SET's provide the charge sensitivity while the FET's provide the gain and the low output impedance. In order to design SET/FET circuits, it is important to have a simulation package that will model both SET's and FET's. The simulation package SPICE is one of the few packages that will do this. [14] Figure 4(b) shows a single-electron transistor that is current biased by a FET and the corresponding SPICE simulation of the circuit. A second FET is used to buffer the output of the SET which increases the speed of the circuit.

5.BASIC PHYSICS OF SET OPERATION

Single Electron Transistor [SET] have been made with critical dimensions of just a few nanometer using metal, semiconductor, carbon nanotubes or individual molecules. A SET consist of a small conducting island [ Quantum Dot] coupled to source and drain leads bytunnel junctions and capactively coupled to one or more gate. Unlike Field Effect transistor, Single electron device based on an intrinsically quantum phenomenon, the tunnel effect. The electrical behaviour of the tunnel junction depends on how effectively barrier transmit the electron wave, which decrease exponentially with the thickness and on the number of electron waves modes that impinge on the barrier, which is given by the area of tunnel junction divided by the square of wave length. Quantum dot [QD] is a mesoscopic system in which the addition or removal of a single electron can cause a change in the electrostatic energy or Coulomb energy that is greater than the thermal energy and can control the electron transport into and out of the QD. This sensitivity to individual electrons has led to electronics based on single electrons. For QD, the discrete energy level of the electrons in the QD becomes pronounced, like those in atoms and molecules, so one can talk about artificial atoms and molecules. When the wave functions between two quantum
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dots overlap, the coupled quantum dots exhibit the properties of a molecule. To understand the electron transport properties in QD. Let us consider a metal nanoparticle sandwiched between two metal electrodes shown in figure 1. The nanoparticle is separated from the electrodes by vacuum or insulation layer such as oxide or organic molecules so that only tunneling is allowed between them. So we can model each of the nanoparticles-electrode junctions with a resistor in parallel with a capacitor. The resistance is determined by the electron tunneling and the capacitance depends on the size of the particle. We denote the resistors and capacitors by R1, R2, C1 and C2, and the applied voltage between the electrodes by V. We will discuss how the current, I depends on V. When we start to increase V from zero, no current can flow between the electrodes because movement of an electron onto (charging) or off (discharging) from an initially neutral nanoparticle cost energy by an amount given by equation 1. International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.4, December 2010

This suppression of electron flow is called Coulomb blockade. Current start to flow through the nanoparticles only when the applied voltage V is large enough to establish a voltage _ at the nanoparticles such that

This voltage is called threshold voltage and denoted by Vth. So in the I-V curve, we expect a flat zero-current regime with a width of 2Vth. When the applied voltage reaches Vth, an electron is added to (removed from) the nanoparticles. Further increasing the voltage, the current does not increase proportionally because it requires us to add (or remove) two electrons onto the nanoparticles, which cost a greater amount of energy. Once the applied voltage is large enough to overcome the Coulomb energy of two electrons, the current starts to increase again. This leads to a stepwise increase in I-V curve, called Coulomb staircase. , the current does not increase proportionally because it requires us to add (or remove) two electrons onto the nanoparticles, which cost a greater amount of energy.

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Figure 1. Quantum Dot Structure

6. THEORETICAL BACKGROUND
Throughout the history of single-electronics "orthodox" theory pioneered by Kulik and Shekhter play a very important role in understanding the behaviour of single electron devices. This is a very generalize theory based on the following major assumptions: A. The electron energy quantization inside the conductors is ignored, i.e. the electron energy spectrum is treated as continuous. This assumption is valid only if Ek << kBT, but it frequently gives an adequate description of observations as soon as Ek << Ec. B. The time _t of electron tunneling through the barrier is assumed to be negligibly small in comparison with other time scales (including the interval between neighbouring tunneling events). This assumption is valid for tunnel barriers used in single-electron devices of practical interest, Where _t ~ 10-15 s. C. Coherent quantum processes consisting of several simultaneous tunneling events ("cotunneling") are ignored. This assumption is valid if the resistance R of all the tunnel barriers of the system is much higher than the quantum unit of resistance RQ : R >>RQ,

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The orthodox theory is in quantitative agreement with virtually all the experimental data for systems with metallic conductors (with their small values of the electron wavelength on the Fermi surface, _F and gives at least a qualitative description of most results for most semiconductor structures (where the quantization effects are more noticeable due to larger _F). These assumptions are followed throughout the study of single electron systems.

7. APPLICATIONS OF SET
Supersensitive Electrometer The high sensitivity of single-electron transistors have enabled them as electrometers in unique physical experiments. For example, they have made possible unambiguous observations of the parity effects in superconductors. Absolute measurements of extremely low dc currents (~10-20 A) have been demonstrated. The transistors have also been used in the first measurements of single-electron effects in single-electron boxes and traps A modified version of the transistor has been used for the first proof of the existence of fractional-charge excitations in the fractional quantum hall effect. Single-Electron Spectroscopy One of the most important application of single-electron electrometry is the possibility of measuring the electron addition energies (and hence the energy level distribution) in quantum dots and other nanoscale objects. DC Current Standards One of the possible applications of single-electron tunneling is fundamental standards of dc current for such a standard a phase lock SET oscillations or Bloch oscillations in a simple oscillator with an external RF source of a well characterized frequency f. The phase locking would provide the transfer of a certain number m of electrons per period of external RF signal and thus generate dc current which is fundamentally related to frequency as I= mef. This arrangement have limitation of coherent oscillation that are Later overcome by the use of such a stable RF source to drive devices such as single-electron turnstiles and pumps , which do not exhibit coherent oscillations in the autonomous mode.

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Temperature Standards One new avenue toward a new standard of absolute temperature can be developed by the use of 1D single-electron arrays. At low temperatures, arrays with N>>1 islands exhibit dc I-V curves generally similar to those of single-electron transistors with a clear Coulomb blockade of tunneling at low voltages (|V|<Vt) and approaching the linear asymptote V = NRI + constant at (|V|Vt ). If the temperature is raised above Ec/kB, thermal fluctuations smear out the Coulomb blockade, and the I-V curve is almost linear at all voltages: G _ dIdV _ Gn_1NR The only remaining artifact of the Coulomb blockade is a small dip in the differential conductance around V=0. Detection of Infrared Radiation The calculations of the photo response of single-electron systems to electromagnetic radiation with frequency ~Ec h have shown that generally the response differs from that the well-known Tien-Gordon theory of photon-assisted tunneling. In fact, this is based on the assumption of independent (uncorrelated) tunneling events, while in single-electron systems the electron transfer is typically correlated. This fact implies that single-electron devices, especially 1D multi-junction array with their low co-tunneling rate, may be used for ultra-sensitive video- and heterodyne detection of high frequency electromagnetic radiation, similar to the superconductorinsulator-superconductor (SIS) junctions and arrays. The Single electron array have advantages over their SIS counterparts: Firstly lower shot noise and secondly convenient International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.4, December 2010 27 adjustment of the threshold voltage. This opportunity is especially promising for detection in the few-terahertz frequency region, where no background-radiation-limited detectors are yet available. Voltage State Logics The single-electron transistors can be used in the "voltage state" mode. In this mode, the input gate voltage U controls the source-drain current of the transistor which is used in digital logic circuits, similarly to the usual field-effect transistors (FETs). This means that the single-electron charging effects are confined to the interior of the transistor, while externally it looks like the usual electronic device switching multi-electron currents, with binary unity/zero presented with high/low dc voltage levels (physically not quantized). This concept simplifies the circuit design which may ignore all the single-electron physics particulars. One substantial disadvantage of
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voltage state circuits is that neither of the transistors in each complementary pair is closed too well, so that the static leakage current in these circuits is fairly substantial, of the order of 10-4 e/RC. The corresponding static power consumption is negligible for relatively large devices operating at helium temperatures. However, at the prospective room-temperature operation this power becomes on the order of 10-7 Watt per transistor. Though apparently low, this number gives an unacceptable static power dissipation density (>10 kW/cm2) for the hypothetical circuits which would be dense enough (>1011 transistors per cm2) to present a real challenge for the prospective CMOS technology. Charge State Logics The problem of leakage current is solved by the use of another logic device name charge state logic in which single bits of information are presented by the presence/absence of single electrons at certain conducting islands throughout the whole circuit. In these circuits the static currents and power vanish, since there is no dc current in any static state. Programmable Single Electron Transistor Logic An SET having non volatile memory function is a key for the programmable SET logic. The half period phase shift makes the function of SET complimentary to the conventional SETs. As a result SETs having non-volatile memory function have the functionality of both the conventional (n-MOS like) SETs and the complementary (p-MOS like) SETs. By utilising this fact the function of SET circuit can be programmed, on the basis of function stored by the memory function. The charged around the QD of the SET namely an SET island shift the phase of coulomb oscillation, the writing/erasing operation of memory function which inject/eject charge to/from the memory node near the SET island , makes it possible to tune the phase of coulomb oscillation. If the injected charge is adequate the phase shift is half period of the coulomb oscillation.

8. PROBLEMS IN SET IMPLEMENTATIONS

Lithography Techniques The first biggest problem with all single-electron logic devices is the requirement Ec~100kBT, which in practice means sub-nanometer island size for room temperature operation. In VLSI circuits, this fabrication technology level is very difficult. Moreover, even if these islands are fabricated by any sort of nanolithography, their shape will hardly be absolutely regular. Since in such small conductors the quantum kinetic energy gives a dominant contribution to the electron
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addition energy (Ek >> Ec,), even small variations in island shape will lead to unpredictable and rather substantial variations in the spectrum of energy levels and hence in the device switching International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.4, December 2010 28 Background Charge The second major problem with single-electron logic circuits is the infamous randomness of the background charge. A single charged impurity trapped in the insulating environment polarizes the island, creating on its surface an image charge Q0 of the order of e. This charge is effectively subtracted from the external charge Qe Cotunneling The essence of the effect is that the tunneling of several (N>1) electrons through different barriers at the same time is possible as a single coherent quantum-mechanical process. The rate of this process is crudely (RQ/R)N-1 times less than that for the single-electron tunneling described by Equation of the orthodox theory G(DW) = (1/e) I(DW/e) [1 - exp{-DW/kBT}]-1 (4) If the condition expressed by equation (3) is satisfied this ratio is rather small; cotunneling can nevertheless be clearly observed within the Coulomb blockade range where orthodox tunneling is suppressed. Room Temperature Operation The first big problem with all the known types of single-electron logic devices is the requirement Ec ~ 100 kBT, which in practice means sub-nanometer island size for room temperature operation. in such small conductors the quantum kinetic energy gives a dominant contribution to the electron addition energy even small variations in island shape will lead to unpredictable and rather substantial variations in the spectrum of energy levels and hence in the device switching thresholds. Linking SETs with the Outside Environment The individual structures patterns which function as logic circuits must be arranged into larger 2D patterns. There are two ideas. The first is to integrating SET as well as related equipments with the existed MOSFET, this is attractive because it can increase the integrating density. The second option is to give up linking by wire, instead utilizing the static electronic force between
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the basic clusters to form a circuit linked by clusters, which is called quantum cellular automata (QCA). The advantage of QCA is its fast information transfer velocity between cells (almost near optic velocity) via electrostatic interactions only, no wire is needed between arrays and the size of each cell can be as small as 2.5nm, this made them very suitable for high density memory and the next generation quantum computer.

9.SINGLE ELECTRON SYSTEMS IN THE SUPERCONDUCTING STATE

When operated in the superconducting state, the behavior of the SET-box circuit is markedly dierent from its normal-state behavior. The aluminum comprising the leads and island of both the SET and the box is described by a BCS ground state, instead of a Fermi sea of electrons, and shows eects due to the coherent nature of that state [rst noted in (Buettiker, 1987); rst studied in detail in (Bouchiat, 1997)]. The box, which is renamed the \Cooper pair box," is able to support coherent superpositions of dierent charge states and is capable of operation as a coherent quantum two-level system. The response of the SET, meanwhile, is complicated by tunneling processes that combine both quasiparticle and single electron tunneling. The combined eects of these changes motivate an understanding of SET backaction in the superconducting state that is entirely dierent from the normal state theory presented . In this chapter, I will provide theoretical background for the understanding of our system in the superconducting state. In section 3.2, I begin by describing our understanding of how tunneling between superconductors diers from the normal metal tunneling described in chapter 2. In section 3.3, the operation of the Cooper pair box will be explained within this framework. Section 3.4 will treat the changes that superconductivity introduces into the operation of the SET. Finally, in section 3.5, I will combine our understanding of these two systems within a density matrix framework to describe the backaction of the superconducting SET on the Cooper pair box.

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Figure 3.1: \Semiconductor model" of tunneling in superconductors. The density of quasiparticle states in a superconductor is shown as a function of energy for two superconductors separated by an insulating barrier. Filled states are indicated in gray, while empty states are indicated in white. Quasiparticle tunneling between superconductors will occur when a quasiparticle can tunnel from a lled state in one superconductor to an empty state in the other superconductor at the same energy.

Tunneling in the Superconducting State

In a superconductor, free electrons join together to form Cooper pairs, which form a condensate and give rise to the unique behaviors that characterize superconductors. Because of this new charge carrier, tunneling between superconductors is more complicated than in the normal state, and two dierent tunneling processes contribute to an overall current: depending on the bias conditions, charge moves across an insulating barrier either as Cooper pairs (understood through the Josephson Eect) or as broken Cooper pairs (which we consider to be electron-like excitations above the superconducting condensate called \quasiparticles"). In this section, I will describe the conditions required for each of these two dierent types of tunneling, in order to motivate our understanding of the operation of the SET and Cooper pair box. Theory of the Superconducting Cooper Pair Box As in the normal state, the simplest Josephson junction circuit that we can construct consists of a single island, connected to ground with a Josephson junction, and capacitively coupled to a voltage bias (see gure 3.3); in the superconducting state, this circuit is usually termed the \Cooper pair box." As we have drawn it, this circuit does not dier from the single electron box discussed. However, because of the coherence of the superconductors discussed in section (3.2.3), the Cooper pair box can show markedly dierent behavior from the analogous normal state system. It has been shown to operate as a coherent quantum two-level system, with an energy level splitting that may be probed spectroscopically (Nakamura et al., 1997). The group of Nakamura has demonstrated coherent control of the Cooper pair box (Nakamura et al., 1999), and earlier measurements in our lab have measured its excited state lifetime (Lehnert et al., 2003b). Current studies of the Cooper pair box focus on its manipulation and use as a candidate component of a quantum computer (Devoret et al., 2004). In this section, I will describe the operation of the Cooper pair box within the larger context of the study of quantum two-level systems. I will provide only the background necessary for an
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understanding of the experiments performed in this thesis; the reader is referred to (Abragam, 1983; Slichter, 1990) for more extensive discussions of possible experiments that may be performed with quantum two-level systems, and to (Cottet, 2002; Schuster, 2007) for descriptions of recent experiments that have been performed on superconducting two-level systems.

10.THEORY OF THE SUPERCONDUCTING SINGLE ELECTRON TRANSISTOR

As with the box, the physical layout of the superconducting SET does not dier from its normal state analog; the only physical dierence between the superconducting and the normal SET is the state of the metal comprising the device. The method of superconducting SET measurement, furthermore, is exactly the same as in the normal state: a response curve of the SET alone is measured, and then used to calibrate the response of the SET to an external voltage signal. A detailed description of this methodology may be found in section 5.5. While the methodology of SET measurement is the same, the processes underlying its operation are quite dierent. Because of the increased complexity of tunneling in the superconducting state, the response and the backaction of the superconducting SET are understood in a dierent and more complex fashion than that of the normal state SET. In this section, I discuss the basic mechanisms of current ow in the superconducting SET. This is not intended to be an exhaustive treatment of the subject, but rather to provide suitable background for our analysis of superconducting SET backaction. I will focus my discussion on the mechanisms of tunneling in the superconducting SET, and the conditions under which dierent types of tunneling will occur. Readers who are interested in a more thorough explanation are referred to (Pohlen, 1999) for further information. Theoretical description of SET Backaction in the Super- conducting State In this section, I will treat the mathematical details of the model used to predict the superconducting SET's backaction. This discussion will focus on the technical details underlying the calculations that we performed; a more phenomenological discussion of these results, oriented towards experimentally measurable eects, will follow in section 3.6. There are two fundamental dierences between our calculation of superconducting state back- action and the backaction modeling performed in the normal state. First, because the Cooper pair box is a

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coherent quantum two level system (TLS), we must account for backaction and noise within the context of quantum mechanics. In order to simplify the resulting calculation, we introduce a second change: we consider the backaction in the weak coupling limit. Before launching into a full description of our model, I should briey explain the content and the ramications of these two statements. To understand our treatment of backaction in the superconducting state, it is instructive to contrast superconducting tunneling with our treatment of tunneling in the normal state. Tunneling rates in the normal state were calculated from the quantum mechanical coupling of single electron states in the leads to states on the box island. There are a fantastic number of such states, and our calculations considered the combined eects of many couplings between individual states and a continuum; each such coupling is very weak4. The weak tunnel coupling and the continuous density of target states allowed us to presume that, once an electron had tunneled onto the island,

11.FABRICATION OF SAMPLES
Samples for the normal state measurements described in this thesis, and for the rst superconducting measurements, were fabricated at Chalmers University in Sweden, by David Gunnarsson, in the group of Per Delsing. For later measurements (after 2003), and particularly for those where the environmental impedance of the Cooper-pair box was considered and carefully engineered, samples were fabricated at Yale. The vast majority of the fabrication work at Yale was completed by Hannes Majer, to whom I am indebted; the following description, of the work done at Yale, is little more than an overview of his process, distilled from the few months where I was assisting him. Dolan Bridge Fabrication Process All samples measured were fabricated out of Aluminum-Aluminum Oxide-Aluminum tunnel junc- tions, using the Dolan bridge double-angle evaporation technique and electron-beam lithography. The Dolan bridge uses a bilayer of two dierent resists: A thick ( 700 nm) bottom layer of easily- developed resist is rst deposited, followed by a thinner ( 100 nm) upper layer which requires a much larger dose to be developed. The two dierent resists used were dierent formulations of Polymethyl Methacrylate (PMMA). An electron beam then selectively exposed a pattern in the resist corresponding to our sample design. The electron beam was provided by a Sirion FEI scanning electron microscope, converted for electron-beam lithography using the Nanometer Pattern Generator System (NPGS)
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software produced JC Nabity Lithography Systems, Inc. (http://www.jcnabity.com/). Beam doses were adjusted so that the pattern was faithfully represented in the upper layer of resist, while the lower layer of resist was developed over a much wider area { thus producing a region of \undercut." In

Figure 4.1: Schematic of Dolan Bridge/double angle evaporation technique for fabrication of Joseph- son junctions. A bridge of resist (shown in cross section) is suspended above a silicon substrate. Aluminum is evaporated at two dierent angles, with an oxidation between the evaporations, to produce two metal reservoirs connected by a tunnel junction.

Figure 4.2: SEM Image of Box-SET Sample. The box is in the left half of the image, while the SET is in the right half of the image. The \ghost" image from the double-angle evaporation process is clearly visible. regions where two exposed areas are nearby, this undercut can create suspended bridges (see gure 4.1) Aluminum was then evaporated at two dierent angles onto the resulting mask. If the bridge is designed correctly, then images of these two separate evaporations will overlap in the area underneath the bridge (see gure 4.1b). If a small amount of an argon-oxygen mixture is introduced into the evaporator between the two evaporations, a thin oxide barrier will grow on
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the surface of the bottom evaporation. This oxide barrier will have a typical thickness of a few atomic layers: thick enough that uctuations in thickness do not create short circuits between the two leads, and yet thin enough that electrons are able to tunnel between the two aluminum reservoirs. The resulting samples could then be viewed in the SEM, although doing so usually destroyed the Josephson junctions in our devices. An SEM image of one of our samples is shown in gure 4.2, where the \ghost" image from the double angle evaporation process is clearly visible. Junctions are formed where the two evaporations overlap { where the leads, extending from the top of the image, overlie the islands, which are in the middle of the image. Design considerations While the theory of SET fabrication may be simple, in practice it proved to be one of the most dicult tasks encountered in the completion of this thesis. This was due, however, largely to the strict requirements for devices: our design required that electron-beam lithography be accurately executed at an extremely wide range of size scales. Small junctions in the SET required accurate lithographical features smaller than 100 nm, while careful engineering of the environmental impedance required wide scale exposure across a 5 mm chip. The following sections describe the various requirements imposed by dierent facets of our experiment, how these requirements translated into considerations for our fabrication process. SET Design Considerations Modulations in conductance in the SET are caused by Coulomb blockade (see section 2.2.2), where a single electron added to the SET island causes an increase in electrostatic energy that forbids the addition of further electrons. The characteristic energy for this process is the charging energy of the SET (EC = e2 2C ), typically expressed in Kelvin. We require that this energy scale be large relative to the other relevant energy scales in the problem. In particular, this charging energy must be much larger than the available thermal energy (kBT), so that thermal excitations cannot bring additional electrons onto a blockaded island. Measurements in the superconducting state imposed a further, stricter restriction on the charging energy of the device: for a SET to have a DJQP feature, the preferred operating point for our superconducting measurements, its charging energy must satisfy 2 > EC > 2 3(Pohlen, 1999),

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where , the superconducting gap of Aluminum, was typically found to be 190 V. For the purposes of our fabrication, this meant that SETs must be fabricated with EC > 1:45K or, more practically, must have a total island capacitance less than approximately 600 aF. The total capacitance of the SET island contained contributions from the geometric capacitance of the SET island, and from the SET junctions. The geometric capacitance of the SET island to grounded leads nearby was typically 200 aF. This number would vary somewhat with our particular design, but could be eectively calculated using electrostatic modeling software such as Ansoft Maxwell. The capacitance of the junctions, which consist of a thin insulating barrier between two large conductors, is typically proportional to their area. The limit on the total island capacitance therefore translated into a requirement that the Josephson junctions in the SET be small. For the junctions fabricated at Chalmers, the junction capacitance was found to be approximately 50 fF=m2 of junc- tion area; The capacitance per area of junctions fabricated at Yale was probably not signicantly dierent. After accounting for the 200 aF geometric capacitance of our SET island, we found our- selves constrained to fabricate SET junctions with a total capacitance less than 400 aF { which could therefore be no larger than approximately 70 nm square. Fabricating such small junctions is a dicult task; it requires very precise electron beam doses, patterned with extreme accuracy. The requirements of our particular junctions were at the limits of the capabilities of the electron-beam pattern generating system we used. 4.3 Additional Fabrication Ventures Of the many side inquiries and blind alleys explored in the fabrication of samples for this thesis, one particular venture deserves mention in this work. This work, done as an attempt to x problems seen in the penultimate round of Yale-made samples, ultimately proved unsuccessful. We report it here so that future work does not fall prey to the same trap. All circuit diagrams shown thus far in this thesis, and all diagrams used for fabrication, show the Cooper-pair box as an isolated metal island, connected via tunnel junctions to a very large grounded reservoir. When samples with this design were measured the Coulomb staircase was almost always purely periodic in 1 electron of gate charge (detailed measurements of this \quasiparticle poisoning" are discussed in section 7.5). This is a situation that is by no means universally true of Cooper-pair box samples: Cooper pair box samples measured in 2003 at Yale, and samples measured by other groups have shown pure Cooper-pair periodicity in the box
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response(Bladh, 2005). Nevertheless, for reasons that are poorly understood, all of the samples fabricated at Yale were aected by this poisoning to some degree. It has been suggested that this poisoning was due to a ready availability of quasiparticles from the Cooper-pair box's reservoir (a theoretical explanation of this idea is provided in section 7.5). According to this thinking, the 2 free energy cost for the addition of a quasiparticle to the Cooper pair box's island does not need to be paid if a population of quasiparticles is readily available in the superconducting reservoirs. Such analyses typically describe a new, \eective" superconducting gap which describes the apparent energy required to create quasiparticles, as a pure a posteriori consideration. On initially seeing quasiparticle poisoning in Yale-fabricated Cooper-pair box samples, it was hypothesized that this was due to the large CPW ground planes. The SET, according to this argument, is breaking and recombining Cooper pairs as current is owing (see section 3.4 for a description of SET operation); when these Cooper pairs recombine, the binding energy is released

Figure 4.4: a) Traditional Cooper-pair box design, where the CPB box island is directly connected to the large CPW ground planes. b) \Floating Island" sample design, where the reservoir for the Cooper-pair box is a small cutout of the larger CPW ground plane. into the substrate as phonons, each with exactly 2 of energy. The large ground planes in the Yale-fabricated samples are thought to act as \antennas" for these 2 phonons; their larger area creates a larger cross-section for the phonons to poison the CPB reservoir.
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A proposed remedy to this was the so-called \Floating Island" Cooper-pair box design (see gure 4.4b). In this design, a path is cut through the CPW ground plane near the CPB, so that the reservoir coupled to the box is signicantly smaller than the entire CPW ground plane. According to this logic, the smaller reservoir will have a smaller cross-section for absorbtion of 2 phonons from the substrate, and may be more immune to quasiparticle poisoning. In designing the oating island, careful consideration was paid to the eects of this new design on the coupling capacitances within the circuit. In the \standard" Box-SET design (gure 4.4a), the reservoir of the box was grounded, and voltages coupled to the box increased its potential relative to ground. In the \oating island" design, however, box gate voltages couple to both the box island and its reservoir. The charge coupled to the box, ngb, will then be determined by the dierence in these two voltages; if the island is poorly designed, then this dierence may be small, and we may eectively lose control of our box. In the same manner, we require that the island and the reservoir are coupled to the SET island by signicantly dierent capacitances, so that the SET response from an additional Cooper pair on the box island is not cancelled by the capacitively coupled loss of charge from the reservoir. These capacitances were modeled using Ansoft Maxwell, and were found to be dierent enough that a measurement was deemed possible. Unfortunately, measurement of a \oating island" sample still showed quasiparticle poisoning. These results are in sad agreement with other groups' attempts to engineer around quasiparticle poisoning (Gunnarsson, 2005), and serve, above all, to illustrate how poorly quasiparticle poisoning in these systems is understood.

12.APPARATUS AND MEASUREMENT TECHNIQUES

The experimental design underlying the measurements made for this thesis integrated careful engi- neering from many dierent disciplines. Samples were measured in a precisely machined cryogenic apparatus and controlled by leads that could transmit accurate electrical impulses across a wide band of frequencies. Careful microwave engineering was required for the readout of our RF-SETs. The entire measurement was then controlled by complicated suites of software that coordinated the control of our measurement. This chapter will discuss the design of each of these facets of our experiment, and will explain our motivation for assembling our experiment as we did. In the rst part of this chapter, I will describe our physical setup, and how we engineered it to the
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requirements of our experiment. This will involve a discussion of the cryogenic (section 5.1.1), electrical (section 5.1.2), and RF (section 5.2) engineering considerations that were taken into account when physically assembling our experimental apparatus. I will then move on to the specic details of the electrical control and readout of our measurement. This will involve a discussion of the electronics used to generate signals and measure our experiment's response (section 5.3), followed by a discussion of the RF tank circuit design that permitted SET readout with high bandwidth (section 5.4). The nal part of this chapter will explain the software and algorithms that were used to measure our system's response in various ways. I will start, in section 5.5, with a discussion of the basic methodology we used to make calibrated RF-SET measurements. This basic software was developed to circumvent the eects of parasitic capacitances in our system; the methodology by which we measured and compensated for these capacitances is described in section 5.6. Section 5.7 will describe how, using our ability to compensate for parasitic capacitances and independently control the box and the SET, we were able to implement slow feedback techniques that counteracted the eects of charge noise on our sample. Finally, in section 5.8, I will close with a brief discussion of techniques that were used for more exotic measurements of our experiment, including time-domain observation of the state of the Cooper pair box.

13.IMPACT
The work described in this thesis is notable both for the results it presents and for the techniques that were employed to nd them. Our most central results describe the theoretical treatment and experimental observation of backaction eects arising when a mesoscopic amplier, the SET, measures a nanoscale system. Other groups concerned with SET measurement will nd these results immediately useful for their description of the nature, the magnitude, and the variation of backaction in SET systems. The general framework in which backaction was theoretically considered { by modeling the collective evolution of strongly coupled systems { will also be of more general use to groups studying other mesoscopic amplication systems. The experimental techniques used for data acquisition in this thesis are also notable. Our measurements were based on algorithms that, concurrent with our data acquisition, observed and rejected the eects of charge oset noise coupled to our devices. Rejecting this noise eectively
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eliminated slow gain drifts in the SET, and allowed us to average the output of our experiment almost inde- nitely. This permitted SET measurement with unprecedented precision, and facilitated many of the measurements in this thesis. Any future groups interested in highprecision SET electrometry are well advised to employ similar methods.

14.Future Work
While the normal state measurements presented in this thesis were conclusive and complete, the superconducting state measurements made in this thesis call for more research. The formalism of quantum noise that we used to model our system in the superconducting state predicted eects that are consistent with the results of some of our measurements, but do not fully explain our results. Further SET-Cooper pair box work could use the formalisms discussed in this thesis and the techniques that we developed to search for these same eects. Such work would serve as a valuable proof of the eects of noise on a quantum mechanical system. Such measurements were not completed in our lab because the samples that we fabricated all experienced serious problems with quasiparticle poisoning. Our observation of trends in poisoning with SET operation suggest that it is another form of SET backaction, but the microscopic details

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15. CONCLUSIONS
Single Electronic Transistor (SET) has proved their value as tool in scientific research. Resistance of SET is determined by the electron tunneling and the capacitance depends on the size of the nanoparticle. The current starts to flow through the junction when applied voltage is just sufficient to raise the energy of electron above the coulomb blocked, this is called threshold voltage Vth and the flat zero current persist for 2Vth. Several applications of nanoscale devices in metrology, including the fundamental standards of current, resistance and temperature also seem quite promising. Another potential application is terahertz radiation detection. The situation is much more complex with digital single electronics. The concept of single electron logic suggested so far face sturdy challenges: either removing background charge or providing continuous charge transfer in nanoscale. The main problem in nanometer era is the fabrication International International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.4, December 201029of nanoscale devices. SET provide the potential for low-power, intelligent LSI chips,appropriate for ubiquitous application.

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16.REFERENCE
Detection of single-charge polarisation in silicon double quantum dots by using seriallyconnected multiple single-electron transistors Kawata, Y.; Oda, S.; Tsuchiya, Y.; Mizuta, H. Solid-State Device Research Conference, 2008. ESSDERC 2008. 38th European Digital Object Identifier: 10.1109/ESSDERC.2008.4681763 Publication Year: 2008 , Page(s): 322 325 Silicon single-electron transistors on a SIMOX substrate Murase, K.; Talahashi, Y.; Fujiwara, A.; Nagase, M.; Tabe, M. Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages; IFIP International Conference on Very Large Scale Integration., Asian and South Pacific Digital Object Identifier: 10.1109/ASPDAC.1995.486389 Publication Year: 1995 , Page(s): 697 698 Study of Single-Charge Polarization on a Pair of Charge Qubits Integrated Onto a Silicon Double Single-Electron Transistor Readout Kawata, Y.; Tsuchiya, Y.; Oda, S.; Mizuta, H. Nanotechnology, IEEE Transactions on Volume: 7 , Issue: 5 Digital Object Identifier: 10.1109/TNANO.2008.2004408 Publication Year: 2008 , Page(s): 617 623 Room temperature operation of a-C based single electron transistors Yamada, A.; Numaguchi, T.; Miura, N.; Konagai, M. Device Research Conference Digest, 1998. 56th Annual Digital Object Identifier: 10.1109/DRC.1998.731112 Publication Year: 1998 , Page(s): 40 - 41 Analog-digital and digital-analog converters using single-electron and MOS transistors

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Xiaobin Ou; Nan-Jian Wu Nanotechnology, IEEE Transactions on Volume: 4 , Issue: 6 Digital Object Identifier: 10.1109/TNANO.2005.858600 Publication Year: 2005 , Page(s): 722 - 729 Cited by: 9 A Novel Hybrid Phase-Locked-Loop Frequency Synthesizer Using Single-Electron Devices and CMOS Transistors Wancheng Zhang; Nan-Jian Wu Circuits and Systems I: Regular Papers, IEEE Transactions on Volume: 54 , Issue: 11 Digital Object Identifier: 10.1109/TCSI.2007.907886 Publication Year: 2007 , Page(s): 2516 - 2527 Cited by: 3 GaAs single electron transistors and logic inverters based on Schottky wrap gate structures Kasai, S.; Hasegawa, H. Device Research Conference, 2000. Conference Digest. 58th DRC Digital Object Identifier: 10.1109/DRC.2000.877129 Publication Year: 2000 , Page(s): 155 - 156 Cited by: 1 Single-electron transistors based on gate-induced Si island for single-electron logic application Dae Hwan Kim; Suk-Kang Sung; Kyung Rok Kim; Jong Duk Lee; Byung-Gook Park Nanotechnology, IEEE Transactions on Volume: 1 , Issue: 4 Digital Object Identifier: 10.1109/TNANO.2002.807382 Publication Year: 2002 , Page(s): 170 - 175 Cited by: 3

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Contents
Page No. 1. Introduction 2. Set Basics 3. Types Of Single-Electron Transistors 4. The Problems: 5.Basic Physics Of Set Operation 6. Theoretical Background 7. Applications Of Set Supersensitive Electrometer Dc Current Standards Temperature Standards Detection Of Infrared Radiation Voltage State Logics Charge State Logics Programmable Single Electron Transistor Logic 8. Problems In Set Implementations Lithography Techniques Background Charge Cotunneling Room Temperature Operation Linking Sets With The Outside Environment 9.Single Electron Systems In The Superconducting State Tunneling In The Superconducting State Theory Of The Superconducting Cooper Pair Box 10.Theory Of The Superconducting Single Electron Transistor 11.Fabrication Of Samples Design Considerations Set Design Considerations 12.Apparatus And Measurement Techniques 13.Impact 14.Future Work 15. Conclusions 16.Reference 1 2 5 7 11 13 14 14 14 15 15 15 16 16 16 16 17 17 17 17 18 19 19 20 21 23 23 26 27 28 29 30

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