Natural PFC Led Lighting Driver Controller: Features Description

TPS92210
www.ti.com SLUS989A JANUARY 2010 REVISED DECEMBER 2010
NATURAL PFC LED LIGHTING DRIVER CONTROLLER

Check for Samples: TPS92210
1
FEATURES
Flexible Operation Modes Constant On-Time Enables Single Stage PFC Implementation Peak Primary Current Cascoded MOSFET Configuration Fully Integrated Current Control Without Sense Resistor Fast and Easy Startup Discontinuous Conduction Mode or Transition Mode Operation Transformer Zero Energy Detection Enables Valley Switching Operation Helps to Achieve High Efficiency and Low EMI Open LED Detection Advanced Overcurrent Protection Output Overvoltage Protection Line Surge Ruggedness Internal Over-Temperature Protection 8-Pin SOIC (D) Package
DESCRIPTION
The TPS92210 is a natural power factor correction (PFC) light emmitting diode (LED) lighting driver controller with advanced energy features to provide high efficiency control for LED lighting applications. A PWM modulation algorithm varies both the switching frequency and primary current while maintaining discontinuous or transition mode operation in all regions of operation. The TPS92210 cascode architecture enables low switching loss in the primary side and when combined with the discontinuous conduction mode (DCM) operation ensures that there is no reverse recovery loss in the output rectifier. These innovations result in efficiency, reliability or system cost improvements over a conventional flyback architecture. The TPS92210 offers a predictable maximum power threshold and a timed response to an overload, allowing safe handling of surge power requirements. The overload fault response is user-programmed for retry or latch mode. Additional protection features include open-LED detection by output overvoltage protection and thermal shutdown. The TPS92210 is offered in the 8-pin SOIC (D) package. Operating junction temperature range is 40C to 125C
APPLICATIONS
TRIAC Dimmable LED Lighting Designs Residential LED Lighting Drivers for Retrofit A19 (E27/26, E14), PAR30/38, GU10, MR16, BR Drivers for Down and Architectural Wall Sconces, Pathway and Overhead Lighting Commercial Troffers and Downlights
VIN AC +
4 3 2 1
TPS92210 OTM VCG PCL TZE FB DRN GND VDD
5 6 7 8 LED ISENSE and Conditioning VOUT
UDG-09152
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2010, Texas Instruments Incorporated
TPS92210
SLUS989A JANUARY 2010 REVISED DECEMBER 2010 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
OPERATING TEMPERATURE RANGE, TA 40C to 125C PACKAGE ORDERABLE DEVICE NUMBER TPS92210DR TPS92210D PINS TRANSPORT MEDIA Tape and Reel Tube QUANTITY 2500 75
SOIC
ABSOLUTE MAXIMUM RATINGS (1)

All voltages are with respect to GND, 40C < TJ = TA < 125C, all currents are positive into and negative out of the specified terminal (unless otherwise noted)
LIMIT VDD DRN, during conduction DRN, during non-conduction Input voltage range VCG (2) TZE, OTM, PCL (3) FB (3) VDD VCG Continuous input current Input current range Output current Operating junction temperature Storage temperature range Lead temperature (1) (2) (3) IVCG DRN DRN, pulsed 200ns, 2% duty cycle TJ Tstg Soldering, 10 s
(2) (3)
UNIT
0.5 to +25 0.5 to +2.0 20 0.5 to +16 0.5 to +7 0.5 to +1.0 7 to +10 10 3 to +1 -4 6 to +1.5 40 to +150 65 to +150 +260 C C C A mA V
ITZE, IOTM, IPCL, IFB
These are stress ratings only. Stress beyond these limits may cause permanent damage to the device. Functional operation of the device at these or any conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods of time may affect device reliability Voltage on VCG is internally clamped. The clamp level varies with operating conditions. In normal use, VCG is current fed with the voltage internally limited In normal use, pins OTM, PCL, TZE, and FB are connected to resistors to GND and internally limited in voltage swing
(2)
PACKAGE DISSIPATION RATINGS (1)

PACKAGE SOIC-8 (D) (1) (2) (3) qJA, THERMAL IMPEDANCE JUNCTION TO AMBIENT, NO AIRFLOW (C/W) 165 (1)
qJB, THERMAL IMPEDANCE JUNCTION TO BOARD, NO AIRFLOW (C/W) 55 (1)
TA = 25C POWER RATING (mW) 606 (3)
TA = 85C POWER RATING (mW) 242 (3)
TB = 85C POWER RATING (mW) 730 (2) (3)
Tested per JEDEC EIA/JESD51-1. Thermal resistance is a function of board construction and layout. Air flow reducex thermal resistance. This number is included only as a general guideline; see TI document (SPRA953) device Package Thermal Metrics. Thermal resistance to the circuit board is lower. Measured with standard single-sided PCB construction. Board temperature, TB, measured approximately 1 cm from the lead to board interface. This number is provided only as a general guideline. Maximum junction temperature, TJ, equal to 125C
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TPS92210
RECOMMENDED OPERATING CONDITIONS

Unless otherwise noted, all voltages are with respect to GND, 40C < TJ = TA < 125C. Components reference Figure 17.
MIN VDD VCG IVCG ROTM RPCL RTZE1 CVCG CBP Input voltage Input voltage from low- impedance source Input current from a high impedance source Resistor to GND Resistor to GND Resistor to auxiliary winding VCG capacitor VDD bypass capacitor, ceramic Shutdown/retry mode Latch-off mode 9 9 10 25 150 24.3 50 33 0.1 MAX 20 13 2000 100 750 100 200 200 1.0 UNIT V A k k k nF mF
ELECTROSTATIC DISCHARGE (ESD) PROTECTION

MAX ESD Rating, Human Body Model (HBM) ESD Rating, Charged Device Model (CDM) 2 500 UNIT kV V
TPS92210
ELECTRICAL CHARACTERISTICS
Unless otherwise stated: VVDD= 12 V, VVCG= 12 V, VTZE= 1 V, VFB= 0 V, GND= 0 V, a 0.1-mF capacitor exists between VDD and GND, a 0.1-mF capacitor exists between VCG and GND, RPCL=33.2 k, ROTM= 380 k, 40C < TA< +125C, TJ= TA
PARAMETER VDD and VCG SUPPLY VCG(OPERATING) VCG(DISABLED) VCG IVCG(SREG) VCG(SREG) VCG(LREG) VCG(LREG, VDD(ON) VDD(OFF) VDD(UVLO) IVDD(OPERATING) IVDD(LPM) IVDD(UVLO) RDS,ON(VDD) VDD(FAULT
RESET) DO)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VCG Voltage, Operating VCG Voltage, PWM Disabled Rise in VCG Clamping Voltage During UVLO, LPM, or Fault VCG Shunt Regulator Current VCG Shunt Load Regulation VCG LDO Regulation Voltage VCG LDO Dropout Voltage UVLO Turn-on Threshold UVLO Turn-off Threshold UVLO Hysteresis Operating Current Idle Current Between Bursts Current for VDD < UVLO VDD Switch on Resistance, DRN to VDD VDD for Fault Latch Reset
VDD = 14 V, IVCG = 2.0 mA VDD = 12 V, IVCG = 15 mA, IFB = 350 mA VCG(DISABLED) VCG(OPERATING) VCG = VCG(DISABLED) - 100 mV, VDD = 12 V 10 mA IVCG 5 mA, IFB = 350 mA VDD = 20 V, IVCG = 2 mA VDD VCG, VDD = 11 V, IVCG = 2 mA
13 15 1.75
14 16 2 6 125 13
15 17 2.15 10 200
V V V mA mV V
1.5 9.7 7.55 1.9
2 10.2 8 2.2 3 550 225 4
2.5 10.7 8.5 2.5 3.7 900 300 10 6.4
V V V V mA mA mA V
VDD= 20 V IFB = 350 mA VDD = VDD(on) 100 mV, increasing VCG = 12 V, VDD == 7V, IDRN = 50 mA
2.5
5.6
MODULATION tSW(HF) tSW(LF)

(1)
Minimum Switching Period, Frequency Modulation (FM) mode Maximum Switching Period, Reached at end of FM Modulation Range Maximum Peak Driver Current Over Amplitude Modulation(AM) Range Minimum Peak Driver Current Reached at End of AM Modulation Range Maximum Power Constant Minimum Peak Driver Independent of RPCL or AM Control Leading Edge Current Limit Blanking Time Voltage of PCL
IFB = 0 mA,
(1)
7.125
(1)
7.5 34 3 0.9 0.85 0.33 0.60 0.45 220
7.875 38 3.15 1.0 1.1 0.5 0.66 0.6
ms ms A A A A W/mH A ns
(1)
IFB = IFB, CNR3 20 mA,
31 2.85 0.8 0.7 0.2 0.54 0.3
IDRN(peak,max) IDRN(peak,min) KP IDRN(peak,absmin) tBLANK(ILIM) PCL IFB,CNR1

(2)
IFB = 0 mA, RPCL = 33. 2 k IFB = 0 mA, RPCL = 100 k IFB, IFB,
CNR2 CNR2
+ 10 mA, RPCL = 33.2 k + 10 mA, RPCL = 100 k
For IDRN(peak,max) = 3 A RPCL = OPEN IFB = 0 mA, RPCL = 100 k, 1.2-A pull-up on DRN IFB = 0 mA IFB = (IFB,CNR3 20 mA) (1) IFB increasing, tSW = tSW(LF), and IDRN(PK,) = IDRN,PK(MAX) tSW = tSW(LF), IDRN PK ranges from IDRN,PK(MAX) to IDRN,PK(MIN) IFB increasing until PWM action is disabled entering a burst-off state IFB decreasing from above IFB,CNR3 IFB = 10 mA
2.94 0.95 145 35 50 10 0.34
3 1 165 45 70 25 0.7
3.06 1.05 195 65 90 40 0.84
V mA mA mA mA V
IFB range for FM modulation

(2)
IFB,CNR2 IFB,CNR1 IFB,CNR3 IFB,CNR2 IFB, FB

LPM-HYST (2)
IFB range for AM modulation IFM range for Low Power Mode(LPM) modulation IFB hysteresis during LPM modulation to enter burst on and off states Voltage of FB
(2)
(1)
(2)
tSW sets a minimum switching period. Following the starting edge of a PWM on time, under normal conditions, the next on time is initiated following the first valley switching at TZE after tSW. The value of tSW is modulated by IFB between a minimum of tSW(HF) and a maximum of tSW(LF) In normal operation, tSW(HF) sets the maximum operating frequency of the power supply and tSW(LF) sets the minimum operating frequency of the power supply. Refer to Figure 24.
TPS92210
ELECTRICAL CHARACTERISTICS (continued)

Unless otherwise stated: VVDD= 12 V, VVCG= 12 V, VTZE= 1 V, VFB= 0 V, GND= 0 V, a 0.1-mF capacitor exists between VDD and GND, a 0.1-mF capacitor exists between VCG and GND, RPCL=33.2 k, ROTM= 380 k, 40C < TA< +125C, TJ= TA
PARAMETER TRANSFORMER ZERO ENERGY DETECTION TZE(TH) TZE(CLAMP) TZE(START) tDLY(TZ2D) tWAIT(TZE) tST DRIVER RDS(on)(DRN) IDRN(OFF) RDS(on)(HSDRV) IDRN,DSCH TZE(OVP) tBLANK,OVP ITZE(bias) OVERLOAD FAULT IFB(OL) tOL tRETRY ROTM(TH) Current to trigger overload delay timer Delay to overload fault Retry delay in retry mode or after shutdown command Boundary ROTM between latch-off and retry modes IFB = 0 A continuously ROTM = 76 k See
(3)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
TZE Zero Crossing Threshold TZE Low Clamp Voltage TZE Voltage Threshold to Enable the Internal Start Timer Delay from zero crossing to Driver turn-on Wait time for zero energy detection Starter time-out period
TZE high to low generates switching period (tSW has expired) ITZE = 10 mA Driver switching periods generated at start timer rate 150- pull-up to 12-V on DRN Driver turn-on edge generated following tSW with previous zero current detected TZE = 0 V
5 -200 0.1
20 -160 0.15 150
50 -100 0.2
mV mV V ns
2 150
2.4 240
2.8 300
ms ms
Driver on-resistance Driver off-leakage current HSDRV on-resistance DRN Bulk Discharge
IDRN = 4.0 A IDRN = 12 V HS Driver Current = 50 mA VDD open, DRN = 12 V, Fault latch set 2
90 1.5 6 2.8
190 20 11 3.6
m mA mA
OVERVOLTAGE FAULT Over voltage fault threshold at TZE TZE blanking and OVP sample time from the turn-off edge of DRN TZE Input bias current TZE = 5 V Fault latch set 4.85 0.6 0.1 5 1 5.15 1.7 0.1 V ms mA
0 200
1.5 250 750
3 300
mA ms ms
100
120
150
SHUTDOWN THRESHOLD VOTM(SR) IOTM,PU MAXIMUM ON TIME tOTM VOTM TSD

(4) (4)
Shutdown/retry threshold OTM current when OTM is pulled low
OTM high to low VOTM = VOTM(SR) ROTM = 383 k ROTM = 76 k
0.7 600
1 450
1.3 300
V mA
Latch-off Shutdown/retry OTM voltage
3.43 3.4 2.7
3.83 3.8 3
4.23 4.2 3.3
ms ms V
THERMAL SHUTDOWN Shutdown temperature Hysteresis TJ, temperature rising (4) TJ, temperature falling, degrees below tSD
(4)
165 15
C C
TSD_HYS
(3) (4)
A latch-off or a shutdown/retry fault response to a sustained overload is selected by the range of ROTM. To select the latch-off mode, ROTM should be greater than 150 k and tOTM is given by ROTM (1.0 10-11). To select the shutdown/retry mode, ROTM should be less than 100 k and tOTM is given by ROTM (5.0 10-11). Thermal shutdown occurs at temperatures higher than the normal operating range. Device performance at or near thermal shutdown temperature is not specified or assured.
TPS92210
DEVICE INFORMATION
Functional Block Diagram
VVCG Fault Latch Reg Reset + 13 V
VVDD Switch 5 VVCG Shunt 14 V HS Drive 2V VCG
10V/6V VDD 8 + 10V/8V IFB FB 1

UVLO
Enable PWM tSW IFB Freq. Modulator 1/tSW IFB Enable PWM D Q VGATE Driver 7.5 kW 6 DRN
Feedback Processing Modulators 0 A <IFB< 200 mA I >200 mA Low-Power Mode

FB
IFB
IFB=0 Overload Transformer Zero Energy Detect Output Voltage Sense 5V On-Time Modulation and Fault Response Control IOTM VGATE 3V + Latch or Retry Shutdown and Restart OV Fault
TZE
Q Bulk Discharge
GND
Fault
Fault Timing & Control IP Fault Latch Reset UVLO Thermal Shutdown
IFB Current Modulator 3 IFB PCL
1V OTM 4
TPS92210
UDG-09157
TPS92210
PIN CONFIGURATION
FB TZE PCL OTM 1 2 3 4 8 7 6 5 VDD GND DRN VCG
PIN DESCRIPTIONS
TERMINAL NAME DRN No. 6 I/O DESCRIPTION The DRN pin is the drain of the internal low voltage power MOSFET of the TPS92210 and carries the peak primary inductor current, IPEAK(pri). Connect this pin to the source of the external cascode power MOSFET. A schottky diode between DRN and VDD is used to provide initial bias at startup. The FB pin is regulated at 0.7 V and only detects current input (FB current,IFB) which commands the operating mode of TPS92210. For peak-current mode control, this pin is connected to the emitter of the feedback opto coupler. In constant on-time control, the minimum switching period is programmed by forcing a constant current into this pin. This GND pin is the current return terminal for both the analog and power signals in the TPS92210. This terminal carries the full drain current, IDRN, which is equal to the peak primary current, IPEAK(pri), in addition to the bias supply current (IVDD) , and the gate voltage current (IVCG). the OTM pin is internally regulated at 3 V and used to program the on-time of the cascode (flyback) switch by connecting a resistor (ROTM) from this pin to the quiet return of GND. The collector of the opto-coupler is connected to this pin for constant-on time control. The range of impedance connected at this pin determines the system fault response (latch-off or shutdown/retry) to overload and brownout fault conditions. An external shutdown/retry response can be initiated by pulling this pin low below 1 V. The PCL pin programs the peak primary inductor current that is reached each switching cycle. The primary current is sensed with the RDS(on) of the internal MOSFET and is programmed by setting a threshold by connecting a low power resistor from this pin to the quiet return of GND. A resistive divider between the primary-side auxiliary winding and this pin is used to detect when the transformer is demagnetized resulting in transformer zero energy. The ratio of the resistive divider at this pin can also be used to program the output overvoltage protection (OVP) feature. The VCG pin provides the bias voltage for the gate of the cascode MOSFET. Place a 0.1-F ceramic capacitor between VCG and GND, as close as possible to the high-voltage MOSFET. This pin also provides start-up bias through a resistor RSU, which is connected between this pin and the bulk voltage. VDD is the bias supply pin for the TPS92210. It can be derived from an external source, or an auxiliary winding. Place a 0.1-F ceramic capacitor between VDD and GND, as close to the device as possible. This pin also enables and disables the general functions of the TPS92210 using the UVLO feature.
FB
GND
OTM
PCL
TZE
VCG
VDD
TPS92210
TYPICAL CHARACTERISTICS
Unless otherwise stated: VVDD = 12 V, VVCG = 12 V, VTZE = 1 V, VFB = 0 V, GND = 0 V, a 0.1F capacitor tied between VDD and GND, a 0.1-F capacitor tied between VCG and GND, RPCL = 33.2 k, ROTM = 380 k, 40C < TA < +125C, TJ = TA
BIAS SUPPLY CURRENT vs BIAS SUPPLY VOLTAGE DURING OPERATION
4.0 IFB = 10 mA VTZE = 1V VVCG = OPEN VVDD decreasing from 20 V
BIAS SUPPLY CURRENT vs BIAS SUPPLY VOLTAGE DURING LOW POWER MODE
900 850
IVDD Bias Supply Current mA
3.8
IFB = 280.4 mA VVCG = OPEN VVDD decreasing from 20 V
3.6
800 750
3.4
3.2
700
3.0 2.8
650 600
2.6 8 10 12 14 16 18 20 VVDD Bias Supply Voltage V
550 8 10 12 14 16 18 20 VVDD Bias Supply Voltage V
Figure 1. BIAS SUPPLY CURRENT vs TEMPERATURE DURING LOW POWER MODE

900
Figure 2. OPERATIONAL IVDD BIAS CURRENT vs BIAS VOLTAGE

3.5
850
3.0
800
2.5
750
2.0 VDD rising 0 V to 20V IFB= 10 mA, VDD falling 20V to 0 V IFB= 0 mA, VDD falling 20V to 0 V 0 5 10 15 20
700
1.5
650
1.0
600
0.5
550 -40 -25 -10
0.0
5 20 35 50 65 80 95 110 125
TJ Junction Temperature C
VVDD Bias Voltage V
Figure 3.
Figure 4.
TPS92210
TYPICAL CHARACTERISTICS (continued)

OSCILLATOR FREQUENCY vs FEEDBACK CURRENT
160 140
fSW Switching Frequency kHz tSW(HF) Minimum Switching Period ms
MINIMUM SWITCHING PERIOD vs TEMPERATURE

8.0
TJ = 125C and TJ = 25C
120 100 80 60 40 20 0 0 50 100 150
Junction Temperature (C) 40 25 125
7.8
7.6
7.4
TJ = 40C
7.2
200
250
300
7.0 -40 -25 -10
20
35
50
65
80
95 110 125
IFB Feedback Control Current mA
TA Ambient Temperature C
Figure 5. SWITCHING PERIOD vs AMBIENT TEMPERATURE

38
tSW(LF) Minimum Switching Period ms
Figure 6. PEAK DRN CURRENT vs FEEDBACK CURRENT

3.5
37
During Amplitude Modulation

IDRN(pk) Peak DRN Current A
3.0 TA = 40C
36
2.5
35
2.0 TA = 25C Ambient Temperature (C) 40 25 125 0 50 100
34
1.5
33
1.0
32
0.5
TA = 125C
31 -40 -25 -10
0.0
5 20 35 50 65 80 95 110 125
150
200
250
300
IFB - Feedback Current - mA
Figure 7.
Figure 8.
TPS92210

PEAK DRN CURRENT vs TRANSCONDUCTANCE (1/RPCL)
5 Best Results 24.3 kW < RPCL< 100 kW
PEAK DRN CURRENT vs AMBIENT TEMPERATURE

3.2 IFB = 0 mA
3.1
3.0
2.9
Avoid Operation Here
0 0 10 20 30 40 50 1/RPCL mS
2.8 -40 -25 -10
20
35
50
65
80
95 110 125
Figure 9. ON TIME vs ON-TIME MODULATION RESISTANCE

6 4.3 4.2 5
tOTM Constant On-Time ms tOTM Constant On-Time ms
Figure 10. ON TIME vs JUNCTION TEMPERATURE
ROTM = 383 kW
4.1 4.0 3.9 3.8 3.7 3.6 3.5 3.4 3.3 -40 -25 -10
MODE Latch Off Shutdown/Retry 0 100 20 300 400 500 600
0 ROTM On-Time Modulation Resistance kW
20
35
50
65
80
95 110 125
TJ Junction Temperature C
Figure 11.
Figure 12.
10
TPS92210

LOW VOLTAGE MOSFET RDS(on) vs AMBIENT TEMPERATURE
160 12 High-Side VDD Switch
RDS(on) On-Time Resistance mW RDS(on) On-Time Resistance W
RDS(on) OF HIGH SIDE DRIVE AND VDD SWITCH vs TEMPERATURE
120
10
100
80
60
40
20 -40 -25 -10
20
35
50
65
80
95 110 125
0 -40 -25 -10
20
35
50
65
80
95 110 125
Figure 13. SAFE OPERATING AREA vs BOARD TEMPERATURE

2.5
60
Figure 14. THERMAL COEFFICIENT qJB vs POWER DISSIPATION
qJB Thermal Coefficient C/W
PDISS Power Dissipation W
2.0
50
40
1.5
30
1.0
20
0.5
10
0 -40 -25 -10
0.0
20
35
50
65
80
95 110 125
0.25
0.50
0.75
1.00
1.25
TB Board Temperature C
PDISS Power Dissipation W
Figure 15.
Figure 16.
11
TPS92210
VIN AC
+ CBULK
RSU NP CVCG NS
TPS92210 4 3 2 1 OTM PCL TZE FB VCG 5 DRN 6 GND 7 CBP VDD 8 + CVDD DBIAS RTZE1 LED ISENSE and Conditioning D1 NB
UDG-09180
Figure 17. Typical Application
12
TPS92210
DETAILED DESCRIPTION BIAS AND START-UP

The TPS92210 controls the turn-ON and turn-OFF of the flyback switch through its source by using the cascode configuration. The cascode configuration is also used to provide the initial bias during start-up. The cascode architecture utilizes a low voltage switch whose drain, namely the DRN pin, is connected to the source of the high voltage MOSFET (HV MOSFET). The gate of the HV MOSFET is held at a constant DC voltage using the VCG pin. The TPS92210 cascode based HVMOSFET drive architecture is shown in Figure 18.
Bulk Primary Winding External High-Voltage MOSFET Bulk Primary Winding External High-Voltage MOSFET
+ Cascoded MOSFET Pair Internal Low-Voltage MOSFET ON
Gate Bias + 14 VDC
PWM Control
PWM Control
Internal Low-Voltage MOSFET OFF
UDG-09185
Figure 18. Cascoded Architecture The start-up bias uses a low-level bleed current from either the AC line or the rectified and filtered AC line through the startup resistor (RSU). The bleed current off the line (approximately 6 A) charges a small VCG capacitor and raises the voltage at the HVMOSFET gate. The HVMOSFET acts as a source follower once the voltage at VCG pin reaches the threshold voltage of the HVMOSFET and raises the DRN pin voltage. During startup the TPS92210 is in undervoltage lockout (UVLO) state with the enable pulse-width modulation (PWM) signal low. This turns on the VDD switch connecting between the DRN pin and the VDD pin, thus allowing VVDD to also rise with VVCG minus a threshold voltage of HVMOSFET. An external schottky diode between DRN and VDD is used to steer away potentially high switching currents from flowing through the body diode of the internal VDD switch. The startup current and the operating current paths in the cascode architecture are shown in Figure 19. The VCG pin is shunt regulated at 14 V during normal operation and the regulation level is increased to 16 V during fault, UVLO and startup conditions.
13
TPS92210
Bulk RSU (~10 MW) ISU HVMOSFET Primary Winding
VDD Start-up Current CVDD (~10 mF) 8
CVCG (100 nF)
VDD
VDD Operating, LPM Current 5
VCG
D2 Auxiliary Winding
UVLO
Enable PWM
14 V
+ 10 V/8 V Fault Internal Regulators VCG Shunt
2V VDD Switch 6
DRN
Enable PWM
UDG-09182
Figure 19. Start-Up and Operating Current in the Cascode Architecture for TPS92210
14
TPS92210
PRIMARY SIDE CURRENT SENSE

The TPS92210 integrates all of the current sensing and drive, thereby eliminating the need for a current sense resistor. The internal low-voltage switch with typical RDS(on) of 90 m drives the HVMOSFET through its source and the entire primary current of the transformer flows through this switch and out of the GND pin. The TPS92210 utilizes a current mirror technique to sense and control the primary current. The primary current flowing through the low-voltage switch is scaled and reflected to the PWM comparator where it is compared with the PCL pin current. Thus the peak current reached at each switching cycle is sensed and limited by this comparison. In peak current-mode control, based on the error signal input at the FB pin, the voltage at the PCL pin and hence the PCL pin current is modulated by TPS92210. The maximum peak primary current is programmed by connecting a low-power resistor from (RPCL) from PCL pin to the quiet return of GND. 100kV IDRN(pk ) = RPCL (1) At the beginning of each switching cycle a blanking time of approximately 220 ns is applied to the internal current limiter. This allows the low-voltage switch to turn on without false limiting on the leading edge capacitive discharge currents. The drain-gate charge in the HVMOSFET does not affect the turn-off speed because the gate is connected to a low impedance DC source with the help of VCG pin. The cascode configuration enables very fast turn-off of the HVMOSFET and helps to keep switching losses low. Figure 20 illustrates the internal current sensing and control exhibited by programming the resistor at the PCL pin.
Current Modulator I DRN,PK

3 1 210
IFB 1 IFB
FB
From Optocoupler Emitter
V PCL, V
PCL 3
IPCL
3 1 165 210
DRN
i FB, A
6 IDRN 100,000 IDRN Drive MOSFET 7
From High-Voltage MOSFET Source
IPCL
GND
PWM Comparator
tBLANKCL
TPS92210
UDG-09186
Figure 20. Peak Current Limit (PCL) Pin Details
15
TPS92210
FEEDBACK AND MODULATION

The TPS92210 can be programmed to operate in constant-on time control or in peak-current mode control based on how the error signal is fed back to its modulator. Constant-On Time Control Using the OTM Pin The power factor describes how well an AC load corresponds to a pure resistance. A flyback transformer operating in discontinuous conduction mode (DCM) creates a peak primary current described in Equation 2 V V t IPEAK = BULK ON = BULK L M LM tON where
LM is the magnetizing inductance of the flyback transformer tON is the on-time of the flyback switch (LM/tON) is expressed in units of (H/s)
(2)
thus,
V IPEAK = BULK (V / W ) LM tON
(3)
If the on-time is limited to a fixed value, then the peak primary current in the transformer is directly proportional to the bulk supply voltage. Consequently, a flyback operating in DCM with a fixed inductance and fixed on-time behaves much like a pure resistance and exhibits a power factor close to unity when operating with a small bulk capacitance. The TPS92210 can easily be configured for constant on-time control, allowing fixed-frequency, single-stage power factor regulation. In constant-on time control, the on-time of the primary switch can be programmed by connecting a resistor (ROTM) between the OTM pin and the quiet return of GND. The on-time can be further modulated by connecting the collector of the opto-coupler to the OTM pin through a resistor as shown in Figure 21.
On-Time Modulation and Fault Response Control IOTM VGATE
Latch or Retry
Fault Timing and Control
+
OTM 4
3V Shutdown and Restart
UVLO
1V
Thermal Shutdown
UDG-09187
Figure 21. On-Time Modulation Detail
16
TPS92210
The OTM multi-function pin is also used to program the system response to overload and brownout conditions. Figure 22 shows how the on-time is programmed over the range of between 1.5 s and 5 s for either range of programming resistors. The resistor range determines the controller response to a sustained overload fault (to either latch-off or to shutdown/retry) which is the same response for a line-sag, or brown out, condition. The on-time is related to the programmed resistor based on the following equations. The on-time for latch-off response to overcurrent faults is show in Equation 4. W ROTM = tOTM 1 1011 s The on-time for the shutdown/retry response to overcurrent faults is shown in Equation 5. W ROTM = tOTM 2 1010 s
(4)
(5)
tOTM Constant On-Time ms
5 Shutdown/ Retry Latch-off
1.5
120-kW Threshold Retry vs Latch-off 100120 150 ROTM Constant On-Time Resistance kW
UDG-09183
500
Figure 22. On-time Programming Range and Overload Fault Response Selection The OTM pin can also be used to externally shutdown the converter by pulling the OTM pin low below VOTM(SR) threshold (typically 1 V). The PWM action is disabled and the controller retries after the shutdown/retry delay of 750 ms.
17
TPS92210
Peak-Current Mode Control Using the FB Pin In peak-current mode control, the FB pin is used to feed back the output error signal to the internal modulator. In this mode of control, the emitter of the opto-coupler is connected to the FB pin and a resistor (RFB) is connected from FB to the quiet return of GND to bleed off the dark current of the opto-coupler. The FB pin detects current input only, and the voltage at this pin is normally 0.7 V. The FB pin interface is outlined in Figure 23.
VVDD VOUT
IFB To Modulators Low-Power Mode Overload 0 A < IFB < 200 mA IFB > 200 mA IFB = 0 A FB 1 IFB RFB CFB Filter RFB Filter U2 Opto-Coupler
ROPT
TL431
TPS92210 GND1 GND1 GND2
UDG-09188
Figure 23. FB Pin Details for Peak-Current Mode Control The FB current (IFB) commands the TPS92210 to operate the flyback converter in one of the three modes Frequency Modulation (FM) mode Amplitude Modulation (AM) mode Low power mode (LPM) The converter operates in FM mode with a large power load (23% to 100% the peak regulated power). The peak HVMOSFET current reaches its maximum programmed value and FB current regulates the output voltage by modulating the switching frequency, which is inversely proportional to tSW. The switching frequency range is nominally from 30 kHz (23% peak power) to 133 kHz (100% peak power).
18
TPS92210
The maximum programmable HVMOSFET current, IDRN,PK(max), is set by the resistor on the PCL pin, as described in Equation 1. The converter operates in AM mode at moderate power levels (2.5% to 23% of the peak regulated power). The FB current regulates the output voltage by modulating the peak HVMOSFET current from 33% to 100% of the maximum programmed value while the switching frequency is fixed at approximately 30 kHz. The TPS92210 modulates the voltage on the PCL pin from 3 V to 1 V to vary the commanded peak current, as shown in Figure 24.
IDRN,PK(max) % of Maximum Peak DRN Current %
IFB Peak Current Control Current Modulator IDRN, PK
FM
AM
Low Power Mode IFB,CNR3 (275 mA)
3
IFB
IFB,CNR1 IFB,CNR2 (165 mA) (210 mA) 100
IFB,CNR3 IFB,CNR2 (65 mA)
33
fSW(max) Max Switching Frequency (kHz)
IFB,CNR2 IFB,CNR1 (45 mA) 130
IFB Frequency Modulator tSW 1/tSW VGATE IFB
IFB,LPM-HYST (20 mA)
30
50
100
150
200
250
300
UDG-09156
IFB Feedback Current mA
Figure 24. FB Pin Based Modulation Modes The converter operates in LPM at light load (0% to 2.5% of the peak regulated power). The FB current regulates the output voltage in the Low Power Mode with hysteretic bursts of pulses using FB current thresholds. The peak HVMOSFET current is 33% of the maximum programmed value. The switching frequency within a burst of pulses is approximately 30 kHz. The duration between bursts is regulated by the power supply control dynamics and the FB hysteresis. The TPS92210 reduces internal bias power between bursts in order to conserve energy during light-load and no-load conditions.
19
TPS92210
TRANSFORMER ZERO ENERGY DETECTION

The TPS92210 ensures that the flyback converter always operates in DCM and initiates a new switching cycle only when the primary transformer has been completely reset or when its energy is zero. The TZE pin is connected through a resistive divider to the primary-side auxiliary winding for zero energy detection. The transformer zero energy is detected by monitoring the current sourced out of the TZE pin when the primary bias winding of the flyback converter is negative with respect to GND. The voltage at this pin is clamped at 160 mV during the negative excursions of the auxiliary winding. A small delay, between 50 ns and 200 ns, can be added with CTZE to align the turn-on of the primary switch with the resonant valley of the primary winding waveform enabling valley switching. Figure 25 shows the waveform on the HVMOSFET drain, the voltage at the TZE pin and the primary current in the transformer. It also illustrates how CTZE delays the voltage at the TZE pin to cause the TPS92210 to switch at the resonant valley.
High Voltage MOSFET Drain CTZE-Based Delay
TZE Input
Modulated Switching Time
Switching Time (tSW)
IDRN (= IPRI) t Time

UDG-09184
Figure 25. TZE and HVMOSFET Drain Voltages for Valley Switching The TPS92210 requires that three conditions are satisfied before it can initiate a new switching cycle. The time since the last turn-on edge must be equal to or greater than the time that is requested by the feedback processor as determined by the feedback current, IFB. The time since the last turn-on edge must be longer than the minimum period that is built into the device (nominally 7.5 s which equals 133 kHz). Immediately following a high-to-low zero crossing of the TZE pin voltage. Or, it has been longer than tWAIT,TZE since the last zero crossing of the current has been detected The TZE pin is also used to program the output overvoltage protection or open-LED detection feature. The output voltage is monitored by TPS92210 by sampling the voltage at the auxiliary winding. The voltage is sampled after a fixed delay of 1 ms after the internal low-voltage switch has turned off. This allows the auxiliary winding to be sampled after the bias winding voltage settles from the transient. The output over-voltage threshold is set using the turns ratio of the auxiliary winding to the output secondary and a resistive divider into the TZE pin. The controller latches-off on an open-LED fault and requires a power recycle to reset the fault latch (VDD recycling below fault reset threshold of 6 V). The interface to the TZE pin for zero energy detection and OVP feature is shown in Figure 26.
20
TPS92210
NP
NS
NB
RTZE1
TZE 2
Transformer Zero Energy Detect OV Fault Fault Timing and Control 5V

UDG-09189
RTZE2
CTZE Output Voltage Sense
TPS92210
Figure 26. TZE and Output Overvoltage Detection
21
TPS92210
Terminal Components (1) (2)

NAME TERMINAL DESCRIPTION
(K P LM ) RPCL = 33.2k W PIN
PCL
100kV IDRN(pk ) = RPCL

where KP = 0.54 W/H LM is the minimum value of primary inductance PIN = POUT/h h = efficiency
DRN FB GND
6 1 7
M1, power MOSFET with adequate voltage and current ratings, VGS must have at least 20 V static rating. D1, Schottky diode, rated for at least 30 V, placed between DRN and VDD 100 k Bypass capacitor to VDD, CBP = 0.1 F, ceramic For Latch-Off response to overcurrent faults:
ROTM
OTM 4
W tOTM 1 1011 s W tOTM 2 1010 s
For shutdown/retry response to overcurrent faults:
ROTM
CVDD =
where
IVDD(LPM) tBURST DVDD(burst )
VDD(BURST) is the allowed VDD ripple during burst operation tBURST is the estimated burst period The typical CVDD value is approximately 48 F. VDD 8 DBIAS must have a voltage rating greater than:
VBULK (max ) N VDBIAS = VOUT PS + NPB NPB

where VDBIAS is the reverse voltage rating of diode D2 VBULK(max) is the maximum rectified voltage of CBULK at the highest line voltage VCG 5 CVCG = at least 10xCGS of the HVMOSFET, usually CVCG = 0.1 F
RTZE1 =
TZE 2 where
(VOUT + VF ) N PS
100 mA NPB
RTZE2
TZEOVP RTZE1 NPS VOUT(pk) NPB - TZEOVP
VOUT is the average output voltage of the secondary VF is the forward bias voltage of the secondary rectifier VOUT(pk) is the desired output overvoltage fault level (1) (2) Refer to the Electrical Characteristics Table for all constants and measured values, unless otherwise noted. Refer to Figure 17 for all component locations in the Terminal Components Table
22
TPS92210
REVISION HISTORY
Changes from Original (JANUARY 2010) to Revision A Page
Changed Corrected Pin 2 name ........................................................................................................................................... 1 Changed Corrected Pin 2 name ......................................................................................................................................... 12 Changed location of Zener diode in Figure 19. .................................................................................................................. 14
23
PACKAGE OPTION ADDENDUM
www.ti.com
13-Sep-2010
PACKAGING INFORMATION
Orderable Device TPS92210D TPS92210DR Status
(1)
Package Type Package Drawing SOIC SOIC D D
Pins 8 8
Package Qty 75 2500
Eco Plan
(2)
Lead/ Ball Finish
MSL Peak Temp
(3)
Samples (Requires Login) Purchase Samples Request Free Samples
ACTIVE ACTIVE
Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 20-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins Type Drawing SOIC D 8
SPQ
Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 12.4 6.4
B0 (mm) 5.2
K0 (mm) 2.1
P1 (mm) 8.0
W Pin1 (mm) Quadrant 12.0 Q1
TPS92210DR
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 20-Jul-2010
*All dimensions are nominal
Device TPS92210DR
Package Type SOIC
Package Drawing D
Pins 8
SPQ 2500
Length (mm) 340.5
Width (mm) 338.1
Height (mm) 20.6
Pack Materials-Page 2
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Natural PFC Led Lighting Driver Controller: Features Description

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TPS92210

www.ti.com SLUS989A JANUARY 2010 REVISED DECEMBER 2010

NATURAL PFC LED LIGHTING DRIVER CONTROLLER

TPS92210 OTM VCG PCL TZE FB DRN GND VDD

5 6 7 8 LED ISENSE and Conditioning VOUT

Copyright 2010, Texas Instruments Incorporated

ABSOLUTE MAXIMUM RATINGS (1)

ITZE, IOTM, IPCL, IFB

PACKAGE DISSIPATION RATINGS (1)

qJB, THERMAL IMPEDANCE JUNCTION TO BOARD, NO AIRFLOW (C/W) 55 (1)

TA = 25C POWER RATING (mW) 606 (3)

TA = 85C POWER RATING (mW) 242 (3)

TB = 85C POWER RATING (mW) 730 (2) (3)

Submit Documentation Feedback Product Folder Link(s): TPS92210

Copyright 2010, Texas Instruments Incorporated

RECOMMENDED OPERATING CONDITIONS

ELECTROSTATIC DISCHARGE (ESD) PROTECTION

Copyright 2010, Texas Instruments Incorporated

Submit Documentation Feedback Product Folder Link(s): TPS92210

1.5 9.7 7.55 1.9

2 10.2 8 2.2 3 550 225 4

2.5 10.7 8.5 2.5 3.7 900 300 10 6.4

MODULATION tSW(HF) tSW(LF)

7.5 34 3 0.9 0.85 0.33 0.60 0.45 220

7.875 38 3.15 1.0 1.1 0.5 0.66 0.6

IFB = IFB, CNR3 20 mA,

31 2.85 0.8 0.7 0.2 0.54 0.3

IDRN(peak,max) IDRN(peak,min) KP IDRN(peak,absmin) tBLANK(ILIM) PCL IFB,CNR1

+ 10 mA, RPCL = 33.2 k + 10 mA, RPCL = 100 k

2.94 0.95 145 35 50 10 0.34

3.06 1.05 195 65 90 40 0.84

IFB range for FM modulation

IFB,CNR2 IFB,CNR1 IFB,CNR3 IFB,CNR2 IFB, FB

Submit Documentation Feedback Product Folder Link(s): TPS92210

Copyright 2010, Texas Instruments Incorporated

ELECTRICAL CHARACTERISTICS (continued)

20 -160 0.15 150

1.5 250 750

SHUTDOWN THRESHOLD VOTM(SR) IOTM,PU MAXIMUM ON TIME tOTM VOTM TSD

Shutdown/retry threshold OTM current when OTM is pulled low

OTM high to low VOTM = VOTM(SR) ROTM = 383 k ROTM = 76 k

Latch-off Shutdown/retry OTM voltage

3.43 3.4 2.7

4.23 4.2 3.3

Copyright 2010, Texas Instruments Incorporated

Submit Documentation Feedback Product Folder Link(s): TPS92210

VVCG Fault Latch Reg Reset + 13 V

VVDD Switch 5 VVCG Shunt 14 V HS Drive 2V VCG

10V/6V VDD 8 + 10V/8V IFB FB 1

Feedback Processing Modulators 0 A <IFB< 200 mA I >200 mA Low-Power Mode

IFB Current Modulator 3 IFB PCL

Submit Documentation Feedback Product Folder Link(s): TPS92210

Copyright 2010, Texas Instruments Incorporated

Copyright 2010, Texas Instruments Incorporated

Submit Documentation Feedback Product Folder Link(s): TPS92210

IFB = 280.4 mA VVCG = OPEN VVDD decreasing from 20 V

2.6 8 10 12 14 16 18 20 VVDD Bias Supply Voltage V

550 8 10 12 14 16 18 20 VVDD Bias Supply Voltage V

Figure 1. BIAS SUPPLY CURRENT vs TEMPERATURE DURING LOW POWER MODE

Figure 2. OPERATIONAL IVDD BIAS CURRENT vs BIAS VOLTAGE

550 -40 -25 -10

VVDD Bias Voltage V