Computer Organization and Microprocessor Semester 2 2012-2013 Danang University of Technology, Faculty of Electronics and Telecommunications Department of Computer

Engineering Prepared by Ho Viet Viet, Pham Xuan Trung, TT Minh Hanh and Nguyen Van Hieu

Lab3: Design a MIPS 32-bit Single-Cycle CPU

Lab Objectives: For this lab3 you are to design a simple 32-bit MIPS Single-Cycle CPU. The CPU instructions to be implemented are LW, SW, J, JR, BNE, XORI, ADD, SUB, and SLT. Chapter 4 will give some examples of how architectures are put together, and will be useful as you design your own CPU. For this CPU, you will use your two previous lab projects (the register and the ALU) so you will need to have these fully functional before proceeding to work on your CPU. The data memory and instruction memory modules are provided in the files datamem.v and instrmem.v respectively. We also provide a bunch of test programs you can change the program loaded by editing the instr.dat string in instrmem.v. You are responsible for coming up with the top-level testbench for this assignment use previous labs testbenches as guidance. Please remember that the rules from lab1 are still in effect. Also, to demonstrate that your CPU actually works, you will need to set things up so that all the registers used in the benchmarks are displayed at the end of the execution. The easiest way to accomplish this is to look at the all lines inside your register file coming out of the DFF array in SignalScan (along with other relevant signals) and save a do-file. We strongly recommend this, even aside from the demonstration, as it will make debugging much simpler. Make sure that the clock in your testbench (1) is long enough so that all processing is done within this clock cycle (a VERY long clock is fine) (2) executes enough clock cycles for the program to finish. The control logic for your CPU can be done behaviorally. If you do this, you can show the control logic on your schematics as black boxes. You need to indicate how the control logic hooks to the rest of the CPU, but do not have to draw the logic for the control logic itself. Note that, although some of the benchmarks are particularly relevant to lab4, they ALL will run successfully on lab3, and you will be evaluated on whether your CPU works on any/all of them. Be sure to test ALL the benchmarks on your CPU. Instruction subset:
ADD rd, rs, rt: Reg[rd] = Reg[rs] + Reg[rt]. BNE rs, rt, imm16: if (Reg[rs] != Reg[rt]) PC = PC + 4 + Sign_ext(Imm16)<<2 else PC = PC + 4. For lab #4 (only) this instr. has a delay slot. J target: PC = { PC[31:28], target, 00 }. For lab #4 (only) this instr. has a delay slot. JR rs: PC = Reg[rs]. For lab #4 (only) this instr. has a delay slot. LW rt, imm16(rs): Reg[rt] = Mem[Reg[rs] + Sign_ext(Imm16)]. For lab #4 (only) the value in rt cannot be used in the next cycle. SLT rd, rs, rt: If (Reg[rs] < Reg[rt]) Reg[rd] = 0000000116 else Reg[rd] = 0000000016. SUB rd, rs, rt: Reg[rd] = Reg[rs] Reg[rt].

SW rt, imm16(rs): Mem[Reg[rs] + Sign_ext(Imm16)] = Reg[rt]. XORI rt, rs, imm16: Reg[rt] = Reg[rs] XOR Zero_ext(Imm16).

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