MC74HC541A Octal 3-State Non-Inverting Buffer/Line Driver/ Line Receiver

HighPerformance SiliconGate CMOS

The MC74HC541A is identical in pinout to the LS541. The device inputs are compatible with Standard CMOS outputs. External pullup resistors make them compatible with LSTTL outputs. The HC541A is an octal noninverting buffer/line driver/line receiver designed to be used with 3state memory address drivers, clock drivers, and other busoriented systems. This device features inputs and outputs on opposite sides of the package and two ANDed activelow output enables. The HC541A is similar in function to the HC540A, which has inverting outputs.
http://onsemi.com MARKING DIAGRAMS
20 PDIP20 N SUFFIX CASE 738
1

MC74HC541AN AWLYYWW 1 20

20

20

Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2 to 6V Low Input Current: 1A High Noise Immunity Characteristic of CMOS Devices In Compliance With the JEDEC Standard No. 7A Requirements Chip Complexity: 134 FETs or 33.5 Equivalent Gates
LOGIC DIAGRAM
A1 A2 A3 Data Inputs A4 A5 A6 A7 A8 Output Enables OE1 OE2 2 3 4 5 6 7 8 9 1 19 18 17 16 15 14 13 12 11 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 NonInverting Outputs

SOIC WIDE20 DW SUFFIX CASE 751D 1 A WL YY WW

HC541A AWLYYWW

= Assembly Location = Wafer Lot = Year = Work Week

FUNCTION TABLE
Inputs OE1 L L H X OE2 L L X H A L H X X L H Z Z Output Y

Z = High Impedance X = Dont Care

ORDERING INFORMATION
Device MC74HC541AN MC74HC541ADW Package PDIP20 SOICWIDE SOICWIDE Shipping 1440 / Box 38 / Rail 1000 / Reel

PIN 20 = VCC PIN 10 = GND

MC74HC541ADWR2

Pinout: 20Lead Packages (Top View)

VCC 20 OE2 19 Y1 18 Y2 17 Y3 16 Y4 15 Y5 14 Y6 13 Y7 12 Y8 11

1 OE1

2 A1

3 A2

4 A3

5 A4

6 A5

7 A6

8 A7

9 A8

10 GND

Semiconductor Components Industries, LLC, 2000

March, 2000 Rev. 2

Publication Order Number: MC74HC541A/D


MAXIMUM RATINGS*
Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) 0.5 to + 7.0 0.5 to VCC + 0.5 0.5 to VCC + 0.5 20 35 75 750 500 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature Range Plastic DIP SOIC Package mW Tstg TL 65 to + 150 260

MC74HC541A

_C _C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP or SOIC Package

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating Plastic DIP: 10 mW/_C from 65_ to 125_C SOIC Package: 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS
Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature Range, All Package Types Input Rise/Fall Time (Figure 1) VCC 55 0 0 0 + 125 1000 500 400

_C
ns

tr, tf

VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V

DC CHARACTERISTICS (Voltages Referenced to GND)

Symbol VIH

Parameter Minimum HighLevel Input Voltage

Condition Vout = 0.1V |Iout| 20A

VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0

Guaranteed Limit 55 to 25C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 1.9 4.4 5.9 2.48 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.26 0.1 85C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 1.9 4.4 5.9 2.34 3.84 5.34 0.1 0.1 0.1 0.33 0.33 0.33 1.0 125C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 1.9 4.4 5.9 2.20 3.70 5.20 0.1 0.1 0.1 0.40 0.40 0.40 1.0 A V Unit V

VIL

Maximum LowLevel Input Voltage

Vout = VCC 0.1V |Iout| 20A

VOH

Minimum HighLevel Output Voltage

Vin = VIL |Iout| 20A Vin = VIL |Iout| 3.6mA |Iout| 6.0mA |Iout| 7.8mA

3.0 4.5 6.0 2.0 4.5 6.0

VOL

Maximum LowLevel Output Voltage

Vin = VIH |Iout| 20A Vin = VIH |Iout| 3.6mA |Iout| 6.0mA |Iout| 7.8mA

3.0 4.5 6.0 6.0

Iin

Maximum Input Leakage Current

Vin = VCC or GND

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MC74HC541A
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol IOZ Parameter Maximum ThreeState Leakage Current Maximum Quiescent Supply Current (per Package) Condition Output in High Impedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND Iout = 0A VCC V 6.0 Guaranteed Limit 55 to 25C 0.5 85C 5.0 125C 10.0 Unit A

ICC

6.0

40

160

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Symbol tPLH, tPHL Parameter Maximum Propagation Delay, Input A to Output Y (Figures 1 and 3) VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 Guaranteed Limit 55 to 25C 80 30 18 15 110 45 25 21 110 45 25 21 60 22 12 10 10 15 85C 100 40 23 20 140 60 31 26 140 60 31 26 75 28 15 13 10 15 125C 120 55 28 25 165 75 38 31 165 75 38 31 90 34 18 15 10 15 Unit ns

tPLZ, tPHZ

Maximum Propagation Delay, Output Enable to Output Y (Figures 2 and 4)

ns

tPZL, tPZH

Maximum Propagation Delay, Output Enable to Output Y (Figures 2 and 4)

ns

tTLH, tTHL

Maximum Output Transition Time, Any Output (Figures 1 and 3)

ns

Cin Cout

Maximum Input Capacitance Maximum ThreeState Output Capacitance (Output in High Impedance State)

pF pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V, VEE = 0 V CPD Power Dissipation Capacitance (Per Buffer)* 35 pF * Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).

SWITCHING WAVEFORMS
tr 90% INPUT A tPLH 90% OUTPUT Y tTLH 50% 10% OUTPUT Y tTHL 50% HIGH IMPEDANCE tPZH tPHZ 90% VOH 50% 10% tPHL GND OUTPUT Y 50% 10% VOL tf VCC VCC OE1 or OE2 50% tPZL tPLZ 50% GND HIGH IMPEDANCE

Figure 1.

Figure 2.

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MC74HC541A
TEST CIRCUITS
TEST POINT OUTPUT DEVICE UNDER TEST CL* DEVICE UNDER TEST OUTPUT TEST POINT 1k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ and tPZH.

CL*

*Includes all probe and jig capacitance

*Includes all probe and jig capacitance

Figure 3.

Figure 4.

PIN DESCRIPTIONS
INPUTS

A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8, 9) Data input pins. Data on these pins appear in noninverted form on the corresponding Y outputs, when the outputs are enabled.
CONTROLS

outputs are enabled and the device functions as an noninverting buffer. When a high voltage is applied to either input, the outputs assume the high impedance state.
OUTPUTS

OE1, OE2 (PINS 1, 19) Output enables (activelow). When a low voltage is applied to both of these pins, the

Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14, 13, 12, 11) Device outputs. Depending upon the state of the output enable pins, these outputs are either noninverting outputs or highimpedance outputs.

LOGIC DETAIL
To 7 Other Buffers

One of Eight Buffers INPUT A

VCC

OUTPUT Y

OE1 OE2

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MC74HC541A
PACKAGE DIMENSIONS
PDIP20 N SUFFIX PLASTIC DIP PACKAGE CASE 73803 ISSUE E
11

A
20

B
1 10

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01

T
SEATING PLANE

K M E G F D
20 PL

N J 0.25 (0.010)
M 20 PL

0.25 (0.010) T A
M

T B

DIM A B C D E F G J K L M N

SO20 DW SUFFIX CASE 751D05 ISSUE F

D A
11 X 45 _

q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_

20

10X

0.25

10

20X

B 0.25
M

B T A
S

A
SEATING PLANE

DIM A A1 B C D E e H h L

18X

A1

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MC74HC541A

Notes

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MC74HC541A

Notes

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MC74HC541A

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MC74HC541A/D