Reg. No.

Question Paper Code :

M.E. DEGREE EXAMINATION, APRIL/MAY 2011 Elective Applied Electronics

VL 9252 LOW POWER VLSI DESIGN (Common to M.E. VLSI Design) (Regulation 2009) Time : Three hours Answer ALL questions PART A (10 2 = 20 marks) 1. 2. 3. 4.

What are the sources of power consumption in VLSI circuits? List any four basic principles of low power VLSI design.

What are the techniques available for reducing power consumption in multipliers? How does the design of supply clock influence power dissipation? Define signal activity with respect to a circuit node.

5. 6. 7.

8.

9.

10.

Distinguish between power estimation at circuit level and high level power estimators. Large improvements in power dissipation are possible only at higher levels of design abstraction. Why?

What are the objectives of power minimization techniques related to memory that can be achieved using software?

What are the drawbacks of zero-delay model used for determination of average power in VLSI circuits?

State the effect of channel length on power dissipation in VLSI circuits.

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Maximum : 100 marks

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PART B (5 16 = 80 marks) 11. (a) Derive the expression for short circuit power dissipation of a CMOS inverter. Also discuss the impact of signal slope on short circuit power dissipation. Or (b)

12.

(a)

Discuss the power optimization techniques used in adders and multipliers. (16) Or

(b)

(i) (ii)

Discuss the dynamic logic and static logic CMOS circuits with respect to power dissipation. (6) Explain in detail about operation reduction and operation substitution with examples. (5 + 5)

13.

(a)

(b)

Draw the resonant driver circuit for generating supply clock and compare it with other methods. Also give the importance of clock generation with respect to power dissipation.

(ii)

Write a note on power estimation based on information theory approach. (8) Or

(b)

Explain the method of estimating average power in combinational and sequential circuits using statistical techniques. Discuss in detail the various levels of abstraction at which power dissipation can be estimated by software. Or

15.

(a)

(b)

Large improvements in power dissipation are possible at higher levels of design abstraction. Justify the above statement and discuss the techniques used.

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14.

(a)

(i)

Draw the flowchart of Monte-Carlo based estimation of glitching power for sequential circuit and explain. (8)

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Or

Explain any two techniques with an example for reducing power consumption in memories.

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Obtain an expression for the power dissipation in a CMOS inverter due to charging and discharging of a capacitor.

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