Abc to dqo transformation: Step 1:

1 In1 2 In2 2*pi/3

cos

cos

Product 2/3 1 Out1

3 In3 4 In4 sin cos

Product1

Gain

Product2

Product3 sin 2/3 Product4 sin Gain1 2 Out2

Product5

This is the model I have used 1.all the input & out put ports have been defined as: int32 Step 2: made a subsystem l

4 t h e t a 1 v a 2 v b 3 v c

I n 1 O u t 1 I n 2

2 V d

I n 3 O u t 2 I n 4

1 V q

d q o

This much .vhd files was created.

In
C lo c k G a te w a y In 1 0

c lk ce_ o u t re se t C o n sta n t5

Out
G a te w a y O u t S co p e

S y s te m G e n e ra to r

1 C o n sta n t4

In

C E P ro b e 1

c lk_ e n a b le

G a te w a y In C l o c k E n a b l e P ro b e

In 1 C o n sta n t3 1 C o n sta n t 1 C o n sta n t1 1 C o n sta n t2 In 2

O u t1

Out
G a te w a y O u t1 S cop e 1

In 3 O u t2 In 4 B la c k B o x

Out
G a te w a y O u t2 S co p e 2

SELECTED ONLY THE dqo_config file when the black box wizard came

VHD FILE:
function dqo_config(this_block) % Revision History: % % 06-Feb-2012 (18:04 hours): % Original code was machine generated by Xilinx's System Generator after parsing % C:\Documents and Settings\E567962\My Documents\MATLAB\hdlsrc\dqo.vhd % % this_block.setTopLevelLanguage('VHDL'); this_block.setEntityName('dqo'); % System Generator has to assume that your entity has a combinational feed through; % if it doesn't, then comment out the following line: this_block.tagAsCombinational; this_block.addSimulinkInport('clk'); this_block.addSimulinkInport('reset'); this_block.addSimulinkInport('clk_enable');

this_block.addSimulinkInport('In1'); this_block.addSimulinkInport('In2'); this_block.addSimulinkInport('In3'); this_block.addSimulinkInport('In4'); this_block.addSimulinkOutport('ce_out'); this_block.addSimulinkOutport('Out1'); this_block.addSimulinkOutport('Out2'); ce_out_port = this_block.port('ce_out'); ce_out_port.setType('UFix_1_0'); ce_out_port.useHDLVector(false); Out1_port = this_block.port('Out1'); Out1_port.setType('UFix_32_0'); Out2_port = this_block.port('Out2'); Out2_port.setType('UFix_32_0'); % ----------------------------if (this_block.inputTypesKnown) % do input type checking, dynamic output type and generic setup in this code block. if (this_block.port('clk').width ~= 1); this_block.setError('Input data type for port "clk" must have width=1.'); end this_block.port('clk').useHDLVector(false); if (this_block.port('reset').width ~= 1); this_block.setError('Input data type for port "reset" must have width=1.'); end this_block.port('reset').useHDLVector(false); if (this_block.port('clk_enable').width ~= 1); this_block.setError('Input data type for port "clk_enable" must have width=1.'); end this_block.port('clk_enable').useHDLVector(false); if (this_block.port('In1').width ~= 32); this_block.setError('Input data type for port "In1" must have width=32.'); end if (this_block.port('In2').width ~= 32); this_block.setError('Input data type for port "In2" must have width=32.'); end if (this_block.port('In3').width ~= 32); this_block.setError('Input data type for port "In3" must have width=32.'); end

if (this_block.port('In4').width ~= 32); this_block.setError('Input data type for port "In4" must have width=32.'); end end % if(inputTypesKnown) % ----------------------------% System Generator found no apparent clock signals in the HDL, assuming combinational logic. % ----------------------------if (this_block.inputRatesKnown) inputRates = this_block.inputRates; uniqueInputRates = unique(inputRates); outputRate = uniqueInputRates(1); for i = 2:length(uniqueInputRates) if (uniqueInputRates(i) ~= Inf) outputRate = gcd(outputRate,uniqueInputRates(i)); end end % for(i) for i = 1:this_block.numSimulinkOutports this_block.outport(i).setRate(outputRate); end % for(i) end % if(inputRatesKnown) % ----------------------------% (!) Set the inout port rate to be the same as the first input % rate. Change the following code if this is untrue. uniqueInputRates = unique(this_block.getInputRates); % Add addtional source files as needed. % |------------% | Add files in the order in which they should be compiled. % | If two files "a.vhd" and "b.vhd" contain the entities % | entity_a and entity_b, and entity_a contains a % | component of type entity_b, the correct sequence of % | addFile() calls would be: % | this_block.addFile('b.vhd'); % | this_block.addFile('a.vhd'); % |------------% this_block.addFile(''); % this_block.addFile(''); this_block.addFile('dqo.vhd'); this_block.addFile('Trigonometric_Function1.vhd'); this_block.addFile('Trigonometric_Function2.vhd'); this_block.addFile('Trigonometric_Function3.vhd'); this_block.addFile('Trigonometric_Function4.vhd'); this_block.addFile('Trigonometric_Function6.vhd'); this_block.addFile('Trigonometric_Function7.vhd'); return;

MATLAB ERROR:

HDL simulation model compilation failed. ERROR:HDLCompiler:104 - "xlisim_dqo.vhd" Line 1861: Cannot find <trigonometric_function6> in library <work>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file. ERROR:HDLCompiler:104 - "xlisim_dqo.vhd" Line 1864: Cannot find <trigonometric_function1> in library <work>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file. ERROR:HDLCompiler:104 - "xlisim_dqo.vhd" Line 1867: Cannot find <trigonometric_function2> in library <work>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file. ERROR:HDLCompiler:104 - "xlisim_dqo.vhd" Line 1870: Cannot find <trigonometric_function7> in library <work>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file. ERROR:HDLCompiler:104 - "xlisim_dqo.vhd" Line 1873: Cannot find <trigonometric_function3> in library <work>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file. ERROR:HDLCompiler:104 - "xlisim_dqo.vhd" Line 1876: Cannot find <trigonometric_function4> in library <work>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file. ERROR:HDLCompiler:854 - "xlisim_dqo.vhd" Line 1802: Unit <rtl> ignored due to previous errors. ERROR:HDLCompiler:854 - "xlisim_dqo.vhd" Line 2107: Unit <trigonometric_function1> ignored due to previous errors. ERROR:HDLCompiler:374 - "xlisim_dqo.vhd" Line 2117: Entity <trigonometric_function1> is not yet compiled. ERROR:HDLCompiler:69 - "xlisim_dqo.vhd" Line 2120: <signed> is not declared. ERROR:HDLCompiler:69 - "xlisim_dqo.vhd" Line 2121: <signed> is not declared. ERROR:HDLCompiler:69 - "xlisim_dqo.vhd" Line 2122: <signed> is not declared. ERROR:HDLCompiler:69 - "xlisim_dqo.vhd" Line 2123: <signed> is not declared. ERROR:HDLCompiler:69 - "xlisim_dqo.vhd" Line 2124: <signed> is not declared. ERROR:HDLCompiler:69 - "xlisim_dqo.vhd" Line 2125: <signed> is not declared.

ERROR:HDLCompiler:69 - "xlisim_dqo.vhd" Line 2126: <std_logic> is not declared. ERROR:HDLCompiler:69 - "xlisim_dqo.vhd" Line 2127: <signed> is not declared. ERROR:HDLCompiler:69 - "xlisim_dqo.vhd" Line 2128: <signed> is not declared. ERROR:HDLCompiler:69 - "xlisim_dqo.vhd" Line 2129: <signed> is not declared. Error occurred during "Simulation Initialization". Reported by: 'abc_to_dqo/Black Box'