1

Multilevel Multiphase Space Vector PWM

Algorithm Applied to Three-Phase Converters

Oscar L opez, Jacobo

Alvarez, Jes us Doval-Gandoy, Francisco Freijedo, Andr es Nogueiras and Carlos M. Pe nalver
Electronics Technology Department
University of Vigo
Vigo, Spain ES-36210
Email: olopez@uvigo.es
AbstractMultilevel technology permits the achievement of
high power ratings with voltage limited devices. Recently a new
space vector pulse-width modulation algorithm for multilevel
multiphase voltage source converters with low computational
cost has been presented. This algorithm can be used with any
number of phases; therefore it can be also used with classical
three-phase topologies. In this paper, the multiphase algorithm
is particularized for three-phase converters and compared with
previous multilevel space vector modulation techniques. Finally,
the algorithm is implemented in a low cost FPGA and it is tested
in laboratory with a real prototype by using a neutral point
clamped inverter.
I. INTRODUCTION
Multilevel converters are becoming more and more popular
in power applications, thanks to their capability to meet the in-
creasing demand of power ratings and power quality associated
with reduced harmonic distortion and lower electromagnetic
interference. Voltage source multilevel inverter topologies [1],
[2] synthesize a voltage waveform from several voltage levels,
typically obtained from several capacitors or dc sources. By
increasing the number of levels in the inverter, the output
voltages have more steps generating a staircase waveform,
which has a reduced harmonic distortion. However, a larger
number of levels increase the number of devices that must be
controlled, and consequently the modulation complexity.
In order to solve the multilevel modulation problem various
pulse-width modulation (PWM) strategies have been devel-
oped and studied in detail such as multilevel sinusoidal PWM,
multilevel selective harmonic elimination and space vector
modulation. Among these strategies, the space vector PWM
(SVPWM) stands out because it offers signicant exibility to
optimize switching waveforms and it is well suited for digital
implementation. Complexity and computational cost of tradi-
tional SVPWM techniques increase with the number of levels
of the converter, and most of them use trigonometric functions
or precomputed tables [3], [4]. In [5], a two-dimensional (2D)
SVPWM algorithm that calculates the switching vectors and
the switching times without using angles, trigonometric func-
tions or precomputed tables was proposed. A tree-dimensional
(3D) SVPWM algorithm that generalizes this 2D algorithm for
This work was supported by the Spanish Ministry of Education and Science
under the project number ENE2006-02930.
systems with neutral wire was presented in [6]. Due to their
low computational cost both techniques are suitable for real-
time hardware implementation in low cost-devices [7]. In [8], a
generalized direct PWM method in which the switching states
and the pulse-width of each phase are directly determined in
terms of the normalized reference voltage vector is proposed.
It is proved that the modulation outputs of the direct algorithm
and the previous 3D SVPWM generalized algorithm [6] are
equivalent.
Recently, in [9], a new multiphase SVPWM technique
with low computational complexity, that makes it suitable for
real-time implementation in low-cost devices, was presented.
This new technique can be used with the standard multilevel
topologies such us diode-clamped, ying capacitor, cascaded
full-bridge or even hybrid converters. That new modulation
algorithm is valid for any number of phases and consequently
it can be applied to three-phase converters.
In this paper, the multilevel multiphase SVPWM algorithm
presented in [9] is particularized for three-phase converters.
The resulting algorithm is compared with previous space
vector modulation techniques. Finally, it is implemented in a
eld-programmable gate array (FPGA) and it is tested by using
a neutral point clamped (NPC) inverter feeding and induction
motor.
II. MULTILEVEL MULTIPHASE SVPWM ALGORITHM
In multiphase converters the space vector PWM is a mul-
tidimensional problem where the vector selection can be
carried out directly in a multidimensional space. In [9], the
modulation problem of a P-phase converter is formulated in a
P-dimension space and it is solved for multilevel topologies in
which the output level of every phase is an integer multiple of a
xed voltage step V
dc
, such as ying capacitor, diode-clamped,
cascaded full-bridge or hybrid converters. The solution is an
algorithm based on a displacement plus a two-level multiphase
SVPWM modulator that is valid for any number of levels
and phases. This multiphase modulation technique is able to
handle all switching states of the inverter, without discard any
one, and it provides a sorted switching vector sequence that
minimizes the number of switchings. In addition, the algorithm
proves suitable for real-time implementation due to its low
computational complexity.
2
Since the switching states of any power converter topology
stay at discrete states, the multilevel multiphase SVPWM
technique is used to synthesize a reference voltage vector V
r
by means of a sequence of space vectors during each modu-
lation cycle. Each space vector v
sj
must be applied during an
interval t
j
in accordance with the following modulation law:
v
r
=
P+1

j=1
v
sj
t
j
where
P+1

j=1
t
j
= 1 (1)
in which
v
r
=
V
r
V
dc
= [v
r
1
, v
r
2
, . . . , v
r
P
]
T
(2)
is the normalized reference vector, which belongs to the P-
dimension real space R
P
, v
sj
= [v
s
1
j
, v
s
2
j
, . . . , v
s
P
j
]
T
are the
switching vectors, which belongs to the integer space Z
P
, and
t
j
are the normalized switching times that correspond to each
switching vector.
If expressions in (1) are rewritten in matrix format the
following system of linear equations, which must be solved
by the multilevel multiphase SVPWM algorithm, is obtained:
_

_
1
v
r
1
v
r
2
.
.
.
v
r
P
_

_
=
_

_
1 1 . . . 1
v
s
1
1
v
s
1
2
. . . v
s
1
P+1
v
s
2
1
v
s
2
2
. . . v
s
2
P+1
.
.
.
.
.
.
.
.
.
.
.
.
v
s
P
1
v
s
P
2
. . . v
s
P
P+1
_

_
_

_
t
1
t
2
.
.
.
t
P+1
_

_
. (3)
The modulation problem solving requires searching a set of
integer numbers for the coefcients matrix that permit to solve
the linear system in order to calculate the switching times.
As Fig. 1 shows, if the reference vector, v
r
, is decomposed
in the sum of an integer, v
i
, and a fractional part, v
f
, as
v
i
= integ(v
r
) Z
P
(4)
v
f
= v
r
v
i
R
P
(5)
then the modulation law in (3) can be solved by means of a
two-level multiphase modulator where the reference vector is
v
f
:
_

_
1
v
f
1
v
f
2
.
.
.
v
f
P
_

_
=
_

_
1 1 . . . 1
v
d
1
1
v
d
1
2
. . . v
d
1
P+1
v
d
2
1
v
d
2
2
. . . v
d
2
P+1
.
.
.
.
.
.
.
.
.
.
.
.
v
d
P
1
v
d
P
2
. . . v
d
P
P+1
_

_
_

_
t
1
t
2
.
.
.
t
P+1
_

_
. (6)
The solution of this new system of equations is the sequence of
displaced switching vectors, v
dj
= [v
d
1
, v
d
2
, . . . , v
d
P
]
T
, that
approximate the reference v
f
. The elements of the multilevel
switching sequence, v
sj
, can be obtained from this two-level
switching sequence by adding the integer part of the reference
to the displaced vectors:
v
sj
= v
i
+v
dj
. (7)
The switching times t
j
of the multilevel algorithm are the
same as the switching times of the two-level algorithm.
SVPWM
two-levels
P-phases
SVPWM
N-levels
P-phases
integ
Fig. 1. Block diagram of the multilevel multiphase SVPWM.
SVPWM
2-levels
P-phases
Fig. 2. Block diagram of the two-level multiphase SVPWM.
Fig. 2 shows the block diagram of the two-level multiphase
space vector PWM algorithm. This algorithm searches a
coefcient matrix
D =
_

_
1 1 . . . 1
v
d
1
1
v
d
1
2
. . . v
d
1
P+1
v
d
2
1
v
d
2
2
. . . v
d
2
P+1
.
.
.
.
.
.
.
.
.
.
.
.
v
d
P
1
v
d
P
2
. . . v
d
P
P+1
_

_
(8)
that permits to solve the linear system in (6) in order to
calculate the switching times. This matrix can be calculated
by means of
D = P
T

D (9)
where

D =
_

_
1 1 1 . . . 1
1 1 . . . 1
.
.
.
.
.
.
.
.
.
.
.
.
1
0 1
_

_
(10)
and P is a permutation matrix that sorts the elements of the
reference vector v
f
in descending order:
P
_
1
v
f
_
=
_
1
v
f
_
(11)
where v
f
= [ v
f
1
, v
f
2
, . . . , v
f
P
]
T
is the sorted vector in which
1 > v
f
1
v
f
k1
v
f
k
v
f
P
0. (12)
3
Decompose
the reference
Generate
trigger signals
Normalize
the reference
Sort the fractional
part of the reference
Rearrage columns
of the matrix D
Extract displaced
switching vectors
Calculate
switching vectors
Calculate
switching times
SVPWM
2-levels
P-phases
SVPWM
N-levels
P-phases
Fig. 3. Multilevel multiphase SVPWM algorithm ow chart.
Finally, the switching times can be calculated from v
f
as
t
j
=
_

_
1 v
f
1
, if j = 1
v
f
j1
v
f
j
, if 2 j P
v
f
P
, if j = P + 1.
(13)
The steps of this algorithm, which are summarized in the
ow chart in Fig. 3, are:
1) Calculate normalized reference, v
r
, from the reference
voltage vector using the expression in (2).
2) Decompose the normalized reference into the sum of its
integer part, v
i
, and its fractional part, v
f
, by means of
(4) and (5) respectively.
3) Calculate the permutation matrix P that sorts the vector
v
f
in descending order in accordance with (11) and (12).
4) Rearrange the rows of the triangular matrix

D in order
to obtain the matrix D by means of (9).
5) Extract the displaced switching vectors, v
dj
, from the
matrix D by taking into account the expression in (8).
6) Obtain the nal switching vectors, v
sj
, by adding the
integer part of the reference, v
i
, to the displaced switch-
ing vectors v
dj
according to (7).
7) Calculate the time corresponding to each switching
vector from components of the vector v
f
by means of
expression in (13).
Finally, trigger signals have to be generated from the switching
vectors and the switching times. The relationship between
switching states and the particular trigger signals of transistors
depends on the multilevel topology [10].
III. ALGORITHM APPLICATION TO THREE-PHASE
CONVERTERS
The modulation algorithm for three-phase systems is ob-
tained making P = 3 in the multiphase algorithm. Therefore,
in three-phase converters, the modulation problem is formu-
lated in a three-dimension space and the switching states are
three-dimension integer vectors:
v
s
= [v
s
a
, v
s
b
, v
s
c
]
T
Z
3
. (14)
And taking into account (2), the normalized voltage reference,
v
r
, is the three-dimension real vector:
v
r
=
V
r
V
dc
= [v
r
a
, v
r
b
, v
r
c
]
T
R
3
(15)
where V
dc
is the voltage step of the multilevel converter.
In accordance with (4) and (2), the integer and fractional
parts of the reference vector are
v
i
= integ(v
r
) = [v
i
a
, v
i
b
, v
i
c
]
T
Z
3
(16)
v
f
= v
r
v
i
= [v
f
a
, v
f
b
, v
f
c
]
T
R
3
. (17)
From v
f
, the permutation matrix, P, can be determined by
testing the following three logical conditions:
C
ab
= [v
f
a
v
f
b
]
C
bc
= [v
f
b
v
f
c
]
C
ca
= [v
f
c
v
f
a
].
(18)
Table I shows the relationship between the results of these
three conditions and the permutation matrix P. Cases 000 and
111 are not coherent, therefore there are only six different
situations that must be taken into account.
Next, the matrix D is calculated from the upper triangular
matrix

D by means of (9) as
D = P
T
_

_
1 1 1 1
0 1 1 1
0 0 1 1
0 0 0 1
_

_
. (19)
The sequence of displaced vectors {v
d1
, v
d2
, v
d3
, v
d4
} is
extracted from the matrix Dtaking into account the expression
in (8):
D =
_

_
1 1 1 1
v
d
a
1
v
d
a
2
v
d
a
3
v
d
a
4
v
d
b
1
v
d
b
2
v
d
b
3
v
d
b
4
v
d
c
1
v
d
c
2
v
d
c
3
v
d
c
4
_

_
(20)
From (7), the nal switching sequence is calculated adding
the integer part of the reference to the vectors of the displaced
switching sequence:
v
s1
= v
i
+v
d1
v
s2
= v
i
+v
d2
v
s3
= v
i
+v
d3
v
s4
= v
i
+v
d4
.
Finally, the time corresponding to each switching vector is
calculated directly from the components of v
f
by means of
4
TABLE I
PERMUTATION MATRIX
C
ab
C
bc
C
ca
Ordered vector v
f
Matrix P
0 0 1
v
f
a
= v
f
c
v
f
b
= v
f
b
v
f
c
= v
f
a
_

_
1 0 0 0
0 0 0 1
0 0 1 0
0 1 0 0
_

_
0 1 0
v
f
a
= v
f
b
v
f
b
= v
f
a
v
f
c
= v
f
c
_

_
1 0 0 0
0 0 1 0
0 1 0 0
0 0 0 1
_

_
0 1 1
v
f
a
= v
f
b
v
f
b
= v
f
c
v
f
c
= v
f
a
_

_
1 0 0 0
0 0 1 0
0 0 0 1
0 1 0 0
_

_
1 0 0
v
f
a
= v
f
a
v
f
b
= v
f
c
v
f
c
= v
f
b
_

_
1 0 0 0
0 1 0 0
0 0 0 1
0 0 1 0
_

_
1 0 1
v
f
a
= v
f
c
v
f
b
= v
f
a
v
f
c
= v
f
b
_

_
1 0 0 0
0 0 0 1
0 1 0 0
0 0 1 0
_

_
1 1 0
v
f
a
= v
f
a
v
f
b
= v
f
b
v
f
c
= v
f
c
_

_
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
_

_
(13) as
t
1
= 1 v
f
a
t
2
= v
f
a
v
f
b
t
3
= v
f
b
v
f
c
t
4
= v
f
c
.
If the modulation problem is solved in all the six possible
cases in Table I then the results shown in Table II are obtained.
This table proves the application of the multiphase algorithm
to a three-phase system is very simple. After normalize the
reference vector, it only requires three comparison operations
and a few simple additions in order to evaluate the switching
vectors and its corresponding switching times.
The simplicity of the new algorithm is here shown by means
of an example. Let us consider a three-phase drive where the
voltage reference for each phase is purely sinusoidal:
V
r
= A
_
_
sin(wt)
sin(wt + 2/3)
sin(wt 2/3)
_
_
.
If a voltage amplitude A = 285 V and a speed w = 2 50 rd/s
are considered, the instantaneous reference when t = 9 ms is
V
r
= [88, 279, 191]
T
V.
From (2), if voltage step of the converter is V
dc
= 150 V then
TABLE II
VECTOR SEQUENCE AND SWITCHING TIMES
C
ab
C
bc
C
ca
Vector sequence v
sj
Switching times t
j
0 0 1
v
s1
= v
i
+ [0, 0, 0]
T
v
s2
= v
i
+ [0, 0, 1]
T
v
s3
= v
i
+ [0, 1, 1]
T
v
s4
= v
i
+ [1, 1, 1]
T
t
1
= 1 v
f
c
t
2
= v
f
c
v
f
b
t
3
= v
f
b
v
f
a
t
4
= v
f
a
0 1 0
v
s1
= v
i
+ [0, 0, 0]
T
v
s2
= v
i
+ [0, 1, 0]
T
v
s3
= v
i
+ [1, 1, 0]
T
v
s4
= v
i
+ [1, 1, 1]
T
t
1
= 1 v
f
b
t
2
= v
f
b
v
f
a
t
3
= v
f
a
v
f
c
t
4
= v
f
c
0 1 1
v
s1
= v
i
+ [0, 0, 0]
T
v
s2
= v
i
+ [0, 1, 0]
T
v
s3
= v
i
+ [0, 1, 1]
T
v
s4
= v
i
+ [1, 1, 1]
T
t
1
= 1 v
f
b
t
2
= v
f
b
v
f
c
t
3
= v
f
c
v
f
a
t
4
= v
f
a
1 0 0
v
s1
= v
i
+ [0, 0, 0]
T
v
s2
= v
i
+ [1, 0, 0]
T
v
s3
= v
i
+ [1, 0, 1]
T
v
s4
= v
i
+ [1, 1, 1]
T
t
1
= 1 v
f
a
t
2
= v
f
a
v
f
c
t
3
= v
f
c
v
f
b
t
4
= v
f
b
1 1 0
v
s1
= v
i
+ [0, 0, 0]
T
v
s2
= v
i
+ [1, 0, 0]
T
v
s3
= v
i
+ [1, 1, 0]
T
v
s4
= v
i
+ [1, 1, 1]
T
t
1
= 1 v
f
a
t
2
= v
f
a
v
f
b
t
3
= v
f
b
v
f
c
t
4
= v
f
c
1 0 1
v
s1
= v
i
+ [0, 0, 0]
T
v
s2
= v
i
+ [0, 0, 1]
T
v
s3
= v
i
+ [1, 0, 1]
T
v
s4
= v
i
+ [1, 1, 1]
T
t
1
= 1 v
f
c
t
2
= v
f
c
v
f
a
t
3
= v
f
a
v
f
b
t
4
= v
f
b
normalized voltage reference is
v
r
=
V
r
V
dc
= [0.59, 1.86, 1.27]
T
.
By means of (4) and (5), this vector is decomposed into an
integer and a fractional part:
v
i
= integ(v
r
) = [0, 2, 1]
T
v
f
= v
r
v
i
= [0.59, 0.14, 0.27]
T
.
If the conditions in (18) are calculated the results are
C
ab
= [v
f
a
v
f
b
] = 1
C
bc
= [v
f
b
v
f
c
] = 0
C
ca
= [v
f
c
v
f
a
] = 0.
The case 100 of Table II provides the following switching
sequence:
v
s1
= v
i
+ [0, 0, 0]
T
= [0, 2, 1]
T
v
s2
= v
i
+ [1, 0, 0]
T
= [1, 2, 1]
T
v
s3
= v
i
+ [1, 0, 1]
T
= [1, 2, 2]
T
v
s4
= v
i
+ [1, 1, 1]
T
= [1, 1, 2]
T
.
together with their corresponding switching times:
t
1
= 1 v
f
a
= 0.41
t
2
= v
f
a
v
f
c
= 0.32
t
3
= v
f
c
v
f
b
= 0.13
t
4
= v
f
b
= 0.14.
5
It is important to remark that consecutive vectors of the
sequence are adjacent. Therefore, the number of switchings
is minimized.
IV. COMPARISON WITH PREVIOUS ALGORITHM
Although the nomenclature is different
1
, if the new three-
phase algorithm is compared with the 3D SVPWM generalized
algorithm then it notices that the Table II here presented is
the same as the table that details the states sequences and the
switching times in [6]. In fact, the six cases corresponding to
the six tetrahedrons in each subcube of the paper are equivalent
to the six cases derived from the three comparison operations
of this work. In particular, the cases 1.1, 1.2, 1.3, 2.1, 2.2 and
2.3 are respectively equivalent to the cases 100, 101, 001 ,011,
010 and 110 in this paper.
Even though, the comparison operations in both algorithms
are not identical, the differences are in the boundaries of the
tetrahedrons where two or more components of the fractional
part of the reference are equal. In such cases both algorithm
provide different switching sequences, but the switching vec-
tors that are different in those sequences have a zero switching
time so they are not executed and the modulation output is
identical in both algorithms.
As a consequence, the multiphase algorithm particularized
the three-phase systems in this paper is nearly the same as the
3D SVPWM generalized algorithm presented in [6]. Fig. 4
shows the modulation output of both modulation techniques
when a balanced three-phase reference with a normalized
amplitude of 1.9 is considered. A low switching frequency
(twenty times the fundamental) has been selected in order
to make the comparison easier. In both cases the modulation
output is identical, even in the sixth sampling period, when
v
r
= [1.9, 0.95, 0.95]
T
, in which the fractional parts of the
phases b and c are equal. In this particular case the multilevel
algorithm particularized for three-phase systems presented
in this paper provides the following switching vectors and
switching times (case 110):
v
s1
= [1, 1, 1]
T
t
1
= 0.10
v
s2
= [2, 1, 1]
T
t
2
= 0.85
v
s3
= [2, 0, 1]
T
t
3
= 0.00
v
s4
= [2, 0, 0]
T
t
4
= 0.05
whereas the 3D generalized SVPWM algorithm in [6] provides
the following results (case 1.1):
v
s1
= [1, 1, 1]
T
t
1
= 0.10
v
s2
= [2, 1, 1]
T
t
2
= 0.85
v
s3
= [2, 1, 0]
T
t
3
= 0.00
v
s4
= [2, 0, 0]
T
t
4
= 0.05.
Both switching sequences differ in their third output vector.
Nevertheless, those vectors has assigned a zero switching time
so nally none of them must be generated by the inverter and
the trigger signals are identical in both cases.
1
The terms [S
j
a
, S
j
b
, S
j
c
], [a, b, c], [u
a
, u
b
, u
c
] and d
j
in [6] are respec-
tively the same as the terms [v
s
a
j
, v
s
b
j
, v
s
c
j
], [v
i
a
, v
i
b
, v
i
c
], [v
r
a
, v
r
b
, v
r
c
]
and t
j
in this paper.
0 0.5 1
2
1
0
1
2
V
o
l
t
a
g
e

(
p
.
u
.
)
Normalized reference voltage
a
b
c
0 0.5 1
2
1
0
1
2
O
u
t
p
u
t

v
o
l
t
a
g
e

(
p
.
u
.
)
New threephase SVPWM algorithm
0 0.5 1
2
1
0
1
2
O
u
t
p
u
t

v
o
l
t
a
g
e

(
p
.
u
.
)
3D SVPWM generalized algorithm
0 0.5 1
1
0.5
0
0.5
1
Time (p.u.)
D
i
f
f
.

(
%
)
Ouputvoltage difference between both algoritms
Fig. 4. Simulation Results.
Since both algorithms are nearly same then all considera-
tions made in other works about the 3D SVPWM generalized
algorithm also applies to this algorithm [7]. Hence, it can
be considered as an extension of the 2D algorithms [6].
It is also equivalent to the 3D direct generalized algorithm
proposed in [8]. It can be used as a modulation algorithm in all
applications needing a three-dimension control vector such as
active lters with four-wire and single-phase distorting loads
which generate large neutral currents, where the conventional
2D space vector modulation can not be used.
Since the algorithm is a the particularization of the multi-
level multiphase space vector PWM in [9] it inherits some
features such as it minimizes the number of switchings,
it does not need trigonometric functions, look-up tables or
memories to store predened switching sequences and it has
low computational cost. Hence, the algorithm is well suited
for real time implementation in low cost devices.
V. HARDWARE IMPLEMENTATION
The SVPWM algorithm was described for a three-level
inverter with the very high speed integrated circuit hardware
description language (VHDL) and it was implemented by
6
TABLE III
RESOURCES SUMMARY
Target Device : xc3s200
Number of Slice Flip Flops: 2,179 out of 3,840 56%
Number of 4 input LUTs: 2,282 out of 3,840 59%
Number of occupied Slices: 1,669 out of 1,920 86%
Total Number 4 input LUTs: 2,450 out of 3,840 63%
Number of bonded IOBs: 63 out of 173 36%
IOB Flip Flops: 39
Number of Block RAMs: 0 out of 12 0%
Number of MULT18X18s: 0 out of 12 0%
Number of GCLKs: 8 out of 8 100%
Number of Startups: 1 out of 1 100%
Total equivalent gate count for design: 32,174
1 Phase a:
Phase b:
Phase c:
1 0 0 0 0 0
0 0 0 0 1 1 1
1 1 1 1 1 1 0
T
Dead time
Fig. 5. Trigger signals.
using a Digilent S3 board. This board hosts a XC3S200
FPGA from Xilinx, which has 4.320 logic cells, each one
constituted by two 16 1 look-up tables and two ip-ops.
This FPGA also has twelve 18 18 hardware multipliers, as
well as twelve 18 kb block random access memories (BRAM).
Table III shows a summary of the resources used by our
implementation. It is important to remark that the BRAMs and
the multipliers available in the FPGA were not used because
the algorithm does not need data storage or multiplication
operations.
Fig. 5 shows the FPGA output waveforms that correspond
to the trigger signals in the case v
r
= [0.16, 0.52, 0.77]
T
.
The needed dead time in complementary trigger signals was
implemented by delaying the rising edges.
The new algorithm was tested with a three-level NPC in-
verter driving a star connected induction motor. A 220/380 V,
1.420 r.p.m., 1.35 kW rated motor was used. According with
the motor characteristics a dc bus of 300 V was selected.
Fig. 6 shows a diagram and a photograph of the experimental
setup used in tests. It includes the power converter, the FPGA
board and a personal computer with a DSPACE DS1103 PPC
Controller Board.
A reference voltage with 50 Hz fundamental frequency
and a 10 kHz output switching frequency were considered.
Fig. 7 shows the inverter output voltage, besides the low-
order voltage harmonics, in the cases of sinusoidal reference
with and without third harmonic injection. Channels one and
three of the oscilloscope show the phase and the phase-to-
phase inverter output waveforms. Channels two and four are
Control SVPWM
NPC
inverter
150 V
150 V
Trigger
signals
DSPACE FPGA
Motor
Optical
link
(a)
DSPACE
FPGA
Motor
NPC inverter
Optical
link
dc bus
(b)
Fig. 6. Experimental test setup. (a) Diagram. (b) Photograph.
(a)
(b)
Fig. 7. Phase a inverter output voltage. Ch1: phase voltage, Ch2: ltered
phase voltage, Ch3: phase-to-phase voltage, Ch4: ltered phase-to-phase
voltage. (a) Without harmonic injection. (b) With third harmonic injection.
the same signals after been ltered. Fig. 7a shows the case
of purely sinusoidal reference with a normalized amplitude of
0.9 p.u.. In this case the low-order harmonics are low and
the total harmonic distortion (THD) is 4.8%. Fig. 7b shows
the case where a third harmonic of amplitude 0.4 p.u. was
added to the reference. In this case the high THD obtained
corresponds mainly to the injected harmonic.
7
VI. CONCLUSION
In this paper the recent SVPWM algorithm for multilevel
multiphase converters is particularized for three-phase sys-
tems. This particularized algorithm provides a sorted switching
vector sequence that minimizes the number of switchings. It
can be used with the standard multilevel topologies with any
number of levels. In addition, the proposed SVPWM algorithm
proves suitable for real-time implementation due to its low
computational complexity.
The particularized algorithm is demonstrated that is nearly
the same as the classical 3D space vector modulation gener-
alized algorithm for multilevel converters.
The three-level version of the new algorithm was imple-
mented in a low-cost FPGA and it was successfully tested by
using a neutral point clamped inverter.
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