Introduction to VHDL

Introduction to VHDL
HDL is short for Hardware Description Language VHDL VHSIC Hardware Description Language (VHSIC: Very High Speed Integrated Circuits) VHDL is a standard developed by IEEE (Institute of Electrical and Electronics Engineers) We will use DirectVHDL program for writing and simulating VHDL codes.

DirectVHDL
An interactive VHDL simulator Allows editing and simulating VHDL design without complicated setup or compilation procedures DirectVHDL includes the following: - VHDL Workspace - VHDL Editor - VHDL Simulator - VHDL Tutorial

Using DirectVHDL
Double click the symbol to open the VHDL Workspace. VHDL Workspace is a manager that serves as a starting point to launch the VHDL editor and simulator. It is the main workstation of DirectVHDL program.

VHDL Workspace

VHDL Workspace

Opening a new file in VHDL Workspace

Opening a new file in VHDL Workspace

VHDL Editor

Simulation of a .vhd file

Simulation of a .vhd file

Simulation of a .vhd file

Changing Time Step

Changing View Interval

Simulation of a .vhd file

Simulation of a .vhd file

Adding Trace/Watch

Opening the waveform report

Programming in VHDL
There are three programming strategies in VHDL: - Dataflow - Structural - Behavioral Most of time a mixture of these three methods are used. Each statement in VHDL ends with ; The comment lines begin with --

Dataflow programming in VHDL

In data-flow approach, circuits are described by indicating how the inputs and outputs of built-in primitive components are connected. In other words, we describe how signals (data) flow through the circuit.

Dataflow programming example in VHDL

entity sample_gate is port(a,b: in bit; c: out bit); end sample_gate; architecture dataflow of sample_gate is begin c <= a nor b; end dataflow;

Dataflow programming example in VHDL

Structural programming in VHDL

In this strategy, every portion of a VHDL design is considered as a block and they are named as entity. The entity describes the interface to that block and a seperate part associated with the entity describes how that block operates.

Structural programming example

Structural programming example: Code Part-1

entity and_gate is port(a1,b1: in bit; c1: out bit); end and_gate; entity nor_gate is port(a2,b2: in bit; c2: out bit); end nor_gate; entity or_gate is port(a3,b3: in bit; c3: out bit); end or_gate; entity simple is port(a4,b4,c4,d4: in bit; g4: out bit); end simple;

Structural programming example: Code Part-2

architecture dataflow of and_gate is begin c1 <= a1 and b1; end dataflow; architecture dataflow of nor_gate is begin c2 <= a2 nor b2; end dataflow; architecture dataflow of or_gate is begin c3 <= a3 or b3; end dataflow;

Structural programming example: Code Part-3

architecture structure of simple is signal e4:bit; signal f4:bit;

component and_gate port(a1,b1: in bit; c1: out bit); end component; component nor_gate port (a2,b2: in bit; c2: out bit); end component; component or_gate port (a3,b3: in bit; c3: out bit); end component;

begin n1:and_gate port map (a4,b4,e4); n2:nor_gate port map (c4,d4,f4); n3:or_gate port map (e4,f4,g4); end structure;

Structural programming example:

Same circuit but programmed with dataflow strategy

entity sample_gate_dataflow is port (a,b,c,d: in bit; o3: out bit); end sample_gate_dataflow; architecture dataflow of sample_gate_dataflow is signal o1: bit; signal o2: bit; begin o1<=a and b; o2<=c nor d; o3<=o1 or o2; end dataflow;

Same circuit but programmed with dataflow strategy

SR Latch using dataflow strategy

SR Latch using dataflow strategy: Code

entity latch is port(s,r: in bit; q,nq: out bit); end latch; architecture dataflow of latch is signal q: bit := '1'; signal nq: bit := '0'; begin q <= r nor nq; nq <= s nor q; end dataflow;

SR Latch using dataflow strategy: Simulation

Behavioral Programming
Blackbox approach to modeling. Used to model complex components that would be tedious to model using the other methods. Behavioral descriptions are supported by process statement The statements in the process are used to compute the outputs of the process from its inputs.

A behavioral & structural programming example: 4-bit Binary Counter Design using D-Flip Flops

4-bit Binary Counter Design using D-Flip Flops Code: Part-1

entity Dflipflop is Port(resetn,D,clock :in bit; Q1,Q2 : out bit); end Dflipflop; -architecture behavior of Dflipflop is begin p1: process (resetn,D,clock) begin if resetn = '1' then Q1<='0'; Q2<='1'; elsif clock = '1' and clock'event then Q1 <= D; Q2 <= NOT D; end if; end PROCESS p1; end behavior; --

4-bit Binary Counter Design using D-Flip Flops Code: Part-2

entity binary_counter is port(resetn,D,clk:in bit; Qb1,Qb1n,Qb2,Qb2n,Qb3,Qb3n,Qb4,Qb4n: out bit); end binary_counter; architecture structure of binary_counter is component Dflipflop Port(resetn,D,clock :in bit; Q1,Q2 : out bit); end component; n1: Dflipflop port map (resetn,Qb1n,clk,Qb1,Qb1n); n2: Dflipflop port map (resetn,Qb2n,Qb1n,Qb2,Qb2n); n3: Dflipflop port map (resetn,Qb3n,Qb2n,Qb3,Qb3n); n4: Dflipflop port map (resetn,Qb4n,Qb3n,Qb4,Qb4n); end structure;

4-bit Binary Counter Design using D-Flip Flops -Simulation-

4-bit Binary Counter Design using D-Flip Flops -Simulation-

References
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