8051 Microcontroller Interview Questions Questions may be asked in interview of ECE students related to 8051 microcontroller: Microcontroller manufacturers

have been competing for a long time for attracting choosy customers and every couple of days a new chip with a higher operating frequency, more memory and upgraded A/D converters appeared on the market.

1)What is meant by micro controller? A device which contains the microprocessor with integrated peripherals like memory, serial ports, parallel ports, timer/counter, interrupt controller, data acquisition interfaces like ADC, DAC is called micro controller.

2)List the features of 8051 micro controllers?

Single supply +5v operation using HMOS technology. 4096 bytes program memory on-chip. 128 data memory on chip.

4 register banks 2 multiple modes, 16 bit timer/counter Extensive Boolean processing capabilities. 64KB external RAM size. 32 bi-directional I/O lines.

3)Explain the operating mode 0 of 8051 serial port? In this mode serial data enters and exists through RXD, TXD outputs the shift clock. 8-bits are transmitted or received:8-data bits(LSB first). The baud rate is fixed at 1/12 the oscillator frequency.

4)Explain the operating mode 2 of 8051 serial port? In this mode 11 bits are transmitted (through TXD) or received (through (RXD): a start bit(0), 8 data bits( LSB first), a programmable 9th data bit and a stop bit(1). On transmit, the 9th data bit can be assigned thevalue 0 or 1. On receive, the9th data bit go into the RB8 in special function register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency.

5)Explain the mode 3 of 8051 serial port? In this mode, 11 bits are transmitted (through TXD) or (received (through RXD): a start bit(0), 8 data bits(LSB first), a programmable 9th data bit and a stop bit(1).It is same as mode 2 except the baud rate. The baud rate in mode 3 is variable.

6)Explain the interrupts of 8051 micro controller?

External interrupt 0 (IE0) Highest priority Timer interrupt 0 (TF0) External interrupt 1 (IE1) Timer interrupt 1 (TF1) Serial port Interrupt Receive interrupt (RI) - lowest priority Transmit interrupt (TI)

7)How many bytes of internal RAM and ROM supported by 8051 micro controller?

128 bytes of internal RAM and 4 bytes of ROM.

8)Define machine cycle of 8051? 8051 machine cycle consists of 6 states, S1 through S7. One state is made up of 2 clock pulses. Thus 12 clock period constitute one machine cycle. Two clock periods in a state is termed as phase 1 and phase 2.

9) What are the special function of port 0 of 8051? Port 0 is used as a multiplexed low order address/data bus during the external memory access. When ALE is enabled, the address on port 0 pins are latched and bus isready to act asa data bus when ALE is low.

10)What are the alternative function of port 3 of 8051? Serial data input (P3.0), serial data output (P3.1), external interrupt 0 (P3.2), external interrupt 1 (P3.3), external input for timer 0(P3.4), external input for timer 1 (P3.5), external memory write pulse (P3.6), external memory read (P3.7) are the alternative functions of port 3.

11)What are the use of scratch pad area of internal RAM of 8051? In internal RAM 80 bytes constitutes the scratch pad area. The scratch pad bytes can be programmed as a general purpose registers.

12)What are the flags supported by 8051 controller?

Carry flag Auxiliary carry flag Over flow flag General purpose user flag Register bank select bit one Register bank select bit zero Parity flag

13)What is meant by Power-on- Reset in 8051 controller? When RESET pin is activated, the 8051 jumps to address location 0000H. This is called as Power-on-Reset. Reset pin is considered as a sixth interrupt source of 8051.

14)What are the significance of SFRs? SFRs denotes Special function Registers the controller registers such as port peripheral control register, accumulator, PC and in SFR region. of8051 controller. All latches, timer register, DPTR all areavailable

15)What are the different group of instructions supported by 8051?

Data Transfer Group Arithmetic Group Logical Group Branching Group Bit manipulation Group

16)Write a program to mask the 0th and 7th bit using 8051? MOV A,#data ANL A,#81 MOV DPTR,#4500 MOVX @DPTR,A LOOP: SJMP LOOP

17) List the addressing modes of 8051?

Direct addressing Register addressing Register indirect addressing Implicit addressing Immediate addressing Index addressing Bit addressing

18)Write about CALL statement in 8051? There are two CALL instructions. They are

LCALL(Long call) ACALL(Absolute call)

19) Write about the jump statement? There are three forms of jump. They are LJMP (Long jump) 16 bit address AJMP(Absolute jump) 11 bit address SJMP (Short jump) relative address

20)Write a program to find the 2s complement using 8051? MOV A, R0 CPL A INC A

21)Write a program to swap two numbers using 8051? MOV A,# data SWAP A

22)Write a program to subtract two numbers & exchange the digits using 8051? MOV A,#9F MOV R0,#40 SUBB A,R0 SWAP A

23)What are the different types of Address decoding Techniques? Absolute decoding/Full decoding Linear decoding/Partial decoding

24) Comparison between full address decoding and Partial address decoding?

Full address decoding 1. All higher address decoded to

Partial address decoding lines are1. Few lines are decoded higher address

select the memory or I/O device.

to select the memory or I/O device.

2. More design

hardware

is required

to2.

Hardware required

to

design

decoding logic.

decoding logic is less and sometimes it can be elimibated

3. Higher cost for decoding circuit.

3. Less cost for decoding circuit.

4. No multiple addresses.

4. It has a disadvantage of multiple addresses. (Shadow addresses)

5. Used in large systems.

5. Used in small systems.

25. What is the significance of wait state generator? This is used to transfer data between slower I/O device and the microprocessor. In some applns, the speed of I/O systems is not compatible with the microprocessors timings. So the microprocessor has to confirm whether the peripheral is ready or not. If READY pin is high, the peripheral is ready otherwise 8085 enters in to wait state.

26. What is a Non-maskable interrupt? It is unaffected by any mask or interrupt enable. Eg: TRAP

27. What is a Data pointer register? The data pointer register (DPTR) consists of a high byte(DPH) and a low byte (DPL) functions to hold 16 bit address. It may be manipulated as a 16-bit data register or as independent 8-bit registers. It serves as a base register in indirect jumps, look up table instructions and external data transfer.

28) What are the operating modes of 8279? 1. Input modes

Scanned keyboard Scanned sensor matrix Strobed input

2.Display modes

Left entry (Type writer mode) Right entry (Calculator mode)

29)What are the different functional units in 8279?

CPU interface section Keyboard section Display section Scan section

30)What are the priority modes in 8259?

Fully nested mode Special fully nested mode c. Special Masked mode e. Rotating Priority mode

Polled mode

31)What is IMR(Interrupt mask register)? IMR stores the masking bits of the interrupt lines to be masked. This register can be programmed by an operation command word (OCW).

32)What is priority resolver? It determines the priorities of the bits set in the Interrupt request register (IRR), bit corresponding to the highest priority interrupt input is set in the ISR during INTA input.

33)What is the use of IRR? The interrupt request register is used to store all the interrupt levels which are requesting the service. The eight interrupt inputs sets corresponding bits of the Interrupt Request Register upon the service request.

34)What is Interrupt service register(ISR)? The interrupt service being serviced. register stores all the levels that are currently

35) What is the difference between SHLD and LHLD? SHLD- Store HL register pair in memory. This instruction is used to store the contents of H and L register directly in to memory. LHLD- Load HL register pair from memory.

This instruction copies the contents of memory location given with in the instruction in to the L register and the contents of next memory location in to the H register.

36)What is the difference between STAX and LDAX? STAX rp Store the contents of Accumulator register (A) in memory location whose address is specified by BC or DE register pair. LDAX rp Load Accumulator register (A) with the contents of memory location whose address is specified byBC or DE register pair.

37)Write an assembly language program to transfer data from memory block B1 to memory block B2? MVI C,0AH; Initialize counter LXI H, 2200H; Initialize source memory pointer LXI D, 2300H; Initialize destination memory pointer Loop: MOV A,M; Get byte from source memory block

STAX D; Store byte in the destination memory block INX H; Increment source memory pointer INX D; Increment destination memory pointer DCR C; Decrement counter JNZ Loop ; If counter 0 repeat HLT

38)What are the types of branching instructions?

Jump instructions Call and Return instructions Restart instructions

39)Write an assembly language program to add 2 BCD numbers? LXI H,2200H; Initialize pointer MOV A,M ; Get the first number INX H; Increment the pointer ADD M ; Add two numbers DAA ; Convert HEX to valid BCD STA 2300; store the result

HLT

40) Explain the instruction LXI rp,data (16)? LXI rp, data(16) Load 16 bit immediate data to specified register pair or stack pointer. The rp is 16 bit register pairs such as BC, DE, HL or stack pointer.

41)Write the difference between LDA and STA instruction?

LDA Load data in to Accumulator register(A) directly from the address specified with in the instruction. STA Store the contents of Accumulator register(A) to the address specified with in the instruction.

42)What are the types of rotate instructions?

RLC Rotate Accumulator Left RRC- Rotate Accumulator Right RAL Rotate Accumulator Left through Carry RAR - Rotate Accumulator Right through Carry

43)What are the operating modes of 8255? Bit set/Reset mode I/O modes a)mode 0 : Simple input/output b)mode 1 : Input/output with handshake c)mode 2 : Bi-directional I/O data transfer

44)What are the priority modes in 8259?

Fully nested mode Special fully nested mode Rotating priority mode Special mask mode Poll mode

45) What is the use of SWAP function in 8051?

SWAP A : Swap nibbles with in the Accumulator bytes. It interchanges the low and high order nibbles of the Accumulator (bits 0-3 and bits 4-7)

46)What is SCON? SCON is the serial port control register , which contains not only the mode selection bits (SM0 SM2 ,REN), but also the 9th data bit for transmit and receive (TB8 and RB8) and the serial port interrupt bits (TI and RI). SM0 Serial port mode control bit 0 SM1 Serial port mode control bit 1 SM2 Serial port mode control bit 2 REN Receiver enable control bit TB8 Transmit bit 8 RB8 Receive bit 8 TI Transmit Interrupt flag RI Receive interrupt flag

47)How we calculate the Baud rate for serial port in mode 0? Baud Rate = Oscillator frequency/12

48)What is the significance of TXD and RXD pins in 8051? TXD Transmit data pin for serial port in UART mode. Clock output in shift register mode. RXD Receive data pin for serial port in UART mode. Data I/O pin in shift register mode.

49)Write two examples of Register indirect Addressing modes in 8051? MOV A,@R0 ; Load thecontents pointed by R0 in A. ADD A,@R1 ; Add thecontents of A and thecontents pointed by R1.

50)What is Accumulator Register? It is an 8 bit register. It holds a source operand and receives the result of the arithmetic instructions (Addition, Subtraction, Multiplication and Division)

4 Kb of ROM is not much at all. 128b of RAM (including SFRs) satisfies the users basic needs. 4 ports having in total of 32 input/output lines are in most cases sufficient to make all necessary connections to peripheral environment.

1. Intel 8051 follows which architecture: Harvard or Newman? 2. What is the architecture? difference between Harvard and Newman

In the architecture Von Mann, the data and the program are stored in the same common memory unit whereas in the architecture Harvard the data and the program are stored in different memory. 3. 8051 was developed using which technology nmos or pmos? 4. Why 8051 is called 8 bit microcontroller? 5. What is the width of data bus? 6. What is the width of address bus? 7. How many memory locations address bus can access (also tell in kb)? 8. The memory locations that the address bus can access will be of RAM or ROM or both? 9. How much on-chip RAM is available? 10.On-chip RAM is also called _____ memory? 11.How much on-chip ROM is available? 12.On-chip ROM is also called _____ memory? 13.How many byte is of the bidirectional input/output port? 14.What is UART? 15.The original 8051 core runs at how many clock cycles per machine cycle? 16.With 12 MHz clock frequency how many instructions(of 1 machine cycle and 2 machine cycle) it can execute per second?

17.What are the four distinct types of memory in 8051? 18.Internal RAM is located from address 0x00 to ___? 19.Tell the addresses which can be accessed directly? 20.Tell the addresses which are bit addressable? 21.Tell the addresses which can be accesssed only by indirect addressing mode? 22.Tell the addresses where the special function registers are present and also which addressing mode is used to access them? 23.Are SFR bit addressable or byte addressable? 24.What type of memory is Program Memory? Read only/Read-write/write only? 25.*Does the program memory can be only used for storing code only, if not then how that data is accessed? 26.What is the address of external data memory from which it starts? 27.How the external data memory is accessed?
The internal RAM memory The 8051 has two 16-bit counter/timers. of the 8051 is: 128 B

The address space of the 8051 is divided into four distinct areas: internal data, external data, internal code, and external code. Data transfer from I/O to external data memory can only be done with the MOVX command.

There are five interrupt sources for the 8051, which means that they can recognize 5 different events that can interrupt regular program execution. Each interrupt can be enabled or disabled by setting bits of the IE register. Likewise, the whole interrupt system can be disabled by clearing the EA bit of the same register.
The special function registers are maintained in the next 128 locations after the general-purpose data storage and stack.

MOV A, @ R1 will copy the contents of memory whose address is in R1 to the accumulator
A label is used to name a single line of code.

Pins 1-8: Port 1 Each of these pins can be configured as an input or an output. Pin 9: RS A logic one on this pin disables the microcontroller and clears the contents of most registers. In other words, the positive voltage on this pin resets the microcontroller. By applying logic zero to this pin, the program starts execution from the beginning. Pins10-17: Port 3 Similar to port 1, each of these pins can serve as general input or output. Besides, all of them have alternative functions: Pin 10: RXD Serial asynchronous communication input or Serial synchronous communication output. Pin 11: TXD Serial asynchronous communication output or Serial synchronous communication clock output. Pin 12: INT0 Interrupt 0 input. Pin 13: INT1 Interrupt 1 input. Pin 14: T0 Counter 0 clock input. Pin 15: T1 Counter 1 clock input. Pin 16: WR Write to external (additional) RAM. Pin 17: RD Read from external RAM. Pin 18, 19: X2, X1 Internal oscillator input and output. A quartz crystal which specifies operating frequency is usually connected to these pins. Instead of it, miniature ceramics resonators can also be used for frequency stability. Later versions of microcontrollers operate at a frequency of 0 Hz up to over 50 Hz. Pin 20: GND Ground. Pin 21-28: Port 2 If there is no intention to use external memory then these port pins are configured as general inputs/outputs. In case external memory is used, the higher address byte, i.e. addresses A8-A15 will appear on this port. Even though memory with capacity of 64Kb is not used, which means that not all eight port bits are used for its addressing, the rest of them are not available as inputs/outputs.

Pin 29: PSEN If external ROM is used for storing program then a logic zero (0) appears on it every time the microcontroller reads a byte from memory. Pin 30: ALE Prior to reading from external memory, the microcontroller puts the lower address byte (A0-A7) on P0 and activates the ALE output. After receiving signal from the ALE pin, the external register (usually 74HCT373 or 74HCT375 add-on chip) memorizes the state of P0 and uses it as a memory chip address. Immediately after that, the ALU pin is returned its previous logic state and P0 is now used as a Data Bus. As seen, port data multiplexing is performed by means of only one additional (and cheap) integrated circuit. In other words, this port is used for both data and address transmission. Pin 31: EA By applying logic zero to this pin, P2 and P3 are used for data and address transmission with no regard to whether there is internal memory or not. It means that even there is a program written to the microcontroller, it will not be executed. Instead, the program written to external ROM will be executed. By applying logic one to the EA pin, the microcontroller will use both memories, first internal then external (if exists). Pin 32-39: Port 0 Similar to P2, if external memory is not used, these pins can be used as general inputs/outputs. Otherwise, P0 is configured as address output (A0-A7) when the ALE pin is driven high (1) or as data output (Data Bus) when the ALE pin is driven low (0). Pin 40: VCC +5V power supply.

The following program will receive data from port 1, determine whether bit 2 is high, and then send the number FFH to port 3: READ: MOV A,P1 ANL A,#2H CJNE A,#02H,READ MOV P3,#FFH
Device pins XTAL1 and XTAL2 for the 8051 are used for connections to an external oscillator or crystal. When the 8051 is reset and the line is HIGH, the program counter points to the first program instruction in the internal code memory: An alternate function of port pin P3.4 in the 8051 is: Timer 0

The I/O ports that are used as address and data for external memory are: ports 0
and 2

Microcontrollers often have: A. B. C. CPUs RAM ROM

The 8051 has 4 parallel I/O ports.

The total external data memory that can be interfaced to the 8051 is 64K

8051 Address Modes? Immediate addressing is used when the operand is a constant value, and is part of the instruction, usually immediately following the op code in program memory. An example would be an instruction that loads a constant into the accumulator, as shown in Table

The instruction would be stored in an 8-bit processors memory as follows: Address Value(hex) 1000 74 op code 1001 35 operand Execution of this instruction would result in two memory cycles, one to fetch the op code and one to fetch the constant. Direct addressing includes the address of the operand as part of the instruction rather than the operand itself. The address part of the instruction acts as a pointer to the data to be accessed. An instruction that loads the byte of data stored in memory location 1234 into the accumulator would consist of the op code followed by the address 1234.

The instruction could be stored in an 8-bit processors memory as follows: Address Value(hex) 1000 E5 op code 1001 34 operand address

Execution of this instruction would result in three memory cycles, one to fetch the op code and one to fetch the address and one to fetch the byte at location 1234. When dealing with values of more than eight bits, different microprocessor vendors use different methods of storing data in memory. Of course, Intel and Motorola chose opposite methods. The 16-bit address stored high byte first followed by the low byte as it is done in the Motorola 68000 family. Other processors, such as the Intel CPUs, reverse the order. For machines that support two byte or four byte values, there are two different ways of storing the bit operands: low byte first (Intel), and high byte first (Motorola). Indirect addressing specifies a memory address that contains the address of the data to be transferred. An instruction that loads the byte of data that is pointed to by the address stored in memory location whose address (1234h) resides in the 16-bit register DPTR into the accumulator is shown below. The instruction could be stored in an 8-bit processors memory as follows, assuming that DPTR contains 1234h:

Code Address__Value(hex) 1000 E0 op code 1234 57 operand

External Memory Data address Value

After completion of this instruction, the value 57 would be left in the accumulator. Execution of this instruction would result in two memory cycles, one to fetch the op code (E0), one to fetch the contents (57) of the address (1234). The 8051 does not support true indirect addressing. In processors that do, the address of the operand is stored at the location contained in the instruction op code. Register indirect addressing (e.g. MOV A,@R1) uses the contents of a register as an address, so the instruction would consist of only an op code byte. A register points to the operand in memory, so there is no need for an address field in the instruction. Two memory cycles are needed, one for instruction fetch and one for fetching the data. Indexed addressing (e.g. MOVC A,@A+DPTR) is a combination of direct and register indirect addressing, because the instruction includes an offset address (DPTR), which is added to an index register (A register) to determine the address of the data to transfer. It should be noted that the nomenclature for the various address modes varies, and the 8051 family address modes used for the examples above are not necessarily the best examples, as other processors support more extensive and flexible address modes.

The 8051 Microcontroller Instruction Set? The following description of the instruction set is not a complete list, but serves to introduce the general character of the standard 8051 instructions. The instruction set utilized by the 8051 microcontroller consists of a total of 111 instructions, which may be divided up into several different categories. These are: 1. Arithmetic (24) 2. Logical (25) 3. Data transfer (28) 4. Bit (Boolean) variable manipulation (17) 5. Program branching and control (17) Each of these categories is comprised of instructions that utilize mnemonics as shown below: Arithmetic ADD, ADDC, SUBB, INC, DEC, MUL, DIV, DA Logical ANL, ORL, XRL, CLR, CPL, RL, RLC, RR, RRC, SWAP Data Transfer MOV, MOVX, MOVC, PUSH, POP, XCH, XCHD Bit (Boolean) Variable Manipulation CLR, SETB, CPL, ANL, ORL, MOV, JC, JNC, JB, JNB, JBC Program Branching and Control ACALL, LCALL, RET, RETI, AJMP, LJMP, SJMP, JMP, JZ, JNZ, CJNE, DJNZ, NOP Direct and Register Addressing While the number of mnemonics is clearly smaller in number than the total of 111 instructions, a given mnemonic may be used in several different ways to make up a valid 8051 instruction. These different ways of forming instructions are classified by the types of arguments that a given mnemonic takes. A mnemonic can refer to data in a number of ways. One can refer to data located in particular address in the data memory space either by specifying its address directly, or indirectly by using a data pointer register. In this case, the data pointer register contains the address of the memory location we seek. The 8051 looks in the data pointer register, and then retrieves the information located in the location referred to (or pointed to) by the data pointer. Additionally, the 8051 has 32 bytes of internal memory divided up into four register banks of eight bytes each. These register banks may be referred to in an 8051 instruction by either their direct address (which ranges between 00h and 1Fh), or by their register name, which is denoted by R0 through R7. When these memory locations are addressed by their register name, it is important to remember which register bank is currently in use. These register banks, numbered 0 through 3, are selected through two bits located in a special register called the program status

word (PSW). The PSW contains a number of very important bits, which are used to indicate the current status of the processor. Note that because the registers R0 through R7 are located in the data memory space, they may be addressed either by the register name or by their direct address location. Consider the instruction: MOV A,R3 This instruction takes the contents of register R3 and moves it (actually, the data is copied) to a register denoted by the letter A, called the accumulator. The accumulator is the working register of the 8051, and is the register that is used in most all arithmetic and logical operations performed by the processor. Assuming we are using register bank 0, the following instruction is identical to the instruction just shown: MOV A,03h Since register R3 is at internal RAM location 03h, the above instruction takes the data stored in RAM location 03h and moves it to the accumulator. What is the difference between these two forms of saying the same thing? The first instruction is called register addressing, while the second instruction is called direct addressing. The reason for the difference in nomenclature is obvious, and while it may seem a bit pointless to dwell on the difference between these two modes, there is a significant difference in the way the 8051 deals with each type of addressing. Looking in the 80C51-Based 8-Bit Microcontrollers Data Book (publication number IC-20) published by Philips, the instruction MOV A,R3 takes up only one byte of program memory space, while the instruction MOV A,03h requires two bytes of program memory space. The reason the register mode instruction requires less program memory to store is that a reference to a register requires three bits to represent its address, and a reference to an arbitrary location in internal data memory requires 8 bits. Once a particular register bank is selected by setting the proper bits in the PSW, any register in that bank may be completely determined by only 3 bits (3 bits are required to distinguish eight possible locations). If we use direct mode to perform the very same operation, we now require 7 bits to completely determine the exact location out of 128 possible locationsthus, direct addressing instructions generally occupy more program memory space than register addressing instructions. There are two other memory locations in the 8051 that may be addressed through register mode. These are the accumulator, which we have already seen is denoted by the letter A, and the data pointer, which is actually two registers. The letters DPTR denotes the data pointer, and is a 16-bit quantity used for addressing locations in data memory external to the microcontroller itself. Since the DPTR is a 16-bit quantity, a total of 64 kilobytes of data may be addressed. This is, of course, the maximum data that may be accessed at any one time by the 8051. The following instructions are examples of data movement instructions that utilize direct addressing: MOV 24h,A ;move accumulator contents to internal RAM location 24h MOV 7Ch,0Fh ;move location 0Fh contents to internal RAM location 7Ch

PUSH 22h ;PUSH location 22h contents onto the stack POP 4Eh ;POP the top of the stack into location 4Eh The following instructions are examples of data movement instructions, which utilize register addressing: MOV R0,49h ;move location 49h to register R0 MOV R2,A ;move accumulator contents to register R2 Note that in all instructions, the order of the memory locations in the instruction is always destination, source. The destination address appears first, followed by the source address. The instructions PUSH and POP perform operations on a portion of memory called the stack. While not a separate memory space, the stack is located in the internal data memory portion of the 8051/52, and is structured as a LIFO (last in, first out) data structure. The instruction: PUSH 49h takes the data stored in internal RAM location 49h and puts it onto the top (that is, the first available location) of the stack. Exactly where the top of the stack is situated is determined by the value contained in the stack pointer (SP) special function register. When the processor executes a PUSH instruction like the one above, it first increments the SP register by 1, and then copies the internal RAM register specified in the PUSH instruction to the address pointed to by the SP register. In other words, the value contained by the SP register is a pointer to the memory location one byte below the top of the stack. The POP instruction takes the data at the top of the stack and copies it to the internal RAM location specified in the POP instruction. After copying the data, the SP is decremented by 1. The SP register in the 8051/52 is therefore a pre-increment, post-decrement register. In the 8051, which contains 128 bytes of internal data RAM, the maximum legal value that the SP register may contain is 07Fh. The 8052 has an additional 128 bytes of internal RAM, separate from the special function registers. This section of RAM is accessible through the stack, and so the 8052 permits a maximum value of the SP register of 0FFh. The SP register can be set by the programmer to any value that is convenient for the particular application. When the processor comes out of RESET, the SP register is loaded with 07h, thus placing the top of the stack at internal RAM location 08h. This is just above register bank 0. The stack always grows upwards through internal RAM. Care must be taken that the stack does not collide with other registers in internal RAM that have other uses. Additionally, if the SP register reaches its maximum value, 0FFh, and then overflows, the stack will continue to grow through the Bank 0 registers. As no stack overflow or underflow features are present on the 8051, this becomes the responsibility of the programmer. Indirect Addressing In many applications, it is inconvenient or impossible to always refer to data directly or as a register. When large amounts of data are being manipulated, either in internal or external data memory, very often it is required to address such data through the use of a data pointer. Use of a data pointer to address data memory is known as indirect addressing. The 8051 has four different methods by which data may be addressed indirectly: 1. The indirect registers R0 and R1, located in each of the 4 register banks 2. The data pointer (DPTR) and the accumulator

3. The program counter and the accumulator 4. The XCHD instruction Indirect addressing of data is used frequently. Many embedded applications require calculation of one form or another, and frequently the most efficient means of doing this is through the use of a look-up table. As an example, an 8051 microcontroller such as the 80C552 has an eight channel, 10-bit analog to digital converter (ADC). The ADC takes an analog voltage as its input, and converts it to a 10-bit binary number between 000h and 3FFh. If this ADC is used, for example, to convert the analog output voltage of a pressure transducer to a digital value, it is necessary to relate each of the 1024 possible counts of the ADC to a pressure value. If the computer in use is very fast, or has a great deal of floating point mathematical ability, it would be possible to directly calculate the pressure value from the ADC countone would need the characteristics of the transducer to accomplish this. However, an 8-bit embedded controller such as the 8051 does not have such capability, or at least the ability to do complex mathematical calculations quickly. In this case, it is far more efficient to simply generate the 1024 numbers that correspond to the pressure output of the transducer and store these numbers in a table. The processor then takes the output of the ADC and uses this 10-bit number as an offset into the table stored in RAM. This offset, when added to the base address of the lookup table (the base address is the address of the first record in the table), constitutes the physical address of the data record that corresponds to the actual pressure sensed by the transducer. Since this lookup table could be located literally anywhere in either the code or data memory spaces, and since each record could be more than a single byte, it is in general not possible to store the actual location of each entry in the table. Rather, the ADC output is used to indirectly address the data through the use of a data pointer. Registers R0 and R1 in each of the four register banks may be used to indirectly access any of the internal data memory space of the 8051. To illustrate by example, consider the instruction: MOV A,@R1 Here, the @ symbol is used to denote indirection, similar to the asterisk * in C. This instruction takes the data located in the location pointed to by register R1 and copies it to the accumulator. Note that the value copied to the accumulator is not the contents of R1, but the value in the memory location equal to the contents of R1. This is why register R0 is said to be a data pointer, pointing to another internal RAM location. Notice that only data located in the internal data memory space of the 8051 may be accessed through @r0 or @R1 instructions. As these registers are only eight bits wide, a total of 256 bytes may be specified. The 8051 microcontroller contains a total of 128 bytes of internal RAM located between addresses 00h and 7Fh, while the 8052 contains an additional 128 bytes of internal RAM between 80h and 0FFh. These upper 128 bytes of internal RAM can only be accessed by indirect addressing. It is important to distinguish these upper 128 bytes of internal RAM in the 8052 microcontroller from the special function registers. The SFRs are not part of the upper 128 bytes of internal RAMthey are a separate memory space. Very often, an embedded system will require a much larger amount of RAM than is present on an 8051 or 8052 microcontroller. When this is the case, one generally uses external RAM chips that are interfaced to the processor

over the address, data, and control bus structure. Since the address bus of the 8051/52 microcontroller family is 16 bits wide, a total of 64 kilobytes of either program memory or data memory may be accessed. Restricting our attention to the data memory space and RAM for the moment, we need some way of accessing the (at most) 64 kilobytes of RAM external to the microcontroller. The MOVX instruction (X denotes external) is used to move data into and out of RAM located external to the microcontroller. The only way the 8051/52 microcontroller can access external RAM is through indirect addressing. The MOVX instruction can be used in two different ways. If the external RAM space is small (small meaning 256 bytes or less in this case), it may be accessed with an 8-bit address. The R0 and R1 registers may be used in this manner just as they are used for indirect addressing of internal RAM. Consider the instruction: MOVX @R0,A This instruction takes the byte in the accumulator and copies it to the location at the address in external RAM pointed to by R0. The instruction MOVX @R1,A performs the opposite operation. It takes the value held in the external RAM location pointed to by R1 and copies it to the accumulator. There is an important difference between this type of external data addressing and internal data addressingwhenever data is being read from or written to external RAM, either the source or the destination register must be the accumulator. What if our external RAM array contains more than 256 bytes? Recall that the 8051/52 family of microcontrollers have a 16-bit address bus, permitting up to 64 kilobytes of external program and/or data memory. The data pointer (DPTR) is used to store a 16-bit address for indirect addressing of external RAM. DPTR is loaded with the address of interest, and the instruction MOVX A,@DPTR copies the data at the external RAM location pointed to by the 16-bit address pointer, called DPTR into the accumulator. The instruction MOVX @DPTR,A performs the opposite operation. The contents of the accumulator A is copied to external RAM at the location pointed to by DPTR. Again it is important to notice that either the source or the destination register in the instruction must be the accumulator. Sometimes it is necessary to store information other than actual program instructions in a nonvolatile memory. Critical configuration data, lookup tables, or serial number information for unit identification oftentimes must be stored and available at system power-up without having to be regenerated by the system itself. While there are external nonvolatile memory technologies available (EEPROM and flash, for example), it is possible to use the program memory space of the 8051/52 for this same purpose. While it is not possible to write to the program memory space during normal operation (that could have potentially disastrous results!), it is possible to read data from it. The MOVC instruction (C denotes Code) copies a byte in the program memory space to the accumulator. In order to accomplish this, the instruction requires the use of a base address and an offset. It is best to illustrate this with some examples. The two allowable forms of the MOVC instruction are:

MOVC A,@A+DPTR MOVC A,@A+PC In each of these instructions, the contents of the accumulator and either the DPTR or the PC (the program counter register) are added together, generating a 16-bit address. The contents of the address in the program memory space pointed to by this 16-bit sum is copied to the accumulator. In this way, either the PC or the DPTR can be used as a base address into a data table in the program memory space. The accumulator then becomes an offset into the data table, with a maximum offset value of 256. The last method of indirect addressing available in the 8051 is the XCHD (exchange digit) instruction. The XCHD instruction is frequently used when BCD (binary coded decimal) arithmetic is being performed, or when a BCD lookup table is stored in internal RAM (a common use of a BCD lookup table would be for driving a 7-segment LED display). The XCHD instruction has the following syntax: XCHD A,@R0 XCHD A,@R1 This instruction exchanges the low nibble (that is, the low 4 bits) of the accumulator with the low nibble of the internal RAM location pointed to by either the R0 or R1 register. Recalling that BCD uses 4 bits to represent the decimal numbers 0 through 9, this instruction offers a quick way to indirectly address a BCD (or any other 4-bit coding scheme) lookup table in internal RAM. To illustrate this with an example: suppose the accumulator contains A6h, register R1 contains 43h, and internal RAM location 43h contains 0BBh. The instruction: XCHD A,@R1 Will result in the accumulator containing 0ABh, and internal RAM location 43h containing 0B6h. Immediate Addressing Sometimes it is necessary to place a fixed constant into a memory location. This may be performed through the use of the immediate operator #. As an example, MOV A,#09h places the number 09h into the accumulator. Likewise, MOV 52h,#3Ah places the constant 3Ah into internal RAM location 52h. The immediate operator indicates that the number that follows is to be interpreted as an immediate constant, rather than a memory location. Notice that, had we issued the instruction MOV 52h,3Ah this would have copied the contents of internal RAM location 3Ah to internal RAM location 52h. Since this is a perfectly valid 8051 instruction, the assembler will not flag this as an error if we had actually meant to prefix the 3Ah with the immediate operator. The code will not function as we might expect it to operate. Watch out for this it is a VERY common error! Immediate data, by its very nature, must only occur as the source operand of an 8051 instruction. The instruction MOV #52h,44h makes no sense, and will be flagged as an error by the assembler. On the other

hand, below is a valid instruction that will put the number 44h into internal data RAM location 52h: MOV 52h,#44h 8051 Memory Organization? In order to grasp the processor, its necessary to ascertain however the varied memory areas area unit organized. The memory organization of the 8051 family of processors could appear complicated at first; but, it as not as random because it might seem. There area unit separate reminiscences for program storage, internal memory and registers, internal I/O functions, and external knowledge memory. The program and external knowledge reminiscences area unit comparatively straightforward. They every delay to sixty four kilobytes of directions and knowledge severally. Program directions area unit always fetched from program memory, and area unit indicated by the central processing unit activating the /PSEN pin. External knowledge is transferred once the central processing unit executes a MOVX (MOV eXternal memory) instruction, and therefore the central processing unit indicates this by activating the /RD or /WR line. The 8051 family chips solely have 3 forms of external memory cycles: Program scan once /PSEN goes low External knowledge scan once /RD goes low External knowledge write when/WR goes low This makes interfacing different bus-oriented devices to the processor comparatively straightforward. (Some general purpose or laptop CPUs have many various forms of bus cycles.) The internal knowledge address area of the 8051 family isnt quite as straightforward because the external reminiscences. It includes four banks of eight registers, memory which will be accessed one computer memory unit or one bit at a time, a stack, and therefore the special operate registers (SFRs) that hold info} and management information for the interface, timers, and different I/O. This internal memory address area are often accessed in many different ways in which. the inner knowledge area of the central processing unit are often rather confusing at first, however its one amongst the characteristics of the 8051 family, that permits thus much to be finished such restricted resources. The 8051 central processing unit manipulates operands in 3 memory address spaces: sixty four K program memory (external program memory on the 8031) which is enabled once the processor is winning AN instruction to be executed and signaled by activating the CPUs /PSEN management line. The MOVC instruction conjointly activates /PSEN to alter reading the code memory into the accumulator for accessing search tables and different unchanging knowledge keep within the program memory area. sixty four K external knowledge memory that is enabled once the processor reads or writes knowledge from the external knowledge memory and signaled by

activating the /RD and /WR management lines. this happens only if a MOVX instruction is employed to scan or write from external memory. Internal knowledge RAM (128 bytes for the 31, 256 bytes for the 32) and special operate registers (SFR). Four register banks (each bank has eight registers), 128 separately available memory bits, and therefore the stack all reside within the internal knowledge RAM. The stack depth is proscribed solely by the available internal knowledge RAM. Its location is set by the 8-bit stack pointer. The 128 computer memory unit special operate register address areas area unit shown in Figure.

The lower 128 computer memory unit 1/2 the 256 computer memory unit internal knowledge memory address area contains four blocks of eight central processing unit registers, R0-7. within the 8032 central processing unit, the upper 128 bytes of the inner knowledge memory address area area unit shared between knowledge memory and therefore the SFRs, relying upon the address mode. The higher 128 bytes of knowledge memory should be accessed victimization the indirect register 0/1 (@R0 or @R1 operands) or stack accesses, and every one different references to addresses of 128 or higher can access the SFRs. All registers except the program counter and the four 8-register banks reside within the special operate register address area. These memory mapped registers embody arithmetic registers, pointers, I/O ports, and registers for the interrupt system, timers and serial channel. There are 128 bit locations within the SFR address area that area unit available as bits. The 8031 contains 128 bytes of internal knowledge RAM and twenty special operate registers (SFRs), whereas most different processor family variants embody an extra 128 bytes of internal knowledge memory overlapped with the SFR addresses. What is the role of segment register? In the x86 processor architecture, memory addresses are specified in two parts called the segment and the offset. One usually thinks of the segment as

specifying the beginning of a block of memory allocated by the system and the offset as an index into it. Segment values are stored in the segment registers. There are four or more segment registers,CS contains the segment of the current instruction (IP is the offset), SS contains the stack segment (SP is the offset), DS is the segment used by default for most data operations, ES is an extra segment register. Most memory operations accept a segment override prefix that allows use of a segment register other than the default one. Basically registers are used to store data and address for specifying the base address that is starting block of memory ,segment registers are used . it gives only the starting address of any segment and one thing is important in the case of 8086 architecture is that ,for producing physical address ,the segment register address must be rotate bit-wise 4 times left and 0000 must be embedded now offset address is added in the modify content of segment register to get the required memory location. The segment register in the 80806/8088 microprocessorcontains the base address of a region of memory. Since the register is 16 bits in size, there are 65,536 possible segment base addresses, ranging from 00000H to FFFF0H, in increments of 00010H.After address translation at the instruction level, the generated 16 bit offset is added to the selected segment register times 16 to generate a physical address between 00000H and FFFFFH.Since the offset is also16 bits in size and since the overlap is only 4 bits,then each 64 kb segment overlaps by 16 bytes. There are four segment registers; CS, DS, ES, and SS, standing for Code Segment, Data Segment, Extra Segment, and Stack Segment.CS is used for opcode fetches. DS is used for normal data. ES is used for certain string operations as the destination address. SS is used for stack and frame (BP) data. The segment registers can be implicitly selected by context, or they can be explicitly selected with a segment prefix opcode Which of the following instructions will load the value 35H into the high byte of timer 0? MOV TH0, #35H Bit-addressable memory locations are: 20H through 2FH The contents MOV ANL will be 00001000 of the accumulator after this operation A,#0BH A,#2CH

This program code will read data from port 0 and write it to port 2, and it will stop looping when bit 3 of port 2 is set: 32 STAT MOV A, PO : MOV P2,A JNB P2.3,

STAT The When the 8051 is reset and the EA line is LOW, the program counter points to the first program instruction in the: number of data registers is: external code memory 8051 CPU Hardware? The 8051 is assessed as associate degree 8-bit machine, since the inner computer memory, RAM, special perform registers, arithmetic logic unit and external knowledge bus are every eight bits wide. The 8031 is a dead ringer for the 8051, except that it doesnt have any internal program computer memory. The 8051 performs operations on bit, nibble, byte and double-byte knowledge varieties. It excels at bit handling since knowledge transfer, logic and conditional branch operations is performed directly on the bit available SFRs. This section describes the hardware design of the 805l central processor. A detailed 8051 useful diagram is displayed in Figure

Control Unit Each program instruction is decoded by the management unit, that is additionally known as the instruction decoder. This unit generates the inner signals that management the functions of all the opposite units inside the central processor section. All directions ar fetched from the program memory solely. directions is fetched from either the inner program memory (for those devices that possess one) or from external program memory. Instruction fetch operations ar indicated when the central processor activates (lowers) the /PSEN line (NOT program scientific instrument enable). A program memory fetch cycle lasts as long as /PSEN stays low. External

program memory should solely drive the info bus with the self-addressed instruction while /PSEN is low. Program Counter This is the pointer to subsequent instruction to be dead. The 16-bit program counter (PC) controls the sequence within which the directions hold on in program memory ar dead. Instruction Register This is the register that contains the instruction thats presently being dead. Internal Program Memory The 8051 family has sixteen address lines, and may directly address 216 = sixty four kilobytes of program memory. the first 8051 has four kilobytes of program memory resident on-chip, the 8031 has no on-chip program memory, and therefore the 8052 has 8 kilobytes of program memory. alternative variants of the family ar obtainable with 1 to sixty four kilobytes of varied forms of non-volatile program memory inbuilt. The sixty four KB program memory address house consists of a mix of internal and external program memory (external program memory only on the 8031 and 8032). once external program memory is accessed, and the processor is taking associate degree instruction to be dead, the external program read cycle is signaled by activating the CPUs /PSEN management line. The MOVC instruction additionally activates /PSEN to modify reading the code memory into the accumulator for accessing search tables and alternative unchanging knowledge hold on within the program memory house. Figure shows a program memory map.

The processor will fetch directions from internal or external program memory. theres an impact input pin, /EA (external access), that forces all directions to be

fetched from the external program memory once the pin is force low. If the /EA pin is force high, then the processor can fetch directions from any obtainable internal program memory. once the processor initial powers up and receives a reset signal, it begins by capital punishment the instruction at location 0000 in program memory. once the processor fetches directions from external program memory, it puts the instruction address out on the address bus, pulses the PSEN (program scientific instrument modify) pin low to enable the external program memory to put the instruction on the info bus to the processor. The generic half list theme is as follows: 8xxx: NMOS logic 8xCxx: CMOS logic 803x: No internal program memory 805x: manufactory programmed internal computer memory program memory 87xx: Internal user programmable ROM program memory 89xx: Internal flash ROM program memory 8xx1: four KB internal program memory, 128 computer memory unit internal RAM eightxx2: 8 KB internal program memory, 256 computer memory unit internal RAM For example, the 80C32 used because the normal processor within the SDK board could be a CMOS give no internal program computer memory, and 256 bytes of internal knowledge RAM. Internal Data Memory Figure shows the info memory areas within the 8051. the inner knowledge RAM provides a convenient 128 computer memory unit scratch pad memory that has the register banks, SFRs, and general knowledge storage. The software engineer (or compiler) may also use this scratch pad memory for storing intermediate calculations on a short lived basis. The 8031 contains a 128 computer memory unit internal knowledge RAM (addresses 0-7Fh, which incorporates registers R0-R7 in every of 4 banks), in addition to the memory-mapped special perform register (locations 80-FFh). The 8032 has a further 128 bytes of internal knowledge RAM additionally at locations 80-FFh, which may solely be accessed by exploitation indirect register addressing (@R0, @R1) and therefore the stack. The lower 128 computer memory unit half the 256 computer memory unit internal data memory address house contains four blocks of eight central processor registers, R0-7.

In the 802 central processor, the higher 128 bytes of the inner knowledge memory address space ar shared between knowledge memory and therefore the SFRs, relying upon the address mode. The higher 128 bytes of knowledge memory should be accessed exploitation the indirect register 0/1 (@R0 or @R1 operands) or stack accesses, and all other references to addresses of 128 or higher can access the SFRs. All registers, except the program counter and therefore the four 8-register banks, reside within the special perform register address house. These memory mapped registers embody arithmetic registers, pointers, I/O ports, and registers for the interrupt system, timers and serial channel. There ar 128 bit locations within the SFR address house that ar available as bits. The 8031 contains 128 bytes of internal knowledge RAM and twenty special perform registers (SFRs), whereas most alternative processor family variants embody a further 128 bytes of internal knowledge memory overlapped with the SFR addresses. DataMemory The 8051 family devices have 2 knowledge recollections, internal and external. With 16 address bits, theres a most of sixty four kilobytes of external knowledge memory, which is helpful for storing massive blocks of variable info that may not fit in the inner knowledge RAM. its enabled once the processor reads or writes data from the external data memory, signaled by activating the /RD and /WR control lines. this happens only a MOVX instruction is employed to browse or write from external memory.

The internal data address house has 2 totally different elements, as shown in Figure . One half contains the general registers and general knowledge storage RAM, and therefore the alternative half contains all the special registers and I/O devices, like the parallel and serial ports, and timers. These registers ar known as special perform registers. theres a most of 256 bytes of internal RAM (128 bytes for the 31/51, 256 bytes for the 32/52) and special perform registers (SFR). Four register banks (each bank has eight registers), 128 singly available memory bits, and therefore the stack all reside within the internal knowledge RAM. The stack depth is restricted solely by the obtainable internal knowledge RAM. The 8-bit stack pointer determines the stacks location. the inner knowledge RAM provides a convenient 128 computer memory unit scratch pad memory which includes the register banks, SFRs, and general purpose knowledge storage. RAM locations 00-7F hex Register banks: There ar four register banks inside the inner knowledge RAM. every register bank contains registers R7-R0. 128 available RAM bits: within the 8031, there ar 128 available software package flags within the internal knowledge RAM. theyre situated within the sixteen computer memory unit locations starting at computer memory unit address 20h and ending with computer memory unit location 2Fh of the RAM

address house. Special perform Register (SFR) locations 80-FF hex General registers A, B, and alternative registers ar mapped here. Parallel I/O ports: The 8031 has four 8-bit ports. Serial I/O port: The serial I/O port designed into the 8031. Timer/counters: There ar counters that may count external events or count processor clock cycles to work as timers. several of the SFRs ar also bit available. Bit available Memory Figure shows the organization of bit available space within the internal data memory. The bit address space encompasses a total of 256 attainable bit addresses. The first 128 bits, 00 to 7F hex, ar wont to access individual bits of the inner memory from location twenty to 2F hex. The second 128 bits, from eighty to FF hex, enable elite bits within the special perform registers to be accessed at the bit level. Not all SFRs ar bit available, and not all bit addresses ar utilized in most processors.

Bit available memory permits the manipulation and take a look at of individual bits, which could be a quite common operation in embedded systems. nearly each application requires that some output bits be wont to management associate degree on/off device, such as associate degree indicator or relay. Likewise input bits ar wont to sense the standing of some external device, like a switch or detector. The bit available address space permits the software engineer to work on info at the bit level even as easily as at the computer memory unit level. this is often contrasted by most alternative processors, in which the software engineer should write multiple directions to pick out the suitable bit in a computer memory unit before process or testing it. Internal memory locations from twenty to 2F hex, ar accessible either one computer memory unit at a time, or one bit at a time. that creates it simple to convert inherently serial

information to parallel and contrariwise, and to perform mathematical logic functions. This bit-level process is one among the foremost distinctive and powerful options of the 8051 family design, and is one among the options that differentiate it from alternative microcontrollers. Register Banks The four register banks inside the inner knowledge RAM every contain eight registers named R0-R7. 128 available Bits There ar 128 available software package flags within the internal knowledge RAM. They are located within the sixteen computer memory unit locations beginning at computer memory unit address 20h and ending with byte location 2Fh of the RAM address house. I/O Ports There ar four 8-bit ports. once exploitation external program or knowledge memory, only Port one (P1) is obtainable for general purpose I/O. External memory uses Port zero (P0) for the multiplexed knowledge bus and address bits 0-7, and Port a pair of (P2) for address bits 8-15, whereas Port three (P3) contains special management signals, such as the browse and write scientific instrument pins. additionally to the essential parallel I/O bits on the four ports, a number of the port bits have alternate functions. The alternate functions embody the serial I/O port signals, timer and interrupt inputs. Timer/Counter The 8031 has 2 timer/counters and therefore the 8032 has 3. Serial I/O The serial I/O port thats designed into the 8031 is wont to transmit and receive asynchronous (un-clocked) serial knowledge, as is employed on a PCs port. It also can be used for synchronous (clocked) serial knowledge transfers. Reset electronic equipment The reset input pin ought to be connected to associate degree external electrical device and capacitance, so that the processor are going to be properly initialized upon initial application of power. theres a capacitance between the reset pin and therefore the power offer, and a electrical device from the reset pin to ground. once power is initial applied, the capacitance has no voltage across it, forcing the processor to reset. when electrical device R1 charges the capacitance C, the reset signal goes low (inactive), and therefore the processor begins capital punishment the program starting at location zero in program memory. The suggested reset circuit is shown in Figure.

When power is initial applied, capacitance C has zero voltage across it, and reset is

held high till this that flows through R1 charges C. Once the capacitance is charged, the reset pin is at zero volts and inactive. The diode permits the capacitor to discharge once Vcc goes to zero, even for a brief amount. If there was no diode, and there was a short power loss, the central processor state would be indeterminate, and wouldnt be reset. Optionally, the processor is reset by closing switch point through a series electrical device R2, that limits this through the switch. this flowing through the switch discharges the capacitance. If resistor R2 wasnt gift, terribly high currents may flow through the switch. These high currents that flow terribly shortly whereas the capacitance is shorted and can cause the switch contacts to fail or perhaps weld the contacts along. The R1*C time constant should be long enough to ensure that the processor will be fully reset to a illustrious state upon power up. The delay should enable the generator to start out up and stabilize, likewise because the time it takes the processor to reset when the generator is stable. {different|totally totally different| completely different} processors need different numbers of clock cycles to reset themselves, and therefore the generator startup time can vary wide betting on the frequency reference, voltage, electrical phenomenon hundreds, and alternative factors. If the processor reset isnt long enough, the processor could behave in unpredictable ways that, and it should not be apparent that the matter is due to associate degree incomplete reset operation. In most cases, its higher to possess a comparatively long reset time constant, on the order of many milliseconds, to be sure that the processor has been fully reset. External peripherals also can exhibit this drawback. throughout the initial development of the SDK, we have a tendency to knowledgeable about occasional issues with the external port chip used on the board. The problem clad to be associated with the length of the reset pulse and therefore the amount of time when the reset once the chip should be left alone to drag itself together! This sort of drawback is terribly tough to trace down, since its tough if not not possible to see once a chip has not been fully reset. The 8051 is exclusive therein its reset signal is active high. alternative processors use active low reset signals, that the reset circuit should be adjusted to perform the equivalent perform with the reset pulse going low at power up and once the capacitor is charged, the reset goes high. The circuit configuration except R and C1 ar swapped, as ar D1 and therefore the SW/R2 combine. The circuit in Figure is good enough for many applications. However, it is not foolproof. Even with the on top of precautions, its attainable that the processor state is topsy-turvy by power transients that ar too short to cause a reset. When a processor is employed in an exceedingly important or long run unattended application, that most likely wont be ok to satisfy the necessity for reliable operation.

To trot out this, processor superordinate chips ar obtainable to watch the power offer voltage for out of tolerance fluctuations and mechanically reset the processor once the ability offer falls out of tolerance. a number of these supervisory chips even have a special watchdog timer circuit that expects to be fed by a pulse that resets the watchdog counter sporadically by a properly functioning program running on the processor. If the watchdog timer isnt fed with a pulse sporadically, the counter can overflow and itll bark by pulling the reset pin active. That method if the processor burst within the weeds, due to a hardware bug or a program bug, the central processor are going to be reset. This is a simple methodology of getting tolerance to fault conditions, however it additionally needs careful style to avoid unsought reset conditions. its additionally the designers responsibility to assure that the processor cant grind to a halt in an exceedingly loop whereas feeding the watchdog timer. When coming up with a microcontroller that has to operate in high noise environments, or wherever correct operation is safety important, special care should be taken to ensure that magnetism noise doesnt cause issues. This noise will come from alternative elements of the system and environmental conditions like electromagnetic fields from alternative devices like wireless communication devices. With the fast increase within the variety of electronic and wireless devices, this drawback is changing into additional and additional serious. the sphere of magnetism compatibility (EMC) covers this noise, likewise as others like electricity discharge (ESD). an honest outline of EMC ideas as they relate to microcontrollers can be found within the Intel application note AP-125, Designing Microcontroller Systems for Electrically abuzz Environments. Oscillator and Timing Circuitry Timing generation is totally self-contained on the 8051, apart from the frequency reference (which is a crystal or external clock source). The on-board generator could be a parallel anti-resonant circuit with a frequency vary of 1.2 rate to twelve rate for the first 8051. theres a divide-by-12 internal clock counter that offers the quality 8051 associate degree instruction cycle of one S with a twelve rate crystal. Higher speed versions of the processor are obtainable, which use fewer than twelve clocks per instruction cycle. The Dallas 80C320 uses solely four clock cycles for many instruction cycles, therefore its thrice faster than the first central processor exploitation identical clock frequency. The XTAL2 pin is that the output of a high-gain electronic equipment whereas XTAL1 is its input. A crystal connected between XTAL1 and XTAL2 provides the feedback and part shift needed for oscillation. For stability and consistent generator start-up, 2 capacitors within the vary of ten to twenty pico farads ought to be connected from the XTAL pins to ground. If XTAL1 is being driven by associate degree external frequency supply, XTAL2 mustnt be connected. associate degree

external clock also can be applied to XTAL1 to permit the employment of a separate clock frequency supply, like associate degree generator module. Figure. shows a typical generator configuration. The generator circuit consists of a crystal connected between the XTAL1 and XTAL a pair of pins of the processor, beside 2 capacitors, one from every XTAL pin to ground to enhance stability and start-up characteristics of the generator. The internal electronic equipment and quartz kind a series resonant generator that operates at the at the crystals resonance frequency. The electronic equipment within the original 8051 was associate degree inverting electronic equipment, however alternative variants and alternative processor families make use of non-inverting amplifiers in some cases. All of the processors timing comes from this generator. For the quality 8051 compatible elements, every instruction cycle needs a multiple of twelve clock cycles. For the Dallas high-speed central processor versions, four clock cycles ar used for many instruction cycles. In most 8051 styles, the capacitors connected to the crystal ought to be in the 10 to fifty picofarads vary, with thirty picofarads being a typical price. The crystal ought to be associate degree AT cut series resonant device. The AT designation refers to the method the quartz is cut from the blank with associate degree orientation relative to the lattice that reduces the crystals frequency dependence on temperature changes. The crystal is factory-made so its series resonant at the desired frequency. A given crystal can resonate in an exceedingly series or parallel mode. A parallel resonant crystal can still operate within the circuit, however itll operate at a rather totally different frequency. Actual operational frequency depends on the load capacitance, and is subject to temperature, and can drift over time. Selection of the capacitors could be a trade-off between generator start-up time and stability. Specification of a crystal depends upon the precise style necessities and the processor getting used. Even elements with identical variety could have totally different necessities, particularly for elements from totally different makers. Theres way more info obtainable from the crystal and processor manufacturers on the right style and operation of crystal oscillators. Other frequency references, like ceramic resonators and even straightforward RC circuits is used for several processors. Some microcontrollers even embody on-chip oscillators that may be mark to work at a particular frequency, albeit with less accuracy and larger drift. Application note AP-155, Oscillators for Microcontrollers from Intel Corporation, could be a terribly helpful reference and describes the characteristics of each the crystal and ceramic resonators operation likewise because the processors generator electronic equipment.

The I/O port that does not have a dual-purpose role is: port 1 To interface external EPROM memory for applications, it is necessary to demultiplex the address/data lines of the 8051. The special function registers can be referred to by their hex addresses or by their register names. The statement LCALL READ passes control to the line labelled READ. The microcontroller is useful in systems that have nonvariable programs for dedicated applications. The ADC0804 has ________ resolution : 8-bit A HIGH on which pin resets the 8051 microcontroller? RST An alternate function of port pin P3.1 in the 8051 is: serial port output

The following command will rotate the 8 bits of the accumulator one position to the left: RL A An alternate function of port pin P3.0 (RXD) in the 8051 is: serial port input