ARCHITCTURE of 8051 micro controller

HARDWARE SUMMRAY
In this lecture the hardware architecture of MCS-51 family is introduced.The 8051, the first device in the family offered commercially. Its features are summarized below. 4K bytes ROM 128 bytes RAM Four 8-bit I/O(input/output) ports Two 16-bit timers Serial interface 64K external code memory space 64K external data memory space 210 bit-addressable location 4 microseconds multiply/divide

Comparison of MCS 51 Ics

Other members of the MCS-51 family offer different combinations of onchip ROM or EPROM, on-chip RAM, or a third timer.

PART NUMBER
8051 8031 8751 8052 8032 8752 89c51

ON-CHIP CODE MEMORY

4K ROM 0K 4K EPROM 8K ROM 0K 8K EPROM

ON-CHIP DATA TIMERS MEMORY

128 BYTES 128 BYTES 128 BYTES 256 BYTES 256 BYTES 256 BYTES 2 2 2 3 3 3 2

4K EEPROM Anil Rose 128 BYTES

INT1* INT0* Timer2(8032/8052) Timer1 Timer0 Serial port

* Alternate pin assignments for P1 & P3

Interrupt control

Other resisters

128 bytes RAM (8032/8052) 128 bytes RAM

EEPROM ROM 0K 8031/8032 4K 8051 8K 8052

T2EX*

Timer 2

T2*

(8032/8052)
Timer 1 Timer 0 T1* T0*

CPU

oscillator

Bus control

I/O port

Serial port

EA RST

ALE

P0 P2 P1 P3 Anil Rose PSEN (Address/data)

TXD*

RXD*

SEMICONDUCTOR MEMORY: RAM AND ROM

Programs and data are stored in memory. The variation of computer memory are so vast,their accompanying terms so plentiful, and technology breakthroughs so frequent, that extensive and continual study is required to keep abreast of the latest developments.the memory devices directly accessible by the CPU consist of semiconductor ICs (integrated circuits) called RAM and ROM.there are two features that distinguish RAM and ROM: first, RAM is read/write memory while ROM is read-only memory, and second , RAM is volatile (the contents are lost when power is removed), while ROM is non-volatile.

ACCUMULATOR (ACC): The accumulator resister (ACC or A) acts as an

operand resisters, in case of some instructions. This may either be implicit or specified in the instruction. The ACC resister has been allotted an address in the on-chip special function resister bank.

B REGISTER: This resister is used to store one of the operands for multiply
and divide instructions. In other instructions, it may just be used as a scratch pad. This register is considered as a special function registers.

PROGRAM STATUS WORD (PSW): This set of flags contains the

status information and is considered as one of the special function resisters.

STACK POINTER (SP): This 8-bit wide resister is incremented before the
data is stored onto the stack using push or call instructions. This contains 8-bit stack top address. The stack may be defined anywhere in the on-chip 128-byte RAM.

DATA POINTER (DPTR): This 16-bit resister contains a higher

byte (DPH) and the lower byte (DPL) of a 16-bit external data RAM address. It is accessed as a 16-bit resister or two 8-bit resisters as specified above. It has been allotted two addresses in the special function resister bank, for its two bytes DPH and DPL.

PORT 0 TO 3 LATCHES AND DRIVERS : These four

latches and driver pairs are allotted to each of the four on-chip I/O ports. These latches have been allotted addresses in the special function resister bank.Using the allotted addresses, the user can communicate with these ports. These are identified as P0, P1, P2 , and P3.

SERIAL DATA BUFFER: The serial data buffer internally

contains two independent resisters. One of them is a transmit buffer which is necessarily a parallel-in serial-out resister. The other is called receive buffer which is a serial-in parallel-out resister. Loading a byte to the transmit buffer initiates serial transmission of that byte. The serial data buffer is defined as SBUF and is one of the special function resisters. If a byte is written to SBUF, it initiates serial transmission and if the SBUF is read , it reads received serial data. Anil Rose

TIMER REGISTERS: these two 16-bit registers can be accessed as

their lower and upper bytes. For example , TL0 represents the lower byte of the timing resister 0. Similarly , TL1and TH1 represents the lower and higher bytes of timing resister 1.

CONTRO; REGISTERS: the special function registers IP , IE ,

TCON , SCON and PCON contains control and status information for interrupts , timers/counters and serial port. All of these resisters have been allotted addresses in the special function resister bank of 8051.

TIMING AND CONTROL UNIT: This unit drives all the

necessary timing and control signals required for the internal operation of the circuit. It also drives control signals required for controlling the external system bus.

OSCILLATOR: this circuit generates the basic timing clock signal

for the operation of the circuit using crystal oscillator.
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INSTRUCTION REGISTER: this register decodes the opcode of

an instruction to be executed and gives information to the timing and control unit to generate necessary signals for the execution of the instruction.

EPROM AND PROGRAM ADDRESS REGISTER: these

blocks provide an on-chip EPROM and a mechanism to internally address it. Note that EPROM is not available in all 8051 versions.

ALU: the arithmetic and logic unit performs 8-bit arithmetic and logical
operations over the operands held by the temporary resisters TMP1 and TMP2. Users cannot access these temporary resisters.

SFR: this is a set of special function registers , which can be addressed

using their respective addresses which lie in the range 80H to FFH. Finally , the interrupt , serial port and timer units control and perform their specific functions under the control of the timing and control unit.
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Pin Description
Port 0 :- it is dual purpose port on pin 32 39, it is used as general purpose I/O port, for larger design with external memory it become multiplexed address and data bus Port 1(1-8):- it is dedicated to interfacing to external devices as required. No alternate function is assigned for port 1. exception are for 8032/8052 P1.0 & P1.1 as a external i/p to third timer Port2 (21-28):- it is dual purpose port serving as general purpose I/O, or as the high byte of the address bus for designs with external code memory or more than 256 bytes of external data memory. Port 3(10-17):- it is also dual purpose port general purpose I/O and these pins are multifunctional with each having an alternate purpose related to special feature of 8051. Cont

Cont.
Bit P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P1.0 P1.1 Name Rxd Txd Int0 Int1 T0 T1 WR RD T2 T2ex Bit address 80H B1H B2H B3H B4H B5H B6H B7H 90H 91H Alternate name receive data for serial port transmitt data for serial port External Interrupt 0 External Interrupt 1 Timer/counter 0 external i/o Timer/counter 1external i/o external data memory with strobe external data memory with strobe Timer/counter 2external i/o Timer/counter 2capture/ reload

Program store enable (PSEN)

It is an output signal on pin 29, it is control signal that enable external memory, it is usually connect to an EPROM output enable

IR 8051

EPROM

Opcode read from EPROM

ALE (Address Latch Enable)

It is on 30 pin used for demultiplexing the address bus and data bus. When port 0 is used in its alternate mode as the data bus and the low bytes of address bus ALE is the signal that latches the address into the external register during first half of a memory cycle and then port 0 is available for the data i/p & o/p during second half.

ALE
ADD

DATA

The ALE signal pulses at a rate of 1/6 the on chip oscillator frequency and can be used as a general purpose clock for the rest of the system. If 8051 is clocked from 12mhz then ALE oscillate 2mhz.only exception is that during movx when one ALE pulse is missed this pin is also used for programming i/p pulse for EPROM of the 8051

EA(EXTERNAL ACCESS)
It is I/P signal on pin 31 is generally tied high or low. If high the 8051/8052 execute program from internal ROM and if low programme execute from external ROM (PSEN will be low). EA must be low for 8031/8032 since there is no on chip memory.if EA is low disable te internal ROM and programme execute from EPROM. The EPROM version of 8051 also use EA line for +21 volt supply for programming the internal EPROM.

EA ROM

EPROM

RST (Reset)
I/P on pin 9 is the master reset for 8051.when the signal is brought high at least for two machine cycles.8051 internal registers are loaded with appropriate value for an orderly system start-up.

ON-CHIP OSCILLATOR :- 8051 features an on

chip oscillator that is typically driven by a crystal connected on pin 18 & 19. stabilizing capacitor are also required. The nominal crystal frequency is 12mhz for most ICs although 8031 requires 16mhz. The chip oscillator need not be driven by crystal a TTL clock source can be connected to XTAL1 and XTAL2.

I/O Port Structure

read latch 8051 internal bus vcc
Internal Pull up register

Read pin

D Port Q latch
Write to latch

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Cont.
Writing pin to load the data in the port latch which drive the FET. Drive capability 4 low schottky TTL loads for port 1,2 & 3. 8 LS load for port 0. An external pull up register may require depend upon the I/p characteristic of the device driven. There is both read latch & read pin capability. Instruction that requires a read modify write operation read the latch to avoid misinterpreting the voltage level in the event the pin is heavily loaded. Port latch must contain 1, otherwise the FET is on and pulls the o/p low.
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Memory organization

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Memory Space

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Internal RAM organization

Summary of the 8051 onchip data memory (RAM)

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Summary of the 8051 onchip data memory (Special Function Registers)

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BASICS
Microprocessor shared memory space for data and programs. Microcontroller rarely used as CPU , instead they are used as control oriented design .there is limited memory and there is no disk or disk operating system. The programs must reside in ROM..
Microcontroller implement separate memory space for code ( Program) and data Internal memory consist on chip RAM & ROM. Two main feature a) the registers and I/O ports are memory mapped and accessible like any other memory location. b) the stack reside with in the internal RAM, rather than external RAM.

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GENERAL PURPOSE RAM

80bit of GPR from address 30H to 7FH. Bottom 32 bit from 00H to 1FH can be used similarly. Any location can be accessed freely either directly or indirectly. e.g. Mov A, 5FH, Mov Ro, #5FH , Mov A, @ Ro

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Bit Addressable RAM

210 bit- addressable location, of which 128 are at byte address 20H to 2FH Individual accessing of bit through S/W is a powerful feature of most microcontroller. Bits can be set, cleared, AND, OR etc with a single instruction . I/O ports are bit addressable 20H to 2FH address are accessed either bits or bytes, depending upon instruction. Eg. SETB 67H

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Register Banks

8051 instruction set support 8 registers R0 to R7 (00 -07H) Instruction using R0 to R7 are shorter and faster than the equivalent instruction using direct addressing
The active register bank may be altered by changing the register bank

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Special Function Register (SFR)

In microprocessor most register are accessed implicitly by the instruction set. E.g. INCA same in microcontroller There are 21 SFR defined at the top of internal RAM from 80H FFH Some SFR are both bit & byte addressable designer should be careful eg. SETB 0E0H

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PSW
CY AC F0 RS1 RS0 OV P D7H D6H D5H D4H D3H D2H D1H D0H
Over flow

flag0
Auxiliary Carry 00 01 10 11

Even parity bank0 bank1 - bank2 - bank3 Reserved

Carry flag
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Carry Flag
It is dual purpose used in traditional way for arithmetic operation: set if there is carry/borrow out of bit 7 during add and subtract Carry flag is also Boolean accumulator. Serving as a 1-bit register for Boolean instructions operating on bits. E.g ANL C 25h
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Auxiliary Carry Flag

When BCD values are added, the auxiliary carry flag set if a carry was generated out of 3 bit into 4 or if the result in lower nibble is in the range 0AH 0FH. If the value added are BCD then add instruction is followed by DAA (decimal adjust accumulator) to bring the results greater than 9 back into range.
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Flag 0
It is general purpose flag bit available for user application.

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Register bit selects bits

The register bank select bit(RS0 RS1) determine the active register bank. They are cleared after a system reset and are changed by s/w as needed. E.g SETB RS1 Register 3 SETB RS0 Mov A, R7

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Overflow Flag
It is set after an addition or subtraction operation if there was an arithmetic overflow. When signed are added or subtracted . S/W can examine this bit to determine if the result is in the proper range. When unsigned number are added, the OV bit can be ignored the result greater then +127 or less than -128 will set the OV E.g. 0F + 7F = 8E (hex) , 15 +127 =142 (decimal) so here 8E represent -116 which is clearly not a correct result of 142 so OV is set.
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Parity Bit
It is automatically set or clear each machine cycle to establish even parity with accumulator plus to establish even parity with accumulator, the number of 1-bit in the accumulator plus the P bit is always even. The parity bit is most commonly used in conjunction with serial port routine to include a parity bit before transmission or to check the parity after reception.
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B Register (F0H)
It is used along with accumulator for multiply and divide operations. MUL AB multiply the 8-bit unsigned values in A and B and leaves the 16-bit results in A (lowbyte) and B (high byte) DIV AB divides A by B leaving the integer results in A and reminder in B. the register B can also be used as general purpose scratch pad. It is bit addressable (F0H F7H).
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Stack Pointer(81H)
It contain the address of the data item currently on the top of the stack. Stack operation includes pushing (writing) data on the stack( increment the SP before) and popping( reading) data (decrement the SP) In 8051 stack is kept in RAM & is limited to address accessible by indirect addressing To reinitialize the SP with the Stack beginning at 60H following instruction is used: MOV SP # 5FH Designer may choose not to initialize the stack pointer and let it retain with default value. Stack is accessed explicitly by PUSH and POP instruction and implicitly by subroutine (ACALL & LCALL) and return instruction (RET ,RET1)

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DPTR(82-83H)
It is used to access the external code and data memory It is 16 bit register DPL and DPH MOV A,#55H MOV DPTR,#1000H MOVX @, A
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Port Register
Port0 at 80H, Port1 at 90H, Port2 at A0H, Port3 at B0H, port 0, 2 & 3 may not available for I/O if external memory or special feature are used. All ports are bit addressable

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Timer Register (8AH 8DH)

It contain two 16 bit timer/counter for timing interval or counting events. Events Timer0 is at 8AH(TL0, Low byte) and 8CH(TH0, high byte) and Timer1 is at 8BH(TL1, Low byte) and 8DH (TH1, high byte) Timer operation is set by timer mode register (TMOD) at 89H and timer control (TCON) at 88H and only TCON is bit addressable.
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Serial Port Register

8051 contain on chip serial port for communication with serial devices ( modems or terminals) or for interface with other ICs. One register SBUF at 99H, it holds both transmitting and receiving the data. SCON at 98H to perform various programmable operations
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Interrupt Register
8051 has 5 source, 2 priority level interrupt structure. Interrupt are disable after system are reset and enable by writing to the interrupt enable register IE at A8H Priority is set through IP register at B8H

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Power Control Register

SMOD ---- ---Double baud rate bit:

-----

GF1

GF0

PD

IDL

When set, baud rate is

Doubled in serial port Modes 1,2&3

General purpose flag bit 1

Gen eral purp ose flag bit 0

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Power down mode: set to activate Power down , only exist is reset

Idle mode: set to activate idle mode, only exist is an interrupt or system reset

External Memory

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 Microcontroller have inbuilt capability to expand the on chip source . Microcontroller provides an option 64 k data and code memory expansion. Extra RAM and ROM can be added as per desire

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