STA CONSTRAINTS ASSIGNMENT

Submitted by: Nandan Roy A.S.

1. What happens if you dont specify these Units ? Is there a default settings, If so what are they ? If not specified, default values from .lib are taken. 2. What happens if you dont specify waveform ? Then Duty cycle of signal is taken as 50% 3. How does propagated clock effects Latency ? Propagated clock increases latency. As b4 propagated clock is activated clock is ideal. 4. Latency how do you specify for list of pin/ports? Write out a script with foreach_in _collection foreach_in_collection port[get_port *] { set _clock_latency -source -late 1.0 $port } 5. Specifying from and to clock uncertainty in both the combination is important why ? -Used when there are multiple clocks in design, so that the timing relationships between those clocks so that the analysis tool can check the timing of a path launched by one clock and captured by another. -By default, the tool assumes that after the occurrence of a launch event at a path startpoint, the very next clock edge that can occur at the path endpoint should capture the data at the end of the path 6.What is Jitter ? Find out various types of it and its importance ? PLL Jitter -Caused due to VCO running at high frequency -Crosstalk effects -Noise ue to phase shifting inside PLL. CTS Jitter Causes can be -Supply noise variation -Local IR Drop variations, and clock switching activity variations -Crosstalk effects . 8. Which has more priority Latency or Propagated Clock ? -Propagated Clock has more priority than Latency. 9. What happens if you specify both? -PT finds out latency by propagating the all clocks of design. -Done after CTS and Layout, when they are Back-Annotated -Estimate and specify explicitly the latency of each clock. This method is typically used before clock tree synthesis .

-If propagated clock is not specified in the design default the value of latency which was set will be taken for calculations. -Hence Propagated clock has more priority than Latency. 10. Can we propagate Virtual Clock ? If yes/no how ? -Virtual clocks for signals that interface to external (off-chip) clocked devices. A virtual clock has no actual source in the current design, but you can use it for setting input or output delays. -virtual clocks for signals that interface to external (off-chip) clocked devices. A virtual clock has no actual source in the current design, but you can use it for setting input or output delays. -Virtual clock cannot be propagated in the design, but the latency can be set or modified in the design. 11. What happens if you dont specify a asynchronous clock to a path ? Justify ? -When data is launched from one clock domain and captured on a different asynchronous domain, metastability can happen. -This Metastability cannot be accepted, and to ensure this error does not happen, false path should be mentioned. 12. What is physically exclusive and how it differs from logically exclusive ? -Logically exclusive -PT does not check for logical timing between them -PT SI does check for cross talk interaction between them. -Physically exclusive -Have no logical timing paths between them -Also they are considered physically isolated from each other. -PT does not check the logical timing between the clocks -PT SI assumes no possible crosstalk interaction between them. 13. How disable_timing is different from set_false_path ? -set_false_path -Declaring a path to be false removes all timing constraints from the path. -But calculates delay, but does not report errors -set_disable_timing -Which disables timing analysis for a specified pin, cell, or port. 14. Does set_false_path overrides min_delay and max_delay ? -The timing exception priority is as follows.. 1. set_false_path 2. set_max_delay and set_min_delay 3.set_multicycle_path -So, yes, False Path will override Min, Max Delays.

15. Does set_false_path even affects cross_talk_analysis ? If yes How ? If no, how can we overcome ? In false Path, the tool can still calculates for the cross talk analysis -You can declare a relationship between two clocks to be asynchronous. In that case, PrimeTime does not check the timing paths launched by one clock and captured by the other clock, which is like declaring a false path between the two clocks. 16. What happens if you dont specify a asynchronous between non synchronous clocks ? -If you do not declare asynchronous between two non-synchronous clocks, Prime time checks the timing path of the data launched by one clock and captured by the other clock. Its like not declaring a false path 17. Hold check on Previous edge isnt possible ? Tool Question 18. Do a report_timing and see with and without Hold Multiplier... Tool Question 19. Is there a limit for the Multiplier (Setup) ? Tool Question 20. For Ideal_clock which (source/network) Latency is applied ? Only Source Latency is applied for ideal clock, network latency is not valid for ideal clock. 21. Can we separately derate cells and Nets ? Yes. For Cells: set_timing_derate -cell_delay -early 0.9 set_timing_derate -cell_delay -late 1.0 For Nets: set_timing_derate -net_delay -early 1.0 set_timing_derate -net_delay -late 1.2 22. Are you aware of sigma factor ? - factor is the derating factor applied during OCV. 23. Which part of logic is actually derated combis or Sequentials or Both ? Derate's affect only Combi Logic.

24. Write a TCL file to be used in commands mentioned in the RC / EDI to with all the presentation for the RTL code you used for synthesis. #####################|####### #### Script for Synthesis ##### #####################|####### ## Setting default Lib Path set_attribute lib_search_path /home/krajput/Data/lib/ ## Setting the Link Library set_attribute library sc7_ts13sl_base_rvt_ff_typical_min_1p32v_0c.lib ## Setting default HDL path set_attribute hdl_search_path /home/krajput/Data/barrel_shifter/code ## Reading the HDL files read_hdl barrel_shifter.v read_hdl ip2_mux4.v read_hdl ip2_mux.v read_hdl ip4_mux4.v ## Compile the HDL Codes elaborate barrel ## Define Clock define_clock -period 500 -name clk -rise 20 -fall 80 [find / -port clk] ##Clock Uncertainty clock_uncertainty -setup -rise 0.4 [find / -port ports_in/clk ] ## Setting Max Transition Values set_attribute max_transition 50 /designs/barrel ##Max Fanout set_attribute max_fanout 5 /designs/barrel ##Max Capaticance set_attribute max_capacitance 40 /designs/barrel ##Slew set_attribute slew {100 110 110 120} [find / -clock clk] ## Setting External Delays

external_delay -output 100 -edge_fall -clock [find / -clock clk] [find / -port ports_out/*] external_delay -input 100 -edge_fall -clock [find / -clock clk] [find / -port ports_in/*] ## Wire load Modules from .lib set_attribute force_wireload Small barrel ## Clock Gating Attributes set_attribute lp_insert_clock_gating true set_attr lp_clock_gating_max_flops 5 /designs/barrel set_attr lp_clock_gating_min_flops 1 /designs/barrel set_attribute lp_clock_gating_style latch /designs/barrel set_attr lp_clock_gating_cell [find / -libcell TLATNTSCAX12M] [find / -design barrel] set clock_gating_integrated_cell latch_posedge_precontrol ## Setting the Operating Conditions set_attr operating_condition "ff_typical_min_1p32v_0c" ## Synthesize to GTECH synthesize -to_generic write -generic > /home/aroy/Synthesis/Netlists/barrel_netlist_gen.v ## Synthesize to Tech Dependent synthesize -to_mapped write -mapped > /home/aroy/Synthesis/Netlists/barrel_netlist.v ## Reporting the required report timing > /home/aroy/Synthesis/Reports/barrel_timing.rpt report gates > /home/aroy/Synthesis/Reports/barrel_gates.rpt report area > /home/aroy/Synthesis/Reports/barrel_area.rpt report power > /home/aroy/Synthesis/Reports/barrel_power.rpt report qor > /home/aroy/Synthesis/Reports/barrel_qor.rpt write_sdc > /home/aroy/Synthesis/SDC/barrel_sdc.sdc 25. Convert the above file to a post CTS constraints file to be used in Primetime or ETS . -Same as above, except remove -Uncertainty -Latency etc.. 26. Show with the help of commands how you will apply derates for setup and hold STA -For applying a derate of 5% -late 1. setup: (data path) x 1.05 2. hold: (clock path) x 1.05 -early

1. setup: (clock path) x 0.95 2. hold: (data path) x 0.95 Therefore, we can use set_timing_derate -early 0.95 set_timing_derate -late 1.05 27. Collect or list down the commands used for back annotating parasitics during Static Timing Analysis . -A typical sequence of commands is to first characterize the timing environment of a block using the characterize_context command and write this information as a dc_shell script using the write_context command. The write_physical_annotations command is then used to export annotated delays and parasitics for internal nets of the block. -Example: pt_shell> characterize_context I2 pt_shell> write_context -format dcsh \ -out I2.dcsh pt_shell> write_physical_annotations \ -sdf I2.sdf 28. Identify the command used for Timing Constraints Coverage analysis to be used in Primetime and describe the reports . -To constrain a design fully for placement, every net or every net arc (connection between two cells) generally requires a constraint. You can ensure that a design is fully constrained by forcing the write_sdf_constraints command to generate constraints for all paths in the design. -The write_sdf_constraints commands -cover_design option generates just enough unique paths to provide constraint coverage for the entire design. -Example: pt_shell> write_sdf_constraints -cover_design \