CHARACTERISTICS OF NAND GATE

ROLL NO: 10EE01038 & 10EE01039

AIM: To build a schematic of a NAND gate using CMOS logic and observe its
characteristics. SOFTWARE USED: Cadence virtuoso tool

PROCEDURE: STARTING CADENCE:

1. In a terminal window, type csh at the command prompt to invoke the C shell. >csh >source cshrc 2. Change to the course directory by entering this command: > cd ~/Database/cadence_analog_labs_614 3. In the same terminal window, enter: > virtuoso & The virtuoso or Command Interpreter Window (CIW) appears at the bottom of the screen.

SCHEMATIC ENTRY:

1. In the Library Manager, execute File - New Library. 2. In the New Library form, type myDesignLib in the Name section. 3. In the field of Directory section, verify that the path to the library is set to
~/Database/cadence_analog_labs_614

4. In the next Technology File for New library form, select option Attach to an existing techfile and attach gpdk180.

SCHEMATIC CELL VIEW:

1. In the CIW or Library manager, execute File New Cellview. 2. Set up the New file form as follows:

Nand

3. In the Inverter schematic window, click the Instance fixed menu icon to display the Add Instance form. 4. Add pmos and nmos components with required specifications to build schematic circuit. 5. Execute Create Pin or press p and add Vin as input pin and Vout as output pin.
6. Click the Wire (narrow) icon in the schematic window and complete the wiring of the diagram.

7. Save the schematic and close the window. The schematic appears as shown

SYMBOL CREATION:
1. In the Nand schematic window, execute Create Cellview From Cellview.

2. Window appears as shown

Nand

3. Modify the pin specifications as following

Nand

4. A window appears as shown

5. Edit the symbol to shape of an Nand gate as shown below using Create option

LOGIC GATE TEST DESIGN: 1. In the CIW or Library Manager, execute File New Cellview and a window appears as shown

Nand_Test

2. Add vpulse, Vdc, ground cells in the test with required properties of the cells. 3. The schematic looks like this

ANALOG SIMULATION: 1. In the Nand_Test schematic window, execute Launch ADE L 2. In the simulation window (ADE), Execute Setup - Model Libraries AND check the following window

3. In the Simulation window (ADE), click the Choose - Analyses icon and for transient analysis set as shown

For DC analysis:

4. Execute Outputs To be plotted Select on Schematic in the simulation window.

5. Click on Vout and Vin pins and a window appears as shown

Nand

6. Execute Simulation Netlist and Run in the simulation window to start the Simulation. SIMULATION OUTPUT:

CONCLUSION: A NAND gate was designed using CMOS logic and the Transient characteristics and DC characteristics of the NAND gate were observed.