IMPLEMENTATION OF VLSI ARCHITECTURE IN INTER INTEGRATED CIRCUIT (I2C)

ABSTRACT
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is primarily used in the customer and telecom market sector and as a broad level communications protocol. The open Cores I2C Master Core provides an interface between a Wishbone Master and an I2C bus. It is an easy path to add I2C capabilities to any Wishbone compatible system. It is most suitable for applications requiring occasional communication over a short distance between many devices. The I2C standard is a true multimaster bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously.

LANGUAGE USED:
VHDL/VERILOG

TOOLS REQUIRED:
MODELSIM Simulation, XILINX-ISE Synthesis

CHAPTER-1 FPGA DESIGN FLOW This is part of chapter deals with the implementation flow specifying the significance of various properties, reports obtained and simulation waveforms of architectures developed to implement. 1.1 FPGA Design flow: The various steps involved in the design flow are as follows: 1) Design entry. 2) Functional simulation. 3) Synthesizing and optimizing (translation) the design. 4) Placing and routing the design 5) Timing simulation of the design after post PAR. 6) Static timing analysis. 7) Configuring the device by bit generation.

4.1.1 Design entry: The first step in implementing the design is to create the HDL code based on design criteria. To support these instantiations we need to include UNISIM library and compile all design libraries before performing the functional simulation. The constraints (timing and area constraints) can also be included during the design entry. Xilinx accepts the constraints in the form of user constraint (UCF) file.

4.1.2 Functional Simulation: This step deals with the verification of the functionality of the written source code. ISE provides its own ISE simulator and also allows for the integration with other tools such as Modelsim. This project uses Modelsim for the functional verification by selecting the option during project creation. Functional simulation determines if the logic in the design is correct before implementing it in a device. Functional simulation can take place at the earliest stages of the design flow. Because timing information for the implemented design is not available at this stage, the simulator tests the logic in the design using unit delays. 4.1.3 Synthesizing and Optimizing: In this stage behavioral information in the HDL file is translated into a structural net list, and the design is optimized for a Xilinx device. To perform synthesis this project uses Xilinx XST tool [17]. From the original design, a net list is created, then synthesized and translated into a native generic object (NGO) file. This file is fed into the Xilinx software program called NGDBuild, which produces a logical native generic database (NGD) file. 4.1.4 Design implementation: In this stage, The MAP program maps a logical design to a Xilinx FPGA. The input to MAP is an NGD file, which is generated using the NGDBuild program. The NGD file contains a logical description of the design that includes both the hierarchical components used to develop the design and the lower level Xilinx primitives. The NGD file also contains any number of NMC (macro library) files, each of which contains the definition of a physical macro. MAP first performs a logical DRC (Design Rule Check) on the design in the NGD file. MAP then maps the design logic to the components (logic cells, I/O cells, and other components) in the target Xilinx FPGA.
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The output from MAP is an NCD (Native Circuit Description) file, and PCF (Physical constraint file). NCD (Native Circuit Description) filea physical description of the design in terms of the components in the target Xilinx device. PCF (Physical Constraints File)an ASCII text file that contains constraints specified during design entry expressed in terms of physical elements. The physical constraints in the PCF are expressed in Xilinxs constraint language. After the creation of Native Circuit Description (NCD) file with the MAP program, place and route that design file using PAR. PAR accepts a mapped NCD file as input, places and routes the design, and outputs an NCD file to be used by the bit stream generator (BitGen). The PAR placer executes multiple phases of the placer. PAR writes the NCD after all the placer phases are complete. During placement, PAR places components into sites based on factors such as constraints specified in the PCF file, the length of connections, and the available routing resources. After placing the design, PAR executes multiple phases of the router. The router performs a converging procedure for a solution that routes the design to completion and meets timing constraints. Once the design is fully routed, PAR writes an NCD file, which can be analyzed against timing. PAR writes a new NCD as the routing improves throughout the router phases. 4.1.5 Timing simulation after post PAR: Timing simulation at this stage verifies that the design runs at the desired speed for the device under worst-case conditions. This process is performed after the design is mapped, placed, and routed for FPGAs. At this time, all design delays are known. Timing simulation is valuable
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because it can verify timing relationships and determine the critical paths for the design under worst-case conditions. It can also determine whether or not the design contains set-up or hold violations. In most of the designs the same test bench can be used to simulate at this stage.

4.1.6 Static timing analysis: Static timing analysis is best for quick timing checks of a design after it is placed and routed. It also allows you to determine path delays in your design. Following are the two major goals of static timing analysis: Timing verification This is verifying that the design meets your timing constraints. Reporting This is enumerating input constraint violations and placing them into an accessible file. ISE provides Timing Reporter and Circuit Evaluator (TRACE) tool to perform STA. The input files to the TRACE are .ncd file and .pcf from PAR .and the output file is a .twr file.

4.2 Processes and properties: Processes and properties enable the interaction of our design with the functionality available in the ISE suite of tools.

4.2.1 Processes Processes are the functions listed hierarchically in the Processes window. They perform functions from the start to the end of the design flow. 4.2.2 Properties Process properties are accessible from the right-click menu for select processes. They enable us to customize the parameters used by the process. Process properties are set at synthesis and implementation phase. 4.3 Synthesize options: The following properties apply to the Synthesize properties using the Xilinx Synthesis Technology (XST) synthesis tool. Optimization Goal Specifies the global optimization goal for area or speed. Select an option from the drop-down list. Speed Optimizes the design for speed by reducing the levels of logic. Area Optimizes the design for area by reducing the total amount of logic used for design implementation. By default, this property is set to Speed.

4.3.1 Optimization Effort Specifies the synthesis optimization effort level. Select an option from the drop-down list. Normal

Optimizes the design using minimization and algebraic factoring algorithms. High Performs additional optimizations that are tuned to the selected device architecture. "High" takes more CPU time than "Normal" because multiple optimization algorithms are tried to get the best result for the target architecture. By default, this property is set to Normal. This project aims at Timing performance and was selected HIGH effort level. 4.3.2 Power Reduction When set to Yes (checkbox is checked), XST optimizes the design to consume as little power as possible. By default, this property is set to No (checkbox is blank). 4.3.3 Use Synthesis Constraints File Specifies whether or not to use the constraints file entered in the previous property. By default, this constraints file is used (property checkbox is checked). 4.3.4 Keep Hierarchy Specifies whether or not the corresponding design unit should be preserved and not merged with the rest of the design. You can specify Yes, No and Soft. Soft is used when you wish to maintain the hierarchy through synthesis, but you do not wish to pass the keep_ hierarchy attributes to place and route. By default, this property is set to No. The change in option of this property from no to yes gave me almost double the speed.

CHAPTER 3 INTRODUCTION OF VLSI

Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistor-based circuits into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device. The term is no longer as common as it once was, as chips have increased in complexity into the hundreds of millions of transistors. Overview The first semiconductor chips held one transistor each. Subsequent advances added more and more transistors, and, as a consequence, more individual functions or systems were integrated over time. The first integrated circuits held only a few devices, perhaps as many as ten diodes, transistors, resistors and capacitors, making it possible to fabricate one or more logic gates on a single device. Now known retrospectively as "small-scale integration" (SSI), improvements in technique led to devices with hundreds of logic gates, known as large-scale integration (LSI), i.e. systems with at least a thousand logic gates. Current technology has moved far past this mark and today's microprocessors have many millions of gates and hundreds of millions of individual transistors. At one time, there was an effort to name and calibrate various levels of large-scale integration above VLSI. Terms like Ultra-large-scale Integration (ULSI) were used. But the huge number of gates and transistors available on
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common devices has rendered such fine distinctions moot. Terms suggesting greater than VLSI levels of integration are no longer in widespread use. Even VLSI is now somewhat quaint, given the common assumption that all microprocessors are VLSI or better. As of early 2008, billion-transistor processors are commercially available, an example of which is Intel's Montecito Itanium chip. This is expected to become more commonplace as semiconductor fabrication moves from the current generation of 65 nm processes to the next 45 nm generations (while experiencing new challenges such as increased variation across process corners). Another notable example is NVIDIAs 280 series GPU. This microprocessor is unique in the fact that its 1.4 Billion transistor count, capable of a teraflop of performance, is almost entirely dedicated to logic (Itanium's transistor count is largely due to the 24MB L3 cache). Current designs, as opposed to the earliest devices, use extensive design automation and automated logic synthesis to lay out the transistors, enabling higher levels of complexity in the resulting logic functionality. Certain high-performance logic blocks like the SRAM cell, however, are still designed by hand to ensure the highest efficiency (sometimes by bending or breaking established design rules to obtain the last bit of performance by trading stability).

What is VLSI?
VLSI stands for "Very Large Scale Integration". This is the field which and more logic devices into smaller and smaller areas. involves packing more

VLSI Simply we say Integrated circuit is many transistors on one chip. Design/manufacturing of extremely small, complex circuitry using modified semiconductor material Integrated circuit (IC) may contain millions of transistors, each a few mm in size Applications wide ranging: most electronic logic devices

History of Scale Integration

late 40s Transistor invented at Bell Labs late 50s First IC (JK-FF by Jack Kilby at TI) early 60s Small Scale Integration (SSI) 10s of transistors on a chip late 60s Medium Scale Integration (MSI) 100s of transistors on a chip early 70s Large Scale Integration (LSI) 1000s of transistor on a chip early 80s VLSI 10,000s of transistors on a chip (later 100,000s & now 1,000,000s) Ultra LSI is sometimes used for 1,000,000s SSI - Small-Scale Integration (0-102) MSI - Medium-Scale Integration (102-103)
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LSI - Large-Scale Integration (103-105)

VLSI - Very Large-Scale Integration (105-107) ULSI - Ultra Large-Scale Integration (>=107)

Advantages of ICs over discrete components

While we will concentrate on integrated circuits , the properties of integrated circuits-what we can and cannot efficiently put in an integrated circuit-largely determine the architecture of the entire system. Integrated circuits improve system characteristics in several critical ways. ICs have three key advantages over digital circuits built from discrete components: Size. Integrated circuits are much smaller-both transistors and wires are shrunk to micrometer sizes, compared to the millimeter or centimeter scales of discrete components. Small size leads to advantages in speed and power consumption, since smaller components have smaller parasitic resistances, capacitances, and inductances. Speed. Signals can be switched between logic 0 and logic 1 much quicker within a chip than they can between chips. Communication within a chip can occur hundreds of times faster than communication between chips on a printed circuit board. The high speed of circuits on-chip is due to their small size-smaller components and wires have smaller parasitic capacitances to slow down the signal. Power consumption. Logic operations within a chip also take much less power. Once again, lower power consumption is largely due to
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the small size of circuits on the chip-smaller parasitic capacitances and resistances require less power to drive them. VLSI and systems These advantages of integrated circuits translate into advantages at the system level: Smaller physical size. Smallness is often an advantage in itselfconsider portable televisions or handheld cellular telephones. Lower power consumption. Replacing a handful of standard parts with a single chip reduces total power consumption. Reducing power consumption has a ripple effect on the rest of the system: a smaller, cheaper power supply can be used; since less power consumption means less heat, a fan may no longer be necessary; a simpler cabinet with less shielding for electromagnetic shielding may be feasible, too. Reduced cost. Reducing the number of components, the power supply requirements, cabinet costs, and so on, will inevitably reduce system cost. The ripple effect of integration is such that the cost of a system built from custom ICs can be less, even though the individual ICs cost more than the standard parts they replace. Understanding why integrated circuit technology has such profound influence on the design of digital systems requires understanding both the technology of IC manufacturing and the economics of ICs and digital systems.

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Applications

Electronic system in cars. Digital electronics control VCRs Transaction processing system, ATM Personal computers and Workstations Medical electronic systems. Etc.
Applications of VLSI

Electronic systems now perform a wide variety of tasks in daily life. Electronic systems in some cases have replaced mechanisms that operated mechanically, hydraulically, or by other means; electronics are usually smaller, more flexible, and easier to service. In other cases electronic systems have created totally new applications. Electronic systems perform a variety of tasks, some of them visible, some more hidden: Personal entertainment systems such as portable MP3 players and DVD players perform sophisticated algorithms with remarkably little energy. Electronic systems in cars operate stereo systems and displays; they also control fuel injection systems, adjust suspensions to varying terrain, and perform the control functions required for anti-lock braking (ABS) systems. Digital electronics compress and decompress video, even at highdefinition data rates, on-the-fly in consumer electronics.

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 Low-cost terminals for Web browsing still require sophisticated electronics, despite their dedicated function. Personal computers and workstations provide word-processing, financial analysis, and games. Computers include both central processing units (CPUs) and special-purpose hardware for disk access, faster screen display, etc. Medical electronic systems measure bodily functions and perform complex processing algorithms to warn about unusual conditions. The availability of these complex systems, far from overwhelming consumers, only creates demand for even more complex systems. The growing sophistication of applications continually pushes the design and manufacturing of integrated circuits and electronic systems to new levels of complexity. And perhaps the most amazing characteristic of this collection of systems is its variety-as systems become more complex, we build not a few general-purpose computers but an ever wider range of special-purpose systems. Our ability to do so is a testament to our growing mastery of both integrated circuit manufacturing and design, but the increasing demands of customers continue to test the limits of design and manufacturing

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CHAPTER 4
This chapter mainly explains the Overview of the VHDL

4.1 VHDL
VHDL is an acronym for Very High Speed Integrated Circuits Hardware description Language. The language can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the gate level. The complexity of the digital system being modeled could vary from that of a simple gate to a complete digital electronic system. The VHDL language can be regarded as an integrated amalgamation of sequential, concurrent, net list and waveform generation languages and timing specifications.

4.1.1 History of VHDL

VHDL stands for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language. It was developed in the 1980s as spin-off of a high-speed integrated circuit research project funded by the US department of defense. During the VHSIC program, researchers were confronted with the daunting task of describing circuits of enormous scale (for their time) and of managing very large circuit design problems that involved multiple teams of engineers. With only gate-level tools available, it soon became clear that more structured design methods and tools would be needed. To meet this challenge, teams of engineers from three companies - IBM, Texas Instruments and Intermetrics were contracted by the department of defense to complete the specification and implementation of a new language based design description method. The first publicly available version of VHDL, version 7.2 was released in 1985. In 1986, the IEEE was presented with a proposal to standardize the language, which it did in 1987 and academic representatives. The resulting standard, IEEE 10761987 is the basis for virtually every simulation and synthesis product sold today. An enhanced and updated version of the language, IEEE 1076-1993, was released in 1994, and VHDL tool vendors have been responding by adding these new language features to their products. Although IEEE standard 1076 defines the complete VHDL language, there are aspects of the language that make it difficult to write completely portable design descriptions (description that can be

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simulated identically using different vendors tools). The problem stems from the fact that VHDL supports many abstract data types, but it does not address the simple problem of characterizing different signal strengths or commonly used simulation conditions such as unknowns and high impedances. Soon after IEEE 1076-1987 [3] was adopted, simulator companies began enhancing VHDL with new non-standard types to allow their customers to accurately simulate complex electronics circuits. This caused problems because design descriptions entered into one simulator were often incompatible with another with other environments. VHDL was quickly becoming a non-standard. To get around the problem of non-standard data types, an IEEE committee adopted another standard. This standard numbered 1164, defines a standard package (a VHDL feature that allows commonly used declaration to be collected into an external library) containing definition for a standard nine-value data type. This standard data type is called standard logic, and the IELL 1164 package is often referred to as the standard logic package.

4.1.2 Levels of abstraction (Styles) VHDL supports many possible styles of design description. These styles differ primarily in how closely they relate to the underlying hardware. When we speak of the different styles of VHDL, then, we are really talking about the differing levels of abstraction possible using the language. To give an example, it is possible to describe a counter circuit in a number of ways. At the lowest level of abstraction, you could use VHDL's hierarchy features to connect a sequence of predefined logic gates and flip-flips to form a counter circuit.

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Fig. 4.1 Levels of abstraction

In a behavioral description, the concept of time may be expressed precisely, with actual delays between related events, or may simply be an ordering of operations that are expressed sequentially. When you are writing VHDL for input to synthesis tools, you may use behavioral statements in VHDL to imply that there are registers in your circuit. It is unlikely, however, that your synthesis tool will be capable of creating precisely the same behavior in actual circuitry as you have defined in the language. The highest level of abstraction supported in VHDL is called the behavioral level of abstraction. When creating a behavioral description of a circuit, you will describe your circuit in terms of its operation over time. The concept of time is the critical distinction between behavioral descriptions of circuits and lower-level descriptions. If you are familiar with event-driven software programming languages then writing behavior level VHDL will not seem like anything new. Just like a programming language, you will be writing one or more small programs that operate sequentially and communicate with one another through their interfaces. The only difference between behavior-level VHDL and a software programming language such as Visual Basic is the underlying execution platform: in the case of Visual Basic, it is the Windows operating system; in the case of VHDL, it is a simulator. An alternate design method, in which a circuit design problem is segmented into registers and combinational input logic, is what is often called the dataflow level of abstraction. Dataflow is an 17

intermediate level of abstraction that allows the drudgery of combinational logic to be hidden while the more important parts of the circuit, the registers, are more completely specified. There are some drawbacks to using a purely dataflow method of design in VHDL. First, there are no built-in registers in VHDL; the language was designed to be general-purpose, and VHDLs designers on its behavioral aspects placed the emphasis. If you are going to write VHDL at the dataflow level of abstraction, then you must first create behavioral descriptions of the register elements that you will be using in your design. These elements must be provided in the form of components or in the form of subprograms. But for hardware designers, for whom it can be difficult to relate the sequential descriptions and operation of behavioral VHDL with the hardware that is being described, using the dataflow level of abstraction can make quite a lot of sense. Using dataflow, it can be easier to relate a design description to actual hardware devices. The dataflow and behavior levels of abstraction are used to describe circuits in terms of their logical function. There is a third style of VHDL that is used to combine such descriptions together into a larger, hierarchical circuit description. Structural VHDL allows you to encapsulate one part of a design description as a re-usable component. Structural VHDL can be thought of as being analogous to a textual schematic, or as a textual block diagram for higher-level design.

4.1.3 Need for VHDL

The complex and laborious manual procedures for the design of the hardware have paved the way for the development of languages for high level description of the digital system. This high-level description can serve as documentation for the part as well as an entry point into the design process. The high level description can be processed through various boards, or gate array using the synthesis tools of Hardware Description language us such a language. VHDL was designed as a solution to provide an integrated design and documentation to communicate design data between various levels of abstractions.

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4.1.4 Advantages of VHDL

VHDL allows quick description and synthesis of circuits of 5, 10, 20 thousand gates. It also provides the following capabilities. The following are the major advantages of VHDL over other hardware description languages:

Power and flexibility VHDL has powerful language constructs which allows code description of complex control logic.

Device independent design VHDL creates design that fits into many device architecture and it also
permits multiple styles of design description.

Portability VHDLs portability permits the design description to be used on different simulators and
synthesis tools. Thus VHDL design descriptions can be used in multiple projects.

ASIC migration The efficiency of VHDL allows design to be synthesized on a CPLD or an FPGA. Sometimes the code can be used with the ASIC.

Quick time to market and low cost VHDL and programmable logic pair together facilitate speedy
design process. VHDL permits designs to be described quickly. Programmable logic eliminates expenses and facilitates quick design iterations

The language can be used as a communication medium between different Computer Aided
Design (CAD) and Computer Aided Engineering (CAE) tools.

The language supports hierarchy, i.e., a digital system can be modeled as a set of interconnected components; each component, in turn, can be modeled as a set of interconnected subcomponents.

The language supports flexible design methodologies: Top-Down, Bottom- Up, or Mixed.
The language is technology independent and hence the same behavior model can be synthesized into different vendor libraries.

Various digital modeling techniques such as finite-state machine descriptions, algorithmic

descriptions and Boolean equations can be modeled using the language. 19

 It supports both synchronous and asynchronous timing models.

It is an IEEE and ANSI standard, and therefore, models described using these languages are portable.

There are no limitations that are imposed by the language on the size of the design.
The language has elements that make large-scale design modeling easier, for e.g. Components, functions, procedures and packages.

Test benches can be written using the same language to test other VHDL models. Nominal propagation delays, min-max delays, setup and holding timing, timingconstraints,
and spike detection can all be described very naturally in this language.

Behavioral models that conform to a certain synthesis description style are capable of being
synthesized to gate-level description.

The capability of defining new data types provides the power to describe and simulate a new
design technique at a very high level of abstraction without any concern about implementation details.

4.1.5 Design methodology using VHDL There are three design methodologies namely: bottom-up, top-down and flat

The bottom-up approach involves the defining and designing the individual components, then bringing the individual components together to form the overall design.

In a flat design the functional components are defined at the same level as the interconnection of those functional components.

A top-down design process involves a divide-and-conquer approach to implement the design

a large system. Top-down design is referred to as recursive partitioning of a system into its 20

sub-components until all sub-components become manageable design parts. Design of a component is manageable if the component is available as part of a library, it can be implemented by modifying an already available part, or it can be described for a synthesis program or an automatic hardware generator.

4.1.6 Elements of VHDL

Constructs of the VHDL language are designed for describing hardware components, packaging parts and utilities use of libraries and for specifying design libraries and parameters. In its simplest form, the description of a component in VHDL consists of an interface specification and an architectural specification. The interface description begins with Entity keyword and contains the input-output ports of the component. An architectural specification begins with the Architectural keyword, which describes the functionality of a component.
This functionality depends on input-output signals and other parameters that are specified in the interface description. Several architectural specifications with different identifiers can exist for one component with a given interface description. VHDL allows architecture to be configured for a specific technology environment. In a hardware design environment it becomes necessary to group components or utilities used for description of components. Components and such utilities can be grouped by use of packages. A package declaration contains components and utilities to be come visible by Entities and Architectures. VHDL allows the use of Libraries and binding of sub-components of a design to elements of various libraries. Constructs for such applications include a library statement and configurations.

4.1.7 VHDL language features The various building blocks and constructs in VHDL which have been used are:

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4.1.7.1 Entity Every VHDL design description consists of at least one entity. In VHDL, an entity declaration describes the circuit as it appears from the "outside", from the perspective of its input and output interfaces. An entity declaration in VHDL provides the complete interface for a circuit. Using the information provided in an entity declaration (the port names and the data type and direction of each port), you have all the information you need to connect that portion of a circuit into other, higher-level circuits. The entity declaration includes a name, compare, and a port statement defining all the inputs and outputs of the entity. Each of the ports is given a direction (either in, out or inout).

Description
All designs are expressed in terms of entities. Entity is the most basic building block in a design. The uppermost level of the design is the top-level entity. If the design is hierarchical, then the top-level description will have lower-level descriptions contained in it. These lower-level descriptions will be lower-level entities contained in the top-level entity description.

4.1.7.2 Architecture Every entity in a VHDL design description must be bound with a corresponding architecture. The architecture describes the actual function of the entity to which it is bound. Using the schematic as a metaphor, you can think of the architecture as being roughly analogous to a lower-level schematic pointed to by the higher-level functional block symbol. The second part of a minimal VHDL source file is the architecture declaration. Every entity declaration you write must be accompanied by at least one corresponding architecture.

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The architecture declaration begins with a unique name, followed by the name of the entity to which the architecture is bound. Within the architecture declaration is found the actual functional description of our comparator. There are many ways to describe combinational logic functions in VHDL.

Formal Definition
A body associated with an entity declaration to describe the internal organization or operation of a design entity. An architecture body is used to describe the behavior, data flow or structure of a design entity:
ure-name];

Description
Architecture assigned to an entity describes internal relationship between input and output ports of the entity. It contains of two parts: declarations and concurrent statements. First (declarative) part of architecture may contain declarations of types, signals, constants, subprograms (functions and procedures), components and groups.

Concurrent statements in the architecture body define the relationship between inputs and outputs. This relationship can be specified using different types of statements: Concurrent signal assignment, process statement, component instantiation, and concurrent procedure call, generate statement, concurrent assertion statement, and block statement. It can be writing in different styles: structural, dataflow, behavioral (functional) or mixed.
The description of a structural body is based on component instantiation and generates statements. It allows creating hierarchical projects, from simple gates to very complex components, describing entire subsystems. The Connections among components are realized through ports.

The Dataflow description is built with concurrent signal assignment statements. Each of the statements can be activated when any of its input signals changes its value.

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The architecture body describes only the expected functionality (behavior) of the circuit, without any direct indication as to the hard ware implementation. Such description consists only of one or more processes, each of which contains sequential statements. The Architecture body may contain statements that define both behavior and structure of the circuit at the same time. Such architecture description is called mixed.

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VERILOG HDL
Verilog HDL is a hardware description language that can be used to model a digital system at many levels of abstraction ranging from the algorithmic-level to the gate-level to the switch-level. The complexity of the digital system being modeled could vary from that of a simple gate to a complete electronic digital system, or anything in between. The digital system can be described hierarchically and timing can be explicitly modeled within the same description. The Verilog HDL language includes capabilities to describe the behavior-al nature of a design, the dataflow nature of a design, a design's structural composition, delays and a waveform generation mechanism including aspects of response monitoring and verification, all modeled using one single language. In addition, the language provides a programming language interface through which the internals of a design can be accessed during simulation including the control of a simulation run. The language not only defines the syntax but also defines very clear simulation semantics for each language construct. Therefore, models written in simulator. The language inherits this language can be verified using a Verilog

many of its operator symbols and constructs from the C

programming language. Verilog HDL provides an extensive range of modeling capabilities, some of which are quite difficult to comprehend initially. However, a core subset of the language is quite easy to leam and use. This is sufficient to model most applications.

2.1 History:
The verilog HDL language was first developed by Gateway Design Automation in 1983 as hardware are modleling language for their simulator product, At that time ,twas a propnetary language. Because of the popularity of the,simulator product, Verilog HDL gained acceptance as a usable and practical language by a number of designers. In an effort to increase the popularity of the language, the language was placed in the public domain in 1990. Open verilog International (OVI) was formed to promote Verilog. In 1992 OVI decided to pursue standardization of verilog HDL as an IEEE standard. This effort was succeful and the language became an IEEE standard in 1995. The complete standard is described in the verilog hardware description language reference manual. The standard is called std 1364-1995.

2.2 Major Capabilities:

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Listed below are the majort capabilities of the verilog hardware description: Primitive logic gates, such as and, or and nand, are built-in into the language. Flexibility of creating a user-defined primitive (UDP). Such a primitive could either be a combinational logic primitive or a sequential logic primitive. Switch-level modeling primitive gates, such as pmos and nmos, are also built-in into the language. Explicit language constructs are provided for specifying pin-to-pin delays, path delays and timing checks of a design. A design can be modeled in three different styles or in a mixed style. These styles are: behavioral style - modeled using procedur-al constructs; dataflow style - modeled using continuous assignments; and structural style - modeled using gate and module instantiations. There are two data types in Verilog HDL; the net data type and the register data type. The net type represents a physical connection between structural elements while a register type represents an abstract data storage element.

Verilog HDL also has built-in logic functions such as & (bitwise-and) and I (bitwise-or).

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 High-level programming language constructs such as condition- als, case statements, and loops
are available in the language.

Notion of concurrency and time can be explicitly modeled. Powerful file read and write capabilities fare provided. The language is non-deterministic under certain situations, that is, a model may produce
different results on different simulators; for example, the ordering of events on an event queue is not defined by the standard.

2.3 SYNTHESIS:
Synthesis is the process of constructing a gate level netlist from a register-transfer level model of a circuit described in Verilog HDL. Figure.2-2 shows such a process. A synthesis system may as an intermediate step, generate a netlist that is comprised of register-transfer level blocks such as flip-flops, arithmetic-logic-units, and multiplexers, interconnected by wires. In such a case, a second program called the RTL module builder is necessary. The purpose of this builder is to build, or acquire from a library of predefined components, each of the required RTL blocks in the user-specified target technology.

Figure.2-2 synthesis process

Having produced a gate level netlist, a logic optimizer reads in the netlist and optimizes the circuit for the user-specified area and timing constraints. These area and timing constraints may also be 27

used by the module builder for appropriate selection or generation of RTL blocks. In this book, we assume that the target netlist is at the gate level. The logic gates used in the synthesized netlists are described in Appendix B. The module building and logic optimization phases are not described in this book. The above figure shows the basic elements ofVerilog HDL and the elements used in hardware. A mapping mechanism or a construction mechanism has to be provided that translates the Verilog HDL elements into their corresponding hardware elements as shown in figure.2-3

Fig.2-3 Typical design process

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VLSI & FPGA

2.1 VLSI TECHNOLOGY
Digital systems are highly complex at their most detailed level. They may consist of millions of elements i.e., transistors or logic gates. For many decades, logic schematics served as requisite of logic design, but not any more. Today, hardware complexity has grown to such a degree that a schematic with logic gates is almost useless as it shows only a web of connectivity and not functionality of design. Since the 1970s, computer engineers, electrical engineers and electronics engineers have moved towards Hardware description language (HDLs).

Digital circuit has rapidly evolved over the last twenty five years .The earliest digital circuits were designed with vacuum tubes and transistors. Integrated circuits were then invented where logic gates were placed on a single chip. The first IC chip was small scale integration (SSI) chips where the gate count is small. When technology became sophisticated, designers were able to place circuits with hundreds of gates on a chip. These chips were called MSI chips with advent of LSI, designers could put thousands of gates on a single chip. At this point, design process is getting complicated and designers felt the need to automate these processes.

With the advent of VLSI technology, designers could design single chip with more than hundred thousand gates. Because of the complexity of these circuits computer aided techniques became critical for verification and for designing these digital circuits. One way to lead

with increasing complexity of electronic systems and the increasing time to market is to design at high levels of abstraction. Traditional paper and pencil and capture and simulate methods have largely given way to the described unsynthesized approach.

For these reasons, hardware description languages have played an important role in describe and synthesis design methodology. They are used for specification, simulation and synthesis of an electronic system. This helps to reduce the complexity in designing and products are made to be available in market quickly.

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The components of a digital system can be classified as being specific to an application or as being standard circuits. Standard components are taken from a set that has been used in other systems. MSI components are standard circuits and their use results in a significant reduction in the total cost as compared to the cost of using SSI Circuits. In contrasts, specific components are particular to the system being implemented and are not commonly found among the standard components.

Design Flow:

System specification

Functional design

X=(ABCD+A+D+A(B+C))

Logic design

Y=(A(B+C)+AC+D+A(BC+D))

Circuit design

Physical design

Fabrication

Packaging and testing

Fig 2.1: Steps involving manufacturing of a chip

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2.2 WHAT ARE FPGAs?

FPGA stands for Field Programmable Gate Array. Field Programmable means that the FPGA's function is defined by a user's program rather than by the manufacturer of the device. It can be programmed in a number of different languages.

Definition: Programmable Digital Logic Chips that can be programmed to perform any digital function. 1. The FPGA is an integrated circuit that contains many (64 to10,000)identical logic cells that can be viewed as a standard components. 2. The individual cells are interconnected by a matrix of wires and programmable switches. 3. Speed up to 200 MHz or more.

As their name implies, FPGAs offer significant benefit of being readily programmable. Unlike their forbearers in PLD category, FPGAs can be programmed again and again, giving designers multiple opportunities to tweak their circuits.

2.3 TYPES OF FPGAS:

1. SRAM based:
a. b. Static memory technology. In system programmable and

reprogrammable. c. Requires external boot devices.

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2. FLASH based:
a. b. c. d.
Flash-erase EPROM technology. Can be erased, even in plastic packages. Can be in-system programmed. Does not require power supply to maintain information.

2.3.1 History of FPGAS:

1. The historical roots of FPGAs are in complex programmable logic devices (CPLDs) of the early to mid 1980s.

2.

Field programmable gate arrays (FPGA) arrived in 1984 as an alternative to programmable logic devices (PLDS) and ASICS.

3. A Xilinx co-founder invented the field programmable gate array in 1984. 4. CPLDs and FPGAs include a relatively large number of programmable logic elements.

5.

While the first FPGAs didn't have internal memories, all new FPGAs have internal memories. That increases a lot their scope of applications.

2.4 BASIC FPGA ARCHITECTURE:

FPGAs fill a gap between discrete logic and the smaller PLDs on the low end of the complexity scale and costly custom ASICs on the high end. They consist of an array of logic blocks that are configured using software. Programmable I/O blocks surround these logic blocks. Both are connected by programmable interconnects. The programming technology in an FPGA determines the type of basic logic cell and the interconnect scheme. In turn, the logic cells and interconnection scheme determine the design of the input and output circuits as well as the programming scheme.

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Fig 2.2: Basic FPGA Architecture

Digital Clock Manager (DCM) blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase shifting clock signals. Configurable Logic Blocks (CLBs) contain RAM-based Look-Up Tables (LUTs) to implement logic and storage elements that can be used as flip-flops or latches. CLBs can be programmed to perform a wide variety of logical functions as well as to store data.

Input/output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. The Input/output Block (IOB) provides a programmable, bidirectional interface between an I/O pin and the FPGAs internal logic. Block RAM provides data storage. Multiplier blocks accept two binary numbers as inputs and calculate the product.

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2.5 FPGA DESIGN FLOW:

The process of implementing a design on an FPGA can be broken down in to several stages, loosely definable as design entry or capture, synthesis, and place and route. Along the way, the design is simulated at various levels of abstraction as in ASIC design. The availability of sophisticated and coherent tool suites for FPGA design makes them all the more attractive.

At one time, design entry was performed in the form of schematic capture. Most designers have moved over to hardware description languages (HDLs) for design entry. Some will prefer a mixture of the two techniques. Schematic-based design-capture tools gave designers a great deal of control over the physical placement and partitioning of logic on the device. But its becoming less likely that designers will take that route. Mean while, language based design entry is faster, but often at the expense of performance or density. For many designers, the choice of whether to use schematic-or HDL-based design entry comes down to their conception of their design .For those who think in software or algorithmiclike terms, HDLs are the better choice. HDLs are well suited for highly complex designs, especially when the designer has a good handle on how the logic must be structured. They can also be very useful for designing smaller functions when you havent the time or inclination to work through the actual hardware implementation.

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Fig 2.3: FPGA Design flow On the other hand, HDLs represent a level of abstraction that can isolate designers from the details of the hardware implementation. Schematic-based entry gives designers much more visibility in to the hardware. Its a better method for those who are hardware - oriented. The downside of schematic-based entry is that it makes the design more difficult to modify or port to another FPGA.

A third option for design entry, state-machine entry, works well for designers who can see their logic design as a series of states that the system control, that can be clearly represented in visual formats. Tool support for finite state-machine entry is limited, though.

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After design entry, the design is simulated at the register-transfer level (RTL). This is the first of several simulation stages, because the design must be simulated at successive levels of abstraction as it moves down the chain toward physical implementation on the FPGA itself. RTL simulation offers the highest performance in terms of speed. As a result, designers can perform many simulation runs in an effort to refine the logic. At this stage, FPGA development isnt unlike software development. Signals and variables are observed, procedures and functions traced, and breakpoints set. The good news is that its a very fast simulation. But because the design hasnt yet been synthesized to gate level, properties such as timing and resources usage are still unknowns.

The next step follows RTL simulation is to convert the RTA representation of the design into a bit-stream file that can be loaded onto the FPGA. The interim step is FPGA synthesis, which translates the VHDL or Verilog code into a device net list format that can be understood by a bit-stream converter.

The synthesis process can be broken down into three steps. First step, the HDL code is converted into device netlist format. Then the resulting file is converted into device netlist format. Then the resulting file is converted into a hexadecimal bit-stream file, or bit file. This step is necessary to change the list of required devices and interconnects into hexadecimal bits to download to the FPGA. This final step completes the FPGA synthesis procedure by programming the design onto the physical FPGA.

Its important to fully constrain designs before synthesis. A constrain file is an input to the synthesis process just as the RTL code itself. Constrains can be applied globally or to specific portions of the design. The synthesis engine uses these constrain to optimize the netlist. However, its equally important to not over-constrain the design, which will generally result in less than-optimal results from the next step in the implementation process-physical device placement-and interconnect routing.

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Following synthesis, device implementation begins. After netlist synthesis, the design is automatically converted into the format supported internally by the FPGA vendors place-androute tools. Design-rule checking and optimization is performed on the incoming netlist and the software partitioning is required to achieve high routing completion and high performance. Increasingly, FPGA designers are turning to floor planning after synthesis and design partitioning. FPGA floor planners work from the netlist hierarchy as defined by the RTL coding. Floor planning can help if area is tight. When possible, its a good idea to place critical logic in separate blocks. After partitioning and floorplaning, the placement tool tries to place the logic blocks to achieve efficient routing. The tool monitors routing length and track congestion while placing the blocks. It may also track the absolute path delays to meet the users timing constraints. Overall the process mimics PCB place and route.

Functional simulation is performed after synthesis and before physical implementation. This step ensures correct logic functionality. After implementation, theres a final verification step with full timing information. After placement and routing, the logic and routing delays are back-annotated to the gate-level netlist for this simulation. At this point, simulation is a much longer process, because timing is also a factor. Often, designers substitute static timing simulation. Static timing analysis calculates the timing of combinational paths between registers and compares it again the designers timing constraints.

Once the design is successfully verified and found to meet timing, the final step is to actually program the FPGA itself. At the completion of placement and routing, a binary programming file is created. Its used to configure the device. No matter what the devices underlying technology, the FPGA interconnect fabric has cells that configure it to connect to the inputs and outputs of the logic blocks. In turn, the cells configure that logic to each other. Most programmable-logic technologies, including the PROMs for SRAM-based FPGAs, require some sort of a device programmer. Device can also be programmed through their configuration ports using a set of dedicated pins.

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Modern FPGAs also incorporate a JTAG port that, happily, can be used for more than boundary-scan testing. The JTAG port can be connected to the devices internal SRAM configuration-cell shift registers, which in turn can be instructed to connect to the chips JTAG scan chain.

Integrated flows for FPGAs make sure sense in general, considering that FPGA vendors will continue to introduce more complex, powerful, and economical devices over time. An integrated third-party flow makes it easier to re-target a design to different technologies from different vendors as conditions warrant.

2.6 GENERALVIEW OF FPGA

FPGAs (Field Programmable Gate Arrays) are semiconductor devices containing programmable logic and programmable interconnects. A FPGA is essentially a hardware processing unit that can be reconfigured at runtime. FPGAs evolved out of the older CPLD (Complex Programmable Logic Device) chips. Compared to CPLDs, FPGAs typically contain a much higher number of logic cells. Additionally the architecture of FPGAs includes several level embedded function blocks, such as multipliers and block RAMs. This allows FPGAs to implement much more complicated functions than the older CPLDs.

The speed of a FPGA is generally slower than that of an equivalent ASIC (Application Specific Integrated Circuit) chip, however an ASICs functionality and architectur e are fixed on manufacture, whereas a FPGA can be reconfigured as necessary. This leads to substantially lower development and manufacturing costs, and also allows the final system a greater degree of flexibility.

On a FPGA, algorithms are constructed from blocks of hardware logic, instead of instructions interpreted and executed by a processor. In addition, the architecture of FPGAs 38

allows for the simultaneous, parallel execution of multiple tasks. All these factors mean that certain algorithms can be executed much, much faster on a FPGA than they could on a CPU.

1. The General Workflow When Working With FPGAs:

1. You use a computer to describe a "logic function" that you want. You might draw a schematic, or create a text file describing the function, doesn't matter. 2. You compile the "logic function" on your computer, using software provided by

the FPGA vendor. That creates a binary file that can be downloaded into the FPGA. 3. You connect a cable from your computer to the FPGA, and download the binary file to the FPGA. That's it! FPGA behaves according to our "logic function".

2. It Is Important That:
1. You can download FPGAs as many time as you want - no limit - with different functionalities every time if you want. If you make a mistake in your design, just fix your "logic function", re-compile and re-download it. No PCB, solder or component to change. 2. The designs can run much faster than if you were to design a board with discrete components, since everything runs within the FPGA, on its silicon die. 3. FPGAs loose their functionality when the power goes away (like RAM in a computer that looses its content). You have to re-download them when power goes back up to restore the functionality.

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2.7 FPGAS Vs CPLDS:

1. Both are programmable digital logic chips. Both are made by the same companies. But
they have different characteristics.

2. FPGAs are "fine-grain" devices. That means that they contain a lot (up to 100000) of
tiny blocks of logic with flip-flops. CPLDs are "coarse-grain" devices. They contain relatively few (a few 100's max) large blocks of logic with flip-flops.

3. FPGAs are RAM based. They need to be "downloaded" (configured) at each power-up.
CPLDs are EEPROM based. They are active at power-up (i.e. as long as they've been programmed at least once...).

4. FPGAs have special routing resources to implement efficiently binary counters and
arithmetic functions (adders, comparators...) and RAM. CPLDs do not.

5. FPGAs can contain very large digital designs, while CPLDs can contain small designs
only.

6. CPLD logic gate densities range from the equivalent of several thousand to tens of
thousands of logic gates, while FPGAs typically range from tens of thousands to several million.

7. Another notable difference between CPLDs and FPGAs is the presence in most FPGAs
of higher-level embedded functions (such as adders and multipliers) and embedded memories.

8. Some FPGAs have the capability of partial re-configuration that lets one portion of the
device be re-programmed while other portions continue running.

9. FPGAs are RAM based. 10. CPLDs are EEPROM based. 11. FPGAs can contain very large digital designs, while CPLDs can contain small designs
only. 12. According to the architecture CPLD has less flexibility and FPGA has more flexibility.

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CPLD

FPGA

LOGIC ELEMENTS OPERATING VOLTAGE

UP TO 500

UP TO 2,50,000

5V

3.3V external, 1.5V internal

2.8 HOW FPGAS WORK:

1. Internal logic:
FPGAs are built from one basic "logic-cell", duplicated hundreds or thousands of time. A logic-cell is composed of a small lookup table, some gates and a D-flipflop. Each logic-cell then can be connected to other logic-cells through interconnect resources (wires/muxes placed around the logic-cells).

Each cell can do little, but with so many of them, complex logic functions can be created. The interconnect wires also go to the boundary of the device where I/O cells are implemented and connected to the pins of the FPGAs.

2. Dedicated routing/carry chains:

In addition to general-purpose interconnect resources; FPGAs have fast dedicated lines in between neighboring logic cells.

The most common type of fast dedicated lines are carry chains. Carry chains allow creating arithmetic functions (counters/adders) very efficiently (low logic usage & high operating speed). Older programmable technologies (PAL/CPLD) don't have carry chains and so are quickly limited when arithmetic operations are required.

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3. Internal ram:
While the first FPGAs didn't have internal memories, all new FPGAs have internal memories. That increases a lot their scope of applications. There are many parameters affecting RAM operation. The main parameter is the number of agents that can access the RAM simultaneously. 1. "single-port" RAMs: only one agent can read/write the RAM. 2. "dual-port" or "quad-port" RAMs: 2 or 4 agents can read/write. Great to get data across clock domains (each agent can use a different clock). To figure out how many agents are available, count the number of separate address buses going to the RAM. Each agent has a dedicated address bus. Each agent has also a read, a write, or both data buses. Having both data buses doesn't always mean an agent can read and write simultaneously.

Writing to the RAM is usually done synchronously. Reading is usually also done synchronously but can also sometimes be done asynchronously.

RAM blocks are usually dedicated memory block ("block rams"). Xilinx has a lot of flexibility in the RAM distribution, because it also allows using the logic-cells as tiny RAMs ("distributed RAM"). Altera usually takes another approach and builds different-size block rams around the device

4. FPGA Power:
FPGAs usually require 2 voltages to operate: a "core voltage" and an "IO voltage". Each voltage is provided through separate power pins. 1. The internal core voltage (called VCCINT here for simplicity), is used to power the logic gates and flip-flops inside the FPGA. The voltage can range from 5V for older FPGA generations, to 3.3V, 2.5V, 1.8V, 1.5V and even lower for the latest devices! The core voltage is fixed (set by the model of FPGA that you are using).

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2. The IO voltage (called VCCIO here for simplicity) is used to power the I/O blocks (= pins) of the FPGA. That voltage should match what the other devices connected to the FPGA expect. Actually, FPGA devices themselves don't prevent VCCINT and VCCIO to be the same (i.e. the VCCINT and VCCIO pins could be connected together). But since FPGAs tend to use low-voltage cores, the two voltages are usually different.

5. Applications:
Applications of FPGAs include digital signal processing, software-defined radio, aerospace and defense systems, ASIC prototyping, medical imaging, computer vision, speech recognition, cryptography, bioinformatics, computer hardware emulation and a growing range of other areas.

2.9 ADVANTAGES AND DISADVANTAGES OF FPGA:

Advantages:
1. Most flexible Processor. 2. Easily upgraded. 3. Newest technology. 4. Low cost and low risk. 5. Allow easy design changes.

Disadvantages:
1. Large and fast devices are expensive. 2. These devices are consumes high power. 3. Programmable software relatively slow.

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2.10 HARDWARE DESCRIPTION LANGUAGES:

To configure a FPGA, users first provide a description of the desired functional modules in the form of either a schematic, or hardware description language (HDL).This description is then synthesized to produce a binary file used to configure the FPGA device.

The advantage of using a hardware description language is that it allows the user to both describe and verify the functioning of a system before it is implemented on hardware. HDLs also allow for the succinct description of concurrent systems, with multiple subcomponents all operating at the same time. This is in contrast to standard programming languages, which are designed to be executed sequentially by a CPU. Using a HDL also allows for a more flexible and powerful expression of system behavior than simply connecting components together using a schematic.

Common HDLs used in FPGA design are VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) and Verilog. VHDL developed from the Ada programming language, and has a relatively verbose syntax. In addition, VHDL is both strongly typed and case insensitive. By contrast, Verilog evolved out of the C programming language, and as such is a much more terse language than VHDL. Verilog is also more weakly typed than VHDL, and is case sensitive. The two languages are highly similar in functionality, and both are widely supported by software synthesis tools.

1. Language Features:
1. Signal data types (in, out, bidir, signal-strength ..) 2. Hardware structures (memory, register-files ..) 3. Logic operators (shift, rotation, masking .) 4. Asynchronous structures (set, reset of memories) 5. Parallel or synchronous structures 44

6. Constraints (pin, technology, areas, delays .) 7. Inter-process communications (shared medium, message passing )

I2C Serial Protocol

Serial communication protocols Meant for short distances inside the box Low complexity Low cost Low speed ( a few Mbps at the fastest ) To be discussed: Applications, protocols, tradeoffs, AVR support

What is I2C?

Shorthand for an Inter-integrated circuit bus Developed by Philips Semiconductor for TV sets in the 1980s I2C devices include EEPROMs, thermal sensors, and real-time clocks Used as a control interface to signal processing devices that have separate data interfaces, e.g. RF tuners, video decoders and
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encoders, and audio processors. I2C bus has three speeds:

...............................Slow (under 100 Kbps) ...............................Fast (400 Kbps) ...............................High-speed (3.4 Mbps) I2C v.2.0

Limited to about 10 feet for moderate speeds

I2C Bus Configuration

2-wire serial bus Serial data (SDA) and Serial clock (SCL) Half-duplex, synchronous, multi-master bus No chip select or arbitration logic required Lines pulled high via resistors, pulled down via open-drain drivers (wired-AND)

I2C Protocol

Master sends start condition (S) and controls the clock signal Master sends a unique 7-bit slave device address Master sends read/write bit (R/W) 0 - slave receive, 1 - slave transmit Receiver sends acknowledge bit (ACK) Transmitter (slave or master) transmits 1 byte of data Receiver issues an ACK bit for the byte received Repeat 5 and 6 if more bytes need to be transmitted. a)For write transaction (master transmitting), master issues stop condition (P) after last byte of data. b)For read transaction (master receiving), master does not acknowledge final byte, just issues stop condition (P) to tell the
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slave the transmission is done I2C Signals

Start high-to-low transition of the SDA line while SCL line is high Stop low-to-high transition of the SDA line while SCL line is high Ack receiver pulls SDA low while transmitter allows it to float high Data transition takes place while SCL is slow, valid while SCL is high

I2C Features

Clock stretching when the slave (receiver) needs more time to process a bit, it can pull SCL low. The master waits until the slave has released SCL before sending the next bit. General call broadcast addresses every device on the bus 10-bit extended addressing for new designs. 7-bit addresses all exhausted

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INTRODUCTION to I2C
I2C is an Asynchronous, bidirectional, two wire interface. It is at the low end of the spectrum of communication options for "inside the box" communication and is pronounced as I2C ("eyesquared- see"). The name I2C is shorthand for a standard InterIC (integrated circuit) bus. I2C provides good support for communication with various slow, on-board peripheral devices that are accessed intermittently, while being extremely modest in its hardware resource needs. It is a simple, low-bandwidth, short-distance protocol. Most available I2C devices operate at speeds up to 400Kbps, with some venturing up into the low megahertz range. I2C is easy to use to link multiple devices together since it has a builtin addressing scheme. Philips originally developed I2C for communication between devices inside of a TV set. Examples of simple I2C-compatible devices found in embedded systems include EEPROMs, thermal sensors, and real-time clocks. I2C is also used as a control interface to signal processing devices that have separate, application-specific data interfaces. For instance, it's commonly used in multimedia applications, where typical devices include RF tuners, video decoders and encoders, and audio processors. In all, Philips, National Semiconductor, Siemens, and other manufacturers offer hundreds of I2C-compatible.

Figure 1: I2C has two lines, SDA for data transfer and SCL for clock signals

FEATURES of I2C
Compatible with Philips I2C standard Multi Master, Multi Slave Operation Two-wire interface, to control multiple slave devices Software programmable clock frequency Built in collision detection and Clock Stretching and Wait state generation Multiple data speeds: standard (100 kbps), fast (400 kbps) and high speed (3.4 Mbps). Software programmable acknowledge bit Interrupt or bit-polling driven byte-by-byte data-transfers Arbitration lost interrupt, with automatic transfer cancelation Start/Stop/Repeated Start/Acknowledge generation Start/Stop/Repeated Start detection Bus busy detection Supports 7 and 10bit addressing mode Data broadcast to all slaves (general call, using address b0000000) Operates from a wide range of input clock frequencies Additional devices do not the affect the cost and complexity of the circuit
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 Static synchronous design Fully synthesizable

ARCHITECTURE
Inside the box
I2C is appropriate for interfacing to devices on a single board, and can be stretched across multiple boards inside a closed system, but not much further. An example is a host CPU on a main embedded board, using I2C to communicate with user interface devices located on a separate front panel board. A second example is SDRAM DIMMs, which can feature an I2C EEPROM containing parameters needed to correctly configure a memory controller for that module. I2C is a two-wire serial bus. There's no need for chip select or arbitration logic, making it cheap and simple to implement in hardware. The two I2C signals are serial data (SDA) and serial clock (SCL). Together, these signals make it possible to support serial transmission of 8-bit bytes of data-7-bit device addresses plus control bits-over the twowire serial bus. The device that initiates a transaction on the I2C bus is termed the master. The master normally controls the clock signal. A device being addressed by the master is called a slave. In a bind, an I2C slave can hold off the master in the middle of a transaction using what's called clock stretching (the slave keeps SCL pulled low until it's ready to continue). Most I2C slave devices don't use this feature, but every master should support it. The I2C protocol supports multiple masters, but most system designs include only one. There may be one or more slaves on the bus. Both masters and slaves can receive and transmit data bytes. Each I2C-compatible hardware slave device comes with a predefined device address, the lower bits of which may be configurable at the board level. The master transmits the device address of the intended slave at the beginning of every transaction. Each slave is responsible for monitoring the bus and responding only to its own address. This addressing scheme limits the number of identical slave devices that can exist on an I2C bus without contention, with the limit set by the number of user-configurable address bits (typically two bits, allowing up to four identical devices).

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Communication
As you can see in Figure 2, the master begins the communication by issuing the start condition(S). The master continues by sending a unique 7-bit slave device address, with the most significant bit (MSB) first. The eighth bit after the start, read/not-write (), specifies whether the slave will now receive (0) or to transmit (1) data. This is followed by an ACK bit issued by the receiver, acknowledging receipt of the previous byte. Then the transmitter (slave or master, as indicated by the bit) transmits a byte of data starting with the MSB. At the end of the byte, the receiver (whether master or slave) issues a new ACK bit. This 9-bit pattern is repeated if more bytes need to be transmitted.

In a write transaction (slave receiving), when the master is done transmitting all of the data bytes it wants to send, it monitors the last ACK and then issues the stop condition (P). In a read transaction (slave transmitting), the master does not acknowledge the final byte it receives. This tells the slave that its transmission is done. The master then issues the stop condition.

A simple bus
As we've seen, the I2C signaling protocol provides device addressing, a read/write flag, and a simple acknowledgement mechanism. There are a few more elements to the I 2C protocol, such as general call (broadcast) and 10-bit extended addressing. Beyond that, each device defines its own command interface or address-indexing scheme. Standard I2C devices operate up to 100Kbps, while fast-mode devices operate at up to 400Kbps. A 1998 revision of the I2C specification (v. 2.0) added a high-speed mode running at up to 3.4Mbps. Most of the I2C devices available today support 400Kbps operation. Higherspeed operation may allow I2C to keep up with the rising demand for bandwidth in multimedia and other applications. Most often, the I2C master is the CPU or microcontroller in the system. Some microcontrollers even feature hardware to implement the I2C protocol. You can also build an all-software implementation using a pair of general-purpose I/O pins (single master implementations only).
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Since the I2C master controls transaction timing, the bus protocol doesn't impose any real-time constraints on the CPU beyond those of the application. (This is in contrast with other serial buses that are timeslot-based and, therefore, take their service overhead even when no real communication is taking place.)

The elegance of I2C

I2C offers good support for communication with on-board devices that are accessed on an occasional basis. I2C's competitive advantage over other low-speed short-distance communication schemes is that its cost and complexity don't scale up with the number of devices on the bus. On the other hand, the complexity of the supporting I2C software components can be significantly higher than that of several competing schemes (SPI and MicroWire, to name two) in a very simple configuration. With its built-in addressing scheme and straightforward means to transfer strings of bytes, I2C is an elegant, minimalist solution for modest, "inside the box" communication needs.

Theory of Operation
I2C bus has two lines: a serial data line (SDA) and a serial clock line (SCL). Any data sent from one device to another goes through the SDA line, whereas the SCL line provides the necessary synchronization clock for the data transfer. The devices on an I2C bus are either Masters or Slaves. Only a Master can initiate a data transfer and Slaves respond to the Master. It is possible to have multiple Masters on a common bus, but only one could be active at a time. The SCL clock line is always driven by the master. The figure below shows an I2C bus with a single master and three slaves. Slaves can never initiate a data transfer but they can transfer data over the I2C bus, and that is always controlled by the Master.

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Both SCL and SDA lines are open drain drivers, and are therefore, connected to a positive supply voltage through pull-up resistors. This means the I2C devices can only pull the line low, but they cannot drive it high. When no device is pulling on the line, it will float high through the pull-up resistor. This is why pull-up resistors are important in I2C. The open-drain outputs of I2C devices help to perform the wired-AND function on the bus. Data on the I2C bus can be transferred at a rate up to 100 Kbps (in standard mode), 400 Kbps (in fast mode), or up to 3.4 Mbps (in high-speed mode).

Start and Stop conditions

Prior to any transaction on the bus, a Start condition is issued by the Master device to inform all the slave devices that something is about to be transmitted on the bus. As a result, all connected slave devices will listen to the serial data line for instructions. The Start condition is issued by pulling the SDA line low followed by the SCL line. Once the data transfer is finished, the bus Master sends a Stop condition to inform other devices that it would like to release the bus. The signaling used for a Stop condition is a release of the SCL line followed by a release of the SDA line. Remember that when the lines are released, they float high because of the pull-up resistors. Thus, the Start and Stop sequences mark the beginning and end of a transaction with the slave device. Signaling for Start and Stop conditions

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I2C device addressing

Each device connected to the bus is software addressable by a unique 7-bit or 10-bit address. The use of 10-bit address is not very common. The first byte sent after the Start condition is known as Control byte. The first seven bits of the control byte make up the slave address, whereas the eighth bit (LSB) is a data direction bit (R/W): a zero in the LSB of the first byte indicates that the Master will write information to a selected slave. A one in this position indicates that the Master will read data from the slave. For 7-bit devices, typically the first four bits are fixed, the next three bits are set by hardware address pins (A0, A1, and A2) that allow the user to modify the I2C address allowing up to eight of the same devices to operate on the I2C bus. These pins are held high to VCC or held low to GND. We will discuss more in the circuit section on how to setup the device address on the bus.

The control byte (first byte after the Start condition) holds the slave address. When a control byte is sent, each device in the system compares the first seven receiving bits with its address. If they match, the device considers itself addressed by the master as a slave-receiver or slavetransmitter, depending upon the value of the data direction bit (8th bit). I2C: Reserved addresses.
0000 0000 0000 0000 0000 1111 000 001 010 011 1XX 1XX 1 X X X X X START byte - for slow micros without I2C h/w CBUS address - a different bus protocol Reserved for different bus format Reserved for future purposes Hs-mode master code Reserved for future purposes

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1111 0XX X 10-bit slave addressing

Data transfer
Every byte put on the SDA line must be 8-bits long. The data is sent on the SDA line starting with the most significant bit (MSB) first and the SCL line produces a synchronization clock. The data on the SDA line is considered valid when SCL is high, and therefore the data must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. This is how the timing of each bit works.

Data is valid only during the High condition of SCL. If a slave is not in a position to receive or transmit another complete byte of data until it has performed some other function, for example servicing an internal interrupt, it can hold the SCL line low to force the master into a wait state. Data transfer continues when the slave is ready for another byte of data and releases the clock line, to make it high again. A data transfer is always terminated by a Stop condition generated by the master. However, if a master still wishes to communicate on the bus, it can generate a repeated-Start condition and address another slave without first generating a Stop condition. The main reason that the repeated-start bit exists is in a multi master configuration where the current bus master does not want to release its mastership. Using the repeated start keeps the bus busy so that no other master can grab the bus.

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Typical SDA and SCL signal SDA : Serial Data_ SCL : Serial Clock

I2C basic command sequence:

1. Send the START bit (S). 2. Send the slave address (ADDR). 3. Send the Read(R)-1 / Write (W)-0 bit. 4. Wait for/Send an acknowledge bit (A). 5. Send/Receive the data byte (8 bits) (DATA). 6. Expect/Send acknowledge bit (A). 7. Send the STOP bit (P).

Data Transfer from master to slave

Instruction sequence data from master to slave A master device sends the sequence S ADDR W and then waits for an acknowledge bit (A) from the slave, which the slave, will only generate if its internal address matches the value sent by the master. If this happens, then the master sends DATA and waits for acknowledge (A) from the slave. The master completes the byte transfer by generating a stop bit (P) (or repeated start).

Data transfer from slave to master

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Instruction sequence data from slave to master

A similar process happens when a master reads, from the slave, but in this case, instead of W, R is sent. After the data is transmitted from the slave to the master, the master sends the acknowledge bit (A). If instead the master does not want any more data it must send a not acknowledge which indicates to the slave that it should release the bus. This lets the master send the STOP or repeated START signal.

Architecture of Hardware Implementation

Three transmission speeds: (CLOCK GENERATOR) Normal: 100Kbps Fast: 400Kbps High speed: 3.5Mbps Only 100Kbps and 400Kbps modes are supported directly. Byte Command Controller The Byte Command Controller handles I2C traffic at the byte level. It takes data from the Command Register and translates it into sequences based on the transmission of a single byte. By setting the START, STOP, and READ bit in the Command Register, for example, the Byte Command Controller generates a sequence that results in the generation of a START signal, the reading of a byte from the slave device, and the generation of a

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STOP signal. It does this by dividing each byte operation into separate bit-operations, which are then sent to the Bit Command Controller. Bit Command Controller The Bit Command Controller handles the actual transmission of data and the generation of the levels for START, Repeated START, and STOP signals by controlling the SCL and SDA lines. The Byte Command Controller tells the Bit Command Controller which operation has to be performed. For a single byte read, the Bit Command Controller receives 8 separate read commands. Each bit-operation is divided into 5 pieces (idle and A, B, C, and D), except for a STOP operation which is divided into 4 pieces (idle and A, B, and C). Data IO Shift Register The Data IO Shift Register contains the data associated with the current transfer. During a read action, data is shifted in from the SDA line. After a byte has been read the contents are copied into the Receive Register. During a write action, the Transmit Registers contents are copied into the Data IO Shift Register and are then transmitted onto the SDA line.starting communication? Does the master respects the clock stretching for slow speed slaves and what happens when we select the general address (the reserved broadcast address), and multiple slaves acknowledgment, etc.

BASIC OPERATION
The I2C-bus has two wires, a serial data line (SDL) and a serial clock line (SCL), to carry information between the ICs connected to the bus. Each IC is recognized by a unique address and can operate as either a transmitter or receiver, depending on the function of the specific ICs. The I2C-bus is a multi-master bus. This means that more than one IC which is capable of controlling the bus can be connected to it. data transfers proceed as follows: Case 1: A master IC wants to send data to another IC (slave): 1. Master addresses slave 2. Master sends data to the slave (master is transmitter, slave is receiver) 3. Master terminates the data transfer Case 2: A master IC wants to receive information from another IC (slave): 1. Master addresses slave 2. Master receives data from the slave (master is receiver, slave is transmitter) 3. Master terminates the data transfer Even in case 2, the master IC must generate the timing signals and terminate the data transfer. If two or more masters try to put information simultaneously onto the bus, the first master to issue a "1" when the other issues a "0" will lose the bus arbitration. The clock signals used for arbitration are a synchronized combination of the clocks generated by the bus masters using the wired-AND connection to the SCL line. The master IC is always responsible for generating the clock signals on the I2C-bus. Bus clock signals from a master can only be altered by 1) a slow slave IC which "stretches" the signal by temporarily holding the clock line Low, or 2) by another master IC during arbitration.

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GENERAL CHARACTERISTICS Both SDA and SCL are bi-directional lines which are connected to a positive supply voltage through a pull-up resistor. When the I2C-bus is free, the SDA and SCL lines are both high level. The output stages of I2C interfaces connected to the bus have an open-drain or open-collector to perform the wired-AND function. Data on the I2C-bus can be transferred at a rate up to 100 Kbits/s. The number of interfaces that can be connected to the bus is solely dependent on the limiting bus capacitance of 400 pF.

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