1

CAD for VLSI

Tutorial #12
Timing Analysis
2
The Problem
Problem:
What is the longest (or shortest) path delay through
the combinational logic ?
L
A
T
C
H
E
S
L
A
T
C
H
E
S
combinational
logic with no
loops
clock
3
Timing Models
How is the delay through a gate (or net) measured ?
Timing Models
Unit Delay Model - the delay though any gate is one time unit.
Nets have zero delay.
Fixed Delay Model - Each gate has its own Iixed delay
independent oI circuit structure. Nets have zero delay.
Many other more complex timing models that take into
consideration:
delay may be any value between some minimum and
maximum value
different delays from different gate inputs to output
output loading of the gate
non-ideal input waveforms
delay due to interconnect
logic function of gates IGNORED
4
Example 1 - Unit Delay Model
Using the unit delay model, find the path with the longest
delay in the following circuit of a two bit adder.
s1
s0
co
ci
b1
a1
b0
a0
5
Example 1 - algorithm
Using the unit delay model, find the path with the longest
delay in the following circuit of a two bit adder.
Simple solution suggested:
Use modified BFS :
Every vertice should have a delay variable.
When a vertice is visited -
it`s delay is set to the maximum between it`s previous value
and its ancestor`s delay incremented.
Nodes will enter the queue only after all the edges entering it
have been visited (otherwise the complexity will be poor).
It is identical to (some) levelization.
Complexity is linear (by gates and wires).
6
Example 1 - Unit Delay Model
Using the unit delay model, find the path with the longest
delay in the following circuit of a two bit adder.
s1
s0
co
ci
b1
a1
b0
a0
0
0
0
0
0
7
Example 1 - Unit Delay Model
Using the unit delay model, find the path with the longest
delay in the following circuit of a two bit adder.
s1
s0
co
ci
b1
a1
b0
a0
0
0
0
0
0
1
1
1
1
8
Example 1 - Unit Delay Model
Using the unit delay model, find the path with the longest
delay in the following circuit of a two bit adder.
s1
s0
co
ci
b1
a1
b0
a0
0
0
0
0
0
1
1
1
2
2
1
9
Example 1 - Unit Delay Model
Using the unit delay model, find the path with the longest
delay in the following circuit of a two bit adder.
s1
s0
co
ci
b1
a1
b0
a0
0
0
0
0
0
1
1
1
2
2
1
3
10
Example 1 - Unit Delay Model
Using the unit delay model, find the path with the longest
delay in the following circuit of a two bit adder.
s1
s0
co
ci
b1
a1
b0
a0
0
0
0
0
0
1
1
1
2
2
1
3
4
4
11
Example 1 - Unit Delay Model
Using the unit delay model, find the path with the longest
delay in the following circuit of a two bit adder.
s1
s0
co
ci
b1
a1
b0
a0
0
0
0
0
0
1
1
1
2
2
1
3
4
4
5
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Example 1 - Critical path
The levelization output is the worst arrival time for each
of the internal gates and the outputs.
However it did not find the path with the longest delay.
To find the critical path, we will use back-tracing (linear):
BackTrace ( outputs )

path ];
current longest_delay ( outputs );
while ( is_not_a_sink ( current ) )

add_to_end ( current , path );

current longest_delay ( ancestors ( current ) );
]
]
13
Example 1 - Back-tracing
Using the unit delay model, find the path with the longest
delay in the following circuit of a two bit adder.
s1
s0
co
ci
b1
a1
b0
a0
0
0
0
0
0
1
1
1
2
2
1
3
4
4
5
14
Example 1 - Back-tracing
Using the unit delay model, find the path with the longest
delay in the following circuit of a two bit adder.
s1
s0
co
ci
b1
a1
b0
a0
0
0
0
0
0
1
1
1
2
2
1
3
4
4
5
15
Example 1 - Back-tracing
Using the unit delay model, find the path with the longest
delay in the following circuit of a two bit adder.
s1
s0
co
ci
b1
a1
b0
a0
0
0
0
0
0
1
1
1
2
2
1
3
4
4
5
16
Example 1 - Back-tracing
Using the unit delay model, find the path with the longest
delay in the following circuit of a two bit adder.
s1
s0
co
ci
b1
a1
b0
a0
0
0
0
0
0
1
1
1
2
2
1
3
4
4
5
17
Example 1 - Back-tracing
Using the unit delay model, find the path with the longest
delay in the following circuit of a two bit adder.
s1
s0
co
ci
b1
a1
b0
a0
0
0
0
0
0
1
1
1
2
2
1
3
4
4
5
18
Example 2 - Fixed Delay Model
Using the fixed delay model, find the path with the longest
delay in the following circuit of a two bit adder
s1
s0
co
ci
b1
a1
b0
a0
3
3
7
2
5
5
4
6
6
4
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Example 2 - Fixed Delay Model
The circuit will be converted into a graph:
Internal nodes and outputs are given new names:
s1
s0
co
ci
b1
a1
b0
a0
3
3
7
2
5
5
4
6
6
4
I
H
F
1
D
B
G
A
E
C
B1
A1
B0
A0
C0
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Example 2 - Fixed Delay Model
The circuit will be converted into a graph:
The vertices are the nets.
Edges are the gate connectivity (function).
Edges weight gate delay.
1
I
ci
b1
a1
b0
a0 A
B
C
D
E
F
G
H
7
4
3
3
5
5
2
2
6
6
3
3
5
5
6
6
4
4
7
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Example 2 - Fixed Delay Model
Use same algorithm as in levelizing, but add-up the delays labeled on the
graph edges, instead of just incrementing the level.
Take the latest input transition if more than one option exists.
Again :
In levelization or BFS , no track of path is kept !!!
Critical path can be found by back tracing - gives only one path !!!
Complexity is linear
1
I
ci
b1
a1
b0
a0 A
B
C
D
E
F
G
H
7
4
3
3
5
5
2
2
6
6
3
3
5
5
6
6
4
4
7
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Example 2 - Fixed Delay Model
Use same algorithm as in levelizing, but add-up the delays labeled on the
graph edges, instead of just incrementing the level.
Take the latest input transition if more than one option exists.
Again :
In levelization or BFS , no track of path is kept !!!
Critical path can be found by back tracing - gives only one path !!!
Complexity is linear
1
I
ci
b1
a1
b0
a0 A
B
C
D
E
F
G
H
7
4
3
3
5
5
2
2
6
6
3
3
5
5
6
6
4
4
7
4
3
5
2
7
10
12
18
16
23
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Path Enumeration
Usually it important to look at the complete path and not
just at the critical delay. (If we wish to modify that path).
The back-tracing described earlier yields the critical path,
but gives no information of other bad (maybe slightly better)
paths (that might be overlapping).
The DFS traversal keeps track of the path as it traverses the
graph - suitable for detecting the worst paths.
All problematic paths can be stored for analysis as the graph
traversal proceeds.
Problem : The number of paths can be exponential !
We need a method of visiting the paths in a ~smart order -
try and visit critical paths first.
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Exercise 1
Problem:
Given a DAG (which represents a circuit) generate a list of K
longest paths in a non-increasing order of their delays.
Remarks:
Vertices with in-degree (out-degree) equal to zero are the
starting (ending) vertices.
Assume that the weight of the vertex is zero, and the weight
of each edge corresponds to the summation of the delay of the
component and of the connection.
(as we did in the fixed delay model example).
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Exercise 1
For the following circuit, find the 4 paths with the
longest delays.
s1
s0
co
ci
b1
a1
b0
a0
3
3
7
2
5
5
4
6
6
4
I
H
F
1
D
B
G
A
E
C
B1
A1
B0
A0
C0
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The Algorithm
A. Add a source node.
Create a new node, labeled S.
Connect it with zero weight edges to the 'real sources.
B. Add the sink node.
Create a new node, labeled T.
Connect it with zero weight edges to the 'real sinks.
(*) Steps A and B mainly simpliIy the boundary conditions.
C. Compute max delay to sink Ior each node.
This is actually the previously seen - BFS Ior Iixed delay
model, only it`s going backwards Irom the sink to the source.
D. Enumerate paths.
Run a version oI DFS scanning only the critical paths.
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Notations
Denoting paths and delays
All paths have the form < sv
0
, v
1
, v
2
, ... v
n
, v
n+1
t >
< v
i
, v
i+1
> for 0 < i < n are directed edges of the graph
P < v
0
, v
1
, v
2
, ... v
j
> is a full path if v
0
s and v
j
t
P < v
0
, v
1
, v
2
, ... v
j
> is a partial path if v
0
! s or v
j
! t
The delay of a path P , D(P) D(< v
0
, v
1
, v
2
, ... v
j
> ) is :
ij
d(< v
i
, v
i+1
> ) where d(< v
i
, v
i+1
> ) is the delay of (< v
i
, v
i+1
> )
i0
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Exercise 1 - Computing Max- Delays
For each of the nodes in the graph, compute the max delay to
sink for each node.
1
I
ci
b1
a1
b0
a0 A
B
C
D
E
F
G
H
Max delay to the sink node:
Run BFS from T to S traversing the edges backwards.
The summation of the delays remains the same.
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4
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3
3
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5
2
2
6
6
3
3
5
5
6
6
4
4
7
s t
0
0
0
0
0
0
0
0
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Exercise 1 - Computing Max- Delays
For each of the nodes in the graph, compute the max delay to
sink for each node.
1
I
ci
b1
a1
b0
a0 A
B
C
D
E
F
G
H
Max delay to the sink node:
Run BFS from T to S traversing the edges backwards.
The summation of the delays remains the same.
7
4
4
3
3
5
5
2
2
6
6
3
3
5
5
6
6
4
4
7
s t
0
0
0
0
0
0
0
0
0
0
0
7
11
16
19
16
23
23
11
7
16
16
19
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Exercise 1 - Enumerating the Paths
For all nodes, order the successors of the nodes in descending
order of max_delay (max delay from the sink).
Starting at s, visit successors of s in the above order.
For each successor v of s evaluate the max_path_delay of
<s,t> through v using :
max_path_delay of < s , t > through v
d( < s , v > ) + max_delay < v , t >
for the four longest max_path_delay enter the respective
partial paths < s , v > in the table.
For each of the K paths (starting at the max) -
visit successors of the path (one node) and compute it`s
max_path_delay.
Keep the top K (K DFS path stacks).
Continue until all K paths have reached t.
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Exercise 1 - Enumerating the Paths
0
0
0
0
path delay
16 s, a1 ~
19 s, ci ~
23 s, b0 ~
23 s, a0 ~
Max path delay path
1
I
ci
b1
a1
b0
a0 A
B
C
D
E
F
G
H
7
4
4
3
3
5
5
2
2
6
6
3
3
5
5
6
6
4
4
7
s t
0
0
0
0
0
0
0
0
0
0
7
11
16
19
16
23
23
11
7
16
16
19
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Exercise 1 - Enumerating the Paths
3
3
4
4
path delay
19 s, a0, C ~
19 s, ci, E ~
23 s, b0, A ~
23 s, a0, A ~
Max path delay path
1
I
ci
b1
a1
b0
a0 A
B
C
D
E
F
G
H
7
4
4
3
3
5
5
2
2
6
6
3
3
5
5
6
6
4
4
7
s t
0
0
0
0
0
0
0
0
0
0
7
11
16
19
16
23
23
11
7
16
16
19
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Exercise 1 - Enumerating the Paths
8
8
7
7
path delay
19 s, a0, C, G ~
19 s, ci, E, G ~
23 s, b0, A, E ~
23 s, a0, A, E ~
Max path delay path
1
I
ci
b1
a1
b0
a0 A
B
C
D
E
F
G
H
7
4
4
3
3
5
5
2
2
6
6
3
3
5
5
6
6
4
4
7
s t
0
0
0
0
0
0
0
0
0
0
7
11
16
19
16
23
23
11
7
16
16
19
34
Exercise 1 - Enumerating the Paths
12
12
12
12
path delay
19 s, a0, C, G, I ~
19 s, ci, E, G, I ~
23 s, b0, A, E, G ~
23 s, a0, A, E, G ~
Max path delay path
1
I
ci
b1
a1
b0
a0 A
B
C
D
E
F
G
H
7
4
4
3
3
5
5
2
2
6
6
3
3
5
5
6
6
4
4
7
s t
0
0
0
0
0
0
0
0
0
0
7
11
16
19
16
23
23
11
7
16
16
19
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Exercise 1 - Enumerating the Paths
19
19
16
16
path delay
19 s, a0, C, G, I, J ~
19 s, ci, E, G, I, J ~
23 s, b0, A, E, G, I ~
23 s, a0, A, E, G, I ~
Max path delay path
1
I
ci
b1
a1
b0
a0 A
B
C
D
E
F
G
H
7
4
4
3
3
5
5
2
2
6
6
3
3
5
5
6
6
4
4
7
s t
0
0
0
0
0
0
0
0
0
0
7
11
16
19
16
23
23
11
7
16
16
19
36
Exercise 1 - Enumerating the Paths
19
19
23
23
path delay
19 s, a0, C, G, I, J, t ~
19 s, ci, E, G, I, J, t ~
23 s, b0, A, E, G, I, J ~
23 s, a0, A, E, G, I, J ~
Max path delay path
1
I
ci
b1
a1
b0
a0 A
B
C
D
E
F
G
H
7
4
4
3
3
5
5
2
2
6
6
3
3
5
5
6
6
4
4
7
s t
0
0
0
0
0
0
0
0
0
0
7
11
16
19
16
23
23
11
7
16
16
19
37
Exercise 1 - Enumerating the Paths
19
19
23
23
path delay
19 s, a0, C, G, I, J, t ~
19 s, ci, E, G, I, J, t ~
23 s, b0, A, E, G, I, J, t ~
23 s, a0, A, E, G, I, J, t ~
Max path delay path
1
I
ci
b1
a1
b0
a0 A
B
C
D
E
F
G
H
7
4
4
3
3
5
5
2
2
6
6
3
3
5
5
6
6
4
4
7
s t
0
0
0
0
0
0
0
0
0
0
7
11
16
19
16
23
23
11
7
16
16
19
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Exercise 1 - Remarks
The process terminates when the table includes 4 full paths
and it is known that no longer paths exist.
The max_path_delay of a full path is the actual path delay
the max_delay of a node is used to avoid traversing the
complete graph.
Many parts of the graph need not be visited as the
max_delay of the nodes can indicate that the paths have
shorter delays than the ones in the table.
Due to various clocking schemes, clock skews (intentional or
not), latch transparencies and time borrowing -
We usually have different arrival times for the inputs and
required times for the outputs.
The longest path is now relative - usualy measured in slacks.
This complicates the algorithms.