COREEL TECHNOLOGIES

HEP-1 Laboratory Manual

Version 0.1
CoreEL University Program Team

2010

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Documentation on HEP-1.
1. Open a terminal and browse to any of the location. 2. Open a C-shell and invoke DAIC following the below commands cd /home/software/practice/my_inverter csh source /home/software/cshrc/ams.cshrc da_ic & 3. Open the palette moving to MGC Setup Show Palette

4. On the Palette click on

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Session

schematic

5. Now click on enter schematic name you required /home/software/practice/my_inverter

6. Click on the worksheet and select the following options from the palette Library Device Library

7. Add a 4-pin PMOS and NMOS from the device lib. 8. Connect the PMOS and NMOS as shown in the figure below to connect from one node to another node select w to select wire. 9. Click on back tab on device lib palette. Select generic lib and add a input port and output port by selecting the portin and portout tabs. 10. Select the input NET, and right click the mouse button and select Name Nets:.Change the net names. 11. Change the properties of transistors by selecting the transistor and pressing Q. Change the ASIM_Model from NCH to N for NMOS & PCH to P for PMOS 12. Change the W & L values of the Transistors to For PMOS : L 2u; W 9u For NMOS : L 2u; W 9u

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12. Go to Miscellanious Generate Symbol 13. Select Replace existing & activate symbol options 14. Click Ok. Symbol gets generated for you. Change the shape of symbol if required. Save the symbol.

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Test Bench Creation 1. Close all schematics & symbols. 2. Create a new schematic inv_test by selecting new schematic from session. 3. Add symbol of the schematic made. Add Instance Choose Symbol.

4. Add a Pulse Source at the input to inverter and a DC Voltage source VDD port. And do the necessary connections. Connect ground symbol from generic library (LIBRARY Generic Library) to VSS. ** (from sources library we can pick various sources) 5. Right click on the Pulse Generator Source and select Properties Modify Multiple.

6. Change the values of the below mentioned parameters and apply the changes. Once you change the values that have to be reflected once you click on OK tab. Initial = 0V Fall = 1nS Pulse = 5V Width = 25nS Delay = 1nS Period = 50ns. Rise = 1nS

7. Also change the magnitude of the Voltage Source from 1V to 5V by following the below step. 8. Right Click on the Voltage source adjacent to VDD and then Properties Modify Multiple

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8. Now from the menu bar click on check and save button. This will report if any errors present. 9. Now click on back tab and then select Simulation from the palette to run the simulation and select ok. 10. Select a New configuration (Give a new name for simulation). 11. Now select the Session tab simulator/viewer from Setup on the palette and ensure that the following options are set. Simulator Eldo and Viewer EZwave and then Ok.

12. Select Lib/Temp/Inc Libraries and provide the following path by selecting the browse button. $ADK/technology/ic/models/ami05.mod. 13. Select Analyses Transient. Give the Start and Stop Time.

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14. Select the input path A and then hold CTRL key and then output path Y and click on Wave Outputs Save Selected from the palette. Select Voltage from the Popup, click Ok and then a Setup Difference Plot window opens where you select the plot type as individual and click on Ok.

15. Now click on Run Eldo tab from the palette where it opens 2 windows showing various steps running in command line. Once it finishes it will invoke the EZWave waveform viewer. If it is not invoked Click on the View Waves Tab from the palette to invoke the EZWave Waveform Viewer. 16. Now the EZWave displays the input and output signals. 17. Here if you go and explore the folders and search for spi file in the simulation folder inside test bench folder. It will be something like the below path /home/student/practice/inverter_test/simulation_name/inverter.spi This .spi file will be used at post layout simulation

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Inverter Layout Generation Before Layout generation, change the ASIM_Model of PMOS from P to PMOS and NMOS from N to NMOS in inverter schematic. Invoke the IC station tool by typing the following command Now choose the create option from the palette. Select DA_IC connectivity. ComponentProcess to the path of inverter schematic Cell name name of inverter schematic ic & on command prompt

$ADK/technology/ic/process/ami05

Rules $ADK/technology/ic/process/ami05.rules

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Set Grid to 0.5. Other Window Set Grid X: 0.5 Y 0.5

Snap Grid Coordinates Setup SDL

In Componet Subtype change model to asim _model Choose SDL parts, then OK.

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Select PMOS in schematic. Go to Place Inst in Palate.

This will place transistor in Layout view. Similarly do for NMOS and ports.

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Select POLY for Layer Palate and connect the two gates of Transistors. Easy Edit Shape

Similarly connect the Drain of PMOS and Drain of NMOS with Metal-1. Extend the Metal-1 layer that connects drains with IRoute option Route IRoute the after extending a layer of metal from M-1 layer that connects drains & press

Shift +V which adds a via on which the port has to be placed. Draw a square of 5X5 at POLY layer connecting two gates. At 1.5 distance from sides of square

draw a square with CONTACT TO PLOY as an inner square to POLY. Now connect input pin to Via drawn with Metal 1 layer using IRoute method.

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Connect VDD to Source of PMOS and VSS to Source of NMOS using M1 layer. Easy Edit shape (M1 from Layer palate).

Draw M1 layer above PMOS & below NMOS to keep NWELL and PSUB contacts. Add Cell

Go to $ADK/technology/ic/process/ami05_via Add Pwell_contact at M1 layer below NMOS Add Nwell_contact at M1 layer above PMOS

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DRC Checking DRC check using Calibre: First we have to generate GDS2 file: Translate Write GDSII Give the path where it has to be saved. Go to Write Options. Check Replace Existing GDSII File & Add Text on Ports.

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Calibre

Run DRC

Give details as Rules: $ADK/technology/ic/process/ami05.rules DRC Run Directory: your directory Inputs: To the gds2 file UnCheck Export from layout Viewer Format : GDSII Run DRC: It will report with no results when the design is error free.

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Layout versus Schematic: Calibre Run LVS

Give details as Rules: $ADK/technology/ic/process/ami05.calibre.rules DRC Run Directory: your directory Inputs: Inputs SPICE layout netlist GDSII file Format: GDSII inverter.spi (in your simulation directory of testbench); Format:

UnCheck Export from layout Viewer & Export from schematic Viewer Format: SPICE Run LVS

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Parasitic Extraction Calibre Run PEX

Give details as Rules: $ADK/technology/ic/process/ami05.calibre.rules DRC Run Directory: your directory Inputs: Inputs layout netlist GDSII file ;Format : GDSII inverter.spi in your simulation directory; Format: SPICE

UnCheck Export from layout Viewer & Export from schematic Viewer Outputs: Netlist Used Names for Format= DSPF Schematic

Select only R+C instead of R+C+C Run LVS It will generate a Pex Netlist file has to be used in post layout simulation

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POST LAYOUT SIMULATION Open your Test Bench: Descend into your schematic and change the Asim_model of PMOS to P and NMOS to N Check and Save. Simulate your Test Bench. In Simulation Window on top palette, Parasitic Add DSPF

Go to the directory to find inverter.pex (inverter.pex.netlsit) Select RC. OK Now Simulate with Eldo. You can Add & Remove DSPF in Parasitic which show results with & without Parasitic.

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