The Effect of Non-linearity PFD on Reference Spur Levels in PLL

Swapna Patil, Shoeb Ismail Shaikh Department of Electronics and Telecommunication Engineering, VIVA Institute of Technology , Virar(E), Mumbai University Swapna80patil@gmail.com Department of Electronics and Telecommunication Engineering, Saraswati college of engineering, Mumbai University Shoebshaikh_i2i@yahoo.com

ABSTRACT
Phase Lock Loop (PLL) is an important model used in various communication applications such as frequency synthesizer, radio, computer, clock generation, clock recovery, global positioning system, etc. .it is integral part of digital system used in telecommunication. The Simulating these modules is very time consuming. Therefore, a number of approaches to evaluate the performance of these modules through high level behavioral modeling are developed. In this paper, the effect of Phase/Frequency Detector (PFD) non-nonlinearity in PLL behavioral model to estimate the periodic noise, which is also known as reference spurs levels is introduced. The proposed model was implemented in Simulink

Keywords
Simulink, Charge pump PLL, spurs

A Phase Locked Loop is a feedback control circuit. As the name suggests, the phase locked loop operates by trying to lock to the phase of a very accurate input signal through the use of its negative feedback path. A basic form of a PLL consists of three fundamental functional blocks namely Phase Detector (PD), Loop Filter (LF), Voltage Controlled Oscillator (VCO).The block diagram of PLL is shown in the figure 1.The different types of PLL can broadly categories as Analog PLL, Digital PLL and Hybrid PLL. PLLs have several unique characteristics when viewed from a control systems perspective. First of all their correct operation depends on the fact that they are nonlinear. The loop does not exist without the presence of two nonlinear devices, namely the phase-detector and VCO[3].
PFD Charge pump Loop filter VCO

1.INTRODUCTION
Phase locked loop is an excellent research topic as it covers many disciplines of electrical engineering such as Communication Theory, Control Theory, Signal Analysis, Noise Characterization, Design with transistors and opAmps, Digital Circuit design and non-linear circuit analysis. Later on with the development of integrated circuits, it found uses in many other applications. The first PLL ICs came in existence around 1965, and was built using purely analog devices. Recent advances in integrated circuit design techniques have led to an increased use of the PLL as it has become more economical and reliable. Now a whole PLL circuit can be integrated as a part of a larger circuit on a single Chip i.e SoC[1][9][13][14]. MATLAB Simulink[12][15][16]is effective tool to get prior idea about PLL parameters, its performance to fulfill requirements before actual chip design. Phase Locked Loops are used in almost every communication system. Some of its uses include recovering clock from digital data signals[3], performing frequency, phase modulation and demodulation, recovering the carrier from satellite transmission signals and as a frequency synthesizer[2]. There are many designs in communication that require frequency synthesizer to generate a range of frequencies; such as cordless telephones, mobile radios and other wireless products. The accuracy of the required frequencies is very important in these designs as the performance is based on this parameter [1] [13] [4].

Divider N Figure 1. The block diagram of Charge pump PLL

The PLL performance is based on the noise seen at its output. There are two types of noise, random noise and periodic noise. Random noise is also known as phase noise, while periodic noise is called reference noise, which at a specified offset frequency from a carrier frequency. The Reference spurs are a serious issue in communication. A spur can degrade the signal-to-noiseratio in data reception and transmission. This spur is caused by non-linear ties in the PFD and charge pump circuits[8]. Here the non-nonlinearity in PFD are discussed in Section I Many research are going on to eliminate or minimize the non-nonlinearity in these circuits to minimize the reference spurs [2][5]. In Section 2, the reference spurs and its sources are discussed, in Section 3 the PLL linear model and its implementation in Simulink are discussed in 4.

2. SOURCES OF REFERENCE SPURS

The main contributions to the reference spurs in PLL are PFD delay, charge pump switching delay, charge pump current leakage, charge pump current mismatch, charge

injection and charge sharing [6], [7]. Figure 2 shows commonly used PFD circuits in PLL design and charge pump circuit .

The VCO was modeled using a continuous time VCO block running at quiescent frequency 450 MHz with a 166.48 MHz/V gain. The VCO output is divided by 10 using a frequency divider, then feed to the second input of the PFD. A 450 MHz signal was used as a reference frequency. This simulation results obtained using matlab2012, version 8.0.0.783

Figure. 3. PLL Simulink model Figure 2. Phase/Frequency Detector (PFD) and charge pump circuits

The two PFD output signals, labeled as UP and DOWN signal in the diagram, control the charge pump switching. The UP switch is using a PMOS, while the DOWN switch is using an NMOS. An equal amount of delay on both these signals is needed to eliminate dead zone problem. So, the PFD delay itself does not contribute to reference spurs. On the other hand, a differential delay between these signals introduce reference spurs, as this will cause either the Iup or Idn to be on for a longer period of time. When UP and DOWN switches in charge pump are OFF, there should be zero net current flow to the filter circuit. However, there is still a very small current due to leakage current in the UP and DOWN transistors of the CP circuit. The amount of this current depends on the used technology Ideally, Iup should equal Idn in a charge pump However, because of the process variation and channel length modulation effect on the current mirror structures, Iup and Idn are slightly different. This mismatch can be as large as 10%-20% between these currents, depending on the current source structure, transistor sizes and used fabrication technology.

Figure: 4 PFD with internal delay

4. MODELLING RESULTS
The reference spurs level was measured from the Simulink model simulation and was compared to reference spurs levels measured from ideal PLL model without delay , as shown in Figure 5.The simulated output obtained on FFT Spectrum scope.

3. PLL MODEL
The developed PLL Simulink model is shown in Figure 3.and figure 4 ie charge pump PLL with transport delay of 10e-6 sec between PFD and charge pump circuit which introduced non-nonlinearity in PLL.

5. CONCULSION AND DISSCUSSION

Simulink model of PLL has been developed. The model allows the investigation of PFD delay, charge pump current mismatch effects on the reference spur level .Due to this non-linearity the spurs levels are get doubled. These non-linearity are very important consideration of PLL design.[10][11]

6. REFERENCES
[1] A. B. Grebene, The monolithic phase-locked loop - a versatile building block, IEEE Spectrum, vol. 8, pp.38-49, March 1971. [2] B. Razavi , Monolithic Phase-Locked Loops and Clock Recovery Circuits, IEEE 2003. Figure: 5 Spectrum output for PLL system without delay [3] Gursharan Reehal, A Digital Frequency Synthesizer Using Phase Locked Loop Technique 1998 [4] F. M. Gardner, Charge-Pump Phase-Lock Loops , IEEE Trans. On Communications, vol. 28, pp. 1849-1858, November 1980. [5] F.M Gardner, Phase lock Techniques , 2nd ed., John-Wiley & Sons, Inc., NY, 1979. [6] K. H. Cheng, W. B. Yang, and C. M. Ying ,A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loop , IEEE Trans. Circuit and System II, vol. 50, pp. 892-896, Nov. 2003. [7] Liu yu-zhen, Design of phase-Locked loop based on SIMULINK, Liaoning Technical Universitys Transaction,vo. 23, no. 2, pp. 236237, 2004. [8] Noorfazila Kamal, Said Al-Sarawi, Neil H. E. Weste and Derek Abbott A Phase-Locked Loop Reference Spur Modelling using Simulinkinternational conference in electronic devices and application,pp279-283,2010 [9] P.E. Allen ,PLL Design Equations & PLL Measurement ECE 6440 - Frequency Synthesizers Figure: 6 Spectrum output for PLL system with delay [10] R. E. Best, Phase-Locked Loops: Theory, Design and Applications. New York McGraw-Hill, 1984 [11] R.E. Best, Phase-Locked Loops: Design, Simulation, and Applications, 4th edition, McGraw-Hill, 1999 (4th edition) [12] ]T. A. Telba and Abdulhameed Al-MazrooA , Wideband Low Jitter Frequency Synthesizer Modeling and Simulation, IJCSNS International Journal of Computer Science and Network Security, VOL.10 No.1, January 2010 [13] ] Ms. Ujwala A. Belorkar and Dr. S.A.Ladhake , Dssign of loe power phase Locked Loop (PLL) using 45NM VLSI TECHNOLOGY,International journal of VLSI design & Communication Systems ( LSICS ), Vol.1, No.2, June 2010 [14] F. You, and S. He, Analysis of Third-order Charge Pump PLLs,IEEE conf., 2004, pp. 1372-1376 [15] A.Carlosena, A.M. Lazaro, A Novel Design Method for Phased-Locked Loops of any Order and Type, IEEE conf., 2006, pp. 569-573.

From figure 6 it was clear that due to the non- nonlinearity in PDF the PLL system performance will get affected which results in increasing spurs levels in outputs. The comparative study for spurs level is given in table 1.
Table 1: Comparative study in spurs levels Model PLL without delay PLL with delay No of spurs levels 3 6

[16] Yunfei Ye ,Ming Zhang Analysis and Simulation Three Order Charge Pump Phase Locked Loop 978-1-42442108-4/08/$25.00 2008 IEEE