Zafar Takhirov

Department of Electrical and Computer Engineering, Boston University 8 St Marys St, PHO 340, Boston, MA 02215 Email: zafar@bu.edu, Phone: 857-247-6589 http://people.bu.edu/zafar/ Education Boston University Boston University Russian-Tajik University

Department of ECE Department of ECE Department of Linguistics

Ph.D., 2012 - present M.S., 2012 (GPA: 3.5) Specialist, 2008 (GPA: 4.0)

Research Experience Fault-tolerant CMOS Circuits Developed a novel feedback equalization with Schmitt Trigger (FEST) circuit to mitigate timing errors and lower energy for standard digital CMOS logic operating in the moderate inversion region. Designed a 4-bit 3-tap FIR lter that uses the FEST circuit for error mitigation. The use of FEST circuit enabled further scaling of supply voltage and 40% more savings in energy while maintaining lter performance. Exploring the application of feedback equalization techniques for error mitigation and energy reduction in pass-transistor logic. Wave-pipelined Equalized Interconnect Circuit Designed a 10 mm long capacitively driven wave-pipelined equalized interconnect having FIR/IIR-based transceiver. Designed bit interleaved SerDes, random number generator and nite state machine as support circuits for measurement. Taped-out design with UMC 0.13 m technology. Chip currently under measurement. Target throughput is 6 Gbps and target energy consumption is 300 fJ/bit. Publications A. Joshi, C. Chen, Z. Takhirov, B. Nazer, A Multi-Layer Approach to Green Computing: Designing Energy-Efcient Digital Circuits and Manycore Architectures, Proc. Workshop on Lighter-than-Green Dependable Multicore Architectures (LGDMA). Held in conjunction with International Green Computing Conference (IGCC), 2012 (Invited Paper). Z. Takhirov, B. Nazer and A. Joshi, Error Mitigation in Digital Logic using Feedback Equalization with Schmitt Trigger (FEST) Circuit, Proc. IEEE International Symposium on Quality Electronic Design (ISQED), March 2012. Z. Takhirov, B. Nazer and A. Joshi, A Preliminary Look at Error Avoidance in Digital Logic Via Feedback Equalization, in Proc. Allerton-11, September 2011. (Invited Paper). Skills Programming languages: C/C++, Assembly (MIPS), Perl, Python, Verilog HDL, SPICE, MATLAB/Octave.

 Applications/Tools: Xilinx ISE, Altium ISE, Cadence Virtuoso, Cadence Encounter, HSPICE, Spectre, ModelSim, ChipScope. Natural Languages: English, Tajik, German, Russian, Turkish, Persian(Dari) Teaching Experience Teaching Fellow for Logic Design course (09/2010 to 12/2012): Taught 100 students the basics of digital logic design, Verilog programming, as well as supervised nal projects. Teaching Fellow for Computer Architecture course (09/2012 to 12/2012): Taught 45 students RISC architecture, microprocessor design (pipelining, multi-cycle execution, instruction set design) design-for-test, as well as microprocessor test automation. Other Projects Hardware Background Subtraction: Implemented image background subtraction algorithm on Xilinx Spartan 6 chip (using Verilog HDL). Two step process was developed: dynamic background detection and background subtraction. Handwriting Calculator: using Verilog HDL a hardware ANN was developed and trained to recognize handwritten digits. Microstrip PCB 1-GHz Receiver/Transmitter: Designed using Altium ISE. Design included HF PLL synthesizer, patch antenae, RF power amplier. Testing performed using Agilent intrumentation (oscilloscope, spectrum/network/logic analyzers).