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Microelectronics Journal

Microelectronics Journal 32 (2001) 733747 www.elsevier.com/locate/mejo

On-chip ESD protection design for integrated circuits: an overview for IC designers
A.Z. Wang*, H.G. Feng, K. Gong, R.Y. Zhan, J. Stine
Integrated Electronics Laboratory, Department of Electrical and Computer Engineering, Illinois Institute of Technology, 3301 S. Dearborn Street, Chicago, IL 60616, USA Received 14 March 2001; accepted 31 May 2001

Abstract This tutorial paper reviews the state of knowledge of on-chip ESD (electrostatic discharging) protection circuit design for integrated circuits. The discussion covers critical issues in ESD protection design, i.e. ESD test models, ESD failure mechanisms, ESD protection structures, ESD device modeling, ESD simulation, ESD layout issues, and ESD-to-circuit interactions, etc. This review serves to provide practical IC designers with a thorough and heady reference in dealing with complex ESD protection design for integrated circuits. q 2001 Published by Elsevier Science Ltd.
Keywords: Electrostatic discharging; Integrated circuits; ESD; HDM; MM; CDM

1. Introduction One of the most pervasive reliability problems facing the IC industry is the ESD (electrostatic discharging) failure. It is reported that up to 35% of total IC eld failures are ESDinduced, with estimated annual costs to the IC industry running to several billion dollars [1,2]. Dedicated on-chip ESD protection structures are commonly used to protect IC parts from being damaged by ESD stresses [35]. Active research on ESD fundamentals and protection has been going on for over two decades. While signicant progresses have been made in the eld of ESD protection, many important issues remain unresolved, for example, latent ESD failure mechanisms, accurate ESD device modeling and predictive ESD CAD design verication, to name a few. Further, as IC technologies continue to advance at a stunning pace, new problems continuously emerge in ESD protection design for very deep sub-micron (VDSM) IC applications. It is therefore believed that ESD protection design will become a major IC design challenge down the road of semiconductor IC technology advancement [6]. It is hence imperative for IC designers to acquire adequate knowledge on ESD protection design and to maintain on the front page of the new development in the eld. This tutorial paper means to address such a critical need among IC designers.
* Corresponding author. Tel.: 11-312-567-6912; fax: 11-312-567-8976. E-mail address: awang@ece.iit.edu (A.Z. Wang). 0026-2692/01/$ - see front matter q 2001 Published by Elsevier Science Ltd. PII: S 0026-269 2(01)00060-X

2. ESD test models ESD is an extremely fast discharging phenomenon, with a typical duration of ,150 ns, occurring when two charged objects are brought into proximity and electrostatic charges transfer in between [4]. The resulting high current (up to a few tens of Amps) and high voltage (up to several tens of kV) transients may damage or degrade IC parts. ESD events can be simulated by different ESD test models categorized according to its origins, upon which on-chip ESD protection circuits are tested and rated. 2.1. HBM model Human body model (HBM) [7,8] simulates ESD events that occur when a charged human body contacts an electronic device directly. HBM circuit model is shown in Fig. 1, where a CESD ( 100 pF) is charged up and then discharges through an RESD ( 1500 V) and LESD ( < 7.5 mH) network to the device under test (DUT). Fig. 2 shows its discharging current waveform. HBM is the most reproducible ESD model that remains the most widely accepted industrial standard currently. 2.2. MM model Machine model (MM) [9,10] describes an ESD pulsing event, where charged machinery discharges when touching IC parts during automatic testing. MM circuit model is

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Fig. 1. A HBM ESD model circuit, where the RLC network reecting normal human body effect [7].

similar to HBM model, however with different parameters: C ESD 200 pF and negligible RESD and LESD, and produces an oscillatory discharging waveform, as shown in Fig. 3, with a higher peak current, Ipeak, and shorter rise time (tr , ns). 2.3. CDM model Charged-device model (CDM) [1113] simulates selfinduced discharging of devices where un-grounded electronic parts are charged up during manufacturing or assembly and then discharge through a ground-pin. Figs. 4 and 5 show its circuit model and typical discharge waveform, respectively, featuring very short rise time, tr (,1 ns), and very high current vales, Ipeak. 2.4. IEC model IEC (International Electrotechnical Commission) model [14] circuit, as illustrated in Fig. 6 with typical current waveform shown in Fig. 7, produces extremely short rise time, tr (#1 ns), and very high current peaks, Ipeak (up to a few tens of Amps), due to its very low R and zero-L. IEC was initially developed as a system ESD model. However, it is being used for IC chip ESD characterization recently to reect tougher ESD protection demands. The sub-ns rise

Fig. 3. Typical MM ESD discharging waveforms (discharge level ,400 V) show oscillatory features caused by varying machine-induced inductances [10].

time ESD pulse property makes IEC ESD protection design very challenging in practical IC design. 2.5. ESD zapping The differences among the above ESD models stem from their model circuit parameters as summarized in Table 1. ESD protection performance is classied by conducting stressing tests where IC chips are stressed by ESD zapping testers, using the above ESD testing models, step-wisely until damage occurs. All the above ESD test models are destructive that provides no insights into the failure mechanisms, highly desired to optimize ESD design performance. 2.6. TLP model The TLP model (transmission line pulse) [15], unlike the above black-box type models, delivers more useful information by stressing IC parts with short square waveforms of varying heights, periods and rise times. TLP tester can probe instantaneous I V curve of a DUT under ESD stress that provides insights into the ESD failure mechanisms. TLP model circuit is shown in Fig. 8 where a transmission line

Fig. 2. A typical HBM ESD discharging waveform shows a typical rise time of ,20 ns and a duration of ,150 ns [7]. Not drawn to scale.

Fig. 4. A CDM ESD model circuit using inductive charge method, with its equivalent circuit same as that in Fig. 1 [11].

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Fig. 5. A typical CDM ESD discharging waveform at a discharge level of ,1100 V[11].

Fig. 7. A typical IEC ESD discharging waveform showing extremely short rise time, very high current peaks, and relative shorter duration [14].

is pre-charged up and then discharges into a DUT to simulate ESD stressing events. TLP model is critical to conducting ESD simulation and predictive ESD protection design. 3. ESD protection device physics On-chip ESD protection units, being either single devices or sub-circuits, are commonly used to protect IC chips by being placed at each I/O or VDD pad. The principle of ESD protection is twofold: to provide a low-impedance discharging path to shunt ESD currents and to clamp pin-voltage to a safe level to avoid dielectric breakdown. The two typical ESD I V characteristics, as illustrated in Fig. 9, are simple turn-on and I V snapback, with the latter being more attractive due to its high current handling capacity. A successful ESD protection design must properly dene such critical parameters as, triggering point, (Vt1 and It1), snapback holding point, (Vh, Ih) and thermal breakdown threshold point, (Vt2 and It2), etc. Typical single ESD protection devices and device physics are discussed as following: 3.1. Diode ESD device Diodes, commonly reverse-connected to I/O pins as shown in Fig. 10, were widely used in early days as ESD protection solutions. Its operation follows the simple

turn-on scheme as depicted in Fig. 9a. Zener diodes are often used in this scheme [4,5]. This is a simple solution that can be simulated by SPICE. Forward-connected diode can handle large current transients. However, the main disadvantage is associated with its xed low forward turnon voltage (,0.65 V for Si) that limits its applications in many varying and high VDD cases. Multiple diode strings (forward or reverse) may address the problem [1618], but the on-resistance add-up reduces their current handling as well as voltage clamping capacity, hence ESD performance unless using large diode sizes, which, in turn, produce more parasitic effects. 3.2. NMOS ESD device Fig. 11 illustrates a well-known grounded-gate NMOS (ggNMOS) ESD structure where the drain (D) is connected to an I/O pad and the gate (G) is grounded. When a positive ESD pulse appears at the I/O pin, the D/Body junction is reverse biased until breakdown occurs. The generated hole current ows into Ground via the B (body) terminal that builds up a positive B/S junction voltage since B and S (source) are shortened. It eventually turns on the parasitic lateral NPN transistor, which forms a low-impedance discharging path to shunt the ESD current, therefore protect ICs from being ESD-damaged. For a negative ESD transient, a parasitic diode takes the charge. The advantage of ggNMOS protection is its active protection mechanism that can be optimized via physical design. The main disadvantages include non-SPICE-compatible snapback I , V, relative high holding point, low area efciency, and
Table 1 Parametric summary of ESD model circuits ESD models HBM MM CDM IEC RESD (V) 1500 0 025 330 LESD (mH) 7.5 0 , 2.5 0.0050.1 0 CESD (pF) 100 200 1100 150

Fig. 6. A typical IEC ESD model circuit featuring zero inductance [14].

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Fig. 8. A typical TLP model circuit where short square waveforms with varying heights are used to stress IC devices.

substantial parasitic effects. Often, a multiple-nger structure is required to achieve better ESD performance. However, data show that the ESD performance level is normally not directly proportional to the number of ngers because of non-uniform turn-on across the ngers. This problem is addressed by inserting ballasting resistor into each nger or using a gate-coupled NMOS structure (gCNMOS), to be discussed in Section 4. NMOS ESD structure is inherently less area-efcient because the parasitic lateral NPN transistor has a low gain. A eldoxide NMOS (FD-NMOS) version, where eld oxide (FOX) serves as the gate [1922], was also in use in the past. 3.3. SCR ESD device A SCR structure may serve as an excellent ESD protection device due to its deep snapback I , V characteristic [4,5,2325]. Figs. 12 and 13 illustrate a typical SCR cross-section and equivalent circuit. As an ESD pulse appears at the anode (A) w.r.t the cathode (K), it breaksdown the BC junction of vertical PNP Q1. The generated hole current ows through parasitic substrate-R, builds up VBE of lateral NPN Q2, turns it on and then triggers off the SCR. A low-impedance active path is therefore formed to discharge ESD current while its low holding voltage clamps

Fig. 10. A typical diode ESD protection scheme.

I/O pad to a safe level to avoid any ESD damages. A SCR is a very area-efcient ESD protection structure because of its high current handling capacity. However, cautions are needed to avoid possible latch-up effect. For example, its holding current must be designed to be higher than other currents on a chip; proper isolation using double guard rings and placement are critical to avoiding early triggering. Another disadvantage of SCR is that it relies on parasitic diode for ESD discharging in the opposite direction, which disqualies it for many relatively high voltage mixed-signal ICs.

4. ESD protection circuit solutions ESD protection circuits are designed for input, output and

Fig. 9. Typical ESD protection structure I , V characteristics: (a) simple turn-on; (b) snapback.

Fig. 11. A ggNMOS ESD protection structure: (a) schematic, (b) crosssection.

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Fig. 12. An X-section of a SCR ESD structure in typical CMOS technology.

power bus based upon their special needs. An ideal ESD structure should feature low-impedance, low-holding, nondestructive discharging path to shunt ESD pulses of all modes, preferably in active device mode suitable for SPICE modeling, as well as negligible leakage in offstate. To achieve full-chip ESD protection, ESD units are placed at all bonding pads and form active paths from each pin to any other pins. Until 1990s, most ESD protection was single-device based. IC technology advancements in recent years made more robust but complex ESD protection networks attractive and possible. 4.1. Input Esd protection 4.1.1. A primarysecondary ESD solution A classic primarysecondary ESD protection scheme [4,5,26] is illustrated in Fig. 14, where a primary ESD structure (PESD) is used to take the brunt of ESD transients; a secondary ESD unit (SESD) serves to ensure CMOS gate voltage clamping as well as to assist the turn-on of the primary that usually has higher triggering point; and an isolation resistor that limits the current owing to inside circuits. A ggNMOS serves as a good secondary. The primary, which can be realized by a FD-NMOS, SCR, or diode strings [2628], must be able to handle large current,

Fig. 14. A classic primarysecondary ESD scheme that consists of a primary ESD structure and a secondary ESD unit separated by an isolation resistor.

has very low holding voltage and small size. The isolationresistor should be large enough to ensure current-limiting without affecting IC speed performance. Low-parasitic poly-Si resistors may be used for low ESD case while a diffusion-resistor with its heads in n-wells has better thermal behavior for high ESD rating. Better ESD performance can be achieved by optimizing layout; for example, current uniformity can be realized by rounding corners to avoid localized heating. 4.1.2. gCNMOS To achieve robust ESD protection (.2 kV HBM), a large size ggNMOS is used in multiple-nger format. However, a linear relationship between ESD performance and the number of NMOS ngers cannot be obtained readily because one NMOS nger is usually damaged rst due to non-uniform turn-on and current-heat distribution across ngers. This happens if the trigger voltage (Vt1) is greater than that of the second breakdown voltage (Vt2), referring to Fig. 9, where one one-nger turns on rst, takes all ESD current and burns out before any other nger may be turned on. Conceptually, a design featuring Vt1 , Vt2 will resolve the problem, which can be realized either by inserting a ballast-R at the drain of each nger, or, using a gatecoupling NMOS (gCNMOS) structure [4] to reduce the

Fig. 13. A schematic for the SCR ESD structure.

Fig. 15. A gCNMOS schematic where the gate coupling leads to reduced triggering threshold.

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Fig. 16. LVSCR structures using (a) N 1 insertion and (b) with an NMOS.

Vt1 as shown in Fig. 15. In principle, a coupling capacitor lifts the gate voltage (VG) of NMOS to boost the substrate current that in turn accelerates the VBE building-up of lateral NPN, hence reduces its Vt1. A very careful design is needed in selecting the values for C and R to avoid over-stressing NMOS gate oxide layers while reducing Vt1 [29,30]. 4.1.3. Low-Vt1 SCR Conceptually, a SCR in Fig. 12 can be used at input pins; however, it is normally not a suitable option because of its relatively high Vt1 that might damage the gate oxide. Its lowVt1 versions work in many fashions [24,25]. Fig. 16a shows one low-Vt1 SCR (LVSCR) where a oating N 1-layer is inserted across the n-well boundary to reduce its avalanche breakdown voltage, hence shows a lower Vt1 (,20 V). Fig. 16b illustrates an even-lower-Vt1 SCR where a ggNMOS is placed over the n-well boundary to further reduce the Vt1 to 1015 V. Since its current handling capacity is determined by the lateral NPN and vertical PNP, the equivalent NPN base spacing (L1) is an important design factor in layout. The P 1 /N 1 spacing at the cathode, L2, also plays a role in determining Vt1 due to its inuence on the Rsub. 4.1.4. Compact multiple-direction ESD structures As IC technologies advance into the VDSM region, areaefciency becomes the number one concern in ESD design in order to simultaneously achieve superior ESD robustness and low ESD parasitic effects on circuit performance. Two novel compact ESD designs were reported in this category. Conventionally, a complete ESD protection scheme

Fig. 17. Complete ESD protection schemes in traditional way (a), and using new dual-direction (b) and all-in-one (c) ESD structures.

requires multiple-devices for one pad to form all active discharging paths to shunt the ESD pulses of all modes, i.e. I/O-to-VDD positively and negatively (PD and ND) and I/O-to-GND positively and negatively (PS and NS), as well as VDD-to-GND (DS), as illustrated in Fig. 17a. While this scheme provides full ESD protection, it consumes too much Si and produces substantial parasitic effect on circuit performance. A dual-direction ESD protection structure [31,32] with its cross-section shown in Fig. 18 can be used to solve

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Fig. 18. A novel dual-direction ESD structure consisting of two SCR units (Q1 Q3 and Q1 Q2) to shunt positive or negative ESD transients, respectively [31].

this problem as illustrated in Fig. 17b. This new ESD protection structure is a two-terminal device working in a dual-SCR fashion, where the SCR unit1 (Q2 Q3) or unit 2 (Q1 Q2) forms the discharging channel during a positive or negative ESD pulse between terminal 1 and 2, respectively. A similar structure can be found in Ref. [33]. An improved, three-terminal all-in-one ESD structure [34] is depicted in Fig. 19, which basically consists of two dual-direction structures. With its three terminals connected to I/O, GND and VDD, one SCR unit (e.g. Q4 Q6, Q4 Q5, Q1 Q2, Q1 Q3, and P2N3P7-Q6) will function under a specic ESD pulsing mode (e.g. PS, NS, PD, ND, and DS), accordingly. Hence, one single such structure can provide complete ESD protection in all directions, including power bus clamping, as illustrated in Fig. 17c. The main advantage of these structures is their high area efciency, extremely desired by mixed-signal and RF ICs. In addition, bonding padoriented designs can also be realized to further improve the performance [35]. Careful ESD simulation is crucial in ensuring proper functionality in designs. Although these structures were developed based upon BiCMOS technologies, implementation of such concepts may be possible in other technologies as long as enough layers are available to construct such structures. Further discussion will be given in Sections 8 and 9. 4.1.5. Trigger-assisting for SCR-type ESD protection The ESD structures in Figs. 18 and 19 allowed tunable Vt1

Fig. 20. A low- Vt1 all-in-one ESD protection circuit [36], where a triggerassisting current-source sub-circuit is used to reduce the trigger voltage.

for different needs by selecting different layers in design. However, the range of Vt1 values are limited in this fashion. For further reduction in Vt1, a trigger-assisting current source sub-circuit can be used. For example, Fig. 20 shows a schematic with trigger-assisting circuit, consisting of a switch (Sx) and a current source (Ix), for the all-in-one structure as shown in Fig. 19, where turn-on of vertical NPN is accelerated by voltage drop across Rxx caused by an extra current Ix, instead of avalanche current owing through an internal parasitic lateral-R. Hence, reduction in trigger voltage, Vt1, is realized. A back-to-back Zener diode string is an easy option for such a switch-current source (Sx Ix) sub-circuit [36]. 4.2. Output ESD protection Most of the ESD protection structures described for the input pins can be used for output pad protection [4,5]. The voltage-clamping requirement is relatively relaxed for output pins because most output ESD protection structures

Fig. 19. A compact all-in-one ESD protection structure, where parasitic SCR units (e.g. Q4 Q6, Q4 Q5, Q1 Q2, Q1 Q3, and P2N3P7-Q6) serve to discharge ESD pulses of all modes (e.g. PS, NS, PD, ND, and DS) [34].

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are not directly connected to CMOS gates. On the other hand, since many output stages are buffers with large sizes and high current driving capability, those big output buffer transistors can be self-protecting devices that are often modied to provide adequate ESD protection while maintaining buffer functionality. A main benet of this technique is eliminating extra ESD structures, resulting in no extra silicon consumed by ESD protection and therefore no ESDinduced parasitic effects. However, trade-offs between the buffer function and ESD performance has to be balanced.
Fig. 22. A Big-NMOS power clamp.

4.3. Power clamps A power clamping structure is commonly used to protect ICs against power bus ESD surges. Multiple-nger gCNMOS and SCR type structures are good candidates for power clamps. Power clamps are normally placed at four corners on a chip, or upon the device density on a chip, connected between VDD and GND, or between different VCCs and VSSs if multiple power buses exist. Another proven power clamp is based on a forward diode string as illustrated in Fig. 21. Since diodes are realized by PNPs in ICs, Darlington multiplication effect takes place in operation that causes noticeable leakage through the ESD protection structures. Under high current condition, the b of PNP becomes very small and diode models can be used for SPICE simulation. To avoid the substantial leakage due to Darlington effect, a snubbing-resistor is used to supply current directly to the emitter of last transistor, Q5, to break up the Darlington multiplication [5,17,18]. Yet another novel big-NMOS based power clamp is shown in Fig. 22. In operation, the capacitor ground the input of the inverter under an ESD transient, which generates a high output to turn on the big NMOS that forms a low-impedance discharge path to shunt ESD transients [37]. The advantage of this scheme is that the ESD protection block can be included into normal circuit simulation using SPICE. However, such kind of power clamp requires detailed timing design, takes substantial silicon assets, produces large parasitic effects, and is very unfriendly to layout design.

4.4. Whole-chip ESD protection schemes A whole-chip ESD planning is critical to complete ESD protection. The rule-of-thumb is to ensure a low-impedance active discharging path from each pad to any other pads on a chip. Fig. 23 illustrates one whole-chip ESD protection scheme that guarantees discharging channels between any two pins. The individual ESD structure may be any of those discussed previously, for example, a simple diode in forward mode in combination with power clamps. One has to estimate the worst case discharging resistance in the longest path (i.e. Pin 1 to Pin 2) to ensure adequate current handling capacity. If there are dual-direction ESD structures available, the scheme can be simplied substantially. A second whole-chip ESD protection scheme is shown in Fig. 24, where a global ESD bus is placed on a chip and dual-direction ESD devices are used. This solution uses fewer ESD protection devices, resulting in less silicon consumption by ESD structures, less parasitic effects and better layout design. The ESD bus should be connected to the substrate for better heat dissipation. 4.5. ESD for mixed-signal and RF ICs ESD protection design is more challenging in mixedsignal and RF IC applications. For mixed-signal ICs, since different circuit blocks on a chip usually have different

Fig. 21. A ve-diode string power clamp, where a snubbing voltage divider network can be used to eliminate the Darlington effect.

Fig. 23. Whole-chip ESD protection scheme 1.

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powered chip by mapping the emission image. Detailed layer-to-layer ESD damage can be inspected by SEM after de-processing a chip. FA research found many unique ESD failure signatures for different ESD structures in different technologies. Readers are referred to the following references for entertaining ESD FA images: a typical ESD damage at an NMOS drain diffusion edge in [38], a sample ESD damage in an NMOS gate oxide in [38], ESD damage occurring in one nger of a NMOS multi-nger structure due to non-uniform turn-on in [39], a `contact spiking' type melting in Si in a gate array in [40], and a typical ESD failure development procedure occurring around the gate of a ggNMOS ESD structure obtained by photon emission microscopy technique in [41].

6. Layout and technology consideration


Fig. 24. Whole-chip ESD protection scheme 2 using a global ESD bus.

specications and most likely use different local power supplies, ranging from 1.8 to 50 V plus, one ought to select different ESD structures to fulll local needs for optimal chip-level ESD performance [3136]. An all-t ESD unit does not exist most of the time. Challenges in RF and VDSM IC ESD design mainly stem from the substantial interactions existing between ESD networks and core IC circuits protected. The most critical requirement for ESD here is the small size and negligible ESD-induced parasitic effects (i.e. RC delay and noises), which will be discussed in Section 9. Keep in mind, ESD solution is not portable among different technologies and/or within a product family using the same technology. Custom-optimization is critical to ESD protection design successes. 5. ESD failure analysis ESD damages are either permanent or latent in nature. Permanent ESD failures are associated with material damages due to localized heating in Si and/or metal interconnects or eld stress induced dielectric rapture in CMOS gate. Latent ESD failures cause circuit performance degradation and lifetime problem; however, detailed mechanism is still under investigation. ESD failure analysis (FA) is extremely important for designers to debug ESD failure problems, to pin-point ESD damage location, and eventually to improve ESD designs. A variety of FA tools are available including destructive and non-destructive methods. Simple FA tools include optical microscope and SEM. Liquid crystal analysis can be used to accurately locate ESD hot-spots by placing a chip on a hot chuck, covering it by liquid crystal, then powering the chip up and inspecting it. A photon emission microscope can provide pin-point level accuracy in FA analysis of a

ESD protection design is extremely geometry-sensitive that makes layout a critical factor. Many ESD protection designs, predicted working by simulation, fail pre-maturely due to non-optimized layout, while thoughtful layout may boost ESD performance signicantly. Fig. 25 illustrates an optimized multiple-nger ggNMOS structure following a BSGD-DGSBSGD-DGSB pattern for better ESD performance [30]. Careful design for current ow path is important in avoiding current-crowdinginduced early-failure (Fig. 25b). All device corners should be smoothed (rounded) to avoid localized heating. Large diffusion-heads for resistors are suggested to avoid resistor overheating. Square cell structures are reported to boost ESD performance [42]. Some novel ESD structures may also allow bonding pad-oriented layout (surrounding or underneath pad) that saves Si areas substantially, as demonstrated in Fig. 26 [35]. If permitted, as many as possible contacts and vias should be used. The width of ESD metal

Fig. 25. A good NMOS nger structure layout, where the layout in (a) ensures a `one-way' type current ow to avoid substantial current crowding effect as illustrated in pattern (b).

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hand, new copper interconnect technology can relax ESD concerns in metal interconnection. It is therefore possible to use narrower ESD metal lines in Cu technologies [44], which may substantially reduce the ESD-metal-induced parasitic effects an especially important gain for highpin-count dense chip design. Other emerging technologies, such as SOI [48] and SiGe, also require more studies and special considerations in ESD protection design. A useful practical ESD design checklist is proposed in Appendix A for reference. 7. ESD failure modeling Analytical models, being thermal or electro-thermal, have been proposed to describe ESD device failure phenomena. A thermal model assumes the ESD failure onset associated with a critical temperature that is correlated with the power delivered to the device under stress while assuming temperature-independent electrical parameters. A power-to-failure (Pf) versus time-to-failure (tf) formula was derived based upon heat equation solution of an assumed localized parallelepiped heat source, as illustrated in Fig. 27 [4952]. Electro-thermal models [5356] correlate device electrical parameters with temperatures based upon a coupled set of semiconductor device equations and heat distribution equation. The failure criteria are related to the device second breakdown, with the It2 (Fig. 9) being the indicator. While argument exists regarding the accurate ESD thermal failure criteria, the It2 seems to provide a reasonable good ESD failure indication in practical ESD simulation and design. More research is under way to better understand ESD device failure mechanisms, particularly for the latent ESD failures. 8. ESD design by simulation ESD protection design traditionally follows a trial-anderror approach due to difculties in failure modeling and CAD tools. To date, experience-based ESD design methods

Fig. 26. A bonding pad oriented novel ESD structure [35].

lines is normally suggested to be 20 mm or as wide as possible. However, the wide ESD metal induced RC parasitic effect is becoming an issue in high-speed dense design [43]. Electro-thermal ESD simulation should be conducted to select just-adequate ESD metal width for full-chip design optimization [44,45]. In this regard, mixed-mode ESD simulation including metal interconnects is desirable [46]. In NMOS ESD structures, accepted design rules suggest using large drain-contact-to-gate-spacing (e.g. DCGS ,5 mm for ballasting resistance effect) and minimum source-contact-to-gate-spacing (SCGS) for optimized ESD performance. This rule generally works for technologies down to 0.25 mm. However, studies indicate the minimum SCGS rule may lead to pre-mature ESD failure in sub-0.25 mm technologies because the heat generated at the drain junction spreads into S-contact regions and causes thermal damages in source contacts and metal [45,46]. Photon-induced overheating is another contributing factor in this regard, which might be a dominating factor in future nano-scale ESD protection [47]. IC technology advancements may affect ESD performance positively or negatively. On the negative part, new techniques, such as, LDD and salicidation, degrade ESD performance signicantly, which calls for extra ESD-xing steps in processes [4]. For example, ESD implant and salicide-blocking steps are commonly added for such purpose, which substantially increase development costs to a technology. From this angle, it is extremely benecial to include ESD simulation and consideration into early process development phase. Some trade-offs between ESD and device performance may be well paid off from the product development viewpoint. On the other

Fig. 27. A piece-wise ESD device failure model.

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still play a main role as ESD simulation techniques advance. ESD simulation methods can be classied into device and circuit level simulation. On one hand, ESD design prediction requires numerical simulation at device physics level to address the electro-thermal behaviors. Efforts have been made in this area by many investigators [5565]. On the other hand, circuit level ESD simulation is preferred by ordinary IC designers to include ESD design into wholechip design work. However, since most advanced ESD structures rely on non-SPICE-compatible snapback characteristics, while accurate high-current ESD device modeling is still not really available yet, it remains very tricky for real world designers to perform successful ESD design using circuit-level ESD simulation in practices. Compared to the usual fact that accurate device modeling always lags process development, the situation in ESD design is ordersof-magnitude worse in this regard. A few electrothermal ESD simulators were developed, using a thermal-electronic analogy network model and snapback device models, for circuit level simulation [60,6567]. However, it is probably too tough a task for a designer to nd out exactly where a hot spot might under ESD stresses that will be modeled by a localized parallelepiped heat source for meaningful ESD simulation, at least in practical design. A mixed-mode TCAD-based ESD design-simulation methodology was reported recently that involves multiple-level coupling effects in simulation, i.e. combined process-device-circuitelectro-thermal consideration [29,64]. The idea behind is to create actual ESD structures by process simulation, evaluate individual ESD structure by device simulation, and simulate ESD circuit performance under real-world transient ESD stressing by mixed device-circuit level simulation. From the design viewpoint, one ought to dene critical I V characteristic parameters, such as, triggering point (Vt1, It1), triggering timing (t1), holding point (Vh, Ih), and failure threshold (Vt2, It2) (refer to Fig. 9). The goal is to predict ESD performance in pre-Si design phase. To make ESD design prediction, calibration is a critical factor in ESD simulation, same as in typical SPICE simulation case. The simulation calibration work must be conducted carefully for every new design, regardless of using different technologies or within the same technology. The reason, often overlooked by designers, is that ESD protection structure is actually custom design in the sense that it is always sensitive to structures, layout, circuits, technologies, and applications. The key point is that ESD protection solution is not portable. The new ESD simulation approach has been used successfully in many practical ESD design cases [3036,4346]. For example, Fig. 28 shows transient ESD simulation results for a multiple nger NMOS ESD structure where the simulation helped to realize reduction of the Vt1 from ggNMOS to gCNMOS in order to realize Vt1 , Vt2 , therefore to achieve uniform turn-on across ngers [30]. Fig. 29 is another design example where a high Vt1 (,23 V) of a dual-direction ESD structure (Fig. 18) was reduced to ,9 V by inserting a trigger-assisting

Fig. 28. Transient ESD simulation of (a) a ggNMOS shows Vt1 ,14.7 V; (b) gCNMOS shows lower Vt1 (,7.5 V).

Fig. 29. Transient ESD simulation shows reduced Vt1 of an ESD structure (Fig. 18) from ,23 to ,9 V by using a triggering-assisting sub-circuit made of Zener diodes.

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A.Z. Wang et al. / Microelectronics Journal 32 (2001) 733747 Table 3 Data summary for noise gures vs different ESD protection devices used for a high-performance LNA circuit in 0.18 mm technology ESD structures None ESDa (GGNMOS) ESDb (dual-direction) LNA NF (dB) 1.54 1.61 1.55

sub-circuit [31,68]. Mixed-mode ESD simulation played a key role in these designs. Once again, it is important to realize that calibration is critical for ESD simulation to achieve design prediction. 9. ESD-circuit interactions Another extremely important, however largely overlooked, aspect in modern ESD protection design is the complex ESD-circuit interactions. On one hand, parasitic devices inside the circuit being protected may cause early ESD failure of a chip even though stand-alone ESD structures work well. Such pre-mature ESD failures are usually caused by weak discharge paths formed by parasitic devices inside the core circuits called circuit-to-ESD inuences. On the other hand, the inevitable parasitic effects induced by the ESD protection units can affect circuit performance dramatically referred to as ESD-to-circuit inuences. Typical ESD-to-circuit inuences include ESD-induced RC delay and extra noises (both ESD coupled noises and ESD self-generated noises). These interactions become intolerable to RF ICs and other high-speed, high-density VDSM chips. It is therefore desirable to explore novel compact ESD protection solutions for advanced IC chips. For example, one study [43] showed that up to 30% performance degradation occurred in a high-speed Op Amp circuit in 0.18 mm technology when using conventional NMOS ESD protection, while using compact ESD structure can recover such performance degradation by 80% as indicated
Table 2 Data summary for performance degradation of a high-speed Op Amp circuit in 0.18 mm technology due to CESD loads using different ESD protection structures

in Table 2. Another study [69] demonstrated that using a big NMOS ESD structure increased the noise gure of a highperformance LNA by 4.5% due to ESD self-generated noises, which was reduced to a merely 0.6% when an improved compact ESD protection structure was adopted, as shown in Table 3, without suffering ESD performance. 10. Future work It is extremely important to realize that ESD protection design takes a system approach in order to address the complex multiple-level coupling issues. It is equally critical to recognize that ESD protection design is not portable even within the same technology. Mixed-mode ESD simulation, though still not perfect and time consuming, should be used in advanced ESD protection design for design assistance and prediction in pre-Si design phase. To achieve full ESD design prediction, much research efforts are expected in such areas as, accurate high-current ESD device modeling, geometry-sensitive ESD device modeling, 3D ESD simulation, as well as whole chip level ESD design synthesis, simulation and verication [70]. 11. Summary In summary, this review discusses the state of knowledge of on-chip ESD protection circuit design for ICs. The discussion covers critical issues in ESD design, such as, ESD test models, ESD failure mechanism, ESD protection structures, ESD device modeling, ESD simulation, ESD layout issues, and ESD-circuit interactions, etc. This review serves to provide practical IC designers with a thorough and heady reference in handling the complex ESD protection circuit design tasks. For more extensive coverage of ESD protection design, see Refs. [4,5,71]. Appendix A. ESD design checklist The following checklist serves to assist IC designers in realizing successful ESD protection design. Understand that ESD protection solution is not portable, even within the same technology. When borrowing a successful ESD protection structure,

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make sure to understand its operation. A specic circuit may affect the ESD protection structure signicantly. Check to make sure every pad has at least one ESD protection structure connected, depending upon the whole-chip ESD protection scheme adopted, excluding the self-protection output pads. Check to make sure a low-impedance discharge path existing between any two pads. Check to make sure a designed discharge path functioning for ESD transients of different polarities, according to ESD test standard to be used. For any ESD protection structure, accurately dene the I V characteristic parameters for triggering point (Vt1, It1), holding point (Vh, Ih), and thermal failure threshold point (Vt2, It2). Check to make sure the Vt1 is set with adequate safe margin (,50% higher than VDD) to avoid accidental turn-on by normal signals. Check to make sure the Vh is low enough to avoid gate oxide overstress. Check to make sure Vt1 , Vt2 condition satised if multinger NMOS ESD is used to ensure uniform turn on. Check to make sure the ESD protection structure responds to ESD pulses quick enough: t1 # tr of the HBM, CDM or IEC model to be used. If a primarysecondary protection scheme is used, check to make sure the isolation resistor is large enough to limit ESD current owing to inside circuit and include the R in circuit simulation. Check all resistors used in ESD protection network for their values and layout. Use smoothed deep-diffusion heads for resistors. If poly-Si resistors are used, check the current handling capacity. For multi-nger ESD structure, properly arrange the current ow paths in layout to avoid current crowding. For NMOS ESD structures, check the DCGS and SCGS for proper values. Pay special attention to the minimum SCGS traditionally suggested if sub-0.25 mm technologies to be used. For gCNMOS ESD structure, check the VG to make sure no overstress occurring at the gate. For SCR type ESD structures, check the latch-up immunity and make sure the Ih is higher than any other on-chip current (i.e. IDD) to avoid staying in latch-up state after ESD transient. Check the spacing between ESD devices and any internal devices that produce substantial current (i.e. charge pumps and output buffers), since such large current may leak into the ESD region via substrate to cause early triggering. Use guard rings to de-couple the substrate current leakage. Check all diffusion layer spacing in layout to avoid any parasitic transistors that often lead to pre-mature ESD failures. Check to make sure the metal interconnects are wide enough to survive ESD pulses. However, be cautious in

using over-widened metal because of its parasitic RC effects. Conduct simulation if possible. Check the current handling capacity of contacts and vias. Use as many of them as possible. To avoid interconnect bridges within ESD protection network if ever possible. To look into possible circuit-to-ESD inuences that often causes pre-mature ESD failures. To evaluate the ESD-to-circuit inuences including RC delay and noises. Make sure to use salicide blocking in the technologies with salicide feature. To use compact ESD protection structures if ever available, particularly in high-speed dense design. To evaluate the leakage current level of ESD protection structure.

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