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Direct Power Control of Series Converter of Unied Power-Flow Controller With Three-Level Neutral Point Clamped Converter
Jan Verveckken, Student Member, IEEE, Fernando Silva, Senior Member, IEEE, Dionsio Barros, Member, IEEE, and Johan Driesen, Senior Member, IEEE

AbstractA unied power-ow controller (UPFC) can enforce unnatural power ows in a transmission grid, to maximize the power ow while maintaining stability. Theoretically, active and reactive power ow can be controlled without overshoot or cross coupling. This paper develops direct power control, based on instantaneous power theory, to apply the full potential of the power converter. Simulation and experimental results of a full three-phase model with nonideal transformers, series multilevel converter, and load conrm minimal control delay, no overshoot nor cross coupling. A comparison with other controllers demonstrates better response under balanced and unbalanced conditions. Direct power control is a valuable control technique for a UPFC, and the presented controller can be used with any topology of voltage-source converters. In this paper, the direct power control is demonstrated in detail for a third-level neutral point clamped converter. Index TermsDirect power control, exible ac transmission control (FACTS), multilevel converter, sliding mode control, unied power-ow controller (UPFC).

Fig. 1. One-wire schematic of the transmission line with UPFC.

I. INTRODUCTION C transmission lines form the backbone of the electricity grid in most countries and continents. The power ow will follow the path of least impedance and is uncontrollable, unless active grid elements are used. To enhance the functionality of the ac transmission grid, exible ac transmission systems (FACTS) support the transmission grid with power electronics. These devices offer a level of control to the transmission system

Manuscript received February 25, 2011; revised July 29, 2011; accepted May 13, 2012. Date of publication June 25, 2012; date of current version September 19, 2012. This research work was carried out at Cie3 and DEEC Laboratories of the Instituto Superior Tcnico, TU Lisbon, Lisbon 1049-00, Portugal. The rst author received a specialization grant from the Institute for the Promotion of Innovation through Science and Technology, Flanders, Belgium (IWT-Vlaanderen). Paper no. TPWRD-00161-2011. J. P. Verveckken is with Katholieke Universiteit Leuven, ESAT, Vlaams Brabant 3001, Belgium (e-mail: jan.verveckken@ieee.org; jan.verveckken@gmail. com). J. F. Silva is with IST, TU Lisbon, DEEC, Lisbon 1049-001, Portugal (e-mail: fernandos@alfa.ist.utl.pt). D. Barros is with Universidade de Madeira, Centro de Competncias das Cincias Exactas e da Engenharia, Campus Universitrio da Penteada, Madeira, Portugal 9000-390 (e-mail: dbarros@uma.pt). J. Driesen is with the Department of Electrical Engineering (ESAT), Katholieke Universiteit Leuven, Div. ELECTA, Heverlee, Belgium B-3001 (e-mail: johan.driesen@esat.kuleuven.be). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TPWRD.2012.2200508

operator [1], [2]. A unied power-ow controller (UPFC) is the most versatile of these FACTS devices. A transmission line equipped with a UPFC can control the balance of the transmitted power between parallel lines and, as such, can optimize the use of the transmission grid for all parallel power ows. A one-wire schematic of a transmission-line system equipped with a UPFC is given in Fig. 1. A UPFC is connected to the transmission line by coupling transformers, both with a shunt and with a series connection. The UPFC consists of two ac/dc converters, the ac sides connected to the shunt and series connection with the transmission line, and the dc sides connected back to back. UPFCs are typically built with voltage-sourced converters, having a capacitor as (limited) dc energy storage. In Fig. 2, an overview of the most common control structure for UPFCs is displayed. An external control describes the setpoints of the power system (steady state or dynamic). The internal control describes the actual power electronics and safeties of the UPFC [3]. The external control is typically divided into a master and middle control [2]. The master control handles targets such as an optimal power system setpoint, increase of transient stability, or subsynchronous resonance dampening and delivers the middle control setpoints. Middle control translates these master setpoints into setpoints for the series and shunt converter. The series and shunt controller can have [4], but do not require [5] and [6], internal communication for stability increase or optimization. The internal controller translates these middle-level control setpoints into switching decisions for the power-electronic components. Higher level control techniques have primarily focussed on optimizing power ow [1]. Later on, the focus shifted to damping subsynchronous resonances of turbine generator shafts and interarea oscillations [7][11] and transient stability increase [12]. Various methods are used to switch intelligently

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Fig. 3. Schematic of the equivalent circuit of the UPFC system.

Fig. 2. UPFC controller classication according to [2] and [3], and the position of the proposed direct power controller (DPC).

between higher level control priorities [7], [13]. Recently, a lot of interest into the increase of grid reliability is shown [14]. The rst designs of middle-level power-ow controllers for UPFC used direct control which suffered from serious cross coupling [15]. Decoupling control improved this cross-coupling, with high sensitivity to system parameter knowledge [16], and cross-coupling control of direct and quadrature series-injected voltages to active and reactive power improved on that. Cross-coupling control with direct control oscillation damping [8] enhanced performance, but based on PI control structures, realized a low control bandwidth [16], [17]. The instantaneous power concept [18][20] enabled faster control techniques, putting, however, a larger strain on the computational capacity of the controllers [5], [21]. The controller proposed in this paper combines two control levelsthe middle-level series converter control and internal converter controlthereby increasing the simplicity of the controller and increasing the control dynamics. Since the series converter is typically used for power-ow control, the controller realizes a direct relation between the desired power ow and switching states, and is therefore named a direct power controller (DPC). In Fig. 2, the precise location of the proposed DPC is displayed. The direct power control technique used in this paper nds its design principles in instantaneous power theory [22], [23] and sliding mode control [24][26]. Relying on these two techniques, a sliding surface is dened in function of the instantaneous active and reactive power, and the system is controlled to stay on the surface. A similar controller was developed for a matrix converter [27]. This paper is a follow up paper to [28], with a more detailed explanation of the controller design and a comparison to other controllers. The series and shunt converter of a UPFC are HV power electronics. To minimize the voltage stress on all components while increasing the system voltage level, multilevel neutral point clamped inverters are a promising topology. The DPC control method described in this paper is divided in two partsa

general external part and an internal topology-specic part. The design principles for both are explained in detail. The external part is universal, the internal part can easily be adapted to different topologies of voltage-source converters. In this paper, a three-level neutral point clamped converter is used. Other converter topologies use the converter independent part without further theoretical development. The converter topology dependent part can be deduced analogously to the given example. The model of the UPFC will be developed in Section II. All assumptions made will be mentioned and claried. In Section III, the three-level inverters topology, its mathematical model, and the derived system equations will be explained in full. In Section IV, the direct power control will be constructed and its theoretical functionality demonstrated. The topology-dependent part is developed for a three-level NPC converter based on Section III. Simulation and experimental results are demonstrated in Section V. The experimental setup is discussed in detail. Conclusions regarding the DPC method, its application for UPFC, and the interaction on the control of a multilevel converter are given in Section VI. II. UPFC SERIES CONVERTER MODEL During model construction and controller design, power sources , are assumed to be innite bus. We assume series transformer inductance and resistance negligible compared to transmission-line impedance. Connection transformers of series and shunt converters of the UPFC as in Fig. 1 are not explicitly included in the mathematical model used for controller design. Under these assumptions, we can simplify the grid as experienced by the UPFC to Fig. 3. Sending and receiving end power sources , are connected by transmission line , . The total current drawn from the sending end consists of the current owing through the line and the current exchanged with the shunt converter . Shunt transformer inductance and and . The series inductance resistance are represented by and resistance are commonly accepted as a model for overhead transmission lines of lengths up to 80 km [29], [30]. The power to be controlled is the sending end power, formed by the current and the sending end voltage . This is the most realistic implementation for control purposes. The UPFC shunt converter model is similar and is not described in this paper; its functions and control are well described

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in literature [1], [2], [31] and the performance of the shunt converter is only of secondary inuence on the control system described in this paper, as demonstrated in previous work [21]. Effects of dc bus dynamics are negligible in the control bandwidth of the power ow. For all simulations and experiments in this paper, the shunt converter is only used to satisfy active power ow requirements of the dc bus. Using the model of Fig. 3, differential equations that describe the current in three phases can be formulated. Voltages are used for notation simplicity. The differential equations for the UPFC model are given as (1) Applying the Clarke and Park transformation results in differential equations in space. Voltages and are introduced for notation simplicity. It is assumed that the pulsation of the grid is known and varies without discontinuities. Applying the Laplace transformation and with substitution between the two space transfer func, are given in tions, (2) is obtained, where currents function of voltages and
Fig. 4. Schematic of the three-level neutral point clamped converter.

(2) The active and reactive power of the power line are determined only by the current over the line and the sending end voltage. Without losing generality of the solution, we synchronize the Park transformation on , resulting in . Assuming relative voltage stability, , . Active and reactive power at the sending end are calculated as

(6) It is interesting to take a further look at the components of the dynamic part of the active and reactive power , , especially at the response to steps in series converter injected voltage , . Using the initial value theorem on (6), we receive

(3) Substituting (2) into (3), we receive the transfer functions, , to , , and . Both active and linking reactive power consist of an uncontrollable constant part, which is determined by power source voltages , and line impedance , and a controllable dynamic part, determined by converter voltage , as made explicit in

(7) effects the derivative It is clear that only instantaneously, and only effects the derivative instantaneously. III. THREE-LEVEL NEUTRAL POINT CLAMPED CONVERTER A schematic of a three-level neutral point clamped converter is given in Fig. 4. This topology and its mathematical model have been diligently described in [32]. Each leg of the con, , , verter consists of four switching components , and two diodes and . The diodes , clamp the voltages of the connections between , , and , , , . respectively, to the neutral point, between capacitors There are three possible switching combinations for each leg , thus three voltages . The three levels for voltages produce ve different converter phase-output voltages . The upper and lower leg currents , or their respective sum , can be described in function of the output line currents . The

(4) Splitting in a constant uncontrollable and a dynamic control, lable part results in (5) and (6). For notation simplicity, are replaced by ,

(5)

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system state variables are the line currents , , , and the capacitor voltages , [32]. This system has the dc-bus curas inputs. rent and the equivalent load source voltages Under the assumption that the converter output voltages are connected to an , system with a sinusoidal voltage source with isolated neutral, as in Fig. 4, we can write the equations for the three-phase currents , , as in (8) , are inuenced by the sum of The capacitor voltages the upper and lower leg currents , and the input current , as in
Fig. 5. Vector arrangement in ve levels in , for three-level three-phase . (b) Five levels in , . converter. (a) Five levels in , TABLE I OUTPUT VOLTAGE VECTORS

(9) From the restrictions on the states of the switching devices in each leg of the converter, we can dene the ternary variable , representing the switching state of the entire leg, as on on on off off off

To simplify notation, combinations of this variable are introduced

(10) , , and

(11) (12) If we assume the voltage balance of the capacitors , , the 27 possible combinations of leg switching state variables , , lead to 27 sets of phase voltages , , and 27 voltage -space. The 27 voltage vectors after Clark transformation to vectors can be divided in 24 active vectors and 3 null vectors. The 24 active vectors form 18 unique vectors; 12 vectors form 6 redundant pairs. The 3 null vectors also form only 1 unique vector. This results in 19 different voltage vectors. To simplify the vector selection, the 27 vectors are grouped into 5 levels in the and dimension, based on their component in this dimension. The levels and vector grouping are represented in Fig. 5. Each combination of levels , corresponds to one unique and have voltage vector. Assuming that the capacitors equal capacity and using the relation of the three line currents , the dynamics of the voltage balance can be derived from (14), leading to

(13) , and the derived variables and [32], With this variable straightforward equations can be found for the description of the other variables in the system. Combining the equations of the system dynamics (8) and (9), the complete system equation is (14) [32], where , , are aiding functions describing the precise dynamics in function of the switching state. It is important to realize that this system equation is not constant, nor continuous

(15) (14) In Table I, the effect of the output voltage vectors on the capacitor voltage balance is listed. Comparing these values with those

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of for the values of the redundant vectors, given in bold, they depend on the same currents and except for the sign, are equal. To know the sign of the derivative of the voltage unbalance , the sign of the instantaneous active power will be used. Since will always be positive, the sign depends only on the sign of . Assuming perof fect voltage balance, the instantaneous outgoing power of the converter is given by the internal product of the switching state variables and outgoing line currents scaled by the capacitor voltage by

From (19), it can be concluded that to instantaneously inuence , should be used. Similarly, for , it is done . It is also clear from (19) that impulse or step best by changes in , cannot be followed instantaneously, yet ramps in , can be followed, pro, viding their rate of change is less than and the combination cannot exceed (20) Considering this conclusion, it is important to determine the conditions to reach the direct power control surfaces using the nal value theorem

(16)

IV. DIRECT POWER CONTROL Direct power control must ensure that the sending end power , follows power references , . Dening the strong relative degree [26] of the controlled output , as the minimum th-order time derivative , that contains a nonzero explicit function of the control vector , a suitable sliding surface is a linear combination of the phase canonical state variable errors. For and , , then

(21) From (21), several important conclusions can be drawn. The control can only handle limited steps or ramps of decaying derivative in references , . Also, a clear limit exists to the controllable reference steps, limited by the maximum UPFC series output voltage amplitude , as

(17) In (17), is a strictly positive constant; therefore, the only possibility for the system to uphold the surface equations , is having the real power , follow the refer, . A control law that enforces the system ences to stay on these surfaces, or move toward them at all times, can be expressed as in (18), [24], [25]

(22) In the selection Power to desired change in of Fig. 6, the implementation of 19 exists. To select a physical voltage vector, this decision process is transformed to the domain, remaining with requested changes of the UPFC series output voltage in to the output voltage vector. To limit the switching frequency, the decision is suppressed until the system state crosses a parallel surface at a certain distance from the direct power control surfaces . Note that this requested change is not expressed in a numeric value of the requested change, but as the direction of change (in this case, a ternary variable, indicating increase , no change 0, decrease ). Depending on the currently used output vector and the requested change in , an appropriate next vector can be selected. This concludes the converter topology independent part of the controller. In Fig. 6, in the selection Desired change in to output Voltage, for a three-level NPC converter, the voltage vector selection is displayed. DPC demands increasing or decreasing the output voltage vector in the and direction. Based on the currently applied vector and this demand, the next vector is selected. This is simplied to selection of the voltage vector levels , . In the cases that vectors coincide, an extra criterium is needed to unambiguously select a set of switching

(18) , are governed by system dynamics involved where (6). To uphold (18), the inverter has to appropriately change the sign of the derivatives , . Using the results of the initial value theorem on the derivative of the sending end power in (7), the following equation can be developed:

(19)

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Fig. 6. Overview of the control algorithm.

IN

TABLE II VECTOR ARRANGEMENT IN FIVE LEVELS , . (a) . (b)

within the selection of the null vector 1, 14, 27. They have the same effect on the output voltage and capacitor voltage imbalance . To minimize the switching losses, the null vector could be chosen within least switching distance from the previous vector. As such, any order from a higher controller to change the output voltage in is translated unambiguously into a voltage-output vector. This voltage vector selection method is well covered, including the necessary balancing of the capacitor voltages by [32]. V. RESULTS

state variables , , . Even though the voltage vectors may realize the same phase voltages , , , the precise also determines wether energy is switching state , , drawn or injected from or into capacitors and

(23) , (23) must be To maintain voltage balance upheld at all times. This is displayed in Fig. 6 in selection Capacitor voltage balance control. Depending on the sign of and output power , the the voltage unbalance voltage vector can be selected so that (23) is upheld. Vector selection, in function of demand for change of the voltage , dimension and capacitor voltage unbalance is vector in given in Table II(a) and (b). To limit the output frequency, the size of the voltage unbalance has to reach a before it is addressed. In this application, certain level it is enforced by a relay system. The last degree of freedom is

The discussed controller is demonstrated in simulation and in experimental results. Fig. 7 shows the experimental setup. A DSpace controller board is used. For controlled startup and ease of use, an autotransformer is used to regulate the mains voltage on the setup. Two isolation transformers are connected to the autotransformer, to represent the sending and receiving . Iron cored coils are used to represent the end voltages , load impedance , and transmission-line impedances , , and , . Another step down isolation transformer is used for the series connection of the UPFC inverter to the grid. The values of the separate components are given in Appendix A. Both the simulation and experimental setups use these parameter values so that results can be compared. The simulation is based on a full three-phase model of the UPFC and the power lines constructed with Matlab Simulink. It is performed on a balanced model of the experimental setup. It contains a model of the converter based on the dynamic equations and control laws as described in Section IV. UPFC shunt converter and dc capacitor dynamics are included in the system

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Fig. 7. Laboratory setup.

Fig. 8. UPFC series converter controlling power ow under balanced conditions, 2.5-s view during stepwise changes of active and reactive power ow reference , . (a) Simulation ( 948 Wpu, 948 VArpu) ( , , 2.38 Apu). (b) Experimental (CH1: 40 W/V, CH2: 40 VAr/V, 5 V/div) (CH3, CH4: , 0.22 A/V, 5 V/div). (c) Simulation ( 948 Wpu, 948 VArpu) ( , , 2.38 Apu). (d) Experimental (CH1: 40 W/V, CH2: 40 VAr/V, 5 V/div) (CH3,CH4: , 0.22 A/V, 5 V/div).

model. The shunt converter is set to control the total dc voltage level of the converter dc bus. No reactive power transfer between the shunt converter and the sending end bus is set; the

sending and receiving end are simulated as innite bus. The transformers are modeled as saturable transformers. In the rst set of results, the DPC method is put to demonstrate power-ow

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Fig. 9. UPFC series converter controlling the power ow under balanced conditions, 250-ms view during stepwise change of active and reactive power ow , . (a) Simulation ( 948 Wpu, 948 VArpu) ( , , 230 Vpu) ( , , 2.38 Apu). (b) Experimental, (CH1: 40 W/V, CH2: 40 reference , , 230 Vpu) ( , , 2.38 Apu). (d) Experimental, VAr/V, 5 V/div)(CH3,CH4: , 0.22 A/V, 5 V/div). (c) Simulation ( 948 Wpu, 948 VArpu) ( (CH1: 40 W/V, CH2: 40 VAr/V, 5 V/div) (CH3,CH4: , 0.22 A/V, 5 V/div). TABLE III SYSTEM PARAMETERS TABLE IV CONTROLLER PARAMETERS

control. In a second set, the DPC method is compared in simulation to two other controllers in normal and unbalanced conditions, to demonstrate the superior performance of the DPC method. A. DPC Simulation and Experiment in Balanced Conditions Both in simulation and in experiment, , take values of 0 to 0.316 p.u. and change stepwise. It should be noted that the , do not represent a realistic reference proreferences le. An overview of 2.5 s of the closed-loop controlled output in

Fig. 8(a)(d) demonstrates that the system can handle any com, , and refbination of sending end power references erence changes , . A more detailed look at the results in Fig. 9(a)(d) shows that there are no low-frequency phenomena in the currents, and that they are balanced. The direct power controlled system demonstrates no overshoot, no cross coupling, no steady-state error, and a fast rising and settling time. B. DPC Compared to Other Controllers The same simulation model is used as in the previous test. The DPC will be compared with two other controllers: advanced dynamic control (ADC) [5] and dynamic inverse control (DIC) [21]. Both are middle-level controllers, with a clearly described

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Fig. 10. UPFC series converter controlling power ow, comparison between controllers DPC (-) ADC(- -) [5] DIC (-.) [21]. (a) Simulation under balanced condi, , 250-ms view ( 948 Wpu, 948 VArpu). (b) Simulation under balanced conditions, tions, simultaneous step in active and reactive power references , , 6 ms view ( 948 Wpu, 948 VArpu). (c) Simulation under unbalanced conditions, 70% simultaneous step in active and reactive power references 0.125 s, 250-ms overview ( 948 Wpu, 948 VArpu) ( , , 230 Vpu). single-phase voltage sag at

design methodology. The controllers are designed as specied in their sources, and the parameters can be found in the Appendix. To create fair comparison conditions, the converter control is implemented by a sliding mode controller for the threelevel converter with the same switching frequency, switching table, and relay widths as the one incorporated in the DPC [32]. 1) Balanced Condition: The three controllers are compared under equal conditions of the previous simulation, which are completely balanced. It can be seen from Fig. 10(a) that the DPC demonstrates the smallest perturbation from the setpoint in steady-state conditions. ADC demonstrates low-order harmonics and steady-state error, while DIC demonstrates serious low-order harmonics. From Fig. 10(b), which is a zoom of Fig. 10(a), it can be seen that the DIC and ADC have a faster response to a step, but present more overshoot, and have a longer settling time. Overall, the DPC presents better performance under balanced conditions, both in steady state and dynamically. 2) Unbalanced Voltage Sag: The controllers are compared during a single line-to-line voltage sag, with 70% of nominal voltage remaining. Fig. 10(c) shows that the DPC is fairly indifferent, whereas DIC and ADC demonstrate an increase in their low-order harmonics. DPC has the best response to unbalanced voltage conditions.

VI. CONCLUSION The DPC technique was applied to a UPFC to control the power ow on a transmission line. The technique has been described in detail and applied to a three-level NPC converter. The main benets of the control technique are fast dynamic control behavior with no cross coupling or overshoot, with a simple controller, independent of nodal voltage changes. The realization was demonstrated by simulation and experimental results on a scaled model of a transmission line. The controller was compared to two other controllers under balanced and unbalanced conditions, and demonstrated better performance, with shorter settling times, no overshoot, and indifference to voltage unbalance. We conclude that direct power control is an effective method that can be used with UPFC. It is readily adaptable to other converter types than the three-level converter demonstrated in this paper. APPENDIX A SYSTEM PARAMETERS The per-unit base values for voltage and apparent power are chosen to be the nominal voltage of sending end voltage and the nominal three-phase apparent sending end power with no UPFC action of the laboratory setup.

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The switching frequency is limited to 3 kHz. The DSpace Controller cycle time is 32 s. 50 rad/s. The system frequency is 50 Hz, meaning

ACKNOWLEDGMENT The rst author would like to thank J. Monteiro for his support and fruitful discussion during the experiments.

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[18] H. Kim and H. Akagi, The instantaneous power theory based on mapping matrices in three-phase four-wire systems, in Proc. Power Convers. Conf., 1997, pp. 361366. [19] K. Sedraoui, K. Al-haddad, A. Chandra, and G. Olivier, Versatile control strategy of the unied power ow controller, Proc. Can. Conf. Elect. Comput. Eng., vol. 1, pp. 142147, 2000. [20] C. Yam, and M. Haque, A svd based controller of upfc for power ow control, Elect. Power Syst. Res., no. 70, pp. 7984, 2004. [21] J. Verveckken, F. Silva, and J. Driesen, Design of inverse controller with cross-coupling suppression for UPFC series converter, in Proc. EUROCON Int. Conf. Comp. Tool, Warsaw, Poland, Sep. 912, 2007, pp. 26132619. [22] M. K. P. Antoniewicz, Predictive direct power control of three phase boost rectier, Bull. Polisch Acad. Sci., vol. 54, no. 3, 2006. [23] S. Venkateschwarlu, B. P. Muni, A. D. Rajkumar, and J. Praveen, Direct power control strategies for multilevel inverter based custom power devices, Int. J. Elect. Syst. Sci. Eng., vol. 1, no. 2, pp. 94102, 2008. [24] V. I. Utkin, Variable structure systems with sliding modes, IEEE Trans. Autom. Control, vol. AC-22, no. 2, pp. 212222, Apr. 1977. [25] V. I. Utkin, J. Guldner, and J. Shi, Sliding Mode Control in Electromechanical Systems. Boca Raton, FL: CRC, 1999. [26] J. Hung, W. Gao, and J. Hung, Variable structure control: A survey, IEEE Trans. Ind. Electron., vol. 40, no. 1, pp. 222, Feb. 1993. [27] J. Monteiro, J. Silva, S. Pinto, and J. Palma, Matrix converter-based unied power-ow controllers: Advanced direct power control method, IEEE Trans. Power Del., vol. 26, no. 1, pp. 420430, Jan. 2011. [28] J. Verveckken, F. A. Silva, D. Barros, and J. Driesen, Direct power control for universal power ow controller series converter, in Proc. IEEE ECCE Conf., 2010, pp. 40624067. [29] P. Kundur, Power System Stability and Control, N. J. Balu and M. G. Lauby, Eds. New York: McGraw-Hill, 1994. [30] J. J. Grainger and D. W. Stevenson, Power System Analysis, A. B. Akay and E. Castellano, Eds. New York: McGraw-Hill, 1994. [31] X. Jiang, J. Chow, A.-A. Edris, B. Fardanesh, and E. Uzunovic, Transfer path stability enhancement by voltage-sourced converter-based facts controllers, IEEE Trans. Power Del., vol. 25, no. 2, pp. 10191025, Apr. 2010. [32] F. A. Silva and S. F. Pinto, Control methods for switching power converters, in Power Electronics Handbook, M. H. Rashid, Ed., 2nd ed. London, U.K.: Academic/Elsevier, 2007, pp. 935998.

Jan Verveckken (S11) was born in Deurne, Antwerpen, Belgium, in 1983. He received the M.Sc. degree in electrical engineering from the University of Leuven (KULeuven), Leuven, Belgium, in 2006. He is a graduate student at KULeuven, where he works on the control of high-frequency power converters. His research interests are sliding mode control, exible ac transmission systems devices, electrical machines, and drives.

Fernando Silva (M92SM00) was born in Mono, Portugal, in 1956. He received the Dipl. Ing. degree in electrical engineering, the Ph.D. degree in electrical and computer engineering (EEC), and the Habilitation degree in EEC from the Instituto Superior Tcnico, Technical University of Lisbon, Lisbon, Portugal, in 1980, 1990, and 2002, respectively.

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Dionsio Barros (M04) received the Dipl.Ing. degree in systems and computer engineering from the University of Madeira, Funchal, Portugal, in 1998, and the M.Sc. degree in electrical and computer engineering, and the Ph.D. degree in electrical and computer engineering from the Instituto Superior Tcnico, Technical University of Lisbon, Lisbon, Portugal, in 2002 and 2008, respectively.

Johan Driesen (S93M97SM12) was born in Belgium in 1973. He received the M.Sc. degree in mechanical electrical engineering and the Ph.D. degree in electrical engineering from the KULeuven, Leuven, Belgium, in 1996 and 2000, respectively. His Ph.D. degree focused on the nite-element solution of coupled thermalelectromagnetic problems and related applications in electrical machines and drives, microsystems, and power-quality issues.