Co Data

Computer Science & Information Technology Department Prepared By: Govind Arya Page 1
Compiler Design Tutorial Kit

Gate Classes 2012
(A Course Conducted by Shivalik Training Academy)

CD_TK_01
GATE Topic: Overview of Compiler & Theory of Automata.
Topics to be covered: Phases of Compiler, Regular Expression, Finite Automata, NFA &
DFA
Study Material
Introduction
Computer programs are formulated in a programming language and specify classes of computing
processes. Computers, however, interpret sequences of particular instructions, but not program
texts. Therefore, the program text must be translated into a suitable instruction sequence before it
can be processed by a computer. This translation can be automated, which implies that it can be
formulated as a program itself. The translation program is called a compiler, and the text to be
translated is called source text (or sometimes source code).
It is not difficult to see that this translation process from source text to instruction sequence
(Assembly or Binary Code) requires considerable effort and follows complex rules. The
construction of the first compiler for the language FORTRAN (formula translator) around 1956
was a daring enterprise, whose success was not at all assured. It involved about 18 many years
of effort, and therefore figured among the largest programming projects of the time.
The intricacy and complexity of the translation process could be reduced only by choosing a
clearly defined, well structured source language.
The translation process is now guided by the structure of the analyzed text. The text is
decomposed, parsed into its components according to the given syntax. For the most elementary
components, their semantics is recognized, and the meaning (semantics) of the composite parts
is the result of the semantics of their components. Naturally, the meaning of the source text must
be preserved by the translation.

The translation process essentially consists of the following parts:

1. Lexical Analysis: The sequence of characters of a source text is translated into a
corresponding sequence of symbols of the vocabulary of the language. For instance,
identifiers consisting of letters and digits, numbers consisting of digits, delimiters and
operators consisting of special characters are recognized in this phase.

2. Syntax Analysis (parsing): The sequence of symbols is transformed into a
representation that directly mirrors the syntactic structure of the source text and lets this
structure easily be recognized.

3. Semantic Analysis (type checking): High-level languages are characterized by the fact
that objects of programs, for example variables and functions, are classified according to
their type. Therefore, in addition to syntactic rules, compatibility rules among types of
operators and operands define the language. Hence, verification of whether these


compatibility rules are observed by a program is an additional duty of a compiler. This
verification is called type checking.

4. Code Generation: On the basis of the representation resulting from step 2, a sequence
of instructions taken from the instruction set of the target computer is generated. This
phase is called code generation. In general it is the most involved part, not least because
the instruction sets of many computers lack the desirable regularity.

5. Code Optimization: Finally the generated code should be optimized to reduce the time
& space complexity. This is done by the code optimization phase.

To load the complete code of a compiler into memory, we need of large space. Hence the
multiple phases of a compiler are grouped together to generate the passes of compiler.
Only individual compiler pass would fit, and they could be loaded one after the other in sequence
and the whole compiler was called a multi pass compiler. The number of passes was typically
4 6.

Formal Languages: is a collection of strings, where format of string is important.
Examples of FL:
L1={ a
n
| n>=1 } i.e. L1= { a,aa, aaa, aaa, ..}
L2={ a
n
b
n
|n>=1

} i.e. L2={ ab, aab, abb,aaaabbb,.}

Regular Expression: In computing, a regular expression provides a concise and flexible means
for "matching" (specifying and recognizing) strings of text, such as particular characters, words,
or patterns of characters.
The concept of regular expressions was first popularized by utilities provided
by UNIX distributions. A regular expression is written in a formal language that can be
interpreted by a regular expression processor, which is a program that either serves as a parser
generator or examines text and identifies parts that match the provided specification.
Here are examples of specifications that could be expressed in a regular expression:
the sequence of characters "car" appearing consecutively in any context, such as in "car",
"cartoon", or "bicarbonate"
the sequence of characters "car" occurring in that order with other characters between them,
such as in "Icelander" or "chandler"
the word "car" when it appears as an isolated word
the word "car" when preceded by the word "blue" or "red"
the word "car" when not preceded by the word "motor"
a dollar sign immediately followed by one or more digits, and then optionally a period and
exactly two more digits (for example, "$100" or "$245.99").


Basic Concepts: A regular expression, often called a pattern, is an expression that specifies
a set of strings. It is more concise to specify a set's members by rules (such as a pattern) than by
a list.
Boolean "or"
A vertical bar separates alternatives. For example, gray|grey can match "gray" or "grey".
Grouping
Parentheses are used to define the scope and precedence of the operators (among other uses). For
example, gray|grey and gr(a|e)y are equivalent patterns which both describe the set of "gray" and
"grey".
Quantification
A quantifier after a token (such as a character) or group specifies how often that preceding
element is allowed to occur. The most common quantifiers are the question mark ?,
the asterisk *(derived from the Kleene star), and the plus sign + (Kleene cross).

? The question mark indicates there is zero or one of the preceding element. For
example, colou?r matches both "color" and "colour".
* The asterisk indicates there is zero or more of the preceding element. For
example, ab*c matches "ac", "abc", "abbc", "abbbc", and so on.
+ The plus sign indicates there is one or more of the preceding element. For
example, ab+c matches "abc", "abbc", "abbbc", and so on, but not "ac"

Standard Examples of Regular Expression: Alphabet is a set of symbols used in Regular
Language
a belongs to is a regular expression
is a regular expression for NULL Language
is a regular expression of single word of length 0
R=R1+R2 => L(R)=L(R1)+ L(R2)
R=R1.R2 => L(R)=L(R1) . L(R2)
R=R1* => L(R)= , R1, R1
2
, R1
3
, R1
4
,
*= ,
*
=
(a+b)= {a,b} A string of either a or b
(a+b)*={ ,aa, ab, ba, bb, aaab, bbaa, aaaaab, bbbbbbbaaaa, ..} All string using a & b
Exercise Set # CD_01
Key-1: Regular expression that derives all strings of as & bs-
Answer: (a+b)*


Key-2: Regular expression for each string that begin with a & end with b -
Answer: a(a+b)*b

Key-3: Regular expression for each string that first & last symbol are different-
Answer: a(a+b)*b + b(a+b)*a

Key-4: Regular expression for each string that first & last symbol are same-
Answer: {a(a+b)*a + + (a+b) + b(a+b)*b}

Key-5: Regular expression for all string having length exactly 3-
Answer: (a+b)(a+b)(a+b)= (a+b)
3

Key-6: Regular expression for all string having length at least 3-
Answer: (a+b)(a+b)(a+b)(a+b)*+ (a+b)*(a+b)
3
(a+b)*+(a+b)*(a+b)
3

Key-7: Regular expression for all string having length at most 3-
Answer: (a+b+ )
2

Key-8: Regular expression for all string having even length-
Answer: (ab+bb+ba+aa)* = ((a+b)
2
)*

Key-9: Regular expression for all string having odd length-
Answer: ((a+b)
2
)*(a+b) or (a+b)((a+b)
2
)*

Key-10: Regular expression for all string start with a, not having two consecutive b,s-
Answer: (a+ab)
+

Key-11: Regular expression for all string not having two consecutive b,s-
Answer: (b+ )(a+ab)* or (a+ba)*( +b)

Key-12: Regular expression for all string not having two consecutive as and b,s-
Answer: (b+ )(ab)*(a+ ) or (a+ )(ba)*( b+) or (ab)*(a+ )+(ba)*( b+)

Key-13: Regular expression for all string that containing two as, those are not consecutive-
Answer: (b*ab*ab*)
Key-14: Regular expression for all string that containing at most two as, those are not
consecutive-
Answer: b*(a+ )b**(a+ ) b*
Key-15: Regular expression for all string that containing at least two as -
Answer: (a+b)*a(a+b)*a(a+b)*
Key-16: For ={0, 1} Find regular expression not containing 100 as substring -
Answer: 0*1*01 or 0*(10+1)*
Practice Paper # CD_01

Q1-

To describe the complement of a language, it is very important to describe the ----------
of that language over which the language is defined.
a) String
b) Regular Expression
c) Alphabet


d) Word

Explanation:

Q2-Any language that can not be expressed by a RE is said to be regular language.
a) True
b) False

Explanation:

Q3-If L1 and L2 are regular languages is/are also regular language(s).
a) L1 + L2
b) L1L2
c) L1*
d) All of above

Explanation:

Q4-Let L is a language of words containing even number of as. Regular Expression is
a) (a+b)*aa(a+b)*
b) (b+ab*a)*
c) a+bb*aab*a
d)
a+b)*ab(a+b)*

Explanation:

Q5-Choose the incorrect statement:
a) (a+b)*aa(a+b)* generates Regular language.
b) A language consisting of all strings over ={a,b} having equal
c) number of as and bs is a regular language
d) Every language that can be expressed by FA can also be expressed by RE
e) None of these
Explanation:
Q6-If r1 =(aa + bb) and r2 =( a + b) then the language (aa + bb)(a + b) will be generated by
a) (r1)(r2)
b) (r1 + r2)
c) (r2)(r1)
d) (r1)*

Explanation:

Q7- Which is the correct regular expression for given transaction graph-


a) (aa+aa+(ab+ab)(aa+ab)*(ab+ba))*
b) (aa+bb+(ab+ba)(aa+bb)*(ab+ba))*
c) (aa+bb+(ab+ba)(aa+bb)(ab+ba))*
d) None of these
Explanation:

Q8-If L1 and L2 are regular languages then which statement is NOT true?
a) (L1/L2 is always regular)
b) L1+L2 are always regular
c) L1*l2 are always regular
d) None of them

Explanation:

Q9-(a+b)*a(a+b)*b(a+b)* is the RE of language defined over ={a,b} having at least one a
and one b-
a) True
b) False
c) Such a language does not exist
d) None of these

Explanation:

Q10-If r1 = (aa + bb) and r2 = ( a + b) then the language (a + b)* (aa + bb)* will be
generated by-
a) (r2)(r1)
b) (r1 + r2)*
c) (r2)*(r1)*
d) (r1)*
Explanation:
Q11-The string 1101 does not belongs to the regular expression represented by-
a) 110*(01)
b) 1(0+1)*101
c) (10)*(01)*(00+11)*
d) ((00+(11)*0)*
Explanation:

Q12- The RE (00)*( +0) is equal to-
a) (00)*


b) 0*
c) 0(00)*
d) All above

Explanation:

Q13- Construct FA (DFA), that accepts all strings of as & bs excluding -

Q14- Construct DFA (minimum), that accepts all strings of as & bs starting with a-

Q15- Construct DFA (minimum), that accepts all strings of as & bs , where the length of
string is exactly 3.

Q16- Construct DFA (minimum), that accepts all strings of as & bs , where the length of
string is divisible by 3.

Q17- Construct DFA (minimum) for sequence ababa that accepts all strings
generated from prefixes of given sequence.

Q18- Construct a DFA that accepts all binary numbers which are divisible by 2. The
minimum numbers of states & final states in the above DFA is-

a) 2 & 1 b) 2 & 2 c) 1 & 2 d) 3 & 2 e) None
CD_TK_02
GATE Topic: Overview of Compiler & Theory of Automata.
Topics to be covered: Context Free & context Sensitive Grammar, ambiguous &
unambiguous grammar, left recursion & left factored grammar

Study Material
Context-free grammar Vs. Context-sensitive grammar

Context-Free Grammar (CFG): In formal language theory, a context-free grammar (CFG) is a
grammar in which every production rule is of the form-
V w
- Where V is a single non-terminal symbol
- w is a string of terminals and/or non-terminals (possibly empty).


The term "context-free" expresses the fact that non-terminals can be rewritten without regard to the
context in which they occur. A formal language is context-free if some context-free grammar generates
it.
Context-free grammars play a central role in the -
- Description and design of programming languages and compilers.
- They are also used for analyzing the syntax of natural languages.
Context-free grammars are simple enough to allow the construction of efficient parsing algorithms.
A context-free grammar G is defined by the 4-tuples-

1. is a finite set; each element is called a non-terminal character or a variable. Each
variable represents a different type of phrase or clause in the sentence.
2. is a finite set of terminals, disjoint from , which make up the actual content of the sentence.
The set of terminals is the alphabet of the language defined by the grammar .
3. is a finite relation from to . The members of are called the (rewrite) rules
or productions of the grammar. (also commonly symbolized by a )
4. is the start variable (or start symbol), used to represent the whole sentence (or program). It
must be an element of .

Context-Sensitive Grammar (CSG): is a formal grammar in which the left-hand sides and right-hand
sides of any production rules may be surrounded by a context of terminal and non-terminal symbols.
Context-sensitive grammars are more general than context-free grammars but still orderly enough to
be parsed by a linear bounded automaton.
A formal grammar G = (N, , P, S) ( this is the same as G = (V, T, P, S), just that the Non-Terminal
V(ariable) is replaced by N and T(erminal) is replaced by ) is context-sensitive if
All rules in P are of the form- A
- A N (i.e., A is a single non-terminal)
- , (N U )* (i.e., and are strings of non-terminals and terminals)
- (N U )
+
(i.e., is a nonempty string of non-terminals and terminals).
The name context-sensitive is explained by the and that form the context of A and determine
whether A can be replaced with or not. This is different from a context-free grammar where the
context of a non-terminal is not taken into consideration. (Indeed, every production of a context free
grammar is of the form V w where V is a single non-terminal symbol, and w is a string of terminals
and/or non-terminals (w can be empty)).
Ambiguous Grammar: A grammar is ambiguous if it has more than one parse tree for the same input
sequence depending which derivations are applied each time.
A A + A | A A | a
is ambiguous since there are two leftmost derivations for the string a + a + a:
As another example, the grammar is ambiguous since there are two parse trees for the string a + a a:


LEFT RECURSION: A grammar is said to be left recursive if it has a non-terminal A such that there is
a derivation A A, for some string . Topdown parsing methods cannot handle left recursive
grammars, so a transformation that eliminates left-recursion is needed.
Immediate left recursion
Immediate left recursion occurs in rules of the form A A|
Where and are sequences of non-terminals and terminals, and doesn't start with A.
For example, the rule ExpExp+Term
is immediately left-recursive. The recursive descent parser for this rule might look like:
function Expr()
{
Expr(); match('+'); Term();
}
and a recursive descent parser would fall into infinite recursion when trying to parse a grammar which
contains this rule.
Indirect left recursion
Indirect left recursion in its simplest form could be defined as:

possibly giving the derivation
More generally, for the non-terminals , indirect left recursion can be defined as being
of the form:

Where are sequences of non-terminals and terminals.

Removal of Indirect Left Recursion:
The Grammar: S Aa | b A Ac | Sd | e Demonstrates indirect left recursion

To remove indirect left recursion there must be no productions
1. Order non-terminals as A1, A2, An
2. for (i = 1; i <=n; ++i)


{
for (j = 1; j <= i 1; ++j)
{
Replace each production of the form Ai -> Ajy
By the productions Ai -> 1y | 2y | . | ky
where Aj -> 1 | 2 | | k are all the current
Aj productions.
}
eliminate the immediate left recursion among all Ai productions.
}

Solution: Let S = A1 A = A2 A1 A2a | b A2 A2c | A1d | e

i = 1: No immediate left recursion in A1 productions.
i = 2: Replace With A2 A1d A2 1y | 2y where 1 = A2a, 2 = b, y = d
rule(Ai -> Ajy)

new rule: A2 A2c | A2ad | bd | e
result: A1 A2a | b A2 A2c | A2ad | bd | e

Eliminate immediate left recursion in A2 productions:
for A A | = {bd, e} A2 bdA2 | eA2
then A A = {c, ad} A2 cA2 | adA2 |
A A |

Final Grammar: S Aa | b
A bdA | eA
A cA | adA |

LEFT FACTORING: Left factoring is a grammar transformation that is useful for producing a grammar
suitable for predictive parsing. The basic idea is that when it is not clear which of two alternative
productions to use to expand a non-terminal A, we may be able to rewrite the A-productions to defer the
decision until we have seen enough of the input to make the right choice.

For example,
A1 | 2 are two A-productions, and the input begins with a non-
do not know whether to expand A to 1 or 2 However, we may defer the decision by expanding A to
B. Then, after seeing the input derived from , we may expand B to 1 or 2.The left factored original
expression becomes:
AB B 1 | 2



Q1- The language generated by the context free grammar

S aSb| ab is-
a) {a
n
b
n
: n>=1} b) {a
n
b
n
: n>1} c) {a
n
b
n
: n>=0} d) {a
n
b
n
: n>0}

Q2- The language generated by the context free grammar

S bSbb | A , A aA | is-
a) {b
n
a
m
b
2n
: n>=0, m>=1} c) {b
n
a
m
b
2n
: n>=1, m>=0}
b) {b
n
a
m
b
2n
: n>=1, m>=1} d) {b
n
a
m
b
2n
: n>=0, m>=0}

Q3- If a parser is using leftmost derivation LMD to parse the input. The most correct statement is-
a) Only the leftmost non-terminal is replaced at every step
b) The leftmost non-terminal is replaced when needed
c) It is depend on the input sequence to be parse
d) The input string is parsed from left to right

Q4- Which is wrong statement for ambiguous grammar-
a) A grammar that produces more than one parse tree for some sentences
b) A grammar that must produce more than one parse tree for every sentence
c) A grammar that produces more than one leftmost derivation for some sentences
d) A grammar that produces more than one rightmost derivation for some sentences

Q5- Which is the correct parse tree for id:=id+id*id , if + have higher precedence than *


(a) (b)

(c) Both a & b (d) neither a or b

Q6- The necessary rule to make a grammar G= {EE*E | E+E | (E) | id} unambiguous-
a) Operator associatively b) Operator precedence c) both a & b d) Neither a or b

Q7- Which grammar may produce wrong result for an arithmetic equation if LMD is used-
a) EE*E | E+E | id c) EE*E | E/E | id
b) EE*E +E | id d) AB-C , BP+P , CP*P , Pid
Q8- A CFG= {SaA | bA , AaA | bA | 0A | 1A | } cab be represented by the RE-
a) (a|b)(a|b|0|1)* b) (a|b)(a|b|0|1)
+
c) (a|b)*(a|b|0|1)* d) (a|b)
+
(a|b|0|1)

Q9- Consider the grammar G={SA, AAd|Ae|aB|aC , BbBC|f , Cg },
After removing left recursion, total minimum number of non-terminals are-
a) 3 b) 4 c) 5 d) 6
Q10- Consider the grammar G={SA, AAd|Ae|aB|aC , BbBC|f , Cg },
After removing left recursion, how many production contain -
a) 0 b) 1 c) 2 d) 3
Q11- Consider the grammar G={S(L) | a , LL, S | S } After removing left recursion, we get-
a) {S(L) | a , LSA , ASA| } c) {S(L) | a , LSA , A,SS| }
b) {S(L) | a , LSA , ASA } d) {S(L) | a , LSA , ASS| }

Q12- Consider the grammar G={SiCtS | iCtSeS | a , Cb} After left-factored we get-
a) {SiCtSS | a , SeS | , Cb } c) {SiCtST | a , TeS | , Cb }
b) {SiCtSS | , SeS | a , Cb } d) {SiCtSS , SeS | a , Cb| }
Q13- Consider the grammar G={SabCDe | aBd | abcD | abcd | a , B g , Cg , D f| }
after left-factored, minimum number of non-terminals are -
a) 4 b) 5 c) 6 d) 7 e) 8 f) 9 g) None
Q14- Consider the grammar G={SabCDe | aBd | abcD | abcd | a , B g , Cg , D f| }
after left-factored, How many production contain -
a) 1 b) 2 c) 3 d) 4 e) 5 f) 6 g) None
Q15- Which grammar contain left recursion-
a) SASB A a | c) BCDB| Ca | DGB | G
b) EE+E | id d) both a & b e) None
Q16- To apply top-down parsing, a grammar must be-
a) Left recursion free b) left factored c) CFG d) a, b e)None


CD_TK_03
GATE Topic: Parsing
Topics to be covered: Need of FIRST & FOLLOW calculation, their algorithms & Use.

Study Material
The construction of a predictive parser is aided by two functions associated with a grammar G. These
functions, FIRST and FOLLOW, allow us to fill in the entries of a predictive parsing table for G,
whenever possible. Sets of tokens yielded by the FOLLOW function can also be used as synchronizing
tokens during panic-mode error recovery.
just suppose for a sec that you r ll(1) parser and you have n supernatural power of seeing the future of
string by one step. in above statement that supernatural power is nothing but finding follow of given non-
terminal to predict the next items.... hope u got the point ...n ya dnt take super natural shit seriously ... ;)

FIRST()
If is any string of grammar symbols, let FIRST() be the set of terminals that begin the strings derived
from . If then is also in FIRST().
To compute FIRST(X) for all grammar symbols X, apply the following rules until no more terminals or
can be added to any FIRST set:

Algorithm to compute FIRST ()
1. If X is terminal, then FIRST(X) is {X}.
2. 2.If X is a production, then add to FIRST(X).
3. 3.If X is nonterminal and X Y1 Y2 ... Yk . is a production, then place a in FIRST(X) if for
some i, a is in FIRST(Yi), and is in all of FIRST(Y1), ... , FIRST(Yi-1); that is, Y1, ... ,Yi-1
. If is in FIRST(Yj) for all j = 1, 2, ... , k, then add to FIRST(X). For example, everything in
FIRST(Y1) is surely in FIRST(X). If Y1 does not derive , then we add nothing more to
FIRST(X), but if Y1 , then we add
4. FIRST(Y2) and so on. Now, we can compute FIRST for any string X1X2 . . . Xn as follows. Add
to FIRST(X1X2 ... Xn) all the non- symbols of FIRST(X1). Also add the non- symbols of
FIRST(X2) if is in FIRST(X1), the non- symbols of FIRST(X 3) if is in both FIRST(X 1) and
FIRST(X2), and so on. Finally, add to FIRST(X1X2 ... Xn) if, for all i, FIRST(X i) contains .

FOLLOW(A)
Define FOLLOW(A), for non-terminal A, to be the set of terminals a that can appear immediately to the
right of A in some sentential form, that is, the set of terminals a such that there exists a derivation of the
form Sa for some and . Note that there may, at some time during the derivation, have been
symbols between A and a, but if so, they derived and disappeared. If A can be the rightmost symbol in
some sentential form, then $, representing the input right end marker, is in FOLLOW (A).
To compute FOLLOW (A) for all non-terminals A, apply the following rules until nothing can be added
to any FOLLOW set:

Algorithm to compute FOLLOW (X)
1. Place $ in FOLLOW(S), where S is the start symbol and $ is the input right end marker.
2. If there is a production A , then everything in FIRST(), except for , is placed in
FOLLOW(B).
3. If there is a production A , or a production A where FIRST() contains (i.e.,
), then everything in FOLLOW(A) is in FOLLOW(B).
EXAMPLE
Consider the expression grammar:


E T E
E + T E |
T F T
T * F T |
F ( E ) | id

Then:
FIRST(E) = FIRST(T) = FIRST(F) = {( , id}
FIRST(E) = {+, }
FIRST(T) = {*, }
FOLLOW(E) = FOLLOW(E) = {) , $}
FOLLOW(T) = FOLLOW(T) = {+, ), $}
FOLLOW(F) = {+, *, ), $

Why Do We Care about FIRST ()?
During parsing, suppose the top-of-stack symbol is non-terminal A, that there are two
productions:
1. A
2. A
And that the current token is x
If x is in FIRST() then use first production
If x is in FIRST() then use second production

FOLLOW(A) sets
Only defined for single non-terminal, A
The set of terminals that can appear immediately to the right of A (may include EOF but never )

FIRST and FOLLOW sets
To compute FIRST(A) you must look for A on a production's left-hand side.
To compute FOLLOW(A) you must look for A on a production's right-hand side.
FIRST and FOLLOW sets are always sets of terminals (plus, perhaps, for FIRST sets, and EOF
for follow sets).
Non-terminals are never in a FIRST or a FOLLOW set.

Example FOLLOW(X) sets
Upper case are non-terminals and lower-case are terminals
S B c | D B
B a b | c S
D d |

X FIRST(X) FOLLOW(X)

D { d, } { a, c }
B { a, c } { c, EOF }
S { a, c, d } { EOF, c }

Note: FOLLOW of S always includes EOF

Consider the following context free grammar-
S A
A BC | DBC
B bB |


B bB |
C c |
D a | d

Q1- How many productions contains -
b) 0 b) 1 c) 2 d) 3

Q2- Which is the correct statement for the above grammar-
a) FIRST(S) = FIRST(A) c) FIRST(A) = FIRST(B) e) FIRST(A) = FIRST(D)
b) FIRST(B) FIRST(B) d) All f) None

Q3- Which is NOT the correct statement for the above grammar-
a) FIRST(B) = FOLLOW(B) c) FIRST(C) = FOLLOW(B) e) FOLLOW(S) = FOLLOW(A)
b) FOLLOW(A) = FOLLOW(C) d) FOLLOW(B) {c} = FOLLOW(C) f) All

Consider the following context free grammar-
S ( )
S a
S ( A )
A S
A A , S

Q4- After removing left recursion, the total number of Non-terminals are -
c) 2 b) 3 c) 5 d) 6 e) 7

Q5- After removing left recursion, the total number of productions are -
a) 2 b) 3 c) 4 d) 5 e) 6

Q6- After removing left recursion, the total number of productions that contains are -
a) 0 b) 1 c) 2 d) 3 e) 4

Q7- After removing left recursion, the total number of productions that contains { ) } are -
a) 0 b) 1 c) 2 d) 3 e) 4

Q8- After removing left recursion, the total number of non-terminals that contains { ) } are -
a) 0 b) 1 c) 2 d) 3 e) 4

Q9- Which is the correct statement for the above grammar-
a) FIRST(S) = FIRST(A) c) FIRST(A) = {a} e) FIRST(S) = { ( }
b) FIRST(S) FIRST(A) d) All f) None

Q10- Which is NOT the correct statement for the above grammar-
a) FOLLOW(S) FOLLOW(A) c) FOLLOW(S) = {$,
,
} e) FOLLOW(A) = {$,
,
}
b) FIRST(S) = FOLLOW(A) d) All f) None

Q11- After removing left recursion, how many non-terminal X have same set of FOLLOW(X) -


a) 0 b) 1 c) 2 d) 3 e) 4

Q12- After removing left recursion, how many non-terminal contains { ( } & { ) } in its FIRST set-
a) 0 b) 1 c) 2 d) 3 e) 4

CD_TK_04
GATE Topic: Parsing
Topics to be covered: Top-down parsing & Bottom up parsing
Study Material
A top-down parser begins with the start symbol at the top of the parse tree and works downward, driving
productions in forward order until it gets to the terminal leaves. A bottom-up parse starts with the string
of terminals itself and builds from the leaves upward, working backwards to the start symbol by applying
the productions in reverse. Along the way, a bottom-up parser searches for substrings of the working
string that match the right side of some production. When it finds such a substring, it reduces it, i.e.,
substitutes the left side non terminal for the matching right side. The goal is to reduce all the way up to
the start symbol and report a successful parse.
In general, bottom-up parsing algorithms are more powerful than top-down methods, but not surprisingly,
the constructions required are also more complex. It is difficult to write a bottom-up parser by hand for


anything but trivial grammars, but fortunately, there are excellent parser generator tools like yacc that
build a parser from an input specification, not unlike the way lex builds a scanner to your spec.

Top-Down Parsing:
1. A parser is top-down if it discovers a parse tree top to bottom
2. A top-down parse corresponds to a preorder traversal of the parse tree
3. A leftmost derivation is applied at each derivation step

Top-down parsers come in two forms-
1. Predictive Parsers: Predict the production rule to be applied using look ahead tokens
2. Backtracking Parsers: Will try different productions, backing up when a parse fails

- Predictive parsers are much faster than backtracking ones
- Predictive parsers operate in linear time
- Backtracking parsers operate in exponential time

Two kinds of basic top-down parsing techniques -
1. Recursive-descent parsing
2. LL parsing

Top-Down Parsing by Recursive-Descent
- We view a non terminal A as a definition of a procedure A
- Procedure A will match the token sequence generated by non terminal A
- The RHS of a production of A specifies the code for procedure A
- Terminals are matched against input tokens
- Non terminals produce calls to corresponding procedures
- If multiple production rules exist for a non terminal A one of them is predicted based on a look
ahead token
- The look ahead token is the next input token that should be matched
- The predicted rule is the only one that applies other rules will not be tried
- This is a predictive parsing technique, not a backtracking one
- A syntax error is detected when next token in the input sequence does not match the expected
token
Bottom- Up Parsing:
A bottom-up parser creates the parse tree of the given input starting from leaves towards the root.
A bottom-up parser tries to find the right-most derivation of the given input in the reverse order.
S ... e (the right-most derivation of e)
(the bottom-up parser finds the right-most derivation in the reverse order)
Bottom-up parsing is also known as shift-reduce parsing because its two main actions are shift and
reduce.
- At each shift action, the current symbol in the input string is pushed to a stack.
- At each reduction step, the symbols at the top of the stack (this symbol sequence is the right side
of a production) will replaced by the non-terminal at the left side of that production.
- There are also two more actions: accept and error.

Shift-Reduce Parsing Example 1:
S aABb input string: aaabb
A aA | a aaAbb
B bB | b aAbb reduction
aABb
S


S aABb aAbb aaAbb aaabb
Right Sentential Forms

Shift-Reduce Parsing Example 2:
E E+T | T Right-Most Derivation of id+id*id
T T*F | F E E+T E+T*F E+T*id E+F*id
F (E) | id E+id*id T+id*id F+id*id id+id*id

Right-Most Sentential Form Reducing Production
id+id*id F id
F+id*id T F
T+id*id E T
E+id*id F id
E+F*id T F
E+T*id F id
E+T*F T T*F
E+T E E+T
E
Handles are underlined in the right-sentential forms.

There are two main categories of shift-reduce parsers-
1. Operator-Precedence Parser: simple, but only a small class of grammars.
2. LR-Parsers: covers wide range of grammars.

SLR simple LR parser
LR most general LR parser
LALR intermediate LR parser (look ahead LR parser)

Note: SLR, LR and LALR work same, only their parsing tables are different.

Q1- Context free grammar is used to -
d) Define the syntax of PL b) Parse a string c) Both a & b d) Neither a or b

Q2- The output of a parser should be in the form of -
a) A Parse Tree b) IR c) Syntax Tree d) Both a & c

Q3- The operator precedence parser is especially suitable for parsing-
a) Production having two adjacent non-terminals c) Any language
b) Expression b) Both a & b

Q4- Which is not the correct statement-
a) Predictive parsers are much faster than backtracking ones
b) Predictive parsers operate in linear time
c) Backtracking parsers operate in exponential time
d) The predictive parser predicted a production to applies other rules will not be tried
e) The recursive decent parsing is a backtracking parsing technique.

Q5- LL (1) is a _______ parsing technique -
a) Top-Down Parsing b) Bottom-Up Parsing c) Both a & b d) None


Q6- SLR is a _______ parsing technique -

Q7- Operator Precedence Parsing is a _______ parsing technique -

Q8- Which is the wrong statement for LR parsing -
a) L denotes Left Derivation c) L denotes Left to Right e) Both a & d
b) R denotes Right Derivation d) R denotes Right to left f) None

Consider the grammar-
E E+T | T
T T*F | F
F (E) | id

Q9- If shift reduce parsing is used, the total number of handle for the input string id+id*id -
a) 5 b) 6 c) 7 d) 8 e) 9 f) Not fixed

Q10- The problem during shift reduce parsing -
a) Shift/Reduce conflict b) Reduce/ Reduce Conflict c) Both a & b d) None

CD_TK_05
GATE Topic: Parsing
Topics to be covered: Bottom up parsing, SLR, CLR, LALR
Study Material
Bottom- Up Parsing:
Stack Implementation of a Bottom-Up Parser
- A bottom-up parser uses an explicit stack in its implementation
- The main actions are shift and reduce
- A bottom-up parser is also known as as shift-reduce parser
- Four operations are defined: shift, reduce, accept, and error
- Shift: parser shifts the next token on the parser stack
- Reduce: parser reduces the RHS of a production to its LHS
- The handle always appears on top of the stack
- Accept: parser announces a successful completion of parsing
- Error: parser discovers that a syntax error has occurred

The parser operates by:
1. Shifting tokens onto the stack
2. When a handle is on top of stack, parser reduces to LHS of production
3. Parsing continues until an error is detected or input is reduced to start symbol


LR Parsing
To have an operational shift-reduce parser, we must determine:
- Whether a handle appears on top of the stack, the reducing production to be used
- The choice of actions to be made at each parsing step

LR parsing provides a solution to the above problems
- Is a general and efficient method of shift-reduce parsing
- Is used in a number of automatic parser generators

The LR (k) parsing technique was introduced by Knuth in 1965
- L is for Left-to-right scanning of input
- R corresponds to a rightmost derivation done in reverse
- k is the number of look ahead symbols used to make parsing decisions

Four LR parsing techniques will be considered

1. LR(0) : LR parsing with no look ahead token to make parsing decisions
2. SLR(1) : Simple LR, with one token of look ahead
3. LR(1) : Canonical LR, with one token of look ahead
4. LALR(1) : Look ahead LR, with one token of look ahead

LALR (1) is the preferable technique used by parser generators


LR (0) Parser Generation Initial State

Consider the following grammar G1:
1: EE + T 3: TID
2: E T 4: T ( E )

For LR parsing, grammars are augmented with a . . .
- New start symbol S
- New start production 0: S E $
- The input should be reduced to E followed by $
- We indicate this by the item: S E $
- The initial state (numbered 0) will have the item: SE $
- An LR parser will start in state 0
- State 0 is initially pushed on top of parser stack

Identifying the Initial State
- Since the dot appears before E, an E is
expected
- There are two productions of
- E: E E + T and E T
- Either E+T or T is expected
- The items: E E + T and E T are
added to the initial state
- Since T can be expected and there are
two productions for T either ID or ( E )
can be expected
- The items: T ID and T ( E ) are
added to the initial state

The initial state (0) is identified by the
following set of items


Shift Actions
- In state 0, we can shift either an ID or a left parenthesis
- If we shift an ID, we shift the dot past the ID
- We obtain a new item TID and a new state (state 1)
- If we shift a left parenthesis, we obtain T( E )
- Since the dot appears before E, an E is expected
- We add the items E E + T and ET
- Since the dot appears before T, we add T ID and T ( E )
- The new set of items forms a new state (state 2)
- In State 2, we can also shift an ID or a left parenthesis as shown

Reduce and Goto Actions
- In state 1, the dot appears at the end of item TID
- This means that ID appears on top of stack and can be reduced to T
- When appears at end of an item, the parser can perform a reduce action
- If ID is reduced to T, what is the next state of the parser?
- ID is popped from the stack; Previous state appears on top of stack
- T is pushed on the stack
- A new item ET and a new state (state 3) are obtained
- If top of stack is state 0 and we push a T, we go to state 3
- Similarly, if top of stack is state 2 and we push a T, we go also to state 3


LR(0) Parsing Table
- The LR(0) parsing table is obtained from the LR(0) state diagram
- The rows of the parsing table correspond to the LR(0) states
- The columns correspond to tokens and non-terminals
- For each state transition ij caused by a token x
- Put Shift j at position [i, x] of the table
- For each transition ij caused by a non terminal A
- Put Goto j at position [i, A] of the table
- For each state containing an item A of rule n
- Put Reduce n at position [i, y] for every token y
- For each transition i Accept
- Put Accept at position [i, $] of the table

LR(0) Parsing Table
The LR(0) table of grammar G1 is shown below
- For a shift, the token to be shifted determines the next state
- For a reduce, the state on top of stack specifies the production to be used

Limitations of the LR(0) Parsing Method
Consider grammar G2 for matched parentheses


0: SS$ 1: S( S ) S 2: S

The LR(0) DFA of grammar G2 is shown below
In states: 0, 2, and 4, parser can shift ( and reduce to S

Q1- Context free grammar is used to -
e) Define the syntax of PL b) Parse a string c) Both a & b d) Neither a or b

Q2- The output of a parser should be in the form of -
b) A Parse Tree b) IR c) Syntax Tree d) Both a & c

Q3- The operator precedence parser is especially suitable for parsing-
c) Production having two adjacent non-terminals c) Any language
d) Expression b) Both a & b

Q4- Which is not the correct statement-
f) Predictive parsers are much faster than backtracking ones
g) Predictive parsers operate in linear time
h) Backtracking parsers operate in exponential time
i) The predictive parser predicted a production to applies other rules will not be tried
j) The recursive decent parsing is a backtracking parsing technique.


Q5- LL (1) is a _______ parsing technique -
b) Top-Down Parsing b) Bottom-Up Parsing c) Both a & b d) None

Q6- SLR is a _______ parsing technique -

Q7- Operator Precedence Parsing is a _______ parsing technique -

Q8- Which is the wrong statement for LR parsing -
c) L denotes Left Derivation c) L denotes Left to Right e) Both a & d
d) R denotes Right Derivation d) R denotes Right to left f) None

Consider the grammar-
E E+T | T
T T*F | F
F (E) | id

Q9- If shift reduce parsing is used, the total number of handle for the input string id+id*id -
b) 5 b) 6 c) 7 d) 8 e) 9 f) Not fixed

Q10- The problem during shift reduce parsing -
b) Shift/Reduce conflict b) Reduce/ Reduce Conflict c) Both a & b d) None

Consider the following augmented grammar-
E E
E E+T | T
T T*F | F
F (E) | id

Q11- If I is the set of item {[ET]}, then the CLOSURE (I) contains LR (0) items -
a) {[ T T*F | F] , [ E E+T | T]} c) {[ T T*F | F] , [ E E+T | T]}
b) {[ T T*F | F],[ E E+T | T]} d) {[ T T*F] , [ TF] , [F(E)| id]}

Q12- If I is the set of item {[E(E)]}, then the CLOSURE (I) contains LR (0) items -
a) {[ E E+T | T] , [ E T*F | F] , [F (E)| id]} c) {[ E (E) | id] , [ E E+T]}
b) {[ E E+T | T] , [ E T*F | F] , [F(E)| id]} d) {[E(E)] , [Eid]}

Q13- If I is the set of item {[EE] , [E E+T] }, then the GOTO (I , +) contains LR (0) items -
a) {[ EE+ T ] , [ T T*F | F] , [F(E)| id]} c) {[ E E] , [ E E+T]}
b) {[ EE+ T ] , [ T T*F | F] , [F(E)| id]} d) {[EE+T}

Consider the following augmented grammar-
S S
S CC


CcC | d

Q14- If I is the set of item {[SCC, $]}, then the CLOSURE (I) contains LR (1) items -
a) {[ C cC , $], [ C d , $]} c) {[ S CC , $] , [ C cC , $]}
b) {[ C cC , $], [ C d , $]} d) {[ S CC , $] , [ C cC , $]}

Q15- If I is the set of item {[SS, $]}, then the CLOSURE (I) contains LR (1) items -
a) {[ S CC , $], [ C cC , c] , [C d , c/d]}
b) {[ S CC , $], [ C cC , c/d] , [C d , c]}
c) {[ S CC , $], [ C cC , c/d] , [C d , c/d]}
d) {[ S CC , $], [ C cC , $] , [C d , $]}

Q16- If state I
1
contains {[Cd, c/d]} and state I
2
contains {[Cd, $]}, then a combined state I
12
of
LR(1) items in LALR parsing will contain

-
a) {[ C d , c/d]} c) {[ C d , c/d/$]}
b) {[ C d , c/$]} c) {[ C d , d/$]}

TK01
Computer Organization
GATE Topic: Machine Instructions
Topics to be covered: Different CPU Organization-Stack, Accumulator, GPR Organization

Study Material
1.1 Introduction
The CPU consists of a set of registers that function as a level of memory above Main memory
and Cache memory. The registers in the CPU are of two types:


User-visible Registers: These enable the machine or assembly language programmer to
minimize main memory references by use of registers.
Control and Status Registers: These are used by the control unit to control the operation of the
CPU and by privileged operating system programs to control the execution of programs.
Note: Sometimes there is no clear separation of registers into these categories. For example, on
some of the machines the register called Program Counter (PC) is user visible, that is, user can
see the contents of PC, but on some machines it is invisible to the user.
Objectives:
1. Explain the register organization of any basic computer.
2. Explain status word, program counter registers.
3. Discuss the register organization of Intel 8085 microprocessor and compare with other
machines.
4. Explain the different phases of basic instruction cycle.
Registers
User-Visible Registers
User visible registers are those registers that are used by the user in the machine language and
can be executed by the CPU. All CPU designs provide a number of user visible registers. These
registers can be categorized into following different types:
General Purpose Registers: They can be assigned a variety of functions by the programmer.
The general purpose registers can be considered for orthogonal usage and non-orthogonal usage.
-If any general purpose register can contain the operand for any opcode then we refer the use of
general purpose as orthogonal usage.
-Sometimes the use of general purpose register is restricted. For example, there may be dedicated
registers that are used for floating point operations. Then we refer to the use of general purpose
as non orthogonal usage.
Data registers: They can only be used to hold data, and cannot be employed in the calculation of
an operand address.
Address registers: They may be used either in general purpose addressing modes, or may be
devoted to a particular addressing mode.
Segment Pointers: In a machine CPU with segmented addressing, a register holds the address of
the base of a segment. There may be multiple segment registers. For example, one for the
operating system, one for the current process.


For example, Intel 8086 family has different segments and they are referred to as
1) code segment: where the code is written
2) data segment: where the data is placed
3) stack segment: acts like a stack
4) extra segment
Thus there may be many registers one for operating system and one for the current process.
Index Registers: These are used for indexed addressing, and may be auto indexed.
Stack Pointer: If there is a user-visible stack addressing, then typically the stack is in memory
and there is a dedicated register that points to the top of the stack. This allows implicit
addressing, that is push, pop and other stack instructions need not contain an explicit stack
operand.
Condition codes: These are least partially visible register types. They are also referred to as
flags. The bits of Flag register are set according to the result of an operation. There can be Zero
flag, Carry flag, etc., that indicate whether the result is zero or the result produced an overflow,
respectively.
Example: Consider the length of all registers to be two bits long. The result of adding two binary
numbers 10 and 11 will be 101. That is
1) The result will be stored in a destination register which will be 01.
2) And the carry is set as there is overflow after execution.
Control and Status Registers
These registers are employed to control the operation of the CPU.
Four registers are essential to instruction execution:
Program Counter (PC): It contains the address of an instruction to be fetched.
Instruction Register (IR): It contains the instruction most recently fetched.
Memory Address Register (MAR): It contains the address of a location in memory.
Memory Buffer Register (MBR): It contains a word of data to be written to memory or the
word most recently read.
These four registers are used for the movement of data between the CPU and memory.


Within the CPU, data must be presented to the ALU for processing. The ALU may have direct
access to the MBR and user-visible registers. Alternatively, there may be additional buffering
registers at the boundary to the ALU; and these registers serve as input and output registers for
the ALU and exchange data with MBR and user-visible registers. This depends on the design of
the CPU and ALU.
Program Status Word (PSW):
It contains status information. PSW typically contains condition codes plus other status
information. Some of these may be user visible. Common flags include:
Sign: contains the sign bit of the result of the last arithmetic operation.
Zero: set when the result is 0.
Carry: set if an operation resulted in a carry (addition) into or borrow (subtraction) out of the
high-order bit.
Equal: set if logical compare result is equality.
Overflow: used to indicate arithmetic overflow.
Interrupt enable/disable: used to enable or disable interrupts.
Supervisor: Indicates whether the CPU is executing in supervisor mode or user mode. Certain
privilege instructions can be executed only in supervisor mode (e.g. halt instruction), and certain
areas of memory can be accessed only in supervisor mode.
1.2 CPU organization

Figure 1.1: CPU with System Bus


As discussed earlier CPU which is the heart of a computer consists of Registers, Control Unit
and Arithmetic Logic Unit. The interconnection of these units is achieved through the system bus
as shown in figure.
The following tasks are to be performed by the CPU:
1. Fetch instructions: The CPU must read instructions from the memory.
2. Interpret instructions: The instructions must be decoded to determine what action is
required.
3. Fetch data: The execution of an instruction may require reading data from memory or an I/O
module.
4. Process data: The execution of an instruction may require performing some arithmetic or
logical operations on data.
5. Write data: The results of an execution may require writing data to the memory or an I/O
module.

Fundamental Computer Architectures
Here we describe the most common Computer Architectures, all of which use stored program
control concept.
The three most popular computer architectures are:
1) The Stack Machine
2) The Accumulator Machine
3) The Load / Store Machine
The Stack Machine
A stack machine implements a stack with registers. The operands of the ALU are always the top
two registers of the stack and the result from the ALU is stored in the top register of the stack.
Examples of the stack machine include Hewlett-Packard RPN calculators and the Java Virtual
Machine (JVM).


Figure 1.2: The Stack Machine Architecture
The advantage of a stack machine is that it can shorten the length of instructions since operands
are implicit. This was important when memory was expensive (2030 years ago). Now, in Java,
it is important since we want to ship executables (class files) over the network.
The Accumulator Machine
An accumulator machine has a special register, called an accumulator, whose contents are
combined with another operand as input to the ALU, with the result of the operation replacing
the contents of the accumulator.
Accumulator = accumulator [op] operand;

Figure 1.3: The Accumulator Machine Architecture


In fact, many machines have more than one accumulator
Pentium: 1, 2, 4 or 6 (depending on how you count)
MC68000: 16
In order to add two numbers in memory,
1) Place one of the numbers into the accumulator (load operand)
2) Execute the add instruction
3) Store the contents of the accumulator back into memory (store operand)
The Load/Store Machine
Registers: Provide faster access but are expensive.
Memory: Provides slower access but is less expensive.
A small amount of high speed memory (expensive), called a register file, is provided for
frequently accessed variables and a much larger but slower memory (less expensive) is provided
for the rest of the program and data. (SPARC: 32 register at any one time)
This is based on the principle of locality" at a given time, a program typically accesses a small
number of variables much more frequently than others.

Figure 1.4: The Load / Store Machine Architecture
The machine loads and stores the registers from memory. The arithmetic and logic instructions
operate with registers, not main memory, for the location of operands.
Since the machine addresses only a small number of registers, the instruction field to refer to a
register (operand) is short; therefore, these machines frequently have instructions with three
operands:


ADD src1, src2, dest
EXAMPLE MACHINE INSTRUCTIONS
y = y+10
y &y
[y] *&y = *& y = y
Stack Machine Accumulator Machine Load / Store Machine
Push [y] Load [y] Load r0, [y]
Push 10 Add 10 Load r1, 10
Add Store y Add r0, r1, r2
Pop y Store r2, y

CPU organization of 8085 microprocessor
In the following sections we will take a look at the CPU organization in Intel 8085. We will
study the register organization and their relationship with other components in a relatively simple
Intel 8085.The Intel 8085 CPU organization is as shown in figure 4.5.
The CPU of 8085 is organized around a single 8-bit internal bus. Connected to the Bus are the
following components.
1. Accumulator: Used as a temporary buffer to store input to the ALU. It is also user visible and
is addressed in some instructions.
2. Temporary register: Used as input for ALU this is other than Accumulator.
3. Flags: These are nothing but condition codes. The result of ALU operations are related back
in the register as flags.


Figure 1.5: Intel 8085 CPU organization
The different flag bits supported by the 8085 CPU are:
1. Z: It stands for Zero Flag. This bit is set when the result of ALU operation is zero. That is
result = zero implies Z=1 and result = non zero implies Z=0.
2. S: It stands for Sign Flag. This bit is set when the result of ALU operation is negative
That is result = negative implies S=1 and result = non negative implies
S=0
3. P: It stands for Parity Flag. This bit is set when the result of ALU operation results in even
parity. That is the result when expressed in binary has even number of ones in it.
That is result contains even number of ones implies even parity P=1 and result contains odd
number of ones implies odd parity P=0
4. CY: It stands for Carry Flag. This bit is set when the result of ALU operation results in
overflow.
That is result contains overflow implies carry flag (CY) =1 and result does not contain overflow
implies CY=0
5. AC: It stands for Auxiliary Carry Flag. This bit is set when the result of
ALU operation results in carry between fourth and fifth bit.
That is result contains carry from fourth to fifth bit implies AC = 1 and result contains carry from
fourth to fifth bit implies AC =0
4. ALU output: The result of an operation is placed on the bus.


5. Instruction register: It is loaded from the memory buffer register (MBR) through the Bus.
The instruction is brought into CPU through the address/data buffer and internal CPU bus to the
instruction register. Then it is decoded here and executed by the control unit.
6. Register Array: It is a collection of registers that are user visible and help to store the
operands or result of the operation.
The register array contains five 16-bit registers. The B C, D E, H L register, Stack pointer
and program register.
1. The first three types of registers can be treated as a single 16 bit register each or two 8-bit
registers each. That is B, C, D, E, H, L are six registers which are 8-bit long.
2. Stack pointer is a 16-bit that points to the location of stack memory. This is used for stack
oriented machines.
3. Program counter is 16 bit that points to the current location of the memory where the
instructions are to be written. It is moved to the MAR (address plus address/data buffers) to
begin the fetching of the next instruction.
Any of these registers may be loaded, 8-bits at a time, from the internal bus or transferred to the
address buffer or address/data buffer. Also any of the 16-bit registers can be transferred to the
MAR that connects to the external address bus.
7. Address/data Buffer: This buffer connects to multiplexed bus lines. Some of the time, this
buffer acts as a memory buffer register (MBR) to exchange data with the system bus. At other
times it acts as the low order 8-bits of a memory address register (MAR). This multiplexing
allows additional pins that are available for control signals to the system bus.
8. Address buffer: Used as a high order 8 bits of the MAR.
Let us consider an instruction ADD B as an example to study the sequence of actions that takes
place.
This instruction causes the contents of register B to be added to the contents of the accumulator.
To execute this instruction, the control unit moves the contents of register B to the temporary
register.
The ALU performs the add operation on its inputs.
The result is placed on the internal CPU bus and copied into the accumulator.
The ALU also updates the flags to reflect the results of add.
1.3 Register Organization of different machines


It is very much instructive to examine and compare the register organization of comparable
systems. In this section we will discuss the register organization of 16-bit microprocessors that
were developed more or less at the same time.
Intel 8086
The approach taken by Intel for register organization is different than Z8000 machine and is as
shown in Figure 4.7.

Figure 4.7: Intel 8086 register organization
In this machine every register is a special purpose register. There are some registers that also
serve as general purpose registers. The 8086 machine contains four 16-bit data registers that are
accessible on a byte or 16-bit basis. It also has four 16-bit pointers and index registers. The data
registers can be used as general purpose registers in some instructions. In others registers are
used implicitly.
Example: A multiply instruction always uses accumulator. The four pointer registers each with
segment offset are also used in a number of operations implicitly. There are also four segment
registers. Three of these segment registers are used in a dedicated, implicit way to point to the
segment of the current instruction, a segment containing data and a segment containing a stack.
This type of structure is useful in branch operations. The dedicated and implicit uses provide for
compact encoding at the cost of reduced flexibility. The 8086 also includes an instruction pointer
and a set of 1 bit status and control flags.
4.5 Instruction Cycles
The basic function performed by a computer is program execution. The program to be executed
consists of a set of instructions stored in memory. The CPU does the actual work by executing
the instructions written in the program.
Basic Instruction cycle
To understand the ways the major components of a computer or rather CPU interact to execute a
program, consider the flow chart as shown in figure 4.9.


Figure 4.9: Basic instruction cycle
The processing required for a single instruction is called an instruction cycle. Referring to the
above figure 4.9, the basic instruction cycle can be assumed to consist of two steps:
1. The CPU reads or fetches instructions from memory one at a time.
2. Then this single instruction is executed.
The program execution consists of repeating these two steps of instruction fetch and instruction
execution until the end of the program.
Thus the instruction cycles consists of fetch cycle and execute cycle.
The execution of program itself may involve a number of steps. The instruction fetch is a
common operation for every instruction, and consists of reading an instruction from a location in
memory. The instruction may involve several operations depending upon the nature of the
instructions. In any CPU we have seen that there is a register called program counter that keeps
track of the instructions to be fetched next from the memory. CPU always increments the PC
after each instruction fetch so that it will fetch the next instructions in sequence.
The fetched instruction is stored in a register in the CPU known as instruction register. The
instruction is in the form of binary code that specifies what action has to be taken by the CPU.
The CPU interprets the instruction and performs the required action.
Example: If PC = [300] that is PC is set to 300 location of memory. If there are three instructions
in a program and next subsequent instructions are placed say 303, 304 and end or Halt at 306.
Then discuss the steps involved in execution of this program.
Solution:


1. First of all the instruction that is present at location 300 in memory is loaded into IR .At the
same time PC is incremented by 3 as the next instruction is at 303.
2. Depending on the instruction that is decoded, it finds that operands are to be read from
memory (as the next instruction is at 303 implies that the operands of first instruction may be
placed at 301 and 302)
3. Then the instruction is executed.
4. Then again reads the instruction from 303 into IR and update PC=304.
5. Decodes the instruction and Executes. (Now operands are definitely not specified in memory
as the next instruction is at 304.)
6. The third instruction is read into IR from location 304 as PC=304 and now PC updates with
306.
7. Decodes the instruction and may find operand in memory location hence gets operands from
memory at 305.
8. and then executes the instruction
9. Finally now the next instruction is at 306 so it is read in IR and PC=307
10. Decodes this instruction which is halt
11. Executes it which terminates the execution of the program.
The following is one view of the instruction cycles:
Fetch the instruction:
=>Place it in a holding area called IR.
=>Update the program counter (PC).
Execute the instruction:
=>Decode the instruction:
-Perform address translation.
-Fetch operands from memory.
=>Perform the required calculation.
=>Store results in registers or memory.
=>Set status flags attached to the CPU.


The required action performed by the CPU falls into four categories.
1. CPU-Memory: Data may be transferred from the CPU to memory or from memory to CPU
2. CPU-I/O: Data may be transferred to/from the outside world by transferring between CPU
and I/O module.
3. Data processing: The CPU may perform some arithmetic or logic operations on data.
4. Control: An instruction may specify the sequence of execution be altered. For example, jump
instruction.
Consider for example that the program is written from location 300 to 320 in the memory. Now
if the instruction present at say 305 is something like jump to 310. When the program is executed
the instruction located at 300 to 305 are executed in sequence one at a time. Then after the
execution of instruction jump to 310, the CPU has updated the PC=310. Hence the next
instruction that is fetched will be from 310 and so on.
Basic Instruction Cycle State diagram
These are the detailed states occurring during the fetch and execution cycles are as shown in
figure 4.10. A few of them occur only once and a few occur multiple times.

Figure 4.10: Instruction Cycle State Diagram
The different possible states occurring in Instruction cycle are:
Instruction Address Calculation (IAC): Determine the address of the next instruction to be
executed. Usually, this involves adding a fixed number to the address of the previous instruction.
For example, if each instruction is 16 bits long and memory is organized into 16-bits words, then
add 1 to the previous address. If, instead memory is organized as individually addressable 8-bit
bytes, then add 2 to the previous address.
Instruction Fetch (IF): Read instruction from its memory location into the processor.


Instruction Operation Decoding (IOD): Analyze instruction to determine type of operation to
be performed and operand(s) to be used.
Operand Address Calculation (OAC): If the operation involves reference to an operand in
memory or available via I/O, then determine the address of the operand.
Operand Fetch (OF): Fetch the operand from memory or read it in, from I/O.
Data Operation (DO): Perform the operation indicated in the instruction.
Operand Store (OS): Write the result into memory or out to I/O.
During the instruction cycles, Instruction address calculation, Instruction fetch and Instruction
operation decoding are performed only once, but operand address calculation and operand fetch
may happen multiple times. Data operation is performed once, and Operand store with the
combination of Operand address calculation may be performed zero or more times depending on
the instruction.
1.4 Summary
We know that CPU consists of a set of registers that function as a level of memory. Here we
have discussed the different types of registers like user visible registers, control registers or flag
registers and so on. We have also introduced the basic instruction cycle so as to get a feel of how
exactly these registers are used in the execution of the instruction. As a case study we have seen
the detail register organization of few machines like Zilog Z8000, Intel 8086 and Motorola
68000 microprocessors.
Self Assessment Questions
1. CPU consists of a set of registers that function as a level of memory above ______________.
2. ______________ enable the machine or assembly language programmer to minimize main
memory references by use of registers.
3. Flags of 8085 are nothing but ______________.
4. ______________ number of flag bits is defined in 8085.
5. The processing required for a single instruction is called an ______________ .


Most computers fall into one of the three following organizations:

1. Single accumulator organization

2. General register organization

3. Stack organization

Single accumulator org. uses one address field ADD X: AC AC + M[X]

The general register org. uses three address fields
ADD R1, R2, R3: R1 R2 + R3

Can use two rather than three fields if the destination is assumed to be one of the source registers

Stack org. would require one address field for PUSH/POP operations and none for operation-
type instructions

PUSH X
ADD

Some computers combine features from more than one organizational structure


Example: X = (A+B) * (C + D)

Three-address instructions:

ADD R1, A, B R1 M[A] + M[B]
ADD R2, C, D R2 M[C] + M[D]
MUL X, R1, R2 M[X] R1 * R2

Two-address instructions:
MOV R1, A R1 M[A]
ADD R1, B R1 R1 + M[B]
MOV R2, C R2 M[C]
ADD R2, D R2 R2 + D
MUL R1, R2 R1 R1 * R2
MOV X, R1 M[X] R1

One-address instructions:

LOAD A AC M[A]
ADD B AC AC + M[B]
STORE T M[T] AC
LOAD C AC M[C]
ADD D AC AC + M[D]
MUL T AC AC * M[T]
STORE X M[X] AC

Zero-address instructions:

PUSH A TOS A
PUSH B TOS B
ADD TOS (A +B)
PUSH C TOS C
PUSH D TOS D
ADD TOS (C + D)
MUL TOS (C + D) * (A + B)
POP X M[X] TOS

RISC instructions:
LOAD R1, A R1 M[A]
LOAD R2, B R2 M[B]
LOAD R3, C R3 M[C]
LOAD R4, D R4 M[D]
ADD R1, R1, R2 R1 R1 + R2
ADD R3, R3, R4 R3 R3 + R4


MUL R1, R1, R3 R1 R1 * R3
STORE X, R1 M[X] R1

CO_TK_02
GATE Topic: ALU and Data-Path
Topics to be covered: Register transfer language, Bus selection, Arithmetic circuits, Logical circuits and
Arithmetic logic shift unit
Study Material
Introduction
A digital system is an interconnection of digital hardware modules that accomplish a specific information-
processing task. Digital systems vary in size and complexity, from a few integrated circuits to a complex
of interconnected and interacting digital computers. Digital system design invariably uses a modular
approach. The modules are constructed from such digital components as registers, decoders, arithmetic
elements, and control logic. The various modules are interconnected with common data and control paths
to form a digital computer system.
Objectives of study: After studying this unit, the students will be able to
- Explain Register Transfer Language
- Understand bus selection techniques
- Explain arithmetic and logical circuits
- Understand the operation of arithmetic logic shift unit

Register Transfer Language
The operations executed on data stored in registers are called micro-operations. A microoperation is an
elementary operation performed on the information stored in one or more registers. The result of the
operation may replace the previous binary information of a register or may be transferred to another
register. Examples of micro-operations are shift, count, clear, and load.
The internal hardware organization of a digital computer is best defined by specifying:
1. The set of registers and their function.
2. The sequence of micro-operations performed on the binary information stored in the registers.
3. The control that initiates the sequence of micro-operations.

The symbolic notation used to describe the micro-operation transfers among registers is called a register
transfer language. The term register transfer implies the availability of hardware logic circuits that
can perform a stated micro-operation and transfer the result of the operation to the same or another
register. The word language is borrowed from programmers, who apply this term to programming
languages. A register transfer language is a system for expressing in symbolic form the micro-operation
sequences among the registers of a digital module.

Register Transfer
Computer registers are designated by capital letters (sometimes followed by numerals) to denote the
function of the register. A list of registers for the basic computer is shown below-
Register Symbol Size in bits Function
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character


OUTR 8 Output Register Holds output character

The most common way to represent a register is by a rectangular box with the name of the register inside,
as in figure.

Block diagram of register

Information transfer from one register to another is designated in symbolic form by means of a
replacement operator. The statement R2 R1 denotes a transfer of the content of register R1 into
register R2. It designates a replacement of the content of R2 by the content of R1. By definition, the
content of the source register R1 does not change after the transfer.

The register transfer symbol to represent if-then statement-
If (P = 1) then (R2 R1) Where P is a control signal generated in the control section.

The control function is included in the statement as follows:
P: R2 R1 it denotes that the transfer operation will be executed by the hardware only if P = 1.

Bus and Memory Transfers
A typical digital computer has many registers, and paths must be provided to transfer information from
one register to another. The number of wires will be excessive if separate lines are used between each
register and all other registers in the system. A more efficient scheme for transferring information
between registers in a multiple-register configuration is a common bus system. A bus structure consists
of a set of common lines, one for each bit of a register, through which binary information is transferred
one at a time. Control signals determine which register is selected by the bus during each particular
register transfer.
One way of constructing a common bus system is with multiplexers. The multiplexers select the source
register whose binary information is then placed on the bus.

S0 S1 MUX I/P Register


Bus system for four registers

In the above figure, the contents of register D is transferring to the bus by selecting S0=1 & S1=1.
The symbolic statement for a bus transfer may mention the bus or its presence may be implied in the
statement. When the bus is included in the statement, the register transfer is symbolized as follows:
BUS C, R1 BUS
The content of register C is placed on the bus, and the content of the bus is loaded into register R1 by
activating its load control input. If the bus is known to exist in the system, it may be convenient just to
show the direct transfer. R1 C
Memory Transfer
A memory word will be symbolized by the letter M. The particular memory word among the many
available is selected by the memory address during the transfer. It is necessary to specify the address of M
when writing memory transfer operations. This will be done by enclosing the address in square brackets
following the letter M as M [AR].

1. Read Operation: The transfer of information from a memory word to the outside environment
like CPU register.
Read: DR M [AR]

2. Write Operation: The transfer of new information to be stored into the memory.
Write: M [AR] R1

A micro-operation is an elementary operation performed with the data stored in registers. The
micro-operations most often encountered in digital computers are classified into four categories:
1. Register transfer micro-operations transfer binary information from one register to another.
2. Arithmetic micro-operations perform arithmetic operations on numeric data stored in registers.
3. Logic micro-operations perform bit manipulation operations on non-numeric data stored in
registers.
4. Shift micro-operations perform shift operations on data stored in registers.

Arithmetic Micro-operations
Selected
0 0 0 A
0 1 1 B
1 0 2 C
1 1 3 D


4-bit Binary Adder: It will add the 4 bit data of register A & B

4-bit Binary Adder-Subtractor: It can add or subtract 4-bit data of register A & B.
- When M = 0 the circuit is an adder
- When M = 1 the circuit becomes a subtractor.

4-bit adder-subtractor
Binary Incrementer: It can increment a 4-bit data of a register A by 1.
The increment micro-operation adds one to a number in a register. For example, if a 4-bit register has a
binary value 0110, it will go to 0111 after it is incremented.

4-bit binary incrementer

Arithmetic Circuit
The arithmetic micro-operations listed above can be implemented in one composite arithmetic circuit. The
basic component of an arithmetic circuit is the parallel adder. By controlling the data inputs to the adder,
it is possible to obtain different types of arithmetic operations.
FA
B0 A0
S0
C0
FA
B1 A1
S1
C1
FA
B2 A2
S2
C2
FA
B3 A3
S3
C3
C4
FA
B0 A0
S0
C0 C1
FA
B1 A1
S1
C2
FA
B2 A2
S2
C3
FA
B3 A3
S3 C4
M
HA
x y
C S
A0 1
S0
HA
x y
C S
A1
S1
HA
x y
C S
A2
S2
HA
x y
C S
A3
S3 C4


4-bit arithmetic circuit
The output of the binary adder is calculated from the following arithmetic sum:
D = A + Y + C
in

Arithmetic Circuit Function Table

Logic Micro-operations
Logic micro-operations specify binary operations for strings of bits stored in registers. These operations
consider each bit of the register separately and treat them as binary variables.


Sixteen Logic Micro-operations
Hardware Implementation
The hardware implementation of logic microoperations requires that logic gates be inserted for each bit or
pair of bits in the registers to perform the required logic function. Although there are 16 logic
microoperations, most computers use only four AND, OR, XOR (exclusive-OR), and complement
from which all others can be derived.

One stage of logic circuit

Some Applications
Logic micro-operations are very useful for manipulating individual bits or a portion of a word stored in a
register. They can be used to change bit values, delete a group of bits, or insert new bit values into a
register. The following examples show how the bits of one register (designated by A) are manipulated by
logic micro-operations as a function of the bits of another register (designated by B). In a typical


application, register A is a processor register and the bits of register B constitute a logic operand extracted
from memory and placed in register B.
- Selective-set A A + B
- Selective-complement A A B
- Selective-clear A A B
- Mask (Delete) A A B
- Clear A A B
- Insert A (A B) + C
- Compare A A B

Selective-set operation (Logical OR): sets to 1 the bits in register A where there are corresponding 1s
in register B. It does not affect bit positions that have 0s in B. The following numerical example clarifies
this operation:
1010 A before
1100 B (logic operand)
1110 A after

Selective-complement (Exclusive-OR): operation complements bits in A where there are corresponding
1s in B. It does not affect bit positions that have 0s in B. For example:
1010 A before
0110 A after
Selective-Clear operation clears to 0 the bits in A only where there are corresponding 1s in B. For
example:
1010 A before
0010 A after

Mask operation (Logical AND): is similar to the selective-clear operation except that the bits of A are
cleared only where there are corresponding 0s in B. The mask operation is an AND micro operation as
seen from the following numerical example:
1010 A before
1000 A after masking

Insert Operation (Mask and OR): inserts a new value into a group of bits. This is done by first masking
the bits and then ORing them with the required value. For example, suppose that an A register contains
eight bits, 0110, 1010. To replace the four leftmost bits by the value 1001 we first mask the four
unwanted bits:
0110 1010 A before
0000 1111 B (mask)
0000 1010 A after masking
and then insert the new value:
0000 1010 A before
1001 0000 B (insert)
1001 1010 A after insertion


The mask operation is an AND microoperation and the insert operation is an OR microoperation.
Clear Operation: compares the words in A and B and produces an all 0s result if the two numbers are
equal. This operation is achieved by an exclusive-OR microoperation as shown by the following example:
1010 A
1010 B
0000 A after operation
When A and B are equal, the two corresponding bits are either both 0 or both 1. In either case the
exclusive-OR operation produces a 0. The all-0s result is then checked to determine if the two numbers
were equal.
Shift Micro-operations
Shift micro-operations are used for serial transfer of data. They are also used in conjunction with
arithmetic, logic, and other data-processing operations. The contents of a register can be shifted to the left
or the right. At the same time that the bits are shifted, the first flip-flop receives its binary information
from the serial input. During a shift-left operation the serial input transfers a bit into the rightmost
position. During a shift-right operation the serial input transfers a bit into the leftmost position. The
information transferred through the serial input determines the type of shift.

There are three types of shifts
Logical shift
Circular shift
Arithmetic shift


LOGICAL SHIFT
In a logical shift the serial input to the shift is a 0.
A right logical shift operation:
A left logical shift operation:
In a Register Transfer Language, the following
notation is used
shl for a logical shift left
shr for a logical shift right
Examples:
R2 shr R2
R3 shl R3
0
0

CIRCULAR SHIFT
In a circular shift the serial input is the bit that is
shifted out of the other end of the register.
A right circular shift operation:
A left circular shift operation:
In a RTL, the following notation is used
cil for a circular shift left
cir for a circular shift right
Examples:
R2 cir R2
R3 cil R3

ARITHMETIC SHIFT
An arithmetic shift is meant for signed binary numbers (integer)
An arithmetic left shift multiplies a signed number by two
An arithmetic right shift divides a signed number by two
The main distinction of an arithmetic shift is that it must keep
the sign of the number the same as it performs the
multiplication or division
A right arithmetic shift operation:
A left arithmetic shift operation:
0
sign
bit
sign
bit


ARITHMETIC LOGIC SHIFT UNIT
S3 S2 S1 S0 Cin Operation Function
0 0 0 0 0 F = A Transfer A
0 0 0 0 1 F = A + 1 Increment A
0 0 0 1 0 F = A + B Addition
0 0 0 1 1 F = A + B + 1 Add with carry
0 0 1 0 0 F = A + B Subtract with borrow
0 0 1 0 1 F = A + B+ 1 Subtraction
0 0 1 1 0 F = A - 1 Decrement A
0 0 1 1 1 F = A TransferA
0 1 0 0 X F = A . B AND
0 1 0 1 X F = A v B OR
0 1 1 0 X F = A B XOR
0 1 1 1 X F = A Complement A
1 0 X X X F = shr A Shift right A into F
1 1 X X X F = shl A Shift left A into F
Arithmetic
Circuit
Logic
Circuit
C
C
4 x 1
MUX
Select
0
1
2
3
F
S3
S2
S1
S0
B
A
i
A
D
A
E
shr
shl
i+1 i
i
i
i+1
i-1
i
i

Function Table for Arithmetic Logic Shift Unit

Practice Paper # CO_02


Q1- The micro-operations are-
a) High level instruction b) Low level instruction c) Operations executed on register data

Q2- Which of the followings is not an example of micro-operation-
a) Shift b) Add c) Load d) AND e) All a,b,c,d

Q3- The address of the next instruction to be executed is stored by-
a) DR b) PC c) IR d) AR

Q4- The program instruction code is stored into-
a) DR b) PC c) IR d) AR

Q5- The total number of multiplexers for a bus system is depends on-
a) Number of Register b) size of register c) size of data d) select lines

Q6- The size of multiplexers for a bus system is depends on-
a) Number of Register b) size of register c) size of data d) select lines

Q7- The number of select lines of multiplexers for a bus system is depends on-
a) Number of Register b) size of register c) size of data d) Inputs of MUX

Q8- The maximum number of select lines of multiplexers for a bus system-
a) 2 b) 3 c) 4 d) depends on size of register e) None

Q8- The operation M [AR] R1 represents-
a) Read memory data into R1 c) Write Memory location with R1
b) Read memory address into R1 d) Write Memory address with R1

Q9- A 4-bit binary incrementoer can increment the value of a register by-
a) 1 b) 2 c) 3 d) 4 e) any number

Q10- The selective set register operation is similar to -
a) AND b) OR c) X-OR d) X-NOR

Q11- The selective complement register operation is similar to

Q11- The mask register operation is similar to

Q12- The insert operation is similar to
a) AND followed by NOR b) OR followed by AND c) AND followed by OR

Q13- In logical shift left operation
a) Insert 0 from left b) Insert 0 from right c) Insert LSB from left d) Insert MSB from right

Q14- In circular shift right operation
a) Insert 0 from left b) Insert 0 from right c) Insert LSB from left d) Insert MSB from right

Q15- In arithmetic shift left operation
a) Insert 0 from left c) Insert 0 from right d) shift sign bit to right


b) remain sign bit unchanged e) None of these

Q16- In arithmetic shift right operation
a) Insert 0 from left c) Insert 0 from right d) shift sign bit to right
b) remain sign bit unchanged e) None of these

Q17- Which of the following shift operations divide a signed binary number by 2?
a) Logical left shift b) logical right shift c) arithmetic left shift d) arithmetic right shift

A digital computer has a common bus system for 16 registers of 32 bits each. The bus is
constructed with multiplexers.
Q18- selection inputs of multiplexer are-
a) 16 b) 32 c) 4 d) 5
Q19- The size of the multiplexer is-
a) 16 b) 32 c) 4 d) 5
Q20- The number of multiplexer are-
a) 16 b) 32 c) 4 d) 5
Q21- A register R1 contain 11011001.The contains of register R1, after applying circular shit left
operation is-
a) 10110011 b)11101100 c) 01101100 d) 10110010
Q22- Starting from the initial value of R = 11011101, Determine the sequence of binary values in R
after a logical shift-left, followed by a circular shift right, followed by a logical shift right and a
circular shift left.
Q23- The operations executed on data stored in registers are called __________.

Q24- The symbolic notation used to describe the micro-operation transfers among registers is
called a __________________.

Q25- The register that holds an address for the memory unit is usually called a _________________.

Q26- It is convenient to separate the control variables from the register transfer operation by
specifying a ______________.

Q27- A more efficient scheme for transferring information between registers in a multiple-register
configuration is a ______________.

CO_TK_03
GATE Topic: CPU Control Design
Topics to be covered: Instruction format, Instruction codes, Control unit, Instruction cycle.
Study Material
Basic Computer specification: The following specification supports 4 K x 16 RAM

12-bit AR, PC 16-bit DR, AC, IR, TR 8-bit INPR, OUTR


3-bit SC 1-bit E, I, IEN, FGI, FGO
- Since memory is 4K in size, it requires 12 address bits. Each word of memory contains 16 bits
of data.
- The address register (AR) is 12 bits wide, since this system requires that many bits in order to
access memory. Similarly, the program counter (PC) is also 12 bits wide.
- Each data word is 16 bits wide. The Data Register (DR) must also be 16 bits wide, since it
receives data from and sends data to memory.
- The accumulator (AC) acts on 16 bits of data.
- The Instruction Register (IR) receives instruction codes from memory which are 16 bits wide.
Note: TR is a temporary register. Only the CPU can cause it to be accessed. The programmer
cannot directly manipulate the contents of TR. Most CPUs have one or more temporary registers
which it uses to perform instructions.
- The input and output registers (INPR and OUTR) are 8 bits wide each. For this CPU, I/O
instructions only transfer 8 bits of data at a time.
- The 3-bit sequence counter (SC) is used to generate the correct timing (T) states.
- Other 1-bit registers are the carry out (E), the indirect register (I), the interrupt enable (IEN)
and the input and output flags (FGI and FGO).

Note that the content of any register can be applied onto the bus and an operation can be performed in the
arithmetic logic unit (ALU) circuit during the same clock cycle. The same clock cycle transfers the
content of the bus into the designated destination register and the output of the ALU into AC.
Consider S2 S1 S0 = 100, with LD of DR enabled, the contents of AC transfer to DR while the
contents of DR transfer to AC via the ALU.
Instruction code: a group of bits that tell the computer to perform a specific operation. The instruction
code is an opcode plus additional information, such as a memory address. It is not the micro-
operations. In terms of programming, it is closest to a single assembly language instruction.


Symbol Hexadecimal code Description / binary (register operations)
I = 0, I = 1 Memory Reference Instruction(MRI) Set
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load memory word to AC
STA 3xxx Bxxx Store content of AC in memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ

6xxx Exxx Increment and skip if zero

Register Reference Instruction(Non- MRI) Set
CLA 7800 Clear AC /
0111100000000000
CLE 7400 Clear E /
0111010000000000
CMA 7200 Complement AC /
0111001000000000
CME 7100 Complement E /
0111000100000000


CIR 7080 Circulate right AC and E / 0111000010000000
CIL 7040 Circulate left AC and E / 0111000001000000
INC 7020 Increment AC /
0111000000100000
SPA 7010 Skip next instruction if AC positive /
0111000000010000
SNA 7008 Skip next instruction if AC negative /
0111000000001000
SZA 7004 Skip next instruction if AC zero /
0111000000000100
SZE 7002 Skip next instruction if E is 0 /
0111000000000010
HLT 7001 Halt computer /
0111000000000001

Input-Output Instruction(Non- MRI) Set
INP F800 Input character to AC
OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off

Instruction Cycle: An instruction cycle (sometimes called fetch-and-execute cycle, fetch-decode-
execute cycle, or FDX) is the basic operation cycle of a computer. It is the process by which a computer
retrieves a program instruction from its memory, determines what actions the instruction requires, and
carries out those actions. This cycle is repeated continuously by the central processing unit (CPU), from
boot up to when the computer is shut down.
The circuits used in the CPU during the instruction cycle are:
1. Program Counter (PC) - an incrementing counter that keeps track of the memory address of which
instruction is to be executed next...
2. Memory Address Register (MAR) - holds the address of a memory block to be read from or written to
3. Memory Data Register (MDR) - a two-way register that holds data fetched from memory (and ready
for the CPU to process) or data waiting to be stored in memory


4. Instruction register (IR) - a temporary holding ground for the instruction that has just been fetched
from memory
5. Control Unit (CU) - decodes the program instruction in the IR, selecting machine resources such as a
data source register and a particular arithmetic operation, and coordinates activation of those resources
6. Arithmetic logic unit (ALU) - performs mathematical and logical operations
There are typically four stages of an instruction cycle that the CPU carries out:
1. Fetch the instruction from memory.
2. Decode" the instruction.
3. Read the effective address" from memory if the instruction has an indirect address.
4. Execute" the instruction.
Each computer's CPU can have different cycles based on different instruction sets, but will be similar to
the following cycle:
Fetch the instruction (FI) : The next instruction is fetched from the memory address that is currently
stored in the Program Counter (PC), and stored in the Instruction register (IR). At the end of the fetch
operation, the PC points to the next instruction that will be read at the next cycle.
Decode the instruction (DI) : The decoder interprets the instruction. During this cycle the instruction
inside the IR (instruction register) gets decoded.
Effective Address Calculation(EAC): In case of a memory instruction (direct or indirect) the execution
phase will be in the next clock pulse. If the instruction has an indirect address, the effective address is
read from main memory, and any required data is fetched from main memory to be processed and then
placed into data registers(Clock Pulse: T
3
). If the instruction is direct, nothing is done at this clock pulse.
If this is an I/O instruction or a Register instruction, the operation is performed (executed) at clock Pulse.
Execute the instruction(EX): The Control Unit of CPU passes the decoded information as a sequence of
control signals to the relevant function units of the CPU to perform the actions required by the instruction
such as reading values from registers, passing them to the ALU to perform mathematical or logic
functions on them, and writing the result back to a register. If the ALU is involved, it sends a condition
signal back to the CU.
The result generated by the operation is stored in the main memory, or sent to an output device. Based on
the condition of any feedback from the ALU, Program Counter may be updated to a different address
from which the next instruction will be fetched. The cycle is then repeated.
The control unit (CU) is responsible to process instruction cycle. The control unit of a computer can be
implemented with the following two approaches-
1. Hardwired Control Unit : Implemented by hardware (i.e. Decoder, Counter, gates etc )
2. Micro-programmed Control Unit: Implemented by software.
Hardwired Control Unit


Control signals are connected to the appropriate registers and ALU. Decoding of the IR in conjunction
with timing signals T
0
T
15
produce control signals causing register and ALU operation.
SC 0 //clear sequence counter to 0 activating the timing signal T
0
.
The sequence counter is incremented or cleared synchronously. For example the combination, D
3
T
4
:
SC 0, synchronously clearing the sequence counter to 0.

Instruction Cycle with basic computer register:
Fetch places the contents of PC onto the bus by making bus selection inputs S
2
S
1
S
0
= 010, then transfers
the contents of the bus to AR by enabling the LD input of AR. This is accomplished during timing signal
T
0
. During timing signal T
1
, fetch places the contents of AR selected memory onto the bus by making
selection inputs S
2
S
1
S
0
= 111, then transfers the content of the bus to IR by enabling the LD input of IR,
and increments PC by enabling the INR of PC.
Decode occurs during timing signal T
2
, at which time the contents of the instruction register are passed to
the I flip-flop IR(15), a 3x8 decoder IR(12-14), and to the address register IR(0-11). We use simple
register transfer statements to represent all of these actions as follows:
1. Fetch
T
0
: AR PC
T
1
: IR M[AR], PC PC + 1
2. Decode
T
2
: D
0
,, D
7
Decode IR(12-14), AR IR(0-11), I IR(15)
3. Read the effective address from memory if the instruction has an indirect address
T
3
: Instruction Formats
Memory Reference (D
7
')
Direct (I') effective address is already in AR, perform Execute at T
3
.
Indirect (I), T
3
: AR M[AR]
Register Reference or Input/output (D
7
)
Register (I') perform Execute at T
3

I/O (I) perform Execute at T
3

4. Execute T
3
or T
4
:


The cycle continues from 4 back to 1 to fetch, decode, and execute until a HALT instruction is
encountered.

Examples

1. AND execute cycle
D0T4: DR M[AR] D0T5: AC AC ^ DR, SC 0

Example: AND 500: AC = 31, M[500] = 25
D0T4: DR 25 D0T5: AC 31 ^ 25 = 21, SC 0

2.ADD execute cycle
D1T4: DR M[AR] D1T5: AC AC + DR, SC 0

Example: ADD 500: AC = 31, M[500] = 25
D1T4: DR 25 D1T5: AC 31 + 25 = 56, SC 0

3.LDA execute cycle
D2T4: DR M[AR] D2T5: AC DR, SC 0

Example: LDA 500: M[500] = 25
D2T4: DR 25 D2T5: AC 25, SC 0

4.STA execute cycle
D3T4: M[AR] AC, SC 0

Example: STA 500: AC = 31, M[500] = 25
D3T4: M[500] 31, SC 0

5.BUN execute cycle
D4T4: PC AR, SC 0

Example: BUN 500
D4T4: PC 500, SC 0

6.BSA execute cycle
D5T4: M[AR] PC, AR AR+1 D5T5: PC AR, SC 0

Example: 100: BSA 200
D5T4: M[AR] PC, AR AR+1 M[200] 101, AR 201
D5T5: PC AR, SC 0 PC 201, SC 0

7.Subroutine return using BUN I
Example: 205: BUN I 200 M[200] = 101
D7IT3: AR M[AR](11-0) AR M[200](11-0) = 101

8.ISZ execute cycle
D6T4: DR M[AR] D6T5: DR DR+1
D6T6: M[AR] DR, SC 0, if (DR=0) then PC PC+1


9.Loop control using ISZ
Example:100: ISZ 200 M[200] = 55
D6T4: DR M[AR] (DR 55) D6T5: DR DR+1 (DR 56)
(M[200] 56, SC 0)

Register-reference execute cycles r = D7IT3 r: SC 0
(CLA) rIR11: AC 0
(CLE) rIR10: E 0
(CMA) rIR9: AC AC
(CME) rIR8: E E
(CIR) rIR7: EAC cir(EAC)
(CIL) rIR6: EAC cil(EAC)
(INC) rIR5:EAC AC+1
(SPA) rIR4: IF AC(15)=0 THEN PC PC+1
(SNA) rIR3: IF AC(15)=1 THEN PC PC+1
(SZA) rIR2: IF AC=0 THEN PC PC+1
(SZE) rIR1: IF E=0 THEN PC PC+1
(HLT) rIR0:HALT

I/O execute cycles p = D7IT3 p: SC 0

(INP) pIR11: AC(7-0) INPR, FGI 0
(OUT) pIR10: OUTR AC(7-0), FG0 0
(SKI) pIR9: IF FGI = 1 THEN PC PC+1
(SKO) pIR8: IF FGO = 1 THEN PC PC+1
(ION) pIR7: IEN 1
(IOF) pIR6: IEN 0


Q1- Which is not the part of MRI instruction-
b) Opcode b) Memory Address c) Address Mode d) Register Operation

Q2- The instructions of a program are loaded into memory at -
a) Program Section b) Data Section c) Stack d) Heap

Q3- At the time of recursion, the return addresses of sub-routines are stored at -

Q4- During the dynamic memory allocation, the memory are allocated at -

Q5- The effective address (EA) of instruction is -


a) Actual Address of Instruction c) Actual Address of Operand
b) Actual Address of Program d) Address of Current Instruction

Q6- If a computer support 16 MRI Instructions, the minimum bit required for opcode -
a) 16 b) 4 c) 5 d) 32

Q7- The decimal value 7 of opcode field (14-12) of a 32-bit instruction indicates the instruction is-
a) Memory-Reference b) Register-Reference c) I/O d) b & c

Q8- For a 32-bit Instruction, the instruction code 7080 belongs to the -
a) Memory-Reference b) Register-Reference c) I/O d) b & c

Q9- For a 32-bit Instruction, the instruction code F800 belongs to the -
a) Memory-Reference b) Register-Reference c) I/O d) None

Q10- An instruction register IR contains data 2384 of 32-bit, the memory address of operand is -
a) 84 b) 384 c) 238 d) 23

Q11- An instruction register IR contains data B384 of 32-bit, the instruction belongs to -
a) Direct Memory-Reference c) Indirect Memory-Reference
b) Register-Reference d) I/O Instruction

Q12- If a 8-bit AC contain -1 and 1-bit register E contain 0, after applying CIR register instruction,
the value of AC is -
a) +255 b) -255 c) +128 d) -254 e) None

Q13- If a 8-bit AC contain -1 and 1-bit register E contain 0, after applying CIR register reference
instruction, the value of E is -
a) 0 b) 1 c) Undefined d) Empty

Q14- If a 8-bit AC contain 00111111, after applying INC register instruction, the value of AC is -
a) +63 b) -63 c) +64 d) -64 e) None

Q15- The instruction which transfer the data of INPR into AC is -
a) OUT b) INP c) LDA d) INC

Q16- Which of the folowing is not neccesory during the instruction cycle -
a) AR b) PC c) CU d) IR e) AC
Q17- The instruction cycle may be carried out by -
a) Hardwired CU b) Microprogrammed CU c) Either a or b d) None
Q18- The address of next instruction to be executed is stotred by -
a) AR b) PC c) MAR d) IR
Q19- Which is the correct operation carried out every time whenever new instruction cycle starts -
a) AR=0 b) PC=0 c) IR=0 d) SC=0
Q20- The flip flop I used in hardwired control unit is responsible to hold -
a) Instruction b) Interrupt c) Address Mode d) Input


Q21- The PC is incremented by 1 during the instruction cycle in hardwired Control unit with the
timing signal -
a) T
0
b) T
1
c) T
2
d) T
3
e) T
4

Q22- In the hardwired control unit, the flip flop I is loaded during the phase-
a) Fetch b) Decode c) Effective address calculation d) Execute
Q23- In the hardwired control unit, the register transfer operation AR M[AR] is used, when the
instruction hold-
a) Direct Memory Address b) Indirect Memory Address c) Effective Address d) Always

Q24- To execute a ADD instruction in hardwired control, total number of timing signals required-
a) 1 b) 2 c) 3 d) 4 e) 5 f) 6
Q25- To execute a STA instruction in hardwired control, total number of timing signals required-
a) 1 b) 2 c) 3 d) 4 e) 5 f) 6
Q26- To execute a ISZ instruction in hardwired control, total number of timing signals required-
a) 1 b) 2 c) 3 d) 4 e) 5 f) 6
Q27- All register reference instruction can execute in ____ timing signals -
a) 1 b) 2 c) 3 d) 4 e) 5 f) 6
Q28- All Input Output instruction can execute in ____ timing signals -
a) 1 b) 2 c) 3 d) 4 e) 5 f) 6
A computer uses memory unit 256k words of 32 bits each. A binary instruction code is stored in one word
of memory. The instruction has four parts: indirect bit , an operation code , a register code part to specify
one of 64 registers, and an address part.
Q29- How many bits are there in the operation code, the register code and the address part?
Q30- What should be the size of data & address bus?
CO_TK_03
GATE Topic: CPU Control Design
Topics to be covered: Instruction format, Instruction codes, Control unit, Instruction cycle.
Study Material
Basic Computer specification: The following specification supports 4 K x 16 RAM

12-bit AR, PC 16-bit DR, AC, IR, TR 8-bit INPR, OUTR
3-bit SC 1-bit E, I, IEN, FGI, FGO
- Since memory is 4K in size, it requires 12 address bits. Each word of memory contains 16 bits
of data.
- The address register (AR) is 12 bits wide, since this system requires that many bits in order to
access memory. Similarly, the program counter (PC) is also 12 bits wide.
- Each data word is 16 bits wide. The Data Register (DR) must also be 16 bits wide, since it
receives data from and sends data to memory.
- The accumulator (AC) acts on 16 bits of data.
- The Instruction Register (IR) receives instruction codes from memory which are 16 bits wide.


Note: TR is a temporary register. Only the CPU can cause it to be accessed. The programmer
cannot directly manipulate the contents of TR. Most CPUs have one or more temporary registers
which it uses to perform instructions.
- The input and output registers (INPR and OUTR) are 8 bits wide each. For this CPU, I/O
instructions only transfer 8 bits of data at a time.
- The 3-bit sequence counter (SC) is used to generate the correct timing (T) states.
- Other 1-bit registers are the carry out (E), the indirect register (I), the interrupt enable (IEN)
and the input and output flags (FGI and FGO).

Note that the content of any register can be applied onto the bus and an operation can be performed in the
arithmetic logic unit (ALU) circuit during the same clock cycle. The same clock cycle transfers the
content of the bus into the designated destination register and the output of the ALU into AC.
Consider S2 S1 S0 = 100, with LD of DR enabled, the contents of AC transfer to DR while the
contents of DR transfer to AC via the ALU.
Instruction code: a group of bits that tell the computer to perform a specific operation. The instruction
code is an opcode plus additional information, such as a memory address. It is not the micro-
operations. In terms of programming, it is closest to a single assembly language instruction.


Symbol Hexadecimal code Description / binary (register operations)
I = 0, I = 1 Memory Reference Instruction(MRI) Set
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load memory word to AC
STA 3xxx Bxxx Store content of AC in memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ

6xxx Exxx Increment and skip if zero

Register Reference Instruction(Non- MRI) Set
CLA 7800 Clear AC /
0111100000000000
CLE 7400 Clear E /
0111010000000000
CMA 7200 Complement AC /
0111001000000000
CME 7100 Complement E /
0111000100000000


CIR 7080 Circulate right AC and E / 0111000010000000
CIL 7040 Circulate left AC and E / 0111000001000000
INC 7020 Increment AC /
0111000000100000
SPA 7010 Skip next instruction if AC positive /
0111000000010000
SNA 7008 Skip next instruction if AC negative /
0111000000001000
SZA 7004 Skip next instruction if AC zero /
0111000000000100
SZE 7002 Skip next instruction if E is 0 /
0111000000000010
HLT 7001 Halt computer /
0111000000000001

Input-Output Instruction(Non- MRI) Set
INP F800 Input character to AC
OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off

Instruction Cycle: An instruction cycle (sometimes called fetch-and-execute cycle, fetch-decode-
execute cycle, or FDX) is the basic operation cycle of a computer. It is the process by which a computer
retrieves a program instruction from its memory, determines what actions the instruction requires, and
carries out those actions. This cycle is repeated continuously by the central processing unit (CPU), from
boot up to when the computer is shut down.
The circuits used in the CPU during the instruction cycle are:
7. Program Counter (PC) - an incrementing counter that keeps track of the memory address of which
instruction is to be executed next...
8. Memory Address Register (MAR) - holds the address of a memory block to be read from or written to
9. Memory Data Register (MDR) - a two-way register that holds data fetched from memory (and ready
for the CPU to process) or data waiting to be stored in memory


10. Instruction register (IR) - a temporary holding ground for the instruction that has just been
fetched from memory
11. Control Unit (CU) - decodes the program instruction in the IR, selecting machine resources such
as a data source register and a particular arithmetic operation, and coordinates activation of those
resources
12. Arithmetic logic unit (ALU) - performs mathematical and logical operations
There are typically four stages of an instruction cycle that the CPU carries out:
5. Fetch the instruction from memory.
6. Decode" the instruction.
7. Read the effective address" from memory if the instruction has an indirect address.
8. Execute" the instruction.
Each computer's CPU can have different cycles based on different instruction sets, but will be similar to
the following cycle:
Fetch the instruction (FI) : The next instruction is fetched from the memory address that is currently
stored in the Program Counter (PC), and stored in the Instruction register (IR). At the end of the fetch
operation, the PC points to the next instruction that will be read at the next cycle.
Decode the instruction (DI) : The decoder interprets the instruction. During this cycle the instruction
inside the IR (instruction register) gets decoded.
Effective Address Calculation(EAC): In case of a memory instruction (direct or indirect) the execution
phase will be in the next clock pulse. If the instruction has an indirect address, the effective address is
read from main memory, and any required data is fetched from main memory to be processed and then
placed into data registers(Clock Pulse: T
3
). If the instruction is direct, nothing is done at this clock pulse.
If this is an I/O instruction or a Register instruction, the operation is performed (executed) at clock Pulse.
Execute the instruction(EX): The Control Unit of CPU passes the decoded information as a sequence of
control signals to the relevant function units of the CPU to perform the actions required by the instruction
such as reading values from registers, passing them to the ALU to perform mathematical or logic
functions on them, and writing the result back to a register. If the ALU is involved, it sends a condition
signal back to the CU.
The result generated by the operation is stored in the main memory, or sent to an output device. Based on
the condition of any feedback from the ALU, Program Counter may be updated to a different address
from which the next instruction will be fetched. The cycle is then repeated.
The control unit (CU) is responsible to process instruction cycle. The control unit of a computer can be
implemented with the following two approaches-
3. Hardwired Control Unit : Implemented by hardware (i.e. Decoder, Counter, gates etc )
4. Micro-programmed Control Unit: Implemented by software.
Hardwired Control Unit


Control signals are connected to the appropriate registers and ALU. Decoding of the IR in conjunction
with timing signals T
0
T
15
produce control signals causing register and ALU operation.
SC 0 //clear sequence counter to 0 activating the timing signal T
0
.
The sequence counter is incremented or cleared synchronously. For example the combination, D
3
T
4
:
SC 0, synchronously clearing the sequence counter to 0.

Instruction Cycle with basic computer register:
Fetch places the contents of PC onto the bus by making bus selection inputs S
2
S
1
S
0
= 010, then transfers
the contents of the bus to AR by enabling the LD input of AR. This is accomplished during timing signal
T
0
. During timing signal T
1
, fetch places the contents of AR selected memory onto the bus by making
selection inputs S
2
S
1
S
0
= 111, then transfers the content of the bus to IR by enabling the LD input of IR,
and increments PC by enabling the INR of PC.
Decode occurs during timing signal T
2
, at which time the contents of the instruction register are passed to
the I flip-flop IR(15), a 3x8 decoder IR(12-14), and to the address register IR(0-11). We use simple
register transfer statements to represent all of these actions as follows:
5. Fetch
T
0
: AR PC
T
1
: IR M[AR], PC PC + 1
6. Decode
T
2
: D
0
,, D
7
Decode IR(12-14), AR IR(0-11), I IR(15)
7. Read the effective address from memory if the instruction has an indirect address
T
3
: Instruction Formats
Memory Reference (D
7
')
Direct (I') effective address is already in AR, perform Execute at T
3
.
Indirect (I), T
3
: AR M[AR]
Register Reference or Input/output (D
7
)
Register (I') perform Execute at T
3

I/O (I) perform Execute at T
3

8. Execute T
3
or T
4
:


The cycle continues from 4 back to 1 to fetch, decode, and execute until a HALT instruction is
encountered.

Examples

1. AND execute cycle
D0T4: DR M[AR] D0T5: AC AC ^ DR, SC 0

Example: AND 500: AC = 31, M[500] = 25
D0T4: DR 25 D0T5: AC 31 ^ 25 = 21, SC 0

2.ADD execute cycle
D1T4: DR M[AR] D1T5: AC AC + DR, SC 0

Example: ADD 500: AC = 31, M[500] = 25
D1T4: DR 25 D1T5: AC 31 + 25 = 56, SC 0

3.LDA execute cycle
D2T4: DR M[AR] D2T5: AC DR, SC 0

Example: LDA 500: M[500] = 25
D2T4: DR 25 D2T5: AC 25, SC 0

4.STA execute cycle
D3T4: M[AR] AC, SC 0

Example: STA 500: AC = 31, M[500] = 25
D3T4: M[500] 31, SC 0

5.BUN execute cycle
D4T4: PC AR, SC 0

Example: BUN 500
D4T4: PC 500, SC 0

6.BSA execute cycle
D5T4: M[AR] PC, AR AR+1 D5T5: PC AR, SC 0

Example: 100: BSA 200
D5T4: M[AR] PC, AR AR+1 M[200] 101, AR 201

7.Subroutine return using BUN I
Example: 205: BUN I 200 M[200] = 101
D7IT3: AR M[AR](11-0) AR M[200](11-0) = 101

8.ISZ execute cycle
D6T4: DR M[AR] D6T5: DR DR+1


9.Loop control using ISZ
Example:100: ISZ 200 M[200] = 55
D6T4: DR M[AR] (DR 55) D6T5: DR DR+1 (DR 56)
(M[200] 56, SC 0)

Register-reference execute cycles r = D7IT3 r: SC 0
(CLA) rIR11: AC 0
(CLE) rIR10: E 0
(CMA) rIR9: AC AC
(CME) rIR8: E E
(CIR) rIR7: EAC cir(EAC)
(CIL) rIR6: EAC cil(EAC)
(INC) rIR5:EAC AC+1
(SPA) rIR4: IF AC(15)=0 THEN PC PC+1
(SNA) rIR3: IF AC(15)=1 THEN PC PC+1
(SZA) rIR2: IF AC=0 THEN PC PC+1
(SZE) rIR1: IF E=0 THEN PC PC+1
(HLT) rIR0:HALT

I/O execute cycles p = D7IT3 p: SC 0

(INP) pIR11: AC(7-0) INPR, FGI 0
(OUT) pIR10: OUTR AC(7-0), FG0 0
(SKI) pIR9: IF FGI = 1 THEN PC PC+1
(SKO) pIR8: IF FGO = 1 THEN PC PC+1
(ION) pIR7: IEN 1
(IOF) pIR6: IEN 0


Q1- Which is not the part of MRI instruction-
c) Opcode b) Memory Address c) Address Mode d) Register Operation

Q2- The instructions of a program are loaded into memory at -
b) Program Section b) Data Section c) Stack d) Heap

Q3- At the time of recursion, the return addresses of sub-routines are stored at -

Q4- During the dynamic memory allocation, the memory are allocated at -

Q5- The effective address (EA) of instruction is -


c) Actual Address of Instruction c) Actual Address of Operand
d) Actual Address of Program d) Address of Current Instruction

Q6- If a computer support 16 MRI Instructions, the minimum bit required for opcode -
b) 16 b) 4 c) 5 d) 32

Q7- The decimal value 7 of opcode field (14-12) of a 32-bit instruction indicates the instruction is-
b) Memory-Reference b) Register-Reference c) I/O d) b & c

Q8- For a 32-bit Instruction, the instruction code 7080 belongs to the -
b) Memory-Reference b) Register-Reference c) I/O d) b & c

Q9- For a 32-bit Instruction, the instruction code F800 belongs to the -
b) Memory-Reference b) Register-Reference c) I/O d) None

Q10- An instruction register IR contains data 2384 of 32-bit, the memory address of operand is -
b) 84 b) 384 c) 238 d) 23

Q11- An instruction register IR contains data B384 of 32-bit, the instruction belongs to -
c) Direct Memory-Reference c) Indirect Memory-Reference
d) Register-Reference d) I/O Instruction

Q12- If a 8-bit AC contain -1 and 1-bit register E contain 0, after applying CIR register instruction,
the value of AC is -
b) +255 b) -255 c) +128 d) -254 e) None

Q13- If a 8-bit AC contain -1 and 1-bit register E contain 0, after applying CIR register reference
instruction, the value of E is -
b) 0 b) 1 c) Undefined d) Empty

Q14- If a 8-bit AC contain 00111111, after applying INC register instruction, the value of AC is -
b) +63 b) -63 c) +64 d) -64 e) None

Q15- The instruction which transfer the data of INPR into AC is -
b) OUT b) INP c) LDA d) INC

Q16- Which of the folowing is not neccesory during the instruction cycle -
b) AR b) PC c) CU d) IR e) AC
Q17- The instruction cycle may be carried out by -
b) Hardwired CU b) Microprogrammed CU c) Either a or b d) None
Q18- The address of next instruction to be executed is stotred by -
b) AR b) PC c) MAR d) IR
Q19- Which is the correct operation carried out every time whenever new instruction cycle starts -
b) AR=0 b) PC=0 c) IR=0 d) SC=0
Q20- The flip flop I used in hardwired control unit is responsible to hold -
b) Instruction b) Interrupt c) Address Mode d) Input


Q21- The PC is incremented by 1 during the instruction cycle in hardwired Control unit with the
timing signal -
b) T
0
b) T
1
c) T
2
d) T
3
e) T
4

Q22- In the hardwired control unit, the flip flop I is loaded during the phase-
b) Fetch b) Decode c) Effective address calculation d) Execute
Q23- In the hardwired control unit, the register transfer operation AR M[AR] is used, when the
instruction hold-
b) Direct Memory Address b) Indirect Memory Address c) Effective Address d) Always

Q24- To execute a ADD instruction in hardwired control, total number of timing signals required-
b) 1 b) 2 c) 3 d) 4 e) 5 f) 6
Q25- To execute a STA instruction in hardwired control, total number of timing signals required-
b) 1 b) 2 c) 3 d) 4 e) 5 f) 6
Q26- To execute a ISZ instruction in hardwired control, total number of timing signals required-
b) 1 b) 2 c) 3 d) 4 e) 5 f) 6
Q27- All register reference instruction can execute in ____ timing signals -
b) 1 b) 2 c) 3 d) 4 e) 5 f) 6
Q28- All Input Output instruction can execute in ____ timing signals -
b) 1 b) 2 c) 3 d) 4 e) 5 f) 6
A computer uses memory unit 256k words of 32 bits each. A binary instruction code is stored in one word
of memory. The instruction has four parts: indirect bit , an operation code , a register code part to specify
one of 64 registers, and an address part.
Q29- How many bits are there in the operation code, the register code and the address part?
Q30- What should be the size of data & address bus?
CO_TK_04
GATE Topic: Computer Instructions
Topics to be covered: Zero, One, Two, Three Address Instructions.
Study Material

Instruction Formats:

The most common fields found in instruction format are:-

(1) An operation code field that specified the operation to be performed
(2) An address field that designates a memory address or a processor registers.
(3) A mode field that specifies the way the operand or the effective address is determined.

Computers may have instructions of several different lengths containing varying number of addresses.
The number of address field in the instruction format of a computer depends on the internal organization
of its registers. Most computers fall into one of three types of CPU organization.

(1) Single Accumulator organization ADD X AC AC + M []


(2) General Register Organization ADD R1, R2, R3 R R2 + R3
(3) Stack Organization PUSH X

Three address Instruction

Computer with three addresses instruction format can use each address field to specify either processor
register are memory operand.

ADD R
1
, A, B A
1
M [A] + M [B]
ADD R
2
, C, D R
2
M [C] + M [B] X = (A + B) * (C + A)
MUL X, R
1
, R
2
M [X] R
1
* R
2

The advantage of the three address formats is that it results in short program when evaluating arithmetic
expression. The disadvantage is that the binary-coded instructions require too many bits to specify three
addresses.

Two Address Instruction

Most common in commercial computers. Each address field can specify either a processes register on a
memory word.

MOV R
1
, A R
1
M [A]
ADD R
1
, B R
1
R
1
+ M [B]
MOV R
2
, C R
2
M [C] X = (A + B) * ( C + D)
ADD R
2
, D R
2
R
2
+ M [D]
MUL R
1
, R
2
R
1
R
1
* R
2

MOV X
1
R
1
M [X] R
1

One Address instruction

It used an implied accumulator (AC) register for all data manipulation. For multiplication/division, there
is a need for a second register.

LOAD A AC M [A]
ADD B AC AC + M [B]
STORE T M [T] AC X = (A +B) (C + A)
LOAD C AC M (C)
ADD D AC AC + M (D)
ML T AC AC + M (T)
STORE X M [] AC

Zero Address Instruction

A stack organized computer does not use an address field for the instruction ADD and MUL. The PUSH
& POP instruction, however, need an address field to specify the operand that communicates with the
stack (TOS top of the stack)

PUSH A TOS A
PUSH B TOS B
ADD TOS (A + B)
All operations are done between the AC
register and a memory operand. Its the
address of a temporary memory location
required for storing the intermediate result.


PUSH C TOS C
PUSH D TOS D
ADD TOS (C + D)
MUL TOS (C + D) * (A + B)
POP X M [X] TOS


Consider the following assembly code for 8-bit data, Size of AC is 8-bit-

ORG 0
LDA b
CMA
ADD a
STA c
HLT

a, DEC 5
b, DEC 2
c, DEC 0
END

Q1- What is the last content (in decimal) of Accumulator AC-
d) 2 b) 3 c) 7 d) Other Value

Q2- What is the last content (in decimal) of M[c]-
a) 2 b) 3 c) 7 d) Other Value

Q3- What is the last content of extended accumulator E-
a) 0 b) 1 c) Either 1 or 0 d) Other Value

Q4- The total number of instructions executed by processor-



Consider the following assembly code for 8-bit data, Size of AC is 8-bit-

ORG 0
LDA b
ISZ c
CMA
ADD a
STA c
HLT

a, DEC 5
b, DEC 2
c, DEC -1
END

Q5- What is the last content (in decimal) of Accumulator AC-

Q6- What is the last content (in decimal) of M[c]-

Q7- The total number of instructions executed by processor-
a) 5 b) 7 c) 9 d) 11 e) Other Value

NOTE: Computer has SUB instruction to subtract two numbers.

Q8- The minimum number of instructions required to execute (c=a-b) with One-address CPU -

Q9- The minimum number of instructions required to execute (c=a+b) with Two-address CPU -

Q10- The minimum number of instructions required to execute (c=a+b) with Three-address CPU -

Q11- The minimum number of instructions required to execute E= (A+B) - (C+D) with One-
address CPU-

Q12- The minimum number of instructions required to execute E= (A+B) - (C+D) with Two-
address CPU-

Q13- The minimum number of instructions required to execute E= (A+B) - (C+D) with Three-
address CPU-


Q14- The minimum number of instructions required to execute E= (A+B) - (C+D) with Zero-
address CPU-

Q15-Zero address instruction formats is used for-
a) Single Accumulator Organization b) General Purpose Register Organization
c) Stack Organization d) None of These

Q16-One modern computer can be implemented using-
a) Zero Address CPU c) One Address CPU e) Two Address CPU g) Three Address CPU
b) Combined a & c d) Combined b & c f) Combined e & f h) Combined a to g

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Computer Science & Information Technology Department Prepared By: Govind Arya Page 1

Compiler Design Tutorial Kit

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