Sei sulla pagina 1di 64

Landmine Detection Architectures And Their Implementation on FPGA

A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science at George Mason University

By

Nikita Charankar Bachelor of Engineering University of Mumbai, 2006

Director: Dr. Kenneth J. Hintz, Professor Department of Electrical and Computer Engineering

Spring Semester 2010 George Mason University Fairfax, VA

ii

Copyright

c 2010 by Nikita Charankar

All Rights Reserved

iii

Dedication

I dedicate this thesis to my parents, Mr. and Mrs. Charankar.

iv

Acknowledgments

I would like to thank Dr. Kenneth J. Hintz, Dr. David Hwang and Dr. Nathalia Peixoto for believing in me and giving me this opportunity to work on this interesting thesis topic and especially, Dr. K. J. Hintz for his invaluable support, patience guidance throughout the thesis. I am thankful to Office of Naval Research (ONR) for funding this project. I thank my team members, Dr. Ahmed Nasif for giving me the motivation and feedback on the thesis and Preethi Rama Dev for being supportive and co-operative. I, also, thank Dr. Jens-Peter Kaps and all CERG members for their valuable time and support. I thank my advisor, Dr. Jill Nelson for being available anytime in need and the entire faculty and staff of George Mason University for their co-operation. I would also like to thank my roommates and all my dear friends for their moral support.

Last but not the least, I would like to thank my parents, my sister, Amita and my friend, Shreyas for being my pillars of strength, encouragement and motivation. Without them, this thesis would not have been possible.

v

Table of Contents

 

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List of Tables

 

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viii

List of Figures .

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ix

Abstract

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xi

1 Introduction

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1

1.1 Motivation

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1

1.2 Detection Techniques

 

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1.3 Previous Research

 

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5

1.4 Hardware Implementation

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6

1.5 Thesis Organization

 

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7

2 Ground Penetrating Radar

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8

2.1 NIITEK GPR .

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8

2.2 Syntactic Pattern Recognition Theory

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3 Hardware Implementation on FPGA

 

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12

3.1

Target Device .

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vi

3.2 FPGA Hardware Programming

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13

3.3 FPGA Design Tools

 

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15

4 Previous Research

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17

4.1 Preprocessing Algorithm .

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17

4.2 Landmine Discrimination

 

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19

4.2.1 Reset Finite State Machine

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19

4.2.2 Parallel Correlator

 

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4.3 FPGA Implementation .

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22

4.3.1 Reset Finite State Machine

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22

4.3.2 Parallel Correlator

 

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23

4.4 Modified Algorithms

 

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23

4.4.1

FPGA Implementation .

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24

5 Hard-Coded Parallel Correlator .

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27

5.1 Architecture

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28

5.2 FPGA Implementation

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30

6 RAM Based Finte State Machine

 

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36

6.1 Architecture

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38

6.2 FPGA Implementation .

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39

7 Conclustion and Scope

 

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44

vii

 

7.1 Conclusion

 

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44

7.2 Scope and Suggestions

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47

A

Appendix

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48

Bibliography

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49

viii

List of Tables

Table

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4.1

Slice Distribution of Reset FSM

 

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4.2

Slice Distribution of Parallel Correlator

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5.1

Noise detection

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29

5.2

Area utilization of HCPC

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5.3

Area utilized for multiple landmines detection .

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6.1

Area utilization of RAM-based FSM

 

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6.2

BRAM utilization of FSM

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ix

List of Figures

Figure

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1.1

Different types of landmines being disposed

 

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NIITEK GPR

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2.2

A GPR Scan

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2.3

A cross-sectional view of VS2.2

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2.4

Depth Locations of VS2.2

 

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2.5

A portion of a GPR Data

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3.1

Device : XC5VFX70Tff1136

 

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3.2

PCI Express Architecture

 

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4.1

Preprocessing Algorithm .

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4.2

Architecture of Reset FSM

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4.3

Architecture of Parallel Correlator

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4.4

Slice Distribution of Reset FSM

 

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25

4.5

Slice Distribution of Parallel Correlator

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5.1

Concept of Hard-Coded Parallel Correlator

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x

5.2

Architecture of Hard-Coded Parallel Correlator

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5.3

Area utilization and Speed of HCPC w.r.t mine length .

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5.4

Area utilization and the Speed of HCPC

 

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34

6.1

Concept of RAM-based FSM

 

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37

6.2

Architecture of RAM-based FSM

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38

6.3

Area utilized and speed of FSM .

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42

7.1

Comparison of HCPC,Parallel Correlator and Reset FSM

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46

A.1

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