Sei sulla pagina 1di 28

Analog Layout - Resistors

•with a guard ring •inside a well to reduce the coupling to the substrate

• with the same orientation • distributed in a interdigitized or common centroid style

dummy resistor should be added in order to minimize the faster etching in large areas

•Contact resistance must be taken into account for small resistance values

•In order to minimize the noise, the resistor can be designed

matching between resistors requires that the resistors are designed

in the layout :

Analog Layout - Resistors

Analog Layout - Resistors

Analog Layout - Capacitors

dummy capacitors should be added in order to minimize the faster etching in large areas

• In order to minimize the noise, the capacitor can be designed •with a guard ring •inside a well to reduce the coupling to the substrate

matching between capacitors requires that the capacitors are designed in the layout using a common centroid style

Analog Layout - Transistors

• The gate resistance is reduced by dividing the gate in several sections

(each section with a width < 40um). N transistors can be instantiated in parallel if the instance name is INST_NAME<1:N>

• The gate resistance is reduced also by adding contacts in both sides of the poly stripes that implement the gate

dummy gates can be added in order to minimize the faster etching in large areas

•Guard rings are usefull to obtain noise imunity and good substrate biasing, preventing latch-up

•matching between transistors requires that the layout is designed:

• using large areas for the gates

• without metal overlapping the gates

• distributed in a interdigitized or common centroid style

Analog Layout - Transistors

Analog Layout - Transistors

Analog Layout - Transistors

Analog Layout - Transistors

Analog Layout - Matching

Common-Centroid Layout: Matching obtained by dividing the gates in two A B Topology: D A
Common-Centroid Layout:
Matching obtained by dividing the gates in two
A
B
Topology: D A S B D B S A D

Analog Layout - Matching

Analog Layout - Matching

Analog Layout - Matching

Examples of interdigitized MOS topologies:

1. ( D A S B D B S A) D

2. ( S A D A)( S B D B S B D B)( S A D A S )

3. ( S A D A S B D B) S (B D B S A D A S )

4. ( S A D A S B D B S A D A) S

5. ( S A D A S B D B S C D C) S (C D C S B D B S A D A S )

A:B = 1:1

A:B = 2:1

A:B:C = 1:1:1

Analog Layout - Matching

Common-Centroid layout design guidelines:

1.

Symmetry: The layout of the devices must be evenly distributed in both directions: x and y

2.

3. Regularity: Partial devices must be distributes uniformly

4. Dispersion: The layout must be as compact and square as possible

Orientation: The number of partial devices oriented in each direction must be the same for each device to be match.

5.

Placement: The geometric center of the devices to match must be very near

Analog Layout - Matching

Common-Centroid Dividing each transistor in two transistors A S B D D B S A
Common-Centroid
Dividing each transistor
in two transistors
A S B
D
D
B S A
D
D
B
A
• A B / B A compliant with the orientation guideline
Analog Layout - Matching Common-Centroid Dividing each transistor in 4 transistors A S B B
Analog Layout - Matching
Common-Centroid
Dividing each transistor
in 4 transistors
A S B
B S A
D
D
D
B S A
A S B
D
D
D

Analog Layout - Matching

D

A S B D B S A D

D

B S A D A S B D

D

A S B D B S A D

D

B S A D A S B D

D

A S B D B S A D A S B D B S A D

D

B S A D A S B D B S A D A S B D

D

A S B D B S A D A S B D B S A D

D

B S A D A S B D B S A D A S B D

D

A S B D B S A D A S B D B S A D

D

B S A D A S B D B S A D A S B D

Common-Centroid

Common Source Stage : Voltage Gain

Common Source Stage : Voltage Gain

Common Drain Stage: Output Resistance

Common Drain Stage: Output Resistance

Common Gate Stage : Input Resistance

Common Gate Stage : Input Resistance

Single stage basic topologies summary

Single stage basic topologies summary

Single stage bandwidth comparison

Single stage bandwidth comparison

Analog Layout – 2 stage AMPOP

2 stage ampop
2 stage ampop

Stabilized bias circuit

Analog Layout – 2 stage AMPOP 2 stage ampop Stabilized bias circuit

Analog design

Initial design criteria (after reading process parameter data):

• current budget limited

• overdrive voltage: V GS -V T > 200mV

• L min = 1µm

(avoid short channel effects and limit sub-threshold current)

• W.L min : Offset limited

• W/L : g m limited

Overdrive in the differential the pair

> overdrive voltage ⇒ > linearity, < gm
> overdrive voltage ⇒ > linearity, < gm

Vos in the differential the pair

A d = g r // r m _ diff o 4 o 2 V
A
d = g
r
//
r
m
_
diff
o
4
o
2
V
= g
r
//
r
× ∆
V
O
_
diff
m
_
diff
o
4
o
2
T
_
diff
3 A
VT
V
= ∆
V
=
OS
_ diff
_ max
T
_
diff
W
L
diff
diff
99,7%

Vos in the differential the pair (c. mirror)

= g r // r × ∆ V V O _ mirr m _ mirr
= g
r
//
r
× ∆
V
V O
_
mirr
m
_
mirr
o
4
o
2
T
_
mirr
A
d = g
r
//
r
m
_
diff
o
4
o
2
3 A
g
m
_
mirr
VT
=
V OS
_
mirr
_ max
W
L
g
mirr
mirr
m
_
diff
=
V
2 + V
V OS
OS _ diff
OS
_
mirr
A g m _ mirr VT = V OS _ mirr _ max W L g

Analog Layout – Cascode dif. pair

•R o = R o2C // R o4C = (g m2C r o2C r o2
•R o = R o2C // R o4C
= (g m2C r o2C r o2 )//(g m4C r o4C r o3 )
•A1 = - g m1 R o
Gain between 5,000 and 10,000
Advantage: higher gain
Inconvenient: highly restricted common mode

Analog Layout – Cascode dif. pair

Cascode versus Folded-Cascode
Cascode
versus
Folded-Cascode
Analog Layout – Cascode dif. pair R o = R o2C //R o4C = [g
Analog Layout – Cascode dif. pair
R o
= R o2C //R o4C
= [g m2C r o2C (r o7 //r o2 )]//(g m4C r o4C r o3 )
A = g m1 R o
Advantage: extended common
mode

Analog Layout – Folded cascode AMPOP

Analog Layout – Folded cascode AMPOP Enhanced current mirror
Analog Layout – Folded cascode AMPOP Enhanced current mirror

Enhanced

current

mirror

Analog Layout – Bandgap example

VBE + Self-biasing Circuit
VBE + Self-biasing Circuit