L-EDIT tutorial (Layout Editor)

Iran University of Science and Technology By : Eng. Bahram Roshan nezhad

Fall 2012

Introduction
L-Edit is an Integrated Circuit Layout Tool used to draw the two dimensional geometry of the masks or layers to fabricate an integrated circuit. Different layers are represented by by different colors and patterns.
Manufacturing constraints can be defined in L-Edit as design rules. L-Edit files are saved as file_name.tdb (Tanner Database).

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L-Edit Modules
L-Edit: The layout editor. L-Edit/DRC: The Design Rule Checker. L-Edit /Extract: The layout extractor to
SPICE.

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L-Edit /SPR: an automatic standard cell. placement and routing package.

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L-Edit Window
L-Edit v8.30
Menu Bar Toolbars
File and cell name Location

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Layer Palette

Drawing windows

Mouse Buttons

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L-Edit Toolbars
File> Open

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File> Print

File> Copy

File> Undo

Edit> Edit-in Place> Edit> Push Into Find

view> Zoom> Mouse

Hierarchy level

Help> L-Edit Cell> Copy User Guid

File> New

File> Save

File> Cut

File> Paste

File> Redo

View> view> Edit> Insides> Cell Edit-in Toggle Browser Place> insides Pop Out

Cell> Open

Tool> Cross Section

Draw> Rotate

Draw> Draw> Flip> Slice> Draw> Vertical Horizontal Merge

Draw> Ungroup

Draw> Move By

Tool> DRC Box

Edit> Find

Tools> Edit> Find Clear Error Previous Layers

Edit> Duplicate

Draw> Draw> Flip> Nibble Horizontal

Draw> Slice> Vertical

Draw> Group

Edit> Edit Object

Tool> DRC

DRC Setup

Edit> Find Next

View> Goto

Tool> Extract

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L-Edit Toolbars
Selection tool Polygon Polygon (90 deg.) (all-angle) Wire (35 deg.) Wire Width

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Circle

Torus

Ruler Ruler (90 deg.) (all angle)

Rectangular Polygon Box (45deg.)

Wire Wire (90 deg.) (all-angle)

Arc

Port

Ruler (45 deg.)

Instance

Layer Palette
Selected Layer name

Layer Palette

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Things to know
Lambda Definition ((

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L = 2
L: The channel length of the MOSFET, i.e, half the size of technology used. Exp) L=180nm 1Lambda=90nm Note: You must set the length of the square to represent One lambda or one Locator Unit.

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Design Parameters Setups

B) Technology
From: Menu> Setup> Design> Technology
Create a name for your fabrication process

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Relationship between L-Edit internal units. one internal unit is1nm (1/1000lambda)

Technology unit

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Design Parameters Setups

B) Grid
From: Menu> Setup> Design> Grid

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These are just the dots shown on the screen. This is where your mouse will snap to.

To set One locator Unit=lambda

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Design Parameters Setups

C) Layers Setup
From: Setup> Layers

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Design Parameters Setups

C) Editing Objects
From: Edit> Edit Object (Ctrl+E)

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Layout Example
Draw the layout of a CMOS inverter given the following: L= 0.5m, Wn= 1.0m, and Wp= 2.5m.
VDD
Pmos L=0.5 m Wp=2.5 m

V in

Vout
Nmos L=0.5 m Wp=1.0 m n

VSS

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Example
Create new Layout file
File > New. In the following open window, Browse and choose mamin 08.tdb in Copy TDB setup from file area. It usually locates in setup directory.

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Example
Design Setup
As mentioned before from: From Menu> Setup> Design >

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Establishing l =0.25mm, therefore 2l =0.5mm.

Click OK: Now the technology is setup!

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Example
Pmos
Choose N-Well in the left palette and draw a box In the N-Well area, draw P-Select (for D&S) and N-Select (for Body). Notice that the size and position should obey Design Rule, which can be found at: http://www.mosis.com/files/scmos/scmos.pdf.
It is a good idea to run DRC at each stage of your design so that you can fix any error along the way

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N-Select
P-Select

10

Draw Active. Draw Poly (Gate).

N-Well

Active

Poly

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Example
Nmos
Do not need to draw P-Well (Why?). Draw N-Select and P-Select. Draw Active. Draw Poly.

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P-Select

N-Select

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Example
Draw VDD and GND Lines.

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VDD

GND

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Example
Connect Poly of PMOS and NMOS.
Connect source of PMOS to VDD by Metal1.

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Connect source of NMOS to GND by Metal 1.

Connect Drain of PMOS and NMOS by Metal 1.

Add an input connect between Metal1 and Poly. Label the INPUT, OUTPUT, VDD and GND.

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Example

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L-Edit Design Rule Check

From Tools> DRC (or the DRC box in the toolbar) Run DRC for the total layout. Fix the errors listed. Once there is no DRC error shown, the layout is ready to extracted.

be

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Example

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L-Edit can be used to generate SPICE-compatible circuit file listings using the Extract option in the setup window of the menu bar menu bar.

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Example
L-Edit Extractor General
Enter the name of the extractor definition file

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Enter the name of the SPICE output file. name.cir for PSPICE name.sp for HSPICE

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Example
L-Edit Extractor Output
Select :
Comments: Write Nodes Names. Write Nodes as: Integers Write Node parasitic Capacitance. Place device labels on layer: Metal1. Then Click Run

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Example
L-Edit Extractor Click: Ignore All

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Example
The generated SPICE file
* NODE NAME ALIASES * 1 = VIN (-7.5,-6.5) * 2 = VOUT (27.5,-6) * 3 = GND (-7.5,-31) * 4 = VDD (-6,30) Cpar1 2 0 C=1.72875E-015 Cpar2 3 0 C=1.0445E-015 Cpar3 4 0 C=1.69675E-015
M2 2 1 4 4 PMOS L=5E-007 W=2.5E-006 AD=4.375E-012 + PD=8.5E-006 AS=4.375E-012 PS=8.5E-006 M1 2 1 3 3 NMOS L=5E-007 W=1E-006 AD=2.5E-012 + PD=6.5E-006 AS=2.5E-012 PS=6.5E-006 * Total Nodes: 4 * Total Elements: 5 * Extract Elapsed Time: 0 seconds .END

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The Nodes corresponding integers

The generated parasitic capacitors

The generated two MOSFETs

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