Noise in Digital Integrated Circuits

Topic 4 The CMOS Inverter

Peter Cheung Department of Electrical & Electronic Engineering Imperial College London

URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk

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DC Operation: Voltage Transfer Characteristic

DC Transfer Curve: Load line

Consider a simple inverter

When Vin = 0 When Vin = Vdd Vout = Vdd Vout = 0

In between, Vout depends on current through transistors as determined by transistor width and length By KCL, steady state condition is: Idsn = |Idsp| Find transfer function by solving equations, but better insight using graphical method

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DC Transfer Curve

Operating Regions

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Effect of beta ratio on switching thresholds

Noise Margins

Extract switching point depends on p/ n If p/ n = 1, switching occurs at around Vdd/2 Otherwise:

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Maximize Noise Margins

Voltage Transfer Characteristic of Real Inverter

Select logic levels at unity gain point of DC transfer characteristic

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The Regenerative Property

Delay Definitions

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Ring Oscillator

Power Dissipation

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Delay Estimation

RC Delay Models

Need to estimate delay without circuit simulation e.g. SPICE

Not as accurate as simulation But easier to ask What if?

For each MOS transistor

Assume ideal switch + capacitance + ON resistance Unit nMOS has resistance R, gate capacitance C Unit pMOS has resistance 2R, gate capacitance C Capacitance width ON resistance 1/width

The step response usually looks like a 1st order RC response with a decaying exponential Use RC delay models to estimate delay
C = total capacitance on output node Use effective resistance R so that t pd = RC

Characterize transistors by finding their effective R depends on average current as gate switches

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Computing the Capacitances

Computing the Capacitances

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Impact of Rise Time on Delay

Delay as a function of VDD

Assuming Vdd = 5V

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Where Does Power Go in CMOS?

Dynamic Power Dissipation

Vdd
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Dynamic power
charging and discharging capacitors

Short circuit currents

short circuit path between power rails during switching

Vin

Vout

Leakage power
Leaking diodes and transistors

CL

Energy/transition = C L * V dd 2 Power = Energy/transition * f = C L * V dd 2 * f

Not a function of transistor sizes! Need to reduce C L , V dd , and f to reduce power.

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Short Circuit Currents

Leakage

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Sub-Threshold in MOS

How to reduce power? Prime choice: Reduce voltage!

Recent years have seen an acceleration in supply voltage reduction Design at very low voltages (0.6 0.9 V by 2010!) Maintaining performance by threshold scaling leads to increased leakage

Reduce switching activity Reduce physical capacitance

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