On Design of Narrow-Band Low-Noise Amplifiers with Inductive Source Degeneration

I. M. Filanovsky
University of Alberta Edmonton, Alberta, Canada, T6G 2E1 E-mail: igor@ee.ualberta.ca
Abstract-The stage of inductively degenerated commonsource amplifer is widely used in narrow-band amplifiers. The noise performance of this stage can be optimized for the noise model that is valid in the range of RF frequencies, and that includes drain and gate correlated noise sources. A ten-step design procedure is given. It results in the circuit with optimal noise figure. An example of design is given. The feasibility of further optimization connected with fmed power dissipation is discussed.

important to emphasize that L, does not bring with it the thermal noise of an ordinary resistor because a pure inductance is noiseless. This fact is exploited to provide a specified input impedance without degrading the noise performance of the amplifier. To avoid using large active devices this circuit is tuned at the resonant frequency, 0 0 , by another inductance, L,, connected in series with the gate (Fig. 1, c) so that the amplifier resonant frequency is
00= 1 / J m . (3) The circuit noise performance is then evaluated using a noise model and calculating the noise figure at the resonant frequency. A simplified noise model [l] of a short-channel MOS transistor at RF includes correlated current noise

I. INTRODUCTION
In design of RF front-end amplifiers one has to choose between the optimal noise and optimal power matching. The designer solves this dilemma building an amplifier with matched input impedance, and using methods that do not degrade the noise performance. The common-source stage with inductive source degeneration (Fig. 1, a) is a popular approach for narrow-band amplifiers. Indeed, using a simplified model for MOS transistor (Fig. 1, b) one finds that , the input impedance of this circuit, Z ( j o ) ,is

sources (Fig. 1, d). Here i d 2 is the drain noise current characterized by the spectral density function (SDF)
i d 2 /(Af) = 4kTEd0, (4) where y=2-3 is a constant, and gdo is the conductance of

iP2

This input impedance is that of a series RLC-network, with a resistive term Re Zin ( j w ) = ( g d s 11C g s = U T L , (2) which is directly proportional to the inductance value. It is

the

device open channel. Then,

igc2 and

are

correlated and uncorrelated with id components of the gate noise current. The SDF of igc2 is given by

igc 4 A f ) = 4kT6gg I c l2

(5)

and the SDF of i P 2 is given by

I-

+1

64

(6) Here 6 4 - 6 is a constant, c=jO.395 is the correlation coefficient

i , 2 /(~f) = 4kr6gg (1- I c l2 .

(7)
and The calculation of the noise figure for the circuit of Fig. 1, c using the model of Fig. 1, d can be found in [1,2]. What was overlooked in [ 1,2] is a possibility to create a step-bystep design process based on matching and noise figure

Fig. 1. Amplifier with source inductive degeneration a) inductive degeneration, b) small-signal equivalent circuit, c) stage circuit, d) transistor noise model used at RF

Roc. 43rd I E E Midwest Symp. on Circuits and Systems, Lansing MI,Aug 8-1 1,ZooO ~ - ~ R ~ ~ - M ~ ~ - ~ X X )QIEEE 2000 I /B~O.IX

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optimization. This deficiency is eliminated here. A ten-step design process is proposed. A numerical example is given. A technical feasibility of further optimization proposed in [1,2] is discussed.

To find the contribution from the uncorrelated part of the gate one has to consider the circuit of Fig. 2, b. It is easy to show that the relationship between the output component i02 and ,i in this circuit is

11. NOISE FIGURE CALCULATION

We have to consider the contributions of the input source noise and noise current sources of the transistor in the output noise current (Fig. 2). To calculate the first component, iol , (Fig. 2, a) one has to find the transconductance

At the resonant frequency one obtains from (14) that 1 R , + i, &+ L, )WO 4 5 ) i02 = i , [l+(WTLs / R s ) l j O O From ( 1 5) one finds that

[Tj

- -

and find its value at

W O . When

L , >> L , ,then

l-woL(Lg +L,)C, neglected. In this case

=l-LgCgsWoL

=o,

(10)

Here

and the term -LSCgswo2in the numerator of (9) can be

QL = ( L g + Ls >(WO Rs = 1 4w0Rs Cgs ) . 1 Substituting ( 6 ) and (8) into (16) one finds

gm jwoc, ( R , + @TLs 1. The SDF of noise voltage for the resistance R, is equal to

Finally, to find the contributions from the drain noise current id , and correlated with it the component of the gate current igc one has to consider the circuit of Fig. 2 , c. Using

vs /(Af)= 4kTRs Multiplying this SDF by the square modulus of the transconductuctance (11) one obtains that
~

( 1 - 1 ) one finds that in this circuit

1
'03 = i g c

+ id
at

[I+ ( W T L s / R, 1

[9j >I
jW0

R,

+ j(Lis+ L , 1 0 0

(18)

[l+(WTLS 4

1 1
rewritten as

W O . This relationship can be

Using the definition (7) one obtains from ( 1 9) that

Substituting in (20) the SDFs of the components one finds

I
C)

Fig. 2 . Calculation of noise contributions

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Combining the contributions made by the transistor in the output noise factor one finds that the SDF of this contribution is

1. Choose a smallest, technologically well controlled and repeatable value of L, (usually 1-3 nH) that can be realized as an integrated inductor or as a bond wire inductor. 2. Find the transistor unity gain fkequency OT = g , I C from the condition W T L , = R, . ,
3. Knowing transistor parameters a,6 , and y , find the

parameter p = ( h 2 ) and calculate the optimal value l(5y)

Q ~ o p r=

&GG .
00,

where
r

4. Knowing the stage resonant operating frequency find the value of gate inductor L, = [ ( Q L R ~001- L, /)
5.

Find

the

device

gate

-capacitance

Now one can find the circuit noise factor

c,,

= 1 /[wo2(Lg+ L,)] .

6. Assume that C ,

= (2 /3)CoxWZ, as usual [ 3 ] .Choose

111. NOISE FACTOR OPTIMIZATION

the minimal possible value of device length L and find the 3 cgs value of the device width W = -. 2 CO& 7. Find the device transconductance g , = O T C ~ , .
8.

The expression (24) can be found in [ 1,2]. The derivation was done here because the model given in Fig. 1 , d is not widely used. A possible optimization of noise figure is also mentioned in [1,2]. -One can create a step-by-step design process based on matching and resulting in noise figure optimization. Indeed, substituting 71 fkom (23) and

Find

the

device

effective

voltage

-vT = g m L . Use this result in bias circuit P?ZCOXW calculation. 9. Find the required device drain current ID =(1/2)gmVe#. Use this result in bias circuit

vefl= v ,

calculation.
10.Find

'

into (24) one can rewrite the noise factor as . . 1 21~I&+2p+-(l+p)+pQ~

QL

, (26)

where p = (& ) I(5y) is a numerical value that depends on the transistor characteristicsonly. One can see that (26) can be optimized with respect to Q L . The optimal value, Q L ~ is found by simple ~ ~ , differentiation.It is equal to
Q ~ o p t=

The first round of design procedure is over. Some secondary effects (gate resistance, resistance of inductors) increase the noise figure. These factors may be taken into consideration after the first stage of design.
V. DESIGN EXAMPLE

Jm ,

As an example we consider design of a GPS narrowband matched amplifier operating at the resonant
fiequency 00 = 10" sec-'. Let R,=50 Q. The amplifier should be realized in CMOS 0.5 pm (drawn) technology. This technology has pnCox=156 pA/V2, and
Cox=3.8*10-3 pF/pm2. The device with the gate drawn length L , =0.5 pm has the effective length L=0.4 pm. We take for this technology [l] that y =2, 6 4, a =0.85, and 1 c I =0.395. As in [11 we start the design choosing L, = 1.4 nH.Then we find that one has to use the device with

(27)

and with this value of QL the noise factor becomes

IV.DESIGN PROCEDURE
Now we can propose the following design procedure for the stage with source inductive degeneration.

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W*

R =s= 50

= 3.57*10" sec-l.

Using

the

Ls

1.4*10-9

4 * 0 852 transistor parameters one finds that p = - 0.289. = 5*2 Then one can find that the optimal value of Q L , ~ is
QLopt = = 2.1 1 . Now we can determine

inductive degeneration circuit is tuned at the same ftequency W O , and the output coil has the Q-factor about 4 to realize the gain of 10. Transistor M I is biased using the current mirror scheme, and the resistor R B ~ ,is chosen large enough that its equivalent noise current can be ignored. The blocking capacitor CB shifts the resonance frequency by 4% only.

that

L, + L , =2.11*50=1.056*10-8H=10.6nH. Then 1o'O the gate inductor will have the value of L , = 10.6-1.4 = 9.2 nH. This inductor is quite large for the integrated realization, and can be realized, for example, as external component. 1 Now one can find that C = , lo2 *10.6*10-9 =0.943pF. Then, with L=0.4 pm the device width will be

W. DISCUSSION CONCLUSIONS AND

The amplifier similar to the proposed one was realized [2], and the obtained noise figure was 3.5 dB (the authors hoped to obtain 2.1 d ) B. The proposed design process requires that y , 6 , and a are known. Yet, these values are known for long-channel devices only ( y = 2 / 3 , 6 = 4 / 3 , a = 1 ) . If one redesign the amplifier using these values one will find that QLopr =1.87. This value is not much different from 2.11 that was found for y =2, 6 4 and a =0.85. If 6 = 2y (as it is , considered now), then the exact value of a has a weak influence on the design process, and one can use the longchannel model. What the designer should expect is an increased value of noise figure. If one uses the long-channel device parameters one can find that Fop =1+2.44(00 / U T ) , (29) and the noise figure would be 1.68 (2.3 dB). Hence, one can expect the increase of noise figure by 1.6 dB at least. The obtained optimal value of Q L coincides with the ~ ~ ~ best figure for a given transconductance design [2] obtained at the step 7 of the proposed design procedure. Finally, in [2] is discussed the optimization of the design process for a fixed power dissipated by the stage. It is found that in this case Fopt =l+l.62(w0 /aT). (30) This optimization would improve the resulting noise figure (1.45 or 1.6 dB) by 0.7 dB only. The design for this optimization could be hardly justifiable because the improvement on the level of 3.9 dB is not very much different from usual measurement errors.
REFERENCES

W = (3/2)*0'943 =930 3.8*10-3 *0.4

pm.

The required device

transconductance is g , = 0.943*10-12 *3.57*10" =3.37*10-2 A!V=33665 p m . This transconductance value is obtained when the effective voltage
156*930 device should be biased by the current I = 0.5*33.7*0.092=1.58 mA. , Finally one can find that he noise factor will be Fop =1+5.24 (00 /0~)=1+1.47=2.47 (3.9 dB).

veH=

33665 * 0'4 =0.094 V. is applied to the device. The

To complete the design requires the addition of bias and output circuitry. For narrow-band applications, it is advantageous to tune out the output capacitance to increase the gain. So, a typical single-ended amplifier might appear as shown in Fig. 3. This design assumes that the output Fig. 3. The narrow-band low-noise amplifier with source

CL

Fig. 3. The narrow-band low-noise amplifier with source inductive degeneration

[l] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, Cambridge, 1998. [2] D. K. Shaeffer, T. H. Lee, A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier, IEEE J. Solid-state Circuits, vol. 32, NO5, pp. 745-759, 1997. [3] D. Johns, K. Martin, Analog Integrated Circuit Design, J. Wiley, New York, 1997.

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