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VLSI Design for Manufacturability

Keh-Jeng Chang Department of Computer Science National Tsing Hua University March 12, 2004

Outline
The VLSI Trend Understanding DFM Nanometer technology challenges From technology to design: SIPPs Nanometer design challenges

The VLSI Trend

VLSI CMOS BULK

* SEM picture courtesy of TSMC, Hsin-Chu, Taiwan


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State-of-the-Art CMOS

Sub-130nm CMOS transistors


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The Back-End of the Line

Deep Submicron to Nanometer


1997 0.25um (8M random logic gates + RAM) 1999 0.18um (14M random logic gates + RAM) 2002 0.13um (24M random logic gates + RAM) 2005 90nm (40M random logic gates + RAM) 2008 65nm (64M random logic gates + RAM) 2011 45nm (100M random logic gates + RAM)

* Source http://www.itrs.org

VLSI Design Flow

VLSI Design+DFM Flow (1/2)


Point tools and integrated tools are used.
RTL
RTL analysis Floorplanning Power analysis

Virtual Prototyping

Synthesis Placement STA

Physical Synthesis

DEF

Routing

VLSI Design+DFM Flow (2/2)


DEF
Layout DRC Extraction Delay calculation STA Noise check EM check

DEF
Concurrent timing & signal integrity: + reliability + manufacturability analysis + optimization

ECO

DEF
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DEF

The Minimum Academia Can Do


Characterizing VLSI Performance

HSPICE

accurate BEOL modeling using Raphael

accurate FEOL modeling using BSIMPro

Characterizing Nanometer CMOS Technologies

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Legacy DFM (1/2)

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Legacy DFM (2/2)

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VLSI DFM Needs


How to survive:
Latchup Dummy metal ESD STI and dummy diffusion Substrate noise Slotted metal OPC Antenna effect Shallow Trench Isolation Electromigration Process drifting and variation Hot electron effect CMP dishing

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VLSI Yields Decrease @ 130nm


When the manufacturing foundries did everything correctly, these five factors still affect yields:
Defects Logic or analog design errors Chips contain incorrect logic functions or analog functions Process parameter variations Incorrect or insufficient electrical characterization of the chip designs before manufacturing Reliability Insufficient electrical, material, or thermal characterization of the chip designs before manufacturing such as ESD, EM, et al. Incorrect chip-package interface models

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Understanding DFM (1/2)


When transistors do not have the designed size; When interconnect does not have the anticipated R,L,C ; When the supplied voltage drops below 0.9*Vdd, dynamically or statically; When the coupling noise causes functional errors at high slew rates; When the guardband must be made more realistic but cannot be more pessimistic.

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Understanding DFM (2/2)


Parametric yield The circuit may work but the performance such as speed, power consumption, gain, and oscillation are subject to process parameter uncertainties or variations. Defect limited yield ESD, electromigration, antenna, particle, contamination,
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Nanometer Technology Challenges


Copper replacing aluminum Low-K replacing silicon dioxide Lower power supplies Sub-wavelength lithography Multiple-Vt CMOS Tighter interconnect densities Integrating digital+AMS+memory as SoC

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Copper Process Variations


Random variations Within-die and die-to-die variations Critical Dimension (CD) Sheet Rho Metal thickness Low-K thickness and permittivity Systematic variations Density-induced variations Trapezoidal cross-section shapes Dummy metals and diffusions [a.k.a. DFM] Metal slotting and cheesing [a.k.a. DFM] Sub-wavelength OPC lithography [a.k.a. DFM] Tall stack vias
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CMP-induced Variations
Cross-section of a pre-production 130-nm copper process

M7 final thickness: 0.447um (Target ~0.375um) M6 final thickness: 0.375um (Target ~0.375um) M5 final thickness: 0.414um (Target ~0.375um)
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Nanometer Design Challenges


Significant process variations OPC/PSM Signal integrity Shortened time to market Larger integration level with hierarchy Faster slew rates Lower power consumption budgets

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Accurate BEOL Modeling

s3 h2 s2 w3 w2 t2 h1 hp s1 w 1 t1 sp w p tp 2 t3 3 b a M2 b 1 a p M1 Poly M3

Standard Interconnect Performance Parameters (SIPPs): 1. critical dimensions (CD) 2. metal thickness 3. dielectric thickness 4. sheet R 5. via resistance 6. same-layer dielectric constant 7. inter-layer dielectric constant

Create Library of 3D primitives (90,000 RC and 60,000 Ls per 1P8M process)

Library Builder

Pre-Characterized IPL Library

RC and L Field Solvers

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Noisy Neighbors
Delay uncertainty
==>
D Q Opp direction switching Slows down the victim Creates setup issues Same direction switching Speeds up the victim Creates hold issues

Glitches on silent lines


D Q

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Coupling Induced Delay

Cc Cc m1Cc m3Cc m2Cc m4Cc

Opposite direction switching: 1 m ~3 Same direction switching: ~ -1 m 1

Simultaneous switching on coupled nets affects loading Static timing analysis is done with grounded caps m-factor is dependent on switching direction victim & aggressor edge times victim & aggressor drivers sizes
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Hierarchical Design Challenges


Block-level Analysis
Top-level routes: Routing over blocks
memory

on-chip bus Hierarchical Parasitics, Extraction

Top-level Analysis
Abstract model Abstract model

Timing, SI, abstraction for blocks, macros, IP

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Modeling Voltage Drop


V(t) = I(t).R + C.dv/dt.R + L.di/dt
Resistive Component Capacitive Component Inductive Component

Package + bond-wire Rpkg Lpkg Cpkg

On-chip Vdd CVdd RVdd Rdecap Cdecap Cn-well Ccell Cp-well Ron Ron Rsignal Csignal

Rpkg Lpkg Cpkg

Vss CVss

Rdecap RVss DECAP1

BUFX1

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On the Horizon
Design closure with third-party IPs Packaging models Interconnect inductance models Spiral inductor models Accurate leakage and power characterization Designing matched components for analog Substrate noise modeling and avoidance

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