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Keh-Jeng Chang Department of Computer Science National Tsing Hua University March 12, 2004
Outline
The VLSI Trend Understanding DFM Nanometer technology challenges From technology to design: SIPPs Nanometer design challenges
State-of-the-Art CMOS
* Source http://www.itrs.org
Virtual Prototyping
Physical Synthesis
DEF
Routing
DEF
Concurrent timing & signal integrity: + reliability + manufacturability analysis + optimization
ECO
DEF
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DEF
HSPICE
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CMP-induced Variations
Cross-section of a pre-production 130-nm copper process
M7 final thickness: 0.447um (Target ~0.375um) M6 final thickness: 0.375um (Target ~0.375um) M5 final thickness: 0.414um (Target ~0.375um)
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s3 h2 s2 w3 w2 t2 h1 hp s1 w 1 t1 sp w p tp 2 t3 3 b a M2 b 1 a p M1 Poly M3
Standard Interconnect Performance Parameters (SIPPs): 1. critical dimensions (CD) 2. metal thickness 3. dielectric thickness 4. sheet R 5. via resistance 6. same-layer dielectric constant 7. inter-layer dielectric constant
Library Builder
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Noisy Neighbors
Delay uncertainty
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D Q Opp direction switching Slows down the victim Creates setup issues Same direction switching Speeds up the victim Creates hold issues
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Simultaneous switching on coupled nets affects loading Static timing analysis is done with grounded caps m-factor is dependent on switching direction victim & aggressor edge times victim & aggressor drivers sizes
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Top-level Analysis
Abstract model Abstract model
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On-chip Vdd CVdd RVdd Rdecap Cdecap Cn-well Ccell Cp-well Ron Ron Rsignal Csignal
Vss CVss
BUFX1
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On the Horizon
Design closure with third-party IPs Packaging models Interconnect inductance models Spiral inductor models Accurate leakage and power characterization Designing matched components for analog Substrate noise modeling and avoidance
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